arch/arm64/boot/dts/qcom/sc8180x.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2020-2023, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
   8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  12 #include <dt-bindings/interconnect/qcom,sc8180x.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/qcom-rpmpd.h>
  15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         clocks {
  25                 xo_board_clk: xo-board {
  26                         compatible = "fixed-clock";
  27                         #clock-cells = <0>;
  28                         clock-frequency = <38400000>;
  29                 };
  30
  31                 sleep_clk: sleep-clk {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <32764>;
  35                         clock-output-names = "sleep_clk";
  36                 };
  37         };
  38
  39         cpus {
  40                 #address-cells = <2>;
  41                 #size-cells = <0>;
  42
  43                 CPU0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "qcom,kryo485";
  46                         reg = <0x0 0x0>;
  47                         enable-method = "psci";
  48                         capacity-dmips-mhz = <602>;
  49                         next-level-cache = <&L2_0>;
  50                         qcom,freq-domain = <&cpufreq_hw 0>;
  51                         operating-points-v2 = <&cpu0_opp_table>;
  52                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
  53                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  54                         power-domains = <&CPU_PD0>;
  55                         power-domain-names = "psci";
  56                         #cooling-cells = <2>;
  57                         clocks = <&cpufreq_hw 0>;
  58
  59                         L2_0: l2-cache {
  60                                 compatible = "cache";
  61                                 cache-level = <2>;
  62                                 cache-unified;
  63                                 next-level-cache = <&L3_0>;
  64                                 L3_0: l3-cache {
  65                                         compatible = "cache";
  66                                         cache-level = <3>;
  67                                 };
  68                         };
  69                 };
  70
  71                 CPU1: cpu@100 {
  72                         device_type = "cpu";
  73                         compatible = "qcom,kryo485";
  74                         reg = <0x0 0x100>;
  75                         enable-method = "psci";
  76                         capacity-dmips-mhz = <602>;
  77                         next-level-cache = <&L2_100>;
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
  81                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         #cooling-cells = <2>;
  85                         clocks = <&cpufreq_hw 0>;
  86
  87                         L2_100: l2-cache {
  88                                 compatible = "cache";
  89                                 cache-level = <2>;
  90                                 cache-unified;
  91                                 next-level-cache = <&L3_0>;
  92                         };
  93
  94                 };
  95
  96                 CPU2: cpu@200 {
  97                         device_type = "cpu";
  98                         compatible = "qcom,kryo485";
  99                         reg = <0x0 0x200>;
 100                         enable-method = "psci";
 101                         capacity-dmips-mhz = <602>;
 102                         next-level-cache = <&L2_200>;
 103                         qcom,freq-domain = <&cpufreq_hw 0>;
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 106                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 107                         power-domains = <&CPU_PD2>;
 108                         power-domain-names = "psci";
 109                         #cooling-cells = <2>;
 110                         clocks = <&cpufreq_hw 0>;
 111
 112                         L2_200: l2-cache {
 113                                 compatible = "cache";
 114                                 cache-level = <2>;
 115                                 cache-unified;
 116                                 next-level-cache = <&L3_0>;
 117                         };
 118                 };
 119
 120                 CPU3: cpu@300 {
 121                         device_type = "cpu";
 122                         compatible = "qcom,kryo485";
 123                         reg = <0x0 0x300>;
 124                         enable-method = "psci";
 125                         capacity-dmips-mhz = <602>;
 126                         next-level-cache = <&L2_300>;
 127                         qcom,freq-domain = <&cpufreq_hw 0>;
 128                         operating-points-v2 = <&cpu0_opp_table>;
 129                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 130                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 131                         power-domains = <&CPU_PD3>;
 132                         power-domain-names = "psci";
 133                         #cooling-cells = <2>;
 134                         clocks = <&cpufreq_hw 0>;
 135
 136                         L2_300: l2-cache {
 137                                 compatible = "cache";
 138                                 cache-unified;
 139                                 cache-level = <2>;
 140                                 next-level-cache = <&L3_0>;
 141                         };
 142                 };
 143
 144                 CPU4: cpu@400 {
 145                         device_type = "cpu";
 146                         compatible = "qcom,kryo485";
 147                         reg = <0x0 0x400>;
 148                         enable-method = "psci";
 149                         capacity-dmips-mhz = <1024>;
 150                         next-level-cache = <&L2_400>;
 151                         qcom,freq-domain = <&cpufreq_hw 1>;
 152                         operating-points-v2 = <&cpu4_opp_table>;
 153                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 154                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 155                         power-domains = <&CPU_PD4>;
 156                         power-domain-names = "psci";
 157                         #cooling-cells = <2>;
 158                         clocks = <&cpufreq_hw 1>;
 159
 160                         L2_400: l2-cache {
 161                                 compatible = "cache";
 162                                 cache-unified;
 163                                 cache-level = <2>;
 164                                 next-level-cache = <&L3_0>;
 165                         };
 166                 };
 167
 168                 CPU5: cpu@500 {
 169                         device_type = "cpu";
 170                         compatible = "qcom,kryo485";
 171                         reg = <0x0 0x500>;
 172                         enable-method = "psci";
 173                         capacity-dmips-mhz = <1024>;
 174                         next-level-cache = <&L2_500>;
 175                         qcom,freq-domain = <&cpufreq_hw 1>;
 176                         operating-points-v2 = <&cpu4_opp_table>;
 177                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 178                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 179                         power-domains = <&CPU_PD5>;
 180                         power-domain-names = "psci";
 181                         #cooling-cells = <2>;
 182                         clocks = <&cpufreq_hw 1>;
 183
 184                         L2_500: l2-cache {
 185                                 compatible = "cache";
 186                                 cache-unified;
 187                                 cache-level = <2>;
 188                                 next-level-cache = <&L3_0>;
 189                         };
 190                 };
 191
 192                 CPU6: cpu@600 {
 193                         device_type = "cpu";
 194                         compatible = "qcom,kryo485";
 195                         reg = <0x0 0x600>;
 196                         enable-method = "psci";
 197                         capacity-dmips-mhz = <1024>;
 198                         next-level-cache = <&L2_600>;
 199                         qcom,freq-domain = <&cpufreq_hw 1>;
 200                         operating-points-v2 = <&cpu4_opp_table>;
 201                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 202                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 203                         power-domains = <&CPU_PD6>;
 204                         power-domain-names = "psci";
 205                         #cooling-cells = <2>;
 206                         clocks = <&cpufreq_hw 1>;
 207
 208                         L2_600: l2-cache {
 209                                 compatible = "cache";
 210                                 cache-unified;
 211                                 cache-level = <2>;
 212                                 next-level-cache = <&L3_0>;
 213                         };
 214                 };
 215
 216                 CPU7: cpu@700 {
 217                         device_type = "cpu";
 218                         compatible = "qcom,kryo485";
 219                         reg = <0x0 0x700>;
 220                         enable-method = "psci";
 221                         capacity-dmips-mhz = <1024>;
 222                         next-level-cache = <&L2_700>;
 223                         qcom,freq-domain = <&cpufreq_hw 1>;
 224                         operating-points-v2 = <&cpu4_opp_table>;
 225                         interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
 226                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 227                         power-domains = <&CPU_PD7>;
 228                         power-domain-names = "psci";
 229                         #cooling-cells = <2>;
 230                         clocks = <&cpufreq_hw 1>;
 231
 232                         L2_700: l2-cache {
 233                                 compatible = "cache";
 234                                 cache-unified;
 235                                 cache-level = <2>;
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 cpu-map {
 241                         cluster0 {
 242                                 core0 {
 243                                         cpu = <&CPU0>;
 244                                 };
 245
 246                                 core1 {
 247                                         cpu = <&CPU1>;
 248                                 };
 249
 250                                 core2 {
 251                                         cpu = <&CPU2>;
 252                                 };
 253
 254                                 core3 {
 255                                         cpu = <&CPU3>;
 256                                 };
 257
 258                                 core4 {
 259                                         cpu = <&CPU4>;
 260                                 };
 261
 262                                 core5 {
 263                                         cpu = <&CPU5>;
 264                                 };
 265
 266                                 core6 {
 267                                         cpu = <&CPU6>;
 268                                 };
 269
 270                                 core7 {
 271                                         cpu = <&CPU7>;
 272                                 };
 273                         };
 274                 };
 275
 276                 idle-states {
 277                         entry-method = "psci";
 278
 279                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 280                                 compatible = "arm,idle-state";
 281                                 arm,psci-suspend-param = <0x40000004>;
 282                                 entry-latency-us = <355>;
 283                                 exit-latency-us = <909>;
 284                                 min-residency-us = <3934>;
 285                                 local-timer-stop;
 286                         };
 287
 288                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 289                                 compatible = "arm,idle-state";
 290                                 arm,psci-suspend-param = <0x40000004>;
 291                                 entry-latency-us = <241>;
 292                                 exit-latency-us = <1461>;
 293                                 min-residency-us = <4488>;
 294                                 local-timer-stop;
 295                         };
 296                 };
 297
 298                 domain-idle-states {
 299                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 300                                 compatible = "domain-idle-state";
 301                                 arm,psci-suspend-param = <0x4100c244>;
 302                                 entry-latency-us = <3263>;
 303                                 exit-latency-us = <6562>;
 304                                 min-residency-us = <9987>;
 305                         };
 306                 };
 307         };
 308
 309         cpu0_opp_table: opp-table-cpu0 {
 310                 compatible = "operating-points-v2";
 311                 opp-shared;
 312
 313                 opp-300000000 {
 314                         opp-hz = /bits/ 64 <300000000>;
 315                         opp-peak-kBps = <800000 9600000>;
 316                 };
 317
 318                 opp-422400000 {
 319                         opp-hz = /bits/ 64 <422400000>;
 320                         opp-peak-kBps = <800000 9600000>;
 321                 };
 322
 323                 opp-537600000 {
 324                         opp-hz = /bits/ 64 <537600000>;
 325                         opp-peak-kBps = <800000 12902400>;
 326                 };
 327
 328                 opp-652800000 {
 329                         opp-hz = /bits/ 64 <652800000>;
 330                         opp-peak-kBps = <800000 12902400>;
 331                 };
 332
 333                 opp-768000000 {
 334                         opp-hz = /bits/ 64 <768000000>;
 335                         opp-peak-kBps = <800000 15974400>;
 336                 };
 337
 338                 opp-883200000 {
 339                         opp-hz = /bits/ 64 <883200000>;
 340                         opp-peak-kBps = <1804000 19660800>;
 341                 };
 342
 343                 opp-998400000 {
 344                         opp-hz = /bits/ 64 <998400000>;
 345                         opp-peak-kBps = <1804000 19660800>;
 346                 };
 347
 348                 opp-1113600000 {
 349                         opp-hz = /bits/ 64 <1113600000>;
 350                         opp-peak-kBps = <1804000 22732800>;
 351                 };
 352
 353                 opp-1228800000 {
 354                         opp-hz = /bits/ 64 <1228800000>;
 355                         opp-peak-kBps = <1804000 22732800>;
 356                 };
 357
 358                 opp-1363200000 {
 359                         opp-hz = /bits/ 64 <1363200000>;
 360                         opp-peak-kBps = <2188000 25804800>;
 361                 };
 362
 363                 opp-1478400000 {
 364                         opp-hz = /bits/ 64 <1478400000>;
 365                         opp-peak-kBps = <2188000 31948800>;
 366                 };
 367
 368                 opp-1574400000 {
 369                         opp-hz = /bits/ 64 <1574400000>;
 370                         opp-peak-kBps = <3072000 31948800>;
 371                 };
 372
 373                 opp-1670400000 {
 374                         opp-hz = /bits/ 64 <1670400000>;
 375                         opp-peak-kBps = <3072000 31948800>;
 376                 };
 377
 378                 opp-1766400000 {
 379                         opp-hz = /bits/ 64 <1766400000>;
 380                         opp-peak-kBps = <3072000 31948800>;
 381                 };
 382         };
 383
 384         cpu4_opp_table: opp-table-cpu4 {
 385                 compatible = "operating-points-v2";
 386                 opp-shared;
 387
 388                 opp-825600000 {
 389                         opp-hz = /bits/ 64 <825600000>;
 390                         opp-peak-kBps = <1804000 15974400>;
 391                 };
 392
 393                 opp-940800000 {
 394                         opp-hz = /bits/ 64 <940800000>;
 395                         opp-peak-kBps = <2188000 19660800>;
 396                 };
 397
 398                 opp-1056000000 {
 399                         opp-hz = /bits/ 64 <1056000000>;
 400                         opp-peak-kBps = <2188000 22732800>;
 401                 };
 402
 403                 opp-1171200000 {
 404                         opp-hz = /bits/ 64 <1171200000>;
 405                         opp-peak-kBps = <3072000 25804800>;
 406                 };
 407
 408                 opp-1286400000 {
 409                         opp-hz = /bits/ 64 <1286400000>;
 410                         opp-peak-kBps = <3072000 31948800>;
 411                 };
 412
 413                 opp-1420800000 {
 414                         opp-hz = /bits/ 64 <1420800000>;
 415                         opp-peak-kBps = <4068000 31948800>;
 416                 };
 417
 418                 opp-1536000000 {
 419                         opp-hz = /bits/ 64 <1536000000>;
 420                         opp-peak-kBps = <4068000 31948800>;
 421                 };
 422
 423                 opp-1651200000 {
 424                         opp-hz = /bits/ 64 <1651200000>;
 425                         opp-peak-kBps = <4068000 40550400>;
 426                 };
 427
 428                 opp-1766400000 {
 429                         opp-hz = /bits/ 64 <1766400000>;
 430                         opp-peak-kBps = <4068000 40550400>;
 431                 };
 432
 433                 opp-1881600000 {
 434                         opp-hz = /bits/ 64 <1881600000>;
 435                         opp-peak-kBps = <4068000 43008000>;
 436                 };
 437
 438                 opp-1996800000 {
 439                         opp-hz = /bits/ 64 <1996800000>;
 440                         opp-peak-kBps = <6220000 43008000>;
 441                 };
 442
 443                 opp-2131200000 {
 444                         opp-hz = /bits/ 64 <2131200000>;
 445                         opp-peak-kBps = <6220000 49152000>;
 446                 };
 447
 448                 opp-2246400000 {
 449                         opp-hz = /bits/ 64 <2246400000>;
 450                         opp-peak-kBps = <7216000 49152000>;
 451                 };
 452
 453                 opp-2361600000 {
 454                         opp-hz = /bits/ 64 <2361600000>;
 455                         opp-peak-kBps = <8368000 49152000>;
 456                 };
 457
 458                 opp-2457600000 {
 459                         opp-hz = /bits/ 64 <2457600000>;
 460                         opp-peak-kBps = <8368000 51609600>;
 461                 };
 462
 463                 opp-2553600000 {
 464                         opp-hz = /bits/ 64 <2553600000>;
 465                         opp-peak-kBps = <8368000 51609600>;
 466                 };
 467
 468                 opp-2649600000 {
 469                         opp-hz = /bits/ 64 <2649600000>;
 470                         opp-peak-kBps = <8368000 51609600>;
 471                 };
 472
 473                 opp-2745600000 {
 474                         opp-hz = /bits/ 64 <2745600000>;
 475                         opp-peak-kBps = <8368000 51609600>;
 476                 };
 477
 478                 opp-2841600000 {
 479                         opp-hz = /bits/ 64 <2841600000>;
 480                         opp-peak-kBps = <8368000 51609600>;
 481                 };
 482
 483                 opp-2918400000 {
 484                         opp-hz = /bits/ 64 <2918400000>;
 485                         opp-peak-kBps = <8368000 51609600>;
 486                 };
 487
 488                 opp-2995200000 {
 489                         opp-hz = /bits/ 64 <2995200000>;
 490                         opp-peak-kBps = <8368000 51609600>;
 491                 };
 492         };
 493
 494         firmware {
 495                 scm: scm {
 496                         compatible = "qcom,scm-sc8180x", "qcom,scm";
 497                 };
 498         };
 499
 500         camnoc_virt: interconnect-camnoc-virt {
 501                 compatible = "qcom,sc8180x-camnoc-virt";
 502                 #interconnect-cells = <2>;
 503                 qcom,bcm-voters = <&apps_bcm_voter>;
 504         };
 505
 506         mc_virt: interconnect-mc-virt {
 507                 compatible = "qcom,sc8180x-mc-virt";
 508                 #interconnect-cells = <2>;
 509                 qcom,bcm-voters = <&apps_bcm_voter>;
 510         };
 511
 512         qup_virt: interconnect-qup-virt {
 513                 compatible = "qcom,sc8180x-qup-virt";
 514                 #interconnect-cells = <2>;
 515                 qcom,bcm-voters = <&apps_bcm_voter>;
 516         };
 517
 518         memory@80000000 {
 519                 device_type = "memory";
 520                 /* We expect the bootloader to fill in the size */
 521                 reg = <0x0 0x80000000 0x0 0x0>;
 522         };
 523
 524         pmu {
 525                 compatible = "arm,armv8-pmuv3";
 526                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 527         };
 528
 529         psci {
 530                 compatible = "arm,psci-1.0";
 531                 method = "smc";
 532
 533                 CPU_PD0: power-domain-cpu0 {
 534                         #power-domain-cells = <0>;
 535                         power-domains = <&CLUSTER_PD>;
 536                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 537                 };
 538
 539                 CPU_PD1: power-domain-cpu1 {
 540                         #power-domain-cells = <0>;
 541                         power-domains = <&CLUSTER_PD>;
 542                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 543                 };
 544
 545                 CPU_PD2: power-domain-cpu2 {
 546                         #power-domain-cells = <0>;
 547                         power-domains = <&CLUSTER_PD>;
 548                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 549                 };
 550
 551                 CPU_PD3: power-domain-cpu3 {
 552                         #power-domain-cells = <0>;
 553                         power-domains = <&CLUSTER_PD>;
 554                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 555                 };
 556
 557                 CPU_PD4: power-domain-cpu4 {
 558                         #power-domain-cells = <0>;
 559                         power-domains = <&CLUSTER_PD>;
 560                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 561                 };
 562
 563                 CPU_PD5: power-domain-cpu5 {
 564                         #power-domain-cells = <0>;
 565                         power-domains = <&CLUSTER_PD>;
 566                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 567                 };
 568
 569                 CPU_PD6: power-domain-cpu6 {
 570                         #power-domain-cells = <0>;
 571                         power-domains = <&CLUSTER_PD>;
 572                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 573                 };
 574
 575                 CPU_PD7: power-domain-cpu7 {
 576                         #power-domain-cells = <0>;
 577                         power-domains = <&CLUSTER_PD>;
 578                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 579                 };
 580
 581                 CLUSTER_PD: power-domain-cpu-cluster0 {
 582                         #power-domain-cells = <0>;
 583                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 584                 };
 585         };
 586
 587         reserved-memory {
 588                 #address-cells = <2>;
 589                 #size-cells = <2>;
 590                 ranges;
 591
 592                 hyp_mem: hyp@85700000 {
 593                         reg = <0x0 0x85700000 0x0 0x600000>;
 594                         no-map;
 595                 };
 596
 597                 xbl_mem: xbl@85d00000 {
 598                         reg = <0x0 0x85d00000 0x0 0x140000>;
 599                         no-map;
 600                 };
 601
 602                 aop_mem: aop@85f00000 {
 603                         reg = <0x0 0x85f00000 0x0 0x20000>;
 604                         no-map;
 605                 };
 606
 607                 aop_cmd_db: cmd-db@85f20000 {
 608                         compatible = "qcom,cmd-db";
 609                         reg = <0x0 0x85f20000 0x0 0x20000>;
 610                         no-map;
 611                 };
 612
 613                 reserved@85f40000 {
 614                         reg = <0x0 0x85f40000 0x0 0x10000>;
 615                         no-map;
 616                 };
 617
 618                 smem_mem: smem@86000000 {
 619                         compatible = "qcom,smem";
 620                         reg = <0x0 0x86000000 0x0 0x200000>;
 621                         no-map;
 622                         hwlocks = <&tcsr_mutex 3>;
 623                 };
 624
 625                 reserved@86200000 {
 626                         reg = <0x0 0x86200000 0x0 0x3900000>;
 627                         no-map;
 628                 };
 629
 630                 reserved@89b00000 {
 631                         reg = <0x0 0x89b00000 0x0 0x1c00000>;
 632                         no-map;
 633                 };
 634
 635                 reserved@9d400000 {
 636                         reg = <0x0 0x9d400000 0x0 0x1000000>;
 637                         no-map;
 638                 };
 639
 640                 reserved@9e400000 {
 641                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 642                         no-map;
 643                 };
 644
 645                 reserved@9f800000 {
 646                         reg = <0x0 0x9f800000 0x0 0x800000>;
 647                         no-map;
 648                 };
 649         };
 650
 651         smp2p-cdsp {
 652                 compatible = "qcom,smp2p";
 653                 qcom,smem = <94>, <432>;
 654
 655                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 656
 657                 mboxes = <&apss_shared 6>;
 658
 659                 qcom,local-pid = <0>;
 660                 qcom,remote-pid = <5>;
 661
 662                 cdsp_smp2p_out: master-kernel {
 663                         qcom,entry-name = "master-kernel";
 664                         #qcom,smem-state-cells = <1>;
 665                 };
 666
 667                 cdsp_smp2p_in: slave-kernel {
 668                         qcom,entry-name = "slave-kernel";
 669
 670                         interrupt-controller;
 671                         #interrupt-cells = <2>;
 672                 };
 673         };
 674
 675         smp2p-lpass {
 676                 compatible = "qcom,smp2p";
 677                 qcom,smem = <443>, <429>;
 678
 679                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 680
 681                 mboxes = <&apss_shared 10>;
 682
 683                 qcom,local-pid = <0>;
 684                 qcom,remote-pid = <2>;
 685
 686                 adsp_smp2p_out: master-kernel {
 687                         qcom,entry-name = "master-kernel";
 688                         #qcom,smem-state-cells = <1>;
 689                 };
 690
 691                 adsp_smp2p_in: slave-kernel {
 692                         qcom,entry-name = "slave-kernel";
 693
 694                         interrupt-controller;
 695                         #interrupt-cells = <2>;
 696                 };
 697         };
 698
 699         smp2p-mpss {
 700                 compatible = "qcom,smp2p";
 701                 qcom,smem = <435>, <428>;
 702
 703                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 704
 705                 mboxes = <&apss_shared 14>;
 706
 707                 qcom,local-pid = <0>;
 708                 qcom,remote-pid = <1>;
 709
 710                 modem_smp2p_out: master-kernel {
 711                         qcom,entry-name = "master-kernel";
 712                         #qcom,smem-state-cells = <1>;
 713                 };
 714
 715                 modem_smp2p_in: slave-kernel {
 716                         qcom,entry-name = "slave-kernel";
 717
 718                         interrupt-controller;
 719                         #interrupt-cells = <2>;
 720                 };
 721
 722                 modem_smp2p_ipa_out: ipa-ap-to-modem {
 723                         qcom,entry-name = "ipa";
 724                         #qcom,smem-state-cells = <1>;
 725                 };
 726
 727                 modem_smp2p_ipa_in: ipa-modem-to-ap {
 728                         qcom,entry-name = "ipa";
 729                         interrupt-controller;
 730                         #interrupt-cells = <2>;
 731                 };
 732
 733                 modem_smp2p_wlan_in: wlan-wpss-to-ap {
 734                         qcom,entry-name = "wlan";
 735                         interrupt-controller;
 736                         #interrupt-cells = <2>;
 737                 };
 738         };
 739
 740         smp2p-slpi {
 741                 compatible = "qcom,smp2p";
 742                 qcom,smem = <481>, <430>;
 743
 744                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 745
 746                 mboxes = <&apss_shared 26>;
 747
 748                 qcom,local-pid = <0>;
 749                 qcom,remote-pid = <3>;
 750
 751                 slpi_smp2p_out: master-kernel {
 752                         qcom,entry-name = "master-kernel";
 753                         #qcom,smem-state-cells = <1>;
 754                 };
 755
 756                 slpi_smp2p_in: slave-kernel {
 757                         qcom,entry-name = "slave-kernel";
 758
 759                         interrupt-controller;
 760                         #interrupt-cells = <2>;
 761                 };
 762         };
 763
 764         soc: soc@0 {
 765                 compatible = "simple-bus";
 766                 #address-cells = <2>;
 767                 #size-cells = <2>;
 768                 ranges = <0 0 0 0 0x10 0>;
 769                 dma-ranges = <0 0 0 0 0x10 0>;
 770
 771                 gcc: clock-controller@100000 {
 772                         compatible = "qcom,gcc-sc8180x";
 773                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 774                         #clock-cells = <1>;
 775                         #reset-cells = <1>;
 776                         #power-domain-cells = <1>;
 777                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 778                                  <&rpmhcc RPMH_CXO_CLK_A>,
 779                                  <&sleep_clk>;
 780                         clock-names = "bi_tcxo",
 781                                       "bi_tcxo_ao",
 782                                       "sleep_clk";
 783                 };
 784
 785                 qupv3_id_0: geniqup@8c0000 {
 786                         compatible = "qcom,geni-se-qup";
 787                         reg = <0 0x008c0000 0 0x6000>;
 788                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 789                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 790                         clock-names = "m-ahb", "s-ahb";
 791                         #address-cells = <2>;
 792                         #size-cells = <2>;
 793                         ranges;
 794                         iommus = <&apps_smmu 0x4c3 0>;
 795                         status = "disabled";
 796
 797                         i2c0: i2c@880000 {
 798                                 compatible = "qcom,geni-i2c";
 799                                 reg = <0 0x00880000 0 0x4000>;
 800                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 801                                 clock-names = "se";
 802                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 803                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 804                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
 805                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
 806                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 807                                 #address-cells = <1>;
 808                                 #size-cells = <0>;
 809                                 status = "disabled";
 810                         };
 811
 812                         spi0: spi@880000 {
 813                                 compatible = "qcom,geni-spi";
 814                                 reg = <0 0x00880000 0 0x4000>;
 815                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 816                                 clock-names = "se";
 817                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 818                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 819                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 820                                 interconnect-names = "qup-core", "qup-config";
 821                                 #address-cells = <1>;
 822                                 #size-cells = <0>;
 823                                 status = "disabled";
 824                         };
 825
 826                         uart0: serial@880000 {
 827                                 compatible = "qcom,geni-uart";
 828                                 reg = <0 0x00880000 0 0x4000>;
 829                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 830                                 clock-names = "se";
 831                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 832                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 833                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 834                                 interconnect-names = "qup-core", "qup-config";
 835                                 status = "disabled";
 836                         };
 837
 838                         i2c1: i2c@884000 {
 839                                 compatible = "qcom,geni-i2c";
 840                                 reg = <0 0x00884000 0 0x4000>;
 841                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 842                                 clock-names = "se";
 843                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 844                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 845                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
 846                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
 847                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 status = "disabled";
 851                         };
 852
 853                         spi1: spi@884000 {
 854                                 compatible = "qcom,geni-spi";
 855                                 reg = <0 0x00884000 0 0x4000>;
 856                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 857                                 clock-names = "se";
 858                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 859                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 860                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 861                                 interconnect-names = "qup-core", "qup-config";
 862                                 #address-cells = <1>;
 863                                 #size-cells = <0>;
 864                                 status = "disabled";
 865                         };
 866
 867                         uart1: serial@884000 {
 868                                 compatible = "qcom,geni-uart";
 869                                 reg = <0 0x00884000 0 0x4000>;
 870                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 871                                 clock-names = "se";
 872                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 873                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 874                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 875                                 interconnect-names = "qup-core", "qup-config";
 876                                 status = "disabled";
 877                         };
 878
 879                         i2c2: i2c@888000 {
 880                                 compatible = "qcom,geni-i2c";
 881                                 reg = <0 0x00888000 0 0x4000>;
 882                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 883                                 clock-names = "se";
 884                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 885                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 886                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
 887                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
 888                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 889                                 #address-cells = <1>;
 890                                 #size-cells = <0>;
 891                                 status = "disabled";
 892                         };
 893
 894                         spi2: spi@888000 {
 895                                 compatible = "qcom,geni-spi";
 896                                 reg = <0 0x00888000 0 0x4000>;
 897                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 898                                 clock-names = "se";
 899                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 900                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 901                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 902                                 interconnect-names = "qup-core", "qup-config";
 903                                 #address-cells = <1>;
 904                                 #size-cells = <0>;
 905                                 status = "disabled";
 906                         };
 907
 908                         uart2: serial@888000 {
 909                                 compatible = "qcom,geni-uart";
 910                                 reg = <0 0x00888000 0 0x4000>;
 911                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 912                                 clock-names = "se";
 913                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 914                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 915                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 916                                 interconnect-names = "qup-core", "qup-config";
 917                                 status = "disabled";
 918                         };
 919
 920                         i2c3: i2c@88c000 {
 921                                 compatible = "qcom,geni-i2c";
 922                                 reg = <0 0x0088c000 0 0x4000>;
 923                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 924                                 clock-names = "se";
 925                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 926                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 927                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
 928                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
 929                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 status = "disabled";
 933                         };
 934
 935                         spi3: spi@88c000 {
 936                                 compatible = "qcom,geni-spi";
 937                                 reg = <0 0x0088c000 0 0x4000>;
 938                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 939                                 clock-names = "se";
 940                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 941                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 942                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 943                                 interconnect-names = "qup-core", "qup-config";
 944                                 #address-cells = <1>;
 945                                 #size-cells = <0>;
 946                                 status = "disabled";
 947                         };
 948
 949                         uart3: serial@88c000 {
 950                                 compatible = "qcom,geni-uart";
 951                                 reg = <0 0x0088c000 0 0x4000>;
 952                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 953                                 clock-names = "se";
 954                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 955                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 956                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 957                                 interconnect-names = "qup-core", "qup-config";
 958                                 status = "disabled";
 959                         };
 960
 961                         i2c4: i2c@890000 {
 962                                 compatible = "qcom,geni-i2c";
 963                                 reg = <0 0x00890000 0 0x4000>;
 964                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 965                                 clock-names = "se";
 966                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 967                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 968                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
 969                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
 970                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 status = "disabled";
 974                         };
 975
 976                         spi4: spi@890000 {
 977                                 compatible = "qcom,geni-spi";
 978                                 reg = <0 0x00890000 0 0x4000>;
 979                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 980                                 clock-names = "se";
 981                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 982                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 983                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 984                                 interconnect-names = "qup-core", "qup-config";
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 status = "disabled";
 988                         };
 989
 990                         uart4: serial@890000 {
 991                                 compatible = "qcom,geni-uart";
 992                                 reg = <0 0x00890000 0 0x4000>;
 993                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 994                                 clock-names = "se";
 995                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 996                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 997                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
 998                                 interconnect-names = "qup-core", "qup-config";
 999                                 status = "disabled";
1000                         };
1001
1002                         i2c5: i2c@894000 {
1003                                 compatible = "qcom,geni-i2c";
1004                                 reg = <0 0x00894000 0 0x4000>;
1005                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1006                                 clock-names = "se";
1007                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1008                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1009                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1010                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1011                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1012                                 #address-cells = <1>;
1013                                 #size-cells = <0>;
1014                                 status = "disabled";
1015                         };
1016
1017                         spi5: spi@894000 {
1018                                 compatible = "qcom,geni-spi";
1019                                 reg = <0 0x00894000 0 0x4000>;
1020                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1021                                 clock-names = "se";
1022                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1023                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1024                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1025                                 interconnect-names = "qup-core", "qup-config";
1026                                 #address-cells = <1>;
1027                                 #size-cells = <0>;
1028                                 status = "disabled";
1029                         };
1030
1031                         uart5: serial@894000 {
1032                                 compatible = "qcom,geni-uart";
1033                                 reg = <0 0x00894000 0 0x4000>;
1034                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1035                                 clock-names = "se";
1036                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1037                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1038                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1039                                 interconnect-names = "qup-core", "qup-config";
1040                                 status = "disabled";
1041                         };
1042
1043                         i2c6: i2c@898000 {
1044                                 compatible = "qcom,geni-i2c";
1045                                 reg = <0 0x00898000 0 0x4000>;
1046                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1047                                 clock-names = "se";
1048                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1049                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1050                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1051                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1052                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1053                                 #address-cells = <1>;
1054                                 #size-cells = <0>;
1055                                 status = "disabled";
1056                         };
1057
1058                         spi6: spi@898000 {
1059                                 compatible = "qcom,geni-spi";
1060                                 reg = <0 0x00898000 0 0x4000>;
1061                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1062                                 clock-names = "se";
1063                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1064                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1065                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1066                                 interconnect-names = "qup-core", "qup-config";
1067                                 #address-cells = <1>;
1068                                 #size-cells = <0>;
1069                                 status = "disabled";
1070                         };
1071
1072                         uart6: serial@898000 {
1073                                 compatible = "qcom,geni-uart";
1074                                 reg = <0 0x00898000 0 0x4000>;
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1076                                 clock-names = "se";
1077                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1078                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1079                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1080                                 interconnect-names = "qup-core", "qup-config";
1081                                 status = "disabled";
1082                         };
1083
1084                         i2c7: i2c@89c000 {
1085                                 compatible = "qcom,geni-i2c";
1086                                 reg = <0 0x0089c000 0 0x4000>;
1087                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1088                                 clock-names = "se";
1089                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1090                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1091                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1092                                                 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1093                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 status = "disabled";
1097                         };
1098
1099                         spi7: spi@89c000 {
1100                                 compatible = "qcom,geni-spi";
1101                                 reg = <0 0x0089c000 0 0x4000>;
1102                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1103                                 clock-names = "se";
1104                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1105                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1106                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1107                                 interconnect-names = "qup-core", "qup-config";
1108                                 #address-cells = <1>;
1109                                 #size-cells = <0>;
1110                                 status = "disabled";
1111                         };
1112
1113                         uart7: serial@89c000 {
1114                                 compatible = "qcom,geni-uart";
1115                                 reg = <0 0x0089c000 0 0x4000>;
1116                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1117                                 clock-names = "se";
1118                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1119                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1120                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1121                                 interconnect-names = "qup-core", "qup-config";
1122                                 status = "disabled";
1123                         };
1124                 };
1125
1126                 qupv3_id_1: geniqup@ac0000 {
1127                         compatible = "qcom,geni-se-qup";
1128                         reg = <0x0 0x00ac0000 0x0 0x6000>;
1129                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1130                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1131                         clock-names = "m-ahb", "s-ahb";
1132                         #address-cells = <2>;
1133                         #size-cells = <2>;
1134                         ranges;
1135                         iommus = <&apps_smmu 0x603 0>;
1136                         status = "disabled";
1137
1138                         i2c8: i2c@a80000 {
1139                                 compatible = "qcom,geni-i2c";
1140                                 reg = <0 0x00a80000 0 0x4000>;
1141                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1142                                 clock-names = "se";
1143                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1144                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1145                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1146                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1147                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1148                                 #address-cells = <1>;
1149                                 #size-cells = <0>;
1150                                 status = "disabled";
1151                         };
1152
1153                         spi8: spi@a80000 {
1154                                 compatible = "qcom,geni-spi";
1155                                 reg = <0 0x00a80000 0 0x4000>;
1156                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1157                                 clock-names = "se";
1158                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1159                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1160                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1161                                 interconnect-names = "qup-core", "qup-config";
1162                                 #address-cells = <1>;
1163                                 #size-cells = <0>;
1164                                 status = "disabled";
1165                         };
1166
1167                         uart8: serial@a80000 {
1168                                 compatible = "qcom,geni-uart";
1169                                 reg = <0 0x00a80000 0 0x4000>;
1170                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1171                                 clock-names = "se";
1172                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1173                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1174                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1175                                 interconnect-names = "qup-core", "qup-config";
1176                                 status = "disabled";
1177                         };
1178
1179                         i2c9: i2c@a84000 {
1180                                 compatible = "qcom,geni-i2c";
1181                                 reg = <0 0x00a84000 0 0x4000>;
1182                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1183                                 clock-names = "se";
1184                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1185                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1186                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1187                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1188                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1189                                 #address-cells = <1>;
1190                                 #size-cells = <0>;
1191                                 status = "disabled";
1192                         };
1193
1194                         spi9: spi@a84000 {
1195                                 compatible = "qcom,geni-spi";
1196                                 reg = <0 0x00a84000 0 0x4000>;
1197                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1198                                 clock-names = "se";
1199                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1200                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1201                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1202                                 interconnect-names = "qup-core", "qup-config";
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 status = "disabled";
1206                         };
1207
1208                         uart9: serial@a84000 {
1209                                 compatible = "qcom,geni-debug-uart";
1210                                 reg = <0 0x00a84000 0 0x4000>;
1211                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1212                                 clock-names = "se";
1213                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1214                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1215                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1216                                 interconnect-names = "qup-core", "qup-config";
1217                                 status = "disabled";
1218                         };
1219
1220                         i2c10: i2c@a88000 {
1221                                 compatible = "qcom,geni-i2c";
1222                                 reg = <0 0x00a88000 0 0x4000>;
1223                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1224                                 clock-names = "se";
1225                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1226                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1227                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1228                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1229                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1230                                 #address-cells = <1>;
1231                                 #size-cells = <0>;
1232                                 status = "disabled";
1233                         };
1234
1235                         spi10: spi@a88000 {
1236                                 compatible = "qcom,geni-spi";
1237                                 reg = <0 0x00a88000 0 0x4000>;
1238                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1239                                 clock-names = "se";
1240                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1241                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1242                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1243                                 interconnect-names = "qup-core", "qup-config";
1244                                 #address-cells = <1>;
1245                                 #size-cells = <0>;
1246                                 status = "disabled";
1247                         };
1248
1249                         uart10: serial@a88000 {
1250                                 compatible = "qcom,geni-uart";
1251                                 reg = <0 0x00a88000 0 0x4000>;
1252                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1253                                 clock-names = "se";
1254                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1255                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1256                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1257                                 interconnect-names = "qup-core", "qup-config";
1258                                 status = "disabled";
1259                         };
1260
1261                         i2c11: i2c@a8c000 {
1262                                 compatible = "qcom,geni-i2c";
1263                                 reg = <0 0x00a8c000 0 0x4000>;
1264                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1265                                 clock-names = "se";
1266                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1267                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1268                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1269                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1270                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1271                                 #address-cells = <1>;
1272                                 #size-cells = <0>;
1273                                 status = "disabled";
1274                         };
1275
1276                         spi11: spi@a8c000 {
1277                                 compatible = "qcom,geni-spi";
1278                                 reg = <0 0x00a8c000 0 0x4000>;
1279                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1280                                 clock-names = "se";
1281                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1282                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1283                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1284                                 interconnect-names = "qup-core", "qup-config";
1285                                 #address-cells = <1>;
1286                                 #size-cells = <0>;
1287                                 status = "disabled";
1288                         };
1289
1290                         uart11: serial@a8c000 {
1291                                 compatible = "qcom,geni-uart";
1292                                 reg = <0 0x00a8c000 0 0x4000>;
1293                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1294                                 clock-names = "se";
1295                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1296                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1297                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1298                                 interconnect-names = "qup-core", "qup-config";
1299                                 status = "disabled";
1300                         };
1301
1302                         i2c12: i2c@a90000 {
1303                                 compatible = "qcom,geni-i2c";
1304                                 reg = <0 0x00a90000 0 0x4000>;
1305                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1306                                 clock-names = "se";
1307                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1308                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1310                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1311                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 status = "disabled";
1315                         };
1316
1317                         spi12: spi@a90000 {
1318                                 compatible = "qcom,geni-spi";
1319                                 reg = <0 0x00a90000 0 0x4000>;
1320                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1321                                 clock-names = "se";
1322                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1323                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1324                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1325                                 interconnect-names = "qup-core", "qup-config";
1326                                 #address-cells = <1>;
1327                                 #size-cells = <0>;
1328                                 status = "disabled";
1329                         };
1330
1331                         uart12: serial@a90000 {
1332                                 compatible = "qcom,geni-uart";
1333                                 reg = <0 0x00a90000 0 0x4000>;
1334                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1335                                 clock-names = "se";
1336                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1337                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1338                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1339                                 interconnect-names = "qup-core", "qup-config";
1340                                 status = "disabled";
1341                         };
1342
1343                         i2c16: i2c@a94000 {
1344                                 compatible = "qcom,geni-i2c";
1345                                 reg = <0 0x00a94000 0 0x4000>;
1346                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1347                                 clock-names = "se";
1348                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1349                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1350                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1351                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1352                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1353                                 #address-cells = <1>;
1354                                 #size-cells = <0>;
1355                                 status = "disabled";
1356                         };
1357
1358                         spi16: spi@a94000 {
1359                                 compatible = "qcom,geni-spi";
1360                                 reg = <0 0x00a94000 0 0x4000>;
1361                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1362                                 clock-names = "se";
1363                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1364                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1365                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1366                                 interconnect-names = "qup-core", "qup-config";
1367                                 #address-cells = <1>;
1368                                 #size-cells = <0>;
1369                                 status = "disabled";
1370                         };
1371
1372                         uart16: serial@a94000 {
1373                                 compatible = "qcom,geni-uart";
1374                                 reg = <0 0x00a94000 0 0x4000>;
1375                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1376                                 clock-names = "se";
1377                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1378                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1379                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1380                                 interconnect-names = "qup-core", "qup-config";
1381                                 status = "disabled";
1382                         };
1383                 };
1384
1385                 qupv3_id_2: geniqup@cc0000 {
1386                         compatible = "qcom,geni-se-qup";
1387                         reg = <0x0 0x00cc0000 0x0 0x6000>;
1388                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1389                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1390                         clock-names = "m-ahb", "s-ahb";
1391                         #address-cells = <2>;
1392                         #size-cells = <2>;
1393                         ranges;
1394                         iommus = <&apps_smmu 0x7a3 0>;
1395                         status = "disabled";
1396
1397                         i2c17: i2c@c80000 {
1398                                 compatible = "qcom,geni-i2c";
1399                                 reg = <0 0x00c80000 0 0x4000>;
1400                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1401                                 clock-names = "se";
1402                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1403                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1404                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1405                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1406                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1407                                 #address-cells = <1>;
1408                                 #size-cells = <0>;
1409                                 status = "disabled";
1410                         };
1411
1412                         spi17: spi@c80000 {
1413                                 compatible = "qcom,geni-spi";
1414                                 reg = <0 0x00c80000 0 0x4000>;
1415                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1416                                 clock-names = "se";
1417                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1418                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1419                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1420                                 interconnect-names = "qup-core", "qup-config";
1421                                 #address-cells = <1>;
1422                                 #size-cells = <0>;
1423                                 status = "disabled";
1424                         };
1425
1426                         uart17: serial@c80000 {
1427                                 compatible = "qcom,geni-uart";
1428                                 reg = <0 0x00c80000 0 0x4000>;
1429                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1430                                 clock-names = "se";
1431                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1432                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1433                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1434                                 interconnect-names = "qup-core", "qup-config";
1435                                 status = "disabled";
1436                         };
1437
1438                         i2c18: i2c@c84000 {
1439                                 compatible = "qcom,geni-i2c";
1440                                 reg = <0 0x00c84000 0 0x4000>;
1441                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1442                                 clock-names = "se";
1443                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1444                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1445                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1446                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1447                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1448                                 #address-cells = <1>;
1449                                 #size-cells = <0>;
1450                                 status = "disabled";
1451                         };
1452
1453                         spi18: spi@c84000 {
1454                                 compatible = "qcom,geni-spi";
1455                                 reg = <0 0x00c84000 0 0x4000>;
1456                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1457                                 clock-names = "se";
1458                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1459                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1460                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1461                                 interconnect-names = "qup-core", "qup-config";
1462                                 #address-cells = <1>;
1463                                 #size-cells = <0>;
1464                                 status = "disabled";
1465                         };
1466
1467                         uart18: serial@c84000 {
1468                                 compatible = "qcom,geni-uart";
1469                                 reg = <0 0x00c84000 0 0x4000>;
1470                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1471                                 clock-names = "se";
1472                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1473                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1474                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1475                                 interconnect-names = "qup-core", "qup-config";
1476                                 status = "disabled";
1477                         };
1478
1479                         i2c19: i2c@c88000 {
1480                                 compatible = "qcom,geni-i2c";
1481                                 reg = <0 0x00c88000 0 0x4000>;
1482                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1483                                 clock-names = "se";
1484                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1485                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1486                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1487                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1488                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1489                                 #address-cells = <1>;
1490                                 #size-cells = <0>;
1491                                 status = "disabled";
1492                         };
1493
1494                         spi19: spi@c88000 {
1495                                 compatible = "qcom,geni-spi";
1496                                 reg = <0 0x00c88000 0 0x4000>;
1497                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1498                                 clock-names = "se";
1499                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1500                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1501                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1502                                 interconnect-names = "qup-core", "qup-config";
1503                                 #address-cells = <1>;
1504                                 #size-cells = <0>;
1505                                 status = "disabled";
1506                         };
1507
1508                         uart19: serial@c88000 {
1509                                 compatible = "qcom,geni-uart";
1510                                 reg = <0 0x00c88000 0 0x4000>;
1511                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1512                                 clock-names = "se";
1513                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1514                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1515                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1516                                 interconnect-names = "qup-core", "qup-config";
1517                                 status = "disabled";
1518                         };
1519
1520                         i2c13: i2c@c8c000 {
1521                                 compatible = "qcom,geni-i2c";
1522                                 reg = <0 0x00c8c000 0 0x4000>;
1523                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1524                                 clock-names = "se";
1525                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1526                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1527                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1528                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1529                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1530                                 #address-cells = <1>;
1531                                 #size-cells = <0>;
1532                                 status = "disabled";
1533                         };
1534
1535                         spi13: spi@c8c000 {
1536                                 compatible = "qcom,geni-spi";
1537                                 reg = <0 0x00c8c000 0 0x4000>;
1538                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1539                                 clock-names = "se";
1540                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1541                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1542                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1543                                 interconnect-names = "qup-core", "qup-config";
1544                                 #address-cells = <1>;
1545                                 #size-cells = <0>;
1546                                 status = "disabled";
1547                         };
1548
1549                         uart13: serial@c8c000 {
1550                                 compatible = "qcom,geni-uart";
1551                                 reg = <0 0x00c8c000 0 0x4000>;
1552                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1553                                 clock-names = "se";
1554                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1555                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1556                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1557                                 interconnect-names = "qup-core", "qup-config";
1558                                 status = "disabled";
1559                         };
1560
1561                         i2c14: i2c@c90000 {
1562                                 compatible = "qcom,geni-i2c";
1563                                 reg = <0 0x00c90000 0 0x4000>;
1564                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1565                                 clock-names = "se";
1566                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1567                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1568                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1569                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1570                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1571                                 #address-cells = <1>;
1572                                 #size-cells = <0>;
1573                                 status = "disabled";
1574                         };
1575
1576                         spi14: spi@c90000 {
1577                                 compatible = "qcom,geni-spi";
1578                                 reg = <0 0x00c90000 0 0x4000>;
1579                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1580                                 clock-names = "se";
1581                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1582                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1583                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1584                                 interconnect-names = "qup-core", "qup-config";
1585                                 #address-cells = <1>;
1586                                 #size-cells = <0>;
1587                                 status = "disabled";
1588                         };
1589
1590                         uart14: serial@c90000 {
1591                                 compatible = "qcom,geni-uart";
1592                                 reg = <0 0x00c90000 0 0x4000>;
1593                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1594                                 clock-names = "se";
1595                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1596                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1597                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1598                                 interconnect-names = "qup-core", "qup-config";
1599                                 status = "disabled";
1600                         };
1601
1602                         i2c15: i2c@c94000 {
1603                                 compatible = "qcom,geni-i2c";
1604                                 reg = <0 0x00c94000 0 0x4000>;
1605                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1606                                 clock-names = "se";
1607                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1608                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1609                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1610                                                 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1611                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 status = "disabled";
1615                         };
1616
1617                         spi15: spi@c94000 {
1618                                 compatible = "qcom,geni-spi";
1619                                 reg = <0 0x00c94000 0 0x4000>;
1620                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1621                                 clock-names = "se";
1622                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1623                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1624                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1625                                 interconnect-names = "qup-core", "qup-config";
1626                                 #address-cells = <1>;
1627                                 #size-cells = <0>;
1628                                 status = "disabled";
1629                         };
1630
1631                         uart15: serial@c94000 {
1632                                 compatible = "qcom,geni-uart";
1633                                 reg = <0 0x00c94000 0 0x4000>;
1634                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1635                                 clock-names = "se";
1636                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1637                                 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1638                                                 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1639                                 interconnect-names = "qup-core", "qup-config";
1640                                 status = "disabled";
1641                         };
1642                 };
1643
1644                 config_noc: interconnect@1500000 {
1645                         compatible = "qcom,sc8180x-config-noc";
1646                         reg = <0 0x01500000 0 0x7400>;
1647                         #interconnect-cells = <2>;
1648                         qcom,bcm-voters = <&apps_bcm_voter>;
1649                 };
1650
1651                 system_noc: interconnect@1620000 {
1652                         compatible = "qcom,sc8180x-system-noc";
1653                         reg = <0 0x01620000 0 0x19400>;
1654                         #interconnect-cells = <2>;
1655                         qcom,bcm-voters = <&apps_bcm_voter>;
1656                 };
1657
1658                 aggre1_noc: interconnect@16e0000 {
1659                         compatible = "qcom,sc8180x-aggre1-noc";
1660                         reg = <0 0x016e0000 0 0xd080>;
1661                         #interconnect-cells = <2>;
1662                         qcom,bcm-voters = <&apps_bcm_voter>;
1663                 };
1664
1665                 aggre2_noc: interconnect@1700000 {
1666                         compatible = "qcom,sc8180x-aggre2-noc";
1667                         reg = <0 0x01700000 0 0x20000>;
1668                         #interconnect-cells = <2>;
1669                         qcom,bcm-voters = <&apps_bcm_voter>;
1670                 };
1671
1672                 compute_noc: interconnect@1720000 {
1673                         compatible = "qcom,sc8180x-compute-noc";
1674                         reg = <0 0x01720000 0 0x7000>;
1675                         #interconnect-cells = <2>;
1676                         qcom,bcm-voters = <&apps_bcm_voter>;
1677                 };
1678
1679                 mmss_noc: interconnect@1740000 {
1680                         compatible = "qcom,sc8180x-mmss-noc";
1681                         reg = <0 0x01740000 0 0x1c100>;
1682                         #interconnect-cells = <2>;
1683                         qcom,bcm-voters = <&apps_bcm_voter>;
1684                 };
1685
1686                 pcie0: pci@1c00000 {
1687                         compatible = "qcom,pcie-sc8180x";
1688                         reg = <0 0x01c00000 0 0x3000>,
1689                               <0 0x60000000 0 0xf1d>,
1690                               <0 0x60000f20 0 0xa8>,
1691                               <0 0x60001000 0 0x1000>,
1692                               <0 0x60100000 0 0x100000>;
1693                         reg-names = "parf",
1694                                     "dbi",
1695                                     "elbi",
1696                                     "atu",
1697                                     "config";
1698                         device_type = "pci";
1699                         linux,pci-domain = <0>;
1700                         bus-range = <0x00 0xff>;
1701                         num-lanes = <2>;
1702
1703                         #address-cells = <3>;
1704                         #size-cells = <2>;
1705
1706                         ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1707                                  <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1708
1709                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1710                         interrupt-names = "msi";
1711                         #interrupt-cells = <1>;
1712                         interrupt-map-mask = <0 0 0 0x7>;
1713                         interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1714                                         <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1715                                         <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1716                                         <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1717
1718                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1719                                  <&gcc GCC_PCIE_0_AUX_CLK>,
1720                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1721                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1722                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1723                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1724                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1725                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1726                         clock-names = "pipe",
1727                                       "aux",
1728                                       "cfg",
1729                                       "bus_master",
1730                                       "bus_slave",
1731                                       "slave_q2a",
1732                                       "ref",
1733                                       "tbu";
1734
1735                         assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1736                         assigned-clock-rates = <19200000>;
1737
1738                         iommus = <&apps_smmu 0x1d80 0x7f>;
1739                         iommu-map = <0x0   &apps_smmu 0x1d80 0x1>,
1740                                     <0x100 &apps_smmu 0x1d81 0x1>;
1741
1742                         resets = <&gcc GCC_PCIE_0_BCR>;
1743                         reset-names = "pci";
1744
1745                         power-domains = <&gcc PCIE_0_GDSC>;
1746
1747                         interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1748                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1749                         interconnect-names = "pcie-mem", "cpu-pcie";
1750
1751                         phys = <&pcie0_lane>;
1752                         phy-names = "pciephy";
1753
1754                         status = "disabled";
1755                 };
1756
1757                 pcie0_phy: phy-wrapper@1c06000 {
1758                         compatible = "qcom,sc8180x-qmp-pcie-phy";
1759                         reg = <0 0x1c06000 0 0x1c0>;
1760                         #address-cells = <2>;
1761                         #size-cells = <2>;
1762                         ranges;
1763                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1764                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1765                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
1766                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1767                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1768
1769                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1770                         reset-names = "phy";
1771
1772                         assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1773                         assigned-clock-rates = <100000000>;
1774
1775                         status = "disabled";
1776
1777                         pcie0_lane: phy@1c06200 {
1778                                 reg = <0 0x1c06200 0 0x170>, /* tx0 */
1779                                       <0 0x1c06400 0 0x200>, /* rx0 */
1780                                       <0 0x1c06a00 0 0x1f0>, /* pcs */
1781                                       <0 0x1c06600 0 0x170>, /* tx1 */
1782                                       <0 0x1c06800 0 0x200>, /* rx1 */
1783                                       <0 0x1c06e00 0 0xf4>; /* pcs_com */
1784                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1785                                 clock-names = "pipe0";
1786
1787                                 #clock-cells = <0>;
1788                                 clock-output-names = "pcie_0_pipe_clk";
1789                                 #phy-cells = <0>;
1790                         };
1791                 };
1792
1793                 pcie3: pci@1c08000 {
1794                         compatible = "qcom,pcie-sc8180x";
1795                         reg = <0 0x01c08000 0 0x3000>,
1796                               <0 0x40000000 0 0xf1d>,
1797                               <0 0x40000f20 0 0xa8>,
1798                               <0 0x40001000 0 0x1000>,
1799                               <0 0x40100000 0 0x100000>;
1800                         reg-names = "parf",
1801                                     "dbi",
1802                                     "elbi",
1803                                     "atu",
1804                                     "config";
1805                         device_type = "pci";
1806                         linux,pci-domain = <3>;
1807                         bus-range = <0x00 0xff>;
1808                         num-lanes = <2>;
1809
1810                         #address-cells = <3>;
1811                         #size-cells = <2>;
1812
1813                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1814                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1815
1816                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1817                         interrupt-names = "msi";
1818                         #interrupt-cells = <1>;
1819                         interrupt-map-mask = <0 0 0 0x7>;
1820                         interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1821                                         <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1822                                         <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1823                                         <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1824
1825                         clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1826                                  <&gcc GCC_PCIE_3_AUX_CLK>,
1827                                  <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1828                                  <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1829                                  <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1830                                  <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1831                                  <&gcc GCC_PCIE_3_CLKREF_CLK>,
1832                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1833                         clock-names = "pipe",
1834                                       "aux",
1835                                       "cfg",
1836                                       "bus_master",
1837                                       "bus_slave",
1838                                       "slave_q2a",
1839                                       "ref",
1840                                       "tbu";
1841
1842                         assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1843                         assigned-clock-rates = <19200000>;
1844
1845                         iommus = <&apps_smmu 0x1e00 0x7f>;
1846                         iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
1847                                     <0x100 &apps_smmu 0x1e01 0x1>;
1848
1849                         resets = <&gcc GCC_PCIE_3_BCR>;
1850                         reset-names = "pci";
1851
1852                         power-domains = <&gcc PCIE_3_GDSC>;
1853
1854                         interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1855                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1856                         interconnect-names = "pcie-mem", "cpu-pcie";
1857
1858                         phys = <&pcie3_lane>;
1859                         phy-names = "pciephy";
1860
1861                         status = "disabled";
1862                 };
1863
1864                 pcie3_phy: phy-wrapper@1c0c000 {
1865                         compatible = "qcom,sc8180x-qmp-pcie-phy";
1866                         reg = <0 0x1c0c000 0 0x1c0>;
1867                         #address-cells = <2>;
1868                         #size-cells = <2>;
1869                         ranges;
1870                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1871                                  <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1872                                  <&gcc GCC_PCIE_3_CLKREF_CLK>,
1873                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1874                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1875
1876                         resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1877                         reset-names = "phy";
1878
1879                         assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1880                         assigned-clock-rates = <100000000>;
1881
1882                         status = "disabled";
1883
1884                         pcie3_lane: phy@1c0c200 {
1885                                 reg = <0 0x1c0c200 0 0x170>, /* tx0 */
1886                                       <0 0x1c0c400 0 0x200>, /* rx0 */
1887                                       <0 0x1c0ca00 0 0x1f0>, /* pcs */
1888                                       <0 0x1c0c600 0 0x170>, /* tx1 */
1889                                       <0 0x1c0c800 0 0x200>, /* rx1 */
1890                                       <0 0x1c0ce00 0 0xf4>; /* pcs_com */
1891                                 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
1892                                 clock-names = "pipe0";
1893
1894                                 #clock-cells = <0>;
1895                                 clock-output-names = "pcie_3_pipe_clk";
1896                                 #phy-cells = <0>;
1897                         };
1898                 };
1899
1900                 pcie1: pci@1c10000 {
1901                         compatible = "qcom,pcie-sc8180x";
1902                         reg = <0 0x01c10000 0 0x3000>,
1903                               <0 0x68000000 0 0xf1d>,
1904                               <0 0x68000f20 0 0xa8>,
1905                               <0 0x68001000 0 0x1000>,
1906                               <0 0x68100000 0 0x100000>;
1907                         reg-names = "parf",
1908                                     "dbi",
1909                                     "elbi",
1910                                     "atu",
1911                                     "config";
1912                         device_type = "pci";
1913                         linux,pci-domain = <1>;
1914                         bus-range = <0x00 0xff>;
1915                         num-lanes = <2>;
1916
1917                         #address-cells = <3>;
1918                         #size-cells = <2>;
1919
1920                         ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1921                                  <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1922
1923                         interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
1924                         interrupt-names = "msi";
1925                         #interrupt-cells = <1>;
1926                         interrupt-map-mask = <0 0 0 0x7>;
1927                         interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1928                                         <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1929                                         <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1930                                         <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1931
1932                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1933                                  <&gcc GCC_PCIE_1_AUX_CLK>,
1934                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1935                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1936                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1937                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1938                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1939                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1940                         clock-names = "pipe",
1941                                       "aux",
1942                                       "cfg",
1943                                       "bus_master",
1944                                       "bus_slave",
1945                                       "slave_q2a",
1946                                       "ref",
1947                                       "tbu";
1948
1949                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1950                         assigned-clock-rates = <19200000>;
1951
1952                         iommus = <&apps_smmu 0x1c80 0x7f>;
1953                         iommu-map = <0x0   &apps_smmu 0x1c80 0x1>,
1954                                     <0x100 &apps_smmu 0x1c81 0x1>;
1955
1956                         resets = <&gcc GCC_PCIE_1_BCR>;
1957                         reset-names = "pci";
1958
1959                         power-domains = <&gcc PCIE_1_GDSC>;
1960
1961                         interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1962                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1963                         interconnect-names = "pcie-mem", "cpu-pcie";
1964
1965                         phys = <&pcie1_lane>;
1966                         phy-names = "pciephy";
1967
1968                         status = "disabled";
1969                 };
1970
1971                 pcie1_phy: phy-wrapper@1c16000 {
1972                         compatible = "qcom,sc8180x-qmp-pcie-phy";
1973                         reg = <0 0x1c16000 0 0x1c0>;
1974                         #address-cells = <2>;
1975                         #size-cells = <2>;
1976                         ranges;
1977                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1978                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1979                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
1980                                  <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1981                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
1982
1983                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1984                         reset-names = "phy";
1985
1986                         assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1987                         assigned-clock-rates = <100000000>;
1988
1989                         status = "disabled";
1990
1991                         pcie1_lane: phy@1c0e200 {
1992                                 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1993                                       <0 0x1c16400 0 0x200>, /* rx0 */
1994                                       <0 0x1c16a00 0 0x1f0>, /* pcs */
1995                                       <0 0x1c16600 0 0x170>, /* tx1 */
1996                                       <0 0x1c16800 0 0x200>, /* rx1 */
1997                                       <0 0x1c16e00 0 0xf4>; /* pcs_com */
1998                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1999                                 clock-names = "pipe0";
2000                                 #clock-cells = <0>;
2001                                 clock-output-names = "pcie_1_pipe_clk";
2002
2003                                 #phy-cells = <0>;
2004                         };
2005                 };
2006
2007                 pcie2: pci@1c18000 {
2008                         compatible = "qcom,pcie-sc8180x";
2009                         reg = <0 0x01c18000 0 0x3000>,
2010                               <0 0x70000000 0 0xf1d>,
2011                               <0 0x70000f20 0 0xa8>,
2012                               <0 0x70001000 0 0x1000>,
2013                               <0 0x70100000 0 0x100000>;
2014                         reg-names = "parf",
2015                                     "dbi",
2016                                     "elbi",
2017                                     "atu",
2018                                     "config";
2019                         device_type = "pci";
2020                         linux,pci-domain = <2>;
2021                         bus-range = <0x00 0xff>;
2022                         num-lanes = <4>;
2023
2024                         #address-cells = <3>;
2025                         #size-cells = <2>;
2026
2027                         ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2028                                  <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2029
2030                         interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>;
2031                         interrupt-names = "msi";
2032                         #interrupt-cells = <1>;
2033                         interrupt-map-mask = <0 0 0 0x7>;
2034                         interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2035                                         <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2036                                         <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2037                                         <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2038
2039                         clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2040                                  <&gcc GCC_PCIE_2_AUX_CLK>,
2041                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2042                                  <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2043                                  <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2044                                  <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2045                                  <&gcc GCC_PCIE_2_CLKREF_CLK>,
2046                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2047                         clock-names = "pipe",
2048                                       "aux",
2049                                       "cfg",
2050                                       "bus_master",
2051                                       "bus_slave",
2052                                       "slave_q2a",
2053                                       "ref",
2054                                       "tbu";
2055
2056                         assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2057                         assigned-clock-rates = <19200000>;
2058
2059                         iommus = <&apps_smmu 0x1d00 0x7f>;
2060                         iommu-map = <0x0   &apps_smmu 0x1d00 0x1>,
2061                                     <0x100 &apps_smmu 0x1d01 0x1>;
2062
2063                         resets = <&gcc GCC_PCIE_2_BCR>;
2064                         reset-names = "pci";
2065
2066                         power-domains = <&gcc PCIE_2_GDSC>;
2067
2068                         interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2069                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2070                         interconnect-names = "pcie-mem", "cpu-pcie";
2071
2072                         phys = <&pcie2_lane>;
2073                         phy-names = "pciephy";
2074
2075                         status = "disabled";
2076                 };
2077
2078                 pcie2_phy: phy-wrapper@1c1c000 {
2079                         compatible = "qcom,sc8180x-qmp-pcie-phy";
2080                         reg = <0 0x1c1c000 0 0x1c0>;
2081                         #address-cells = <2>;
2082                         #size-cells = <2>;
2083                         ranges;
2084                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2085                                  <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2086                                  <&gcc GCC_PCIE_2_CLKREF_CLK>,
2087                                  <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2088                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2089
2090                         resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2091                         reset-names = "phy";
2092
2093                         assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2094                         assigned-clock-rates = <100000000>;
2095
2096                         status = "disabled";
2097
2098                         pcie2_lane: phy@1c0e200 {
2099                                 reg = <0 0x1c1c200 0 0x170>, /* tx0 */
2100                                       <0 0x1c1c400 0 0x200>, /* rx0 */
2101                                       <0 0x1c1ca00 0 0x1f0>, /* pcs */
2102                                       <0 0x1c1c600 0 0x170>, /* tx1 */
2103                                       <0 0x1c1c800 0 0x200>, /* rx1 */
2104                                       <0 0x1c1ce00 0 0xf4>; /* pcs_com */
2105                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2106                                 clock-names = "pipe0";
2107
2108                                 #clock-cells = <0>;
2109                                 clock-output-names = "pcie_2_pipe_clk";
2110
2111                                 #phy-cells = <0>;
2112                         };
2113                 };
2114
2115                 ufs_mem_hc: ufshc@1d84000 {
2116                         compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2117                                      "jedec,ufs-2.0";
2118                         reg = <0 0x01d84000 0 0x2500>;
2119                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2120                         phys = <&ufs_mem_phy_lanes>;
2121                         phy-names = "ufsphy";
2122                         lanes-per-direction = <2>;
2123                         #reset-cells = <1>;
2124                         resets = <&gcc GCC_UFS_PHY_BCR>;
2125                         reset-names = "rst";
2126
2127                         iommus = <&apps_smmu 0x300 0>;
2128
2129                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2130                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2131                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
2132                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2133                                  <&rpmhcc RPMH_CXO_CLK>,
2134                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2135                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2136                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2137                         clock-names = "core_clk",
2138                                       "bus_aggr_clk",
2139                                       "iface_clk",
2140                                       "core_clk_unipro",
2141                                       "ref_clk",
2142                                       "tx_lane0_sync_clk",
2143                                       "rx_lane0_sync_clk",
2144                                       "rx_lane1_sync_clk";
2145                         freq-table-hz = <37500000 300000000>,
2146                                         <0 0>,
2147                                         <0 0>,
2148                                         <37500000 300000000>,
2149                                         <0 0>,
2150                                         <0 0>,
2151                                         <0 0>,
2152                                         <0 0>;
2153
2154                         status = "disabled";
2155                 };
2156
2157                 ufs_mem_phy: phy-wrapper@1d87000 {
2158                         compatible = "qcom,sc8180x-qmp-ufs-phy";
2159                         reg = <0 0x01d87000 0 0x1c0>;
2160                         #address-cells = <2>;
2161                         #size-cells = <2>;
2162                         ranges;
2163                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2164                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2165                         clock-names = "ref",
2166                                       "ref_aux";
2167
2168                         resets = <&ufs_mem_hc 0>;
2169                         reset-names = "ufsphy";
2170                         status = "disabled";
2171
2172                         ufs_mem_phy_lanes: phy@1d87400 {
2173                                 reg = <0 0x01d87400 0 0x108>,
2174                                       <0 0x01d87600 0 0x1e0>,
2175                                       <0 0x01d87c00 0 0x1dc>,
2176                                       <0 0x01d87800 0 0x108>,
2177                                       <0 0x01d87a00 0 0x1e0>;
2178                                 #phy-cells = <0>;
2179                         };
2180                 };
2181
2182                 ipa_virt: interconnect@1e00000 {
2183                         compatible = "qcom,sc8180x-ipa-virt";
2184                         reg = <0 0x01e00000 0 0x1000>;
2185                         #interconnect-cells = <2>;
2186                         qcom,bcm-voters = <&apps_bcm_voter>;
2187                 };
2188
2189                 tcsr_mutex: hwlock@1f40000 {
2190                         compatible = "qcom,tcsr-mutex";
2191                         reg = <0x0 0x01f40000 0x0 0x40000>;
2192                         #hwlock-cells = <1>;
2193                 };
2194
2195                 gpu: gpu@2c00000 {
2196                         compatible = "qcom,adreno-680.1", "qcom,adreno";
2197                         #stream-id-cells = <16>;
2198
2199                         reg = <0 0x02c00000 0 0x40000>;
2200                         reg-names = "kgsl_3d0_reg_memory";
2201
2202                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2203
2204                         iommus = <&adreno_smmu 0 0xc01>;
2205
2206                         operating-points-v2 = <&gpu_opp_table>;
2207
2208                         interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2209                         interconnect-names = "gfx-mem";
2210
2211                         qcom,gmu = <&gmu>;
2212                         status = "disabled";
2213
2214                         gpu_opp_table: opp-table {
2215                                 compatible = "operating-points-v2";
2216
2217                                 opp-514000000 {
2218                                         opp-hz = /bits/ 64 <514000000>;
2219                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2220                                 };
2221
2222                                 opp-500000000 {
2223                                         opp-hz = /bits/ 64 <500000000>;
2224                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2225                                 };
2226
2227                                 opp-461000000 {
2228                                         opp-hz = /bits/ 64 <461000000>;
2229                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2230                                 };
2231
2232                                 opp-405000000 {
2233                                         opp-hz = /bits/ 64 <405000000>;
2234                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2235                                 };
2236
2237                                 opp-315000000 {
2238                                         opp-hz = /bits/ 64 <315000000>;
2239                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2240                                 };
2241
2242                                 opp-256000000 {
2243                                         opp-hz = /bits/ 64 <256000000>;
2244                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2245                                 };
2246
2247                                 opp-177000000 {
2248                                         opp-hz = /bits/ 64 <177000000>;
2249                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2250                                 };
2251                         };
2252                 };
2253
2254                 gmu: gmu@2c6a000 {
2255                         compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2256
2257                         reg = <0 0x02c6a000 0 0x30000>,
2258                               <0 0x0b290000 0 0x10000>,
2259                               <0 0x0b490000 0 0x10000>;
2260                         reg-names = "gmu",
2261                                     "gmu_pdc",
2262                                     "gmu_pdc_seq";
2263
2264                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2265                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2266                         interrupt-names = "hfi", "gmu";
2267
2268                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2269                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2270                                  <&gpucc GPU_CC_CXO_CLK>,
2271                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2272                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2273                         clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2274
2275                         power-domains = <&gpucc GPU_CX_GDSC>,
2276                                         <&gpucc GPU_GX_GDSC>;
2277                         power-domain-names = "cx", "gx";
2278
2279                         iommus = <&adreno_smmu 5 0xc00>;
2280
2281                         operating-points-v2 = <&gmu_opp_table>;
2282
2283                         gmu_opp_table: opp-table {
2284                                 compatible = "operating-points-v2";
2285
2286                                 opp-200000000 {
2287                                         opp-hz = /bits/ 64 <200000000>;
2288                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2289                                 };
2290
2291                                 opp-500000000 {
2292                                         opp-hz = /bits/ 64 <500000000>;
2293                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2294                                 };
2295                         };
2296                 };
2297
2298                 gpucc: clock-controller@2c90000 {
2299                         compatible = "qcom,sc8180x-gpucc";
2300                         reg = <0 0x02c90000 0 0x9000>;
2301                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2302                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2303                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2304                         clock-names = "bi_tcxo",
2305                                       "gcc_gpu_gpll0_clk_src",
2306                                       "gcc_gpu_gpll0_div_clk_src";
2307                         #clock-cells = <1>;
2308                         #reset-cells = <1>;
2309                         #power-domain-cells = <1>;
2310                 };
2311
2312                 adreno_smmu: iommu@2ca0000 {
2313                         compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2314                                      "qcom,smmu-500", "arm,mmu-500";
2315                         reg = <0 0x02ca0000 0 0x10000>;
2316                         #iommu-cells = <2>;
2317                         #global-interrupts = <1>;
2318                         interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2319                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2320                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2321                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2322                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2323                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2324                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2325                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2326                                      <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2327                         clocks = <&gpucc GPU_CC_AHB_CLK>,
2328                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2329                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2330                         clock-names = "ahb", "bus", "iface";
2331
2332                         power-domains = <&gpucc GPU_CX_GDSC>;
2333                 };
2334
2335                 tlmm: pinctrl@3100000 {
2336                         compatible = "qcom,sc8180x-tlmm";
2337                         reg = <0 0x03100000 0 0x300000>,
2338                               <0 0x03500000 0 0x700000>,
2339                               <0 0x03d00000 0 0x300000>;
2340                         reg-names = "west", "east", "south";
2341                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2342                         gpio-controller;
2343                         #gpio-cells = <2>;
2344                         interrupt-controller;
2345                         #interrupt-cells = <2>;
2346                         gpio-ranges = <&tlmm 0 0 191>;
2347                         wakeup-parent = <&pdc>;
2348                 };
2349
2350                 remoteproc_mpss: remoteproc@4080000 {
2351                         compatible = "qcom,sc8180x-mpss-pas";
2352                         reg = <0x0 0x04080000 0x0 0x4040>;
2353
2354                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2355                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2356                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2357                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2358                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2359                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2360                         interrupt-names = "wdog", "fatal", "ready", "handover",
2361                                           "stop-ack", "shutdown-ack";
2362
2363                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2364                         clock-names = "xo";
2365
2366                         power-domains = <&rpmhpd SC8180X_CX>,
2367                                         <&rpmhpd SC8180X_MSS>;
2368                         power-domain-names = "cx", "mss";
2369
2370                         qcom,qmp = <&aoss_qmp>;
2371
2372                         qcom,smem-states = <&modem_smp2p_out 0>;
2373                         qcom,smem-state-names = "stop";
2374
2375                         glink-edge {
2376                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2377                                 label = "modem";
2378                                 qcom,remote-pid = <1>;
2379                                 mboxes = <&apss_shared 12>;
2380                         };
2381                 };
2382
2383                 remoteproc_cdsp: remoteproc@8300000 {
2384                         compatible = "qcom,sc8180x-cdsp-pas";
2385                         reg = <0x0 0x08300000 0x0 0x4040>;
2386
2387                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2388                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2389                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2390                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2391                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2392                         interrupt-names = "wdog", "fatal", "ready",
2393                                           "handover", "stop-ack";
2394
2395                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2396                         clock-names = "xo";
2397
2398                         power-domains = <&rpmhpd SC8180X_CX>;
2399                         power-domain-names = "cx";
2400
2401                         qcom,qmp = <&aoss_qmp>;
2402
2403                         qcom,smem-states = <&cdsp_smp2p_out 0>;
2404                         qcom,smem-state-names = "stop";
2405
2406                         status = "disabled";
2407
2408                         glink-edge {
2409                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2410                                 label = "cdsp";
2411                                 qcom,remote-pid = <5>;
2412                                 mboxes = <&apss_shared 4>;
2413                         };
2414                 };
2415
2416                 usb_prim_hsphy: phy@88e2000 {
2417                         compatible = "qcom,sc8180x-usb-hs-phy",
2418                                      "qcom,usb-snps-hs-7nm-phy";
2419                         reg = <0 0x088e2000 0 0x400>;
2420                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2421                         clock-names = "ref";
2422                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2423
2424                         #phy-cells = <0>;
2425
2426                         status = "disabled";
2427                 };
2428
2429                 usb_sec_hsphy: phy@88e3000 {
2430                         compatible = "qcom,sc8180x-usb-hs-phy",
2431                                      "qcom,usb-snps-hs-7nm-phy";
2432                         reg = <0 0x088e3000 0 0x400>;
2433                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2434                         clock-names = "ref";
2435                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2436
2437                         #phy-cells = <0>;
2438
2439                         status = "disabled";
2440                 };
2441
2442                 usb_prim_qmpphy: phy@88e9000 {
2443                         compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2444                         reg = <0 0x088e9000 0 0x18c>,
2445                               <0 0x088e8000 0 0x38>,
2446                               <0 0x088ea000 0 0x40>;
2447                         reg-names = "reg-base", "dp_com";
2448                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2449                                  <&rpmhcc RPMH_CXO_CLK>,
2450                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2451                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2452                         clock-names = "aux",
2453                                       "ref_clk_src",
2454                                       "ref",
2455                                       "com_aux";
2456                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2457                                  <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2458                         reset-names = "phy", "common";
2459
2460                         #clock-cells = <1>;
2461                         #address-cells = <2>;
2462                         #size-cells = <2>;
2463                         ranges;
2464
2465                         status = "disabled";
2466
2467                         usb_prim_ssphy: usb3-phy@88e9200 {
2468                                 reg = <0 0x088e9200 0 0x200>,
2469                                       <0 0x088e9400 0 0x200>,
2470                                       <0 0x088e9c00 0 0x218>,
2471                                       <0 0x088e9600 0 0x200>,
2472                                       <0 0x088e9800 0 0x200>,
2473                                       <0 0x088e9a00 0 0x100>;
2474                                 #phy-cells = <0>;
2475                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2476                                 clock-names = "pipe0";
2477                                 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2478                         };
2479
2480                         usb_prim_dpphy: dp-phy@88ea200 {
2481                                 reg = <0 0x088ea200 0 0x200>,
2482                                       <0 0x088ea400 0 0x200>,
2483                                       <0 0x088eaa00 0 0x200>,
2484                                       <0 0x088ea600 0 0x200>,
2485                                       <0 0x088ea800 0 0x200>;
2486                                 #clock-cells = <1>;
2487                                 #phy-cells = <0>;
2488                         };
2489                 };
2490
2491                 usb_sec_qmpphy: phy@88ee000 {
2492                         compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2493                         reg = <0 0x088ee000 0 0x18c>,
2494                               <0 0x088ed000 0 0x10>,
2495                               <0 0x088ef000 0 0x40>;
2496                         reg-names = "reg-base", "dp_com";
2497                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2498                                  <&rpmhcc RPMH_CXO_CLK>,
2499                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2500                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2501                         clock-names = "aux",
2502                                       "ref_clk_src",
2503                                       "ref",
2504                                       "com_aux";
2505                         resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2506                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
2507                         reset-names = "phy", "common";
2508
2509                         #clock-cells = <1>;
2510                         #address-cells = <2>;
2511                         #size-cells = <2>;
2512                         ranges;
2513
2514                         status = "disabled";
2515
2516                         usb_sec_ssphy: usb3-phy@88e9200 {
2517                                 reg = <0 0x088ee200 0 0x200>,
2518                                       <0 0x088ee400 0 0x200>,
2519                                       <0 0x088eec00 0 0x218>,
2520                                       <0 0x088ee600 0 0x200>,
2521                                       <0 0x088ee800 0 0x200>,
2522                                       <0 0x088eea00 0 0x100>;
2523                                 #phy-cells = <0>;
2524                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2525                                 clock-names = "pipe0";
2526                                 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2527                         };
2528
2529                         usb_sec_dpphy: dp-phy@88ef200 {
2530                                 reg = <0 0x088ef200 0 0x200>,
2531                                       <0 0x088ef400 0 0x200>,
2532                                       <0 0x088efa00 0 0x200>,
2533                                       <0 0x088ef600 0 0x200>,
2534                                       <0 0x088ef800 0 0x200>;
2535                                 #clock-cells = <1>;
2536                                 #phy-cells = <0>;
2537                                 clock-output-names = "qmp_dptx1_phy_pll_link_clk",
2538                                                      "qmp_dptx1_phy_pll_vco_div_clk";
2539                         };
2540                 };
2541
2542                 system-cache-controller@9200000 {
2543                         compatible = "qcom,sc8180x-llcc";
2544                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2545                         reg-names = "llcc_base", "llcc_broadcast_base";
2546                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2547                 };
2548
2549                 gem_noc: interconnect@9680000 {
2550                         compatible = "qcom,sc8180x-gem-noc";
2551                         reg = <0 0x09680000 0 0x58200>;
2552                         #interconnect-cells = <2>;
2553                         qcom,bcm-voters = <&apps_bcm_voter>;
2554                 };
2555
2556                 usb_prim: usb@a6f8800 {
2557                         compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2558                         reg = <0 0x0a6f8800 0 0x400>;
2559                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2560                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2561                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2562                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2563                         interrupt-names = "hs_phy_irq",
2564                                           "ss_phy_irq",
2565                                           "dm_hs_phy_irq",
2566                                           "dp_hs_phy_irq";
2567
2568                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2569                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2570                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2571                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2572                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2573                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2574                         clock-names = "cfg_noc",
2575                                       "core",
2576                                       "iface",
2577                                       "mock_utmi",
2578                                       "sleep",
2579                                       "xo";
2580                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2581                         power-domains = <&gcc USB30_PRIM_GDSC>;
2582
2583                         interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2584                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2585                         interconnect-names = "usb-ddr", "apps-usb";
2586
2587                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2588                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2589                         assigned-clock-rates = <19200000>, <200000000>;
2590
2591                         #address-cells = <2>;
2592                         #size-cells = <2>;
2593                         ranges;
2594                         dma-ranges;
2595
2596                         status = "disabled";
2597
2598                         usb_prim_dwc3: usb@a600000 {
2599                                 compatible = "snps,dwc3";
2600                                 reg = <0 0x0a600000 0 0xcd00>;
2601                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2602                                 iommus = <&apps_smmu 0x140 0>;
2603                                 snps,dis_u2_susphy_quirk;
2604                                 snps,dis_enblslpm_quirk;
2605                                 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
2606                                 phy-names = "usb2-phy", "usb3-phy";
2607                         };
2608                 };
2609
2610                 usb_sec: usb@a8f8800 {
2611                         compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2612                         reg = <0 0x0a8f8800 0 0x400>;
2613
2614                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2615                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
2616                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2617                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2618                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2619                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2620                         clock-names = "cfg_noc",
2621                                       "core",
2622                                       "iface",
2623                                       "mock_utmi",
2624                                       "sleep",
2625                                       "xo";
2626                         resets = <&gcc GCC_USB30_SEC_BCR>;
2627                         power-domains = <&gcc USB30_SEC_GDSC>;
2628                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2629                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2630                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
2631                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
2632                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2633                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2634
2635                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2636                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
2637                         assigned-clock-rates = <19200000>, <200000000>;
2638
2639                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2640                                         <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2641                         interconnect-names = "usb-ddr", "apps-usb";
2642
2643                         #address-cells = <2>;
2644                         #size-cells = <2>;
2645                         ranges;
2646                         dma-ranges;
2647
2648                         status = "disabled";
2649
2650                         usb_sec_dwc3: usb@a800000 {
2651                                 compatible = "snps,dwc3";
2652                                 reg = <0 0x0a800000 0 0xcd00>;
2653                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2654                                 iommus = <&apps_smmu 0x160 0>;
2655                                 snps,dis_u2_susphy_quirk;
2656                                 snps,dis_enblslpm_quirk;
2657                                 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
2658                                 phy-names = "usb2-phy", "usb3-phy";
2659                         };
2660                 };
2661
2662                 mdss: mdss@ae00000 {
2663                         compatible = "qcom,sc8180x-mdss";
2664                         reg = <0 0x0ae00000 0 0x1000>;
2665                         reg-names = "mdss";
2666
2667                         power-domains = <&dispcc MDSS_GDSC>;
2668
2669                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2670                                  <&gcc GCC_DISP_HF_AXI_CLK>,
2671                                  <&gcc GCC_DISP_SF_AXI_CLK>,
2672                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2673                         clock-names = "iface",
2674                                       "bus",
2675                                       "nrt_bus",
2676                                       "core";
2677
2678                         resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2679
2680                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2681                         interrupt-controller;
2682                         #interrupt-cells = <1>;
2683
2684                         interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
2685                                         <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
2686                         interconnect-names = "mdp0-mem", "mdp1-mem";
2687
2688                         iommus = <&apps_smmu 0x800 0x420>;
2689
2690                         #address-cells = <2>;
2691                         #size-cells = <2>;
2692                         ranges;
2693
2694                         status = "disabled";
2695
2696                         mdss_mdp: mdp@ae01000 {
2697                                 compatible = "qcom,sc8180x-dpu";
2698                                 reg = <0 0x0ae01000 0 0x8f000>,
2699                                       <0 0x0aeb0000 0 0x2008>;
2700                                 reg-names = "mdp", "vbif";
2701
2702                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2703                                          <&gcc GCC_DISP_HF_AXI_CLK>,
2704                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2705                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2706                                 clock-names = "iface",
2707                                               "bus",
2708                                               "core",
2709                                               "vsync";
2710
2711                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2712                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2713                                 assigned-clock-rates = <460000000>,
2714                                                        <19200000>;
2715
2716                                 operating-points-v2 = <&mdp_opp_table>;
2717                                 power-domains = <&rpmhpd SC8180X_MMCX>;
2718
2719                                 interrupt-parent = <&mdss>;
2720                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2721
2722                                 ports {
2723                                         #address-cells = <1>;
2724                                         #size-cells = <0>;
2725
2726                                         port@0 {
2727                                                 reg = <0>;
2728                                                 dpu_intf0_out: endpoint {
2729                                                         remote-endpoint = <&dp0_in>;
2730                                                 };
2731                                         };
2732
2733                                         port@1 {
2734                                                 reg = <1>;
2735                                                 dpu_intf1_out: endpoint {
2736                                                         remote-endpoint = <&mdss_dsi0_in>;
2737                                                 };
2738                                         };
2739
2740                                         port@2 {
2741                                                 reg = <2>;
2742                                                 dpu_intf2_out: endpoint {
2743                                                         remote-endpoint = <&mdss_dsi1_in>;
2744                                                 };
2745                                         };
2746
2747                                         port@4 {
2748                                                 reg = <4>;
2749                                                 dpu_intf4_out: endpoint {
2750                                                         remote-endpoint = <&dp1_in>;
2751                                                 };
2752                                         };
2753
2754                                         port@5 {
2755                                                 reg = <5>;
2756                                                 dpu_intf5_out: endpoint {
2757                                                         remote-endpoint = <&edp_in>;
2758                                                 };
2759                                         };
2760                                 };
2761
2762                                 mdp_opp_table: opp-table {
2763                                         compatible = "operating-points-v2";
2764
2765                                         opp-200000000 {
2766                                                 opp-hz = /bits/ 64 <200000000>;
2767                                                 required-opps = <&rpmhpd_opp_low_svs>;
2768                                         };
2769
2770                                         opp-300000000 {
2771                                                 opp-hz = /bits/ 64 <300000000>;
2772                                                 required-opps = <&rpmhpd_opp_svs>;
2773                                         };
2774
2775                                         opp-345000000 {
2776                                                 opp-hz = /bits/ 64 <345000000>;
2777                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2778                                         };
2779
2780                                         opp-460000000 {
2781                                                 opp-hz = /bits/ 64 <460000000>;
2782                                                 required-opps = <&rpmhpd_opp_nom>;
2783                                         };
2784                                 };
2785                         };
2786
2787                         mdss_dsi0: dsi@ae94000 {
2788                                 compatible = "qcom,mdss-dsi-ctrl";
2789                                 reg = <0 0x0ae94000 0 0x400>;
2790                                 reg-names = "dsi_ctrl";
2791
2792                                 interrupt-parent = <&mdss>;
2793                                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2794
2795                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2796                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2797                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2798                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2799                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2800                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2801                                 clock-names = "byte",
2802                                               "byte_intf",
2803                                               "pixel",
2804                                               "core",
2805                                               "iface",
2806                                               "bus";
2807
2808                                 operating-points-v2 = <&dsi_opp_table>;
2809                                 power-domains = <&rpmhpd SC8180X_MMCX>;
2810
2811                                 phys = <&mdss_dsi0_phy>;
2812                                 phy-names = "dsi";
2813
2814                                 status = "disabled";
2815
2816                                 ports {
2817                                         #address-cells = <1>;
2818                                         #size-cells = <0>;
2819
2820                                         port@0 {
2821                                                 reg = <0>;
2822                                                 mdss_dsi0_in: endpoint {
2823                                                         remote-endpoint = <&dpu_intf1_out>;
2824                                                 };
2825                                         };
2826
2827                                         port@1 {
2828                                                 reg = <1>;
2829                                                 mdss_dsi0_out: endpoint {
2830                                                 };
2831                                         };
2832                                 };
2833
2834                                 dsi_opp_table: opp-table {
2835                                         compatible = "operating-points-v2";
2836
2837                                         opp-187500000 {
2838                                                 opp-hz = /bits/ 64 <187500000>;
2839                                                 required-opps = <&rpmhpd_opp_low_svs>;
2840                                         };
2841
2842                                         opp-300000000 {
2843                                                 opp-hz = /bits/ 64 <300000000>;
2844                                                 required-opps = <&rpmhpd_opp_svs>;
2845                                         };
2846
2847                                         opp-358000000 {
2848                                                 opp-hz = /bits/ 64 <358000000>;
2849                                                 required-opps = <&rpmhpd_opp_svs_l1>;
2850                                         };
2851                                 };
2852                         };
2853
2854                         mdss_dsi0_phy: dsi-phy@ae94400 {
2855                                 compatible = "qcom,dsi-phy-7nm";
2856                                 reg = <0 0x0ae94400 0 0x200>,
2857                                       <0 0x0ae94600 0 0x280>,
2858                                       <0 0x0ae94900 0 0x260>;
2859                                 reg-names = "dsi_phy",
2860                                             "dsi_phy_lane",
2861                                             "dsi_pll";
2862
2863                                 #clock-cells = <1>;
2864                                 #phy-cells = <0>;
2865
2866                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2867                                          <&rpmhcc RPMH_CXO_CLK>;
2868                                 clock-names = "iface", "ref";
2869
2870                                 status = "disabled";
2871                         };
2872
2873                         mdss_dsi1: dsi@ae96000 {
2874                                 compatible = "qcom,mdss-dsi-ctrl";
2875                                 reg = <0 0x0ae96000 0 0x400>;
2876                                 reg-names = "dsi_ctrl";
2877
2878                                 interrupt-parent = <&mdss>;
2879                                 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2880
2881                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2882                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2883                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2884                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2885                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2886                                          <&gcc GCC_DISP_HF_AXI_CLK>;
2887                                 clock-names = "byte",
2888                                               "byte_intf",
2889                                               "pixel",
2890                                               "core",
2891                                               "iface",
2892                                               "bus";
2893
2894                                 operating-points-v2 = <&dsi_opp_table>;
2895                                 power-domains = <&rpmhpd SC8180X_MMCX>;
2896
2897                                 phys = <&mdss_dsi1_phy>;
2898                                 phy-names = "dsi";
2899
2900                                 status = "disabled";
2901
2902                                 ports {
2903                                         #address-cells = <1>;
2904                                         #size-cells = <0>;
2905
2906                                         port@0 {
2907                                                 reg = <0>;
2908                                                 mdss_dsi1_in: endpoint {
2909                                                         remote-endpoint = <&dpu_intf2_out>;
2910                                                 };
2911                                         };
2912
2913                                         port@1 {
2914                                                 reg = <1>;
2915                                                 mdss_dsi1_out: endpoint {
2916                                                 };
2917                                         };
2918                                 };
2919                         };
2920
2921                         mdss_dsi1_phy: dsi-phy@ae96400 {
2922                                 compatible = "qcom,dsi-phy-7nm";
2923                                 reg = <0 0x0ae96400 0 0x200>,
2924                                       <0 0x0ae96600 0 0x280>,
2925                                       <0 0x0ae96900 0 0x260>;
2926                                 reg-names = "dsi_phy",
2927                                             "dsi_phy_lane",
2928                                             "dsi_pll";
2929
2930                                 #clock-cells = <1>;
2931                                 #phy-cells = <0>;
2932
2933                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2934                                          <&rpmhcc RPMH_CXO_CLK>;
2935                                 clock-names = "iface", "ref";
2936
2937                                 status = "disabled";
2938                         };
2939
2940                         mdss_dp0: displayport-controller@ae90000 {
2941                                 compatible = "qcom,sc8180x-dp";
2942                                 reg = <0 0xae90000 0 0x200>,
2943                                       <0 0xae90200 0 0x200>,
2944                                       <0 0xae90400 0 0x600>,
2945                                       <0 0xae90a00 0 0x400>;
2946                                 interrupt-parent = <&mdss>;
2947                                 interrupts = <12>;
2948                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2949                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2950                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2951                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
2952                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
2953                                 clock-names = "core_iface",
2954                                               "core_aux",
2955                                               "ctrl_link",
2956                                               "ctrl_link_iface",
2957                                               "stream_pixel";
2958
2959                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
2960                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
2961                                 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
2962
2963                                 phys = <&usb_prim_dpphy>;
2964                                 phy-names = "dp";
2965
2966                                 #sound-dai-cells = <0>;
2967
2968                                 operating-points-v2 = <&dp0_opp_table>;
2969                                 power-domains = <&rpmhpd SC8180X_MMCX>;
2970
2971                                 status = "disabled";
2972
2973                                 ports {
2974                                         #address-cells = <1>;
2975                                         #size-cells = <0>;
2976
2977                                         port@0 {
2978                                                 reg = <0>;
2979                                                 dp0_in: endpoint {
2980                                                         remote-endpoint = <&dpu_intf0_out>;
2981                                                 };
2982                                         };
2983
2984                                         port@1 {
2985                                                 reg = <1>;
2986                                         };
2987                                 };
2988
2989                                 dp0_opp_table: opp-table {
2990                                         compatible = "operating-points-v2";
2991
2992                                         opp-160000000 {
2993                                                 opp-hz = /bits/ 64 <160000000>;
2994                                                 required-opps = <&rpmhpd_opp_low_svs>;
2995                                         };
2996
2997                                         opp-270000000 {
2998                                                 opp-hz = /bits/ 64 <270000000>;
2999                                                 required-opps = <&rpmhpd_opp_svs>;
3000                                         };
3001
3002                                         opp-540000000 {
3003                                                 opp-hz = /bits/ 64 <540000000>;
3004                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3005                                         };
3006
3007                                         opp-810000000 {
3008                                                 opp-hz = /bits/ 64 <810000000>;
3009                                                 required-opps = <&rpmhpd_opp_nom>;
3010                                         };
3011                                 };
3012                         };
3013
3014                         mdss_dp1: displayport-controller@ae98000 {
3015                                 compatible = "qcom,sc8180x-dp";
3016                                 reg = <0 0xae98000 0 0x200>,
3017                                       <0 0xae98200 0 0x200>,
3018                                       <0 0xae98400 0 0x600>,
3019                                       <0 0xae98a00 0 0x400>;
3020                                 interrupt-parent = <&mdss>;
3021                                 interrupts = <13>;
3022                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3023                                          <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
3024                                          <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
3025                                          <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
3026                                          <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
3027                                 clock-names = "core_iface",
3028                                               "core_aux",
3029                                               "ctrl_link",
3030                                               "ctrl_link_iface",
3031                                               "stream_pixel";
3032
3033                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3034                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
3035                                 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3036
3037                                 phys = <&usb_sec_dpphy>;
3038                                 phy-names = "dp";
3039
3040                                 #sound-dai-cells = <0>;
3041
3042                                 operating-points-v2 = <&dp0_opp_table>;
3043                                 power-domains = <&rpmhpd SC8180X_MMCX>;
3044
3045                                 status = "disabled";
3046
3047                                 ports {
3048                                         #address-cells = <1>;
3049                                         #size-cells = <0>;
3050
3051                                         port@0 {
3052                                                 reg = <0>;
3053                                                 dp1_in: endpoint {
3054                                                         remote-endpoint = <&dpu_intf4_out>;
3055                                                 };
3056                                         };
3057
3058                                         port@1 {
3059                                                 reg = <1>;
3060                                         };
3061                                 };
3062
3063                                 dp1_opp_table: opp-table {
3064                                         compatible = "operating-points-v2";
3065
3066                                         opp-160000000 {
3067                                                 opp-hz = /bits/ 64 <160000000>;
3068                                                 required-opps = <&rpmhpd_opp_low_svs>;
3069                                         };
3070
3071                                         opp-270000000 {
3072                                                 opp-hz = /bits/ 64 <270000000>;
3073                                                 required-opps = <&rpmhpd_opp_svs>;
3074                                         };
3075
3076                                         opp-540000000 {
3077                                                 opp-hz = /bits/ 64 <540000000>;
3078                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3079                                         };
3080
3081                                         opp-810000000 {
3082                                                 opp-hz = /bits/ 64 <810000000>;
3083                                                 required-opps = <&rpmhpd_opp_nom>;
3084                                         };
3085                                 };
3086                         };
3087
3088                         mdss_edp: displayport-controller@ae9a000 {
3089                                 compatible = "qcom,sc8180x-edp";
3090                                 reg = <0 0xae9a000 0 0x200>,
3091                                       <0 0xae9a200 0 0x200>,
3092                                       <0 0xae9a400 0 0x600>,
3093                                       <0 0xae9aa00 0 0x400>;
3094                                 interrupt-parent = <&mdss>;
3095                                 interrupts = <14>;
3096                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3097                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3098                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3099                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3100                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3101                                 clock-names = "core_iface",
3102                                               "core_aux",
3103                                               "ctrl_link",
3104                                                "ctrl_link_iface",
3105                                               "stream_pixel";
3106
3107                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3108                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3109                                 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3110
3111                                 phys = <&edp_phy>;
3112                                 phy-names = "dp";
3113
3114                                 #sound-dai-cells = <0>;
3115
3116                                 operating-points-v2 = <&edp_opp_table>;
3117                                 power-domains = <&rpmhpd SC8180X_MMCX>;
3118
3119                                 status = "disabled";
3120
3121                                 ports {
3122                                         #address-cells = <1>;
3123                                         #size-cells = <0>;
3124
3125                                         port@0 {
3126                                                 reg = <0>;
3127                                                 edp_in: endpoint {
3128                                                         remote-endpoint = <&dpu_intf5_out>;
3129                                                 };
3130                                         };
3131                                 };
3132
3133                                 edp_opp_table: opp-table {
3134                                         compatible = "operating-points-v2";
3135
3136                                         opp-160000000 {
3137                                                 opp-hz = /bits/ 64 <160000000>;
3138                                                 required-opps = <&rpmhpd_opp_low_svs>;
3139                                         };
3140
3141                                         opp-270000000 {
3142                                                 opp-hz = /bits/ 64 <270000000>;
3143                                                 required-opps = <&rpmhpd_opp_svs>;
3144                                         };
3145
3146                                         opp-540000000 {
3147                                                 opp-hz = /bits/ 64 <540000000>;
3148                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3149                                         };
3150
3151                                         opp-810000000 {
3152                                                 opp-hz = /bits/ 64 <810000000>;
3153                                                 required-opps = <&rpmhpd_opp_nom>;
3154                                         };
3155                                 };
3156                         };
3157                 };
3158
3159                 edp_phy: phy@aec2a00 {
3160                         compatible = "qcom,sc8180x-edp-phy";
3161                         reg = <0 0x0aec2a00 0 0x1c0>,
3162                               <0 0x0aec2200 0 0xa0>,
3163                               <0 0x0aec2600 0 0xa0>,
3164                               <0 0x0aec2000 0 0x19c>;
3165
3166                         clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3167                                  <&dispcc DISP_CC_MDSS_AHB_CLK>;
3168                         clock-names = "aux", "cfg_ahb";
3169
3170                         power-domains = <&dispcc MDSS_GDSC>;
3171
3172                         #clock-cells = <1>;
3173                         #phy-cells = <0>;
3174                 };
3175
3176                 dispcc: clock-controller@af00000 {
3177                         compatible = "qcom,sc8180x-dispcc";
3178                         reg = <0 0x0af00000 0 0x20000>;
3179                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3180                                  <&sleep_clk>,
3181                                  <&usb_prim_dpphy 0>,
3182                                  <&usb_prim_dpphy 1>,
3183                                  <&usb_sec_dpphy 0>,
3184                                  <&usb_sec_dpphy 1>,
3185                                  <&edp_phy 0>,
3186                                  <&edp_phy 1>;
3187                         clock-names = "bi_tcxo",
3188                                       "sleep_clk",
3189                                       "dp_phy_pll_link_clk",
3190                                       "dp_phy_pll_vco_div_clk",
3191                                       "dptx1_phy_pll_link_clk",
3192                                       "dptx1_phy_pll_vco_div_clk",
3193                                       "edp_phy_pll_link_clk",
3194                                       "edp_phy_pll_vco_div_clk";
3195                         power-domains = <&rpmhpd SC8180X_MMCX>;
3196                         #clock-cells = <1>;
3197                         #reset-cells = <1>;
3198                         #power-domain-cells = <1>;
3199                 };
3200
3201                 pdc: interrupt-controller@b220000 {
3202                         compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3203                         reg = <0 0x0b220000 0 0x30000>;
3204                         qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3205                         #interrupt-cells = <2>;
3206                         interrupt-parent = <&intc>;
3207                         interrupt-controller;
3208                 };
3209
3210                 tsens0: thermal-sensor@c263000 {
3211                         compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3212                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3213                               <0 0x0c222000 0 0x1ff>; /* SROT */
3214                         #qcom,sensors = <16>;
3215                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3216                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3217                         interrupt-names = "uplow", "critical";
3218                         #thermal-sensor-cells = <1>;
3219                 };
3220
3221                 tsens1: thermal-sensor@c265000 {
3222                         compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3223                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3224                               <0 0x0c223000 0 0x1ff>; /* SROT */
3225                         #qcom,sensors = <9>;
3226                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3227                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3228                         interrupt-names = "uplow", "critical";
3229                         #thermal-sensor-cells = <1>;
3230                 };
3231
3232                 aoss_qmp: power-controller@c300000 {
3233                         compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3234                         reg = <0x0 0x0c300000 0x0 0x100000>;
3235                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3236                         mboxes = <&apss_shared 0>;
3237
3238                         #clock-cells = <0>;
3239                         #power-domain-cells = <1>;
3240                 };
3241
3242                 spmi_bus: spmi@c440000 {
3243                         compatible = "qcom,spmi-pmic-arb";
3244                         reg = <0x0 0x0c440000 0x0 0x0001100>,
3245                               <0x0 0x0c600000 0x0 0x2000000>,
3246                               <0x0 0x0e600000 0x0 0x0100000>,
3247                               <0x0 0x0e700000 0x0 0x00a0000>,
3248                               <0x0 0x0c40a000 0x0 0x0026000>;
3249                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3250                         interrupt-names = "periph_irq";
3251                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3252                         qcom,ee = <0>;
3253                         qcom,channel = <0>;
3254                         #address-cells = <2>;
3255                         #size-cells = <0>;
3256                         interrupt-controller;
3257                         #interrupt-cells = <4>;
3258                         cell-index = <0>;
3259                 };
3260
3261                 apps_smmu: iommu@15000000 {
3262                         compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3263                         reg = <0 0x15000000 0 0x100000>;
3264                         #iommu-cells = <2>;
3265                         #global-interrupts = <1>;
3266                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3287                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3288                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3289                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3290                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3291                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3292                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3312                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3313                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3314                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3315                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3316                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3317                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3318                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3319                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3320                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3321                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3322                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3323                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3324                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3325                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3326                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3327                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3328                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3329                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3330                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3331                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3332                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3333                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3334                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3335                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3336                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3337                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3338                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3339                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3340                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3341                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3342                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3343                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3344                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3345                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3346                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3347                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3348                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3349                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3350                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3351                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3352                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3353                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3354                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3355                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3356                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3357                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3358                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3359                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3360                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3361                                      <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
3362                                      <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
3363                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3364                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3365                                      <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
3366                                      <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
3367                                      <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
3368                                      <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
3369                                      <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
3370                                      <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
3371                                      <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
3372                                      <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
3373
3374                 };
3375
3376                 remoteproc_adsp: remoteproc@17300000 {
3377                         compatible = "qcom,sc8180x-adsp-pas";
3378                         reg = <0x0 0x17300000 0x0 0x4040>;
3379
3380                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3381                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3382                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3383                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3384                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3385                         interrupt-names = "wdog", "fatal", "ready",
3386                                           "handover", "stop-ack";
3387
3388                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3389                         clock-names = "xo";
3390
3391                         power-domains = <&rpmhpd SC8180X_CX>;
3392                         power-domain-names = "cx";
3393
3394                         qcom,qmp = <&aoss_qmp>;
3395
3396                         qcom,smem-states = <&adsp_smp2p_out 0>;
3397                         qcom,smem-state-names = "stop";
3398
3399                         status = "disabled";
3400
3401                         remoteproc_adsp_glink: glink-edge {
3402                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3403                                 label = "lpass";
3404                                 qcom,remote-pid = <2>;
3405                                 mboxes = <&apss_shared 8>;
3406                         };
3407                 };
3408
3409                 intc: interrupt-controller@17a00000 {
3410                         compatible = "arm,gic-v3";
3411                         interrupt-controller;
3412                         #interrupt-cells = <3>;
3413                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
3414                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
3415                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3416                 };
3417
3418                 apss_shared: mailbox@17c00000 {
3419                         compatible = "qcom,sc8180x-apss-shared";
3420                         reg = <0x0 0x17c00000 0x0 0x1000>;
3421                         #mbox-cells = <1>;
3422                 };
3423
3424                 timer@17c20000 {
3425                         compatible = "arm,armv7-timer-mem";
3426                         reg = <0x0 0x17c20000 0x0 0x1000>;
3427
3428                         #address-cells = <1>;
3429                         #size-cells = <1>;
3430                         ranges = <0 0 0 0x20000000>;
3431
3432                         frame@17c21000{
3433                                 reg = <0x17c21000 0x1000>,
3434                                       <0x17c22000 0x1000>;
3435                                 frame-number = <0>;
3436                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3437                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3438                         };
3439
3440                         frame@17c23000 {
3441                                 reg = <0x17c23000 0x1000>;
3442                                 frame-number = <1>;
3443                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3444                                 status = "disabled";
3445                         };
3446
3447                         frame@17c25000 {
3448                                 reg = <0x17c25000 0x1000>;
3449                                 frame-number = <2>;
3450                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3451                                 status = "disabled";
3452                         };
3453
3454                         frame@17c27000 {
3455                                 reg = <0x17c26000 0x1000>;
3456                                 frame-number = <3>;
3457                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3458                                 status = "disabled";
3459                         };
3460
3461                         frame@17c29000 {
3462                                 reg = <0x17c29000 0x1000>;
3463                                 frame-number = <4>;
3464                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3465                                 status = "disabled";
3466                         };
3467
3468                         frame@17c2b000 {
3469                                 reg = <0x17c2b000 0x1000>;
3470                                 frame-number = <5>;
3471                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3472                                 status = "disabled";
3473                         };
3474
3475                         frame@17c2d000 {
3476                                 reg = <0x17c2d000 0x1000>;
3477                                 frame-number = <6>;
3478                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3479                                 status = "disabled";
3480                         };
3481                 };
3482
3483                 apps_rsc: rsc@18200000 {
3484                         compatible = "qcom,rpmh-rsc";
3485                         reg = <0x0 0x18200000 0x0 0x10000>,
3486                               <0x0 0x18210000 0x0 0x10000>,
3487                               <0x0 0x18220000 0x0 0x10000>;
3488                         reg-names = "drv-0", "drv-1", "drv-2";
3489                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3490                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3491                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3492                         qcom,tcs-offset = <0xd00>;
3493                         qcom,drv-id = <2>;
3494                         qcom,tcs-config = <ACTIVE_TCS  2>,
3495                                           <SLEEP_TCS   1>,
3496                                           <WAKE_TCS    1>,
3497                                           <CONTROL_TCS 0>;
3498                         label = "apps_rsc";
3499                         power-domains = <&CLUSTER_PD>;
3500
3501                         apps_bcm_voter: bcm-voter {
3502                                 compatible = "qcom,bcm-voter";
3503                         };
3504
3505                         rpmhcc: clock-controller {
3506                                 compatible = "qcom,sc8180x-rpmh-clk";
3507                                 #clock-cells = <1>;
3508                                 clock-names = "xo";
3509                                 clocks = <&xo_board_clk>;
3510                         };
3511
3512                         rpmhpd: power-controller {
3513                                 compatible = "qcom,sc8180x-rpmhpd";
3514                                 #power-domain-cells = <1>;
3515                                 operating-points-v2 = <&rpmhpd_opp_table>;
3516
3517                                 rpmhpd_opp_table: opp-table {
3518                                         compatible = "operating-points-v2";
3519
3520                                         rpmhpd_opp_ret: opp1 {
3521                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3522                                         };
3523
3524                                         rpmhpd_opp_min_svs: opp2 {
3525                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3526                                         };
3527
3528                                         rpmhpd_opp_low_svs: opp3 {
3529                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3530                                         };
3531
3532                                         rpmhpd_opp_svs: opp4 {
3533                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3534                                         };
3535
3536                                         rpmhpd_opp_svs_l1: opp5 {
3537                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3538                                         };
3539
3540                                         rpmhpd_opp_nom: opp6 {
3541                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3542                                         };
3543
3544                                         rpmhpd_opp_nom_l1: opp7 {
3545                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3546                                         };
3547
3548                                         rpmhpd_opp_nom_l2: opp8 {
3549                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3550                                         };
3551
3552                                         rpmhpd_opp_turbo: opp9 {
3553                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3554                                         };
3555
3556                                         rpmhpd_opp_turbo_l1: opp10 {
3557                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3558                                         };
3559                                 };
3560                         };
3561                 };
3562
3563                 osm_l3: interconnect@18321000 {
3564                         compatible = "qcom,sc8180x-osm-l3";
3565                         reg = <0 0x18321000 0 0x1400>;
3566
3567                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3568                         clock-names = "xo", "alternate";
3569
3570                         #interconnect-cells = <1>;
3571                 };
3572
3573                 lmh@18350800 {
3574                         compatible = "qcom,sc8180x-lmh";
3575                         reg = <0 0x18350800 0 0x400>;
3576                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3577                         cpus = <&CPU4>;
3578                         qcom,lmh-temp-arm-millicelsius = <65000>;
3579                         qcom,lmh-temp-low-millicelsius = <94500>;
3580                         qcom,lmh-temp-high-millicelsius = <95000>;
3581                         interrupt-controller;
3582                         #interrupt-cells = <1>;
3583                 };
3584
3585                 lmh@18358800 {
3586                         compatible = "qcom,sc8180x-lmh";
3587                         reg = <0 0x18358800 0 0x400>;
3588                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3589                         cpus = <&CPU0>;
3590                         qcom,lmh-temp-arm-millicelsius = <65000>;
3591                         qcom,lmh-temp-low-millicelsius = <94500>;
3592                         qcom,lmh-temp-high-millicelsius = <95000>;
3593                         interrupt-controller;
3594                         #interrupt-cells = <1>;
3595                 };
3596
3597                 cpufreq_hw: cpufreq@18323000 {
3598                         compatible = "qcom,cpufreq-hw";
3599                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3600                         reg-names = "freq-domain0", "freq-domain1";
3601
3602                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3603                         clock-names = "xo", "alternate";
3604
3605                         #freq-domain-cells = <1>;
3606                         #clock-cells = <1>;
3607                 };
3608
3609                 wifi: wifi@18800000 {
3610                         compatible = "qcom,wcn3990-wifi";
3611                         reg = <0 0x18800000 0 0x800000>;
3612                         reg-names = "membase";
3613                         clock-names = "cxo_ref_clk_pin";
3614                         clocks = <&rpmhcc RPMH_RF_CLK2>;
3615                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3616                                      <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3617                                      <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3618                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3619                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3620                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3621                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3622                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3623                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3624                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3625                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3626                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3627                         iommus = <&apps_smmu 0x0640 0x1>;
3628                         qcom,msa-fixed-perm;
3629                         status = "disabled";
3630                 };
3631         };
3632
3633         thermal-zones {
3634                 cpu0-thermal {
3635                         polling-delay-passive = <250>;
3636                         polling-delay = <1000>;
3637
3638                         thermal-sensors = <&tsens0 1>;
3639
3640                         trips {
3641                                 cpu-crit {
3642                                         temperature = <110000>;
3643                                         hysteresis = <1000>;
3644                                         type = "critical";
3645                                 };
3646                         };
3647                 };
3648
3649                 cpu1-thermal {
3650                         polling-delay-passive = <250>;
3651                         polling-delay = <1000>;
3652
3653                         thermal-sensors = <&tsens0 2>;
3654
3655                         trips {
3656                                 cpu-crit {
3657                                         temperature = <110000>;
3658                                         hysteresis = <1000>;
3659                                         type = "critical";
3660                                 };
3661                         };
3662                 };
3663
3664                 cpu2-thermal {
3665                         polling-delay-passive = <250>;
3666                         polling-delay = <1000>;
3667
3668                         thermal-sensors = <&tsens0 3>;
3669
3670                         trips {
3671                                 cpu-crit {
3672                                         temperature = <110000>;
3673                                         hysteresis = <1000>;
3674                                         type = "critical";
3675                                 };
3676                         };
3677                 };
3678
3679                 cpu3-thermal {
3680                         polling-delay-passive = <250>;
3681                         polling-delay = <1000>;
3682
3683                         thermal-sensors = <&tsens0 4>;
3684
3685                         trips {
3686                                 cpu-crit {
3687                                         temperature = <110000>;
3688                                         hysteresis = <1000>;
3689                                         type = "critical";
3690                                 };
3691                         };
3692                 };
3693
3694                 cpu4-top-thermal {
3695                         polling-delay-passive = <250>;
3696                         polling-delay = <1000>;
3697
3698                         thermal-sensors = <&tsens0 7>;
3699
3700                         trips {
3701                                 cpu-crit {
3702                                         temperature = <110000>;
3703                                         hysteresis = <1000>;
3704                                         type = "critical";
3705                                 };
3706                         };
3707                 };
3708
3709                 cpu5-top-thermal {
3710                         polling-delay-passive = <250>;
3711                         polling-delay = <1000>;
3712
3713                         thermal-sensors = <&tsens0 8>;
3714
3715                         trips {
3716                                 cpu-crit {
3717                                         temperature = <110000>;
3718                                         hysteresis = <1000>;
3719                                         type = "critical";
3720                                 };
3721                         };
3722                 };
3723
3724                 cpu6-top-thermal {
3725                         polling-delay-passive = <250>;
3726                         polling-delay = <1000>;
3727
3728                         thermal-sensors = <&tsens0 9>;
3729
3730                         trips {
3731                                 cpu-crit {
3732                                         temperature = <110000>;
3733                                         hysteresis = <1000>;
3734                                         type = "critical";
3735                                 };
3736                         };
3737                 };
3738
3739                 cpu7-top-thermal {
3740                         polling-delay-passive = <250>;
3741                         polling-delay = <1000>;
3742
3743                         thermal-sensors = <&tsens0 10>;
3744
3745                         trips {
3746                                 cpu-crit {
3747                                         temperature = <110000>;
3748                                         hysteresis = <1000>;
3749                                         type = "critical";
3750                                 };
3751                         };
3752                 };
3753
3754                 cpu4-bottom-thermal {
3755                         polling-delay-passive = <250>;
3756                         polling-delay = <1000>;
3757
3758                         thermal-sensors = <&tsens0 11>;
3759
3760                         trips {
3761                                 cpu-crit {
3762                                         temperature = <110000>;
3763                                         hysteresis = <1000>;
3764                                         type = "critical";
3765                                 };
3766                         };
3767                 };
3768
3769                 cpu5-bottom-thermal {
3770                         polling-delay-passive = <250>;
3771                         polling-delay = <1000>;
3772
3773                         thermal-sensors = <&tsens0 12>;
3774
3775                         trips {
3776                                 cpu-crit {
3777                                         temperature = <110000>;
3778                                         hysteresis = <1000>;
3779                                         type = "critical";
3780                                 };
3781                         };
3782                 };
3783
3784                 cpu6-bottom-thermal {
3785                         polling-delay-passive = <250>;
3786                         polling-delay = <1000>;
3787
3788                         thermal-sensors = <&tsens0 13>;
3789
3790                         trips {
3791                                 cpu-crit {
3792                                         temperature = <110000>;
3793                                         hysteresis = <1000>;
3794                                         type = "critical";
3795                                 };
3796                         };
3797                 };
3798
3799                 cpu7-bottom-thermal {
3800                         polling-delay-passive = <250>;
3801                         polling-delay = <1000>;
3802
3803                         thermal-sensors = <&tsens0 14>;
3804
3805                         trips {
3806                                 cpu-crit {
3807                                         temperature = <110000>;
3808                                         hysteresis = <1000>;
3809                                         type = "critical";
3810                                 };
3811                         };
3812                 };
3813
3814                 aoss0-thermal {
3815                         polling-delay-passive = <250>;
3816                         polling-delay = <1000>;
3817
3818                         thermal-sensors = <&tsens0 0>;
3819
3820                         trips {
3821                                 trip-point0 {
3822                                         temperature = <90000>;
3823                                         hysteresis = <2000>;
3824                                         type = "hot";
3825                                 };
3826                         };
3827                 };
3828
3829                 cluster0-thermal {
3830                         polling-delay-passive = <250>;
3831                         polling-delay = <1000>;
3832
3833                         thermal-sensors = <&tsens0 5>;
3834
3835                         trips {
3836                                 cluster-crit {
3837                                         temperature = <110000>;
3838                                         hysteresis = <2000>;
3839                                         type = "critical";
3840                                 };
3841                         };
3842                 };
3843
3844                 cluster1-thermal {
3845                         polling-delay-passive = <250>;
3846                         polling-delay = <1000>;
3847
3848                         thermal-sensors = <&tsens0 6>;
3849
3850                         trips {
3851                                 cluster-crit {
3852                                         temperature = <110000>;
3853                                         hysteresis = <2000>;
3854                                         type = "critical";
3855                                 };
3856                         };
3857                 };
3858
3859                 gpu-thermal-top {
3860                         polling-delay-passive = <250>;
3861                         polling-delay = <1000>;
3862
3863                         thermal-sensors = <&tsens0 15>;
3864
3865                         trips {
3866                                 trip-point0 {
3867                                         temperature = <90000>;
3868                                         hysteresis = <2000>;
3869                                         type = "hot";
3870                                 };
3871                         };
3872                 };
3873
3874                 aoss1-thermal {
3875                         polling-delay-passive = <250>;
3876                         polling-delay = <1000>;
3877
3878                         thermal-sensors = <&tsens1 0>;
3879
3880                         trips {
3881                                 trip-point0 {
3882                                         temperature = <90000>;
3883                                         hysteresis = <2000>;
3884                                         type = "hot";
3885                                 };
3886                         };
3887                 };
3888
3889                 wlan-thermal {
3890                         polling-delay-passive = <250>;
3891                         polling-delay = <1000>;
3892
3893                         thermal-sensors = <&tsens1 1>;
3894
3895                         trips {
3896                                 trip-point0 {
3897                                         temperature = <90000>;
3898                                         hysteresis = <2000>;
3899                                         type = "hot";
3900                                 };
3901                         };
3902                 };
3903
3904                 video-thermal {
3905                         polling-delay-passive = <250>;
3906                         polling-delay = <1000>;
3907
3908                         thermal-sensors = <&tsens1 2>;
3909
3910                         trips {
3911                                 trip-point0 {
3912                                         temperature = <90000>;
3913                                         hysteresis = <2000>;
3914                                         type = "hot";
3915                                 };
3916                         };
3917                 };
3918
3919                 mem-thermal {
3920                         polling-delay-passive = <250>;
3921                         polling-delay = <1000>;
3922
3923                         thermal-sensors = <&tsens1 3>;
3924
3925                         trips {
3926                                 trip-point0 {
3927                                         temperature = <90000>;
3928                                         hysteresis = <2000>;
3929                                         type = "hot";
3930                                 };
3931                         };
3932                 };
3933
3934                 q6-hvx-thermal {
3935                         polling-delay-passive = <250>;
3936                         polling-delay = <1000>;
3937
3938                         thermal-sensors = <&tsens1 4>;
3939
3940                         trips {
3941                                 trip-point0 {
3942                                         temperature = <90000>;
3943                                         hysteresis = <2000>;
3944                                         type = "hot";
3945                                 };
3946                         };
3947                 };
3948
3949                 camera-thermal {
3950                         polling-delay-passive = <250>;
3951                         polling-delay = <1000>;
3952
3953                         thermal-sensors = <&tsens1 5>;
3954
3955                         trips {
3956                                 trip-point0 {
3957                                         temperature = <90000>;
3958                                         hysteresis = <2000>;
3959                                         type = "hot";
3960                                 };
3961                         };
3962                 };
3963
3964                 compute-thermal {
3965                         polling-delay-passive = <250>;
3966                         polling-delay = <1000>;
3967
3968                         thermal-sensors = <&tsens1 6>;
3969
3970                         trips {
3971                                 trip-point0 {
3972                                         temperature = <90000>;
3973                                         hysteresis = <2000>;
3974                                         type = "hot";
3975                                 };
3976                         };
3977                 };
3978
3979                 mdm-dsp-thermal {
3980                         polling-delay-passive = <250>;
3981                         polling-delay = <1000>;
3982
3983                         thermal-sensors = <&tsens1 7>;
3984
3985                         trips {
3986                                 trip-point0 {
3987                                         temperature = <90000>;
3988                                         hysteresis = <2000>;
3989                                         type = "hot";
3990                                 };
3991                         };
3992                 };
3993
3994                 npu-thermal {
3995                         polling-delay-passive = <250>;
3996                         polling-delay = <1000>;
3997
3998                         thermal-sensors = <&tsens1 8>;
3999
4000                         trips {
4001                                 trip-point0 {
4002                                         temperature = <90000>;
4003                                         hysteresis = <2000>;
4004                                         type = "hot";
4005                                 };
4006                         };
4007                 };
4008
4009                 gpu-thermal-bottom {
4010                         polling-delay-passive = <250>;
4011                         polling-delay = <1000>;
4012
4013                         thermal-sensors = <&tsens1 11>;
4014
4015                         trips {
4016                                 trip-point0 {
4017                                         temperature = <90000>;
4018                                         hysteresis = <2000>;
4019                                         type = "hot";
4020                                 };
4021                         };
4022                 };
4023         };
4024
4025         timer {
4026                 compatible = "arm,armv8-timer";
4027                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4028                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4029                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4030                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4031         };
4032 };