1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
9 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,osm-l3.h>
12 #include <dt-bindings/interconnect/qcom,sc8180x.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&intc>;
25 xo_board_clk: xo-board {
26 compatible = "fixed-clock";
28 clock-frequency = <38400000>;
31 sleep_clk: sleep-clk {
32 compatible = "fixed-clock";
34 clock-frequency = <32764>;
35 clock-output-names = "sleep_clk";
45 compatible = "qcom,kryo485";
47 enable-method = "psci";
48 capacity-dmips-mhz = <602>;
49 next-level-cache = <&L2_0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
51 operating-points-v2 = <&cpu0_opp_table>;
52 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
53 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
57 clocks = <&cpufreq_hw 0>;
63 next-level-cache = <&L3_0>;
74 compatible = "qcom,kryo485";
76 enable-method = "psci";
77 capacity-dmips-mhz = <602>;
78 next-level-cache = <&L2_100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 operating-points-v2 = <&cpu0_opp_table>;
81 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
86 clocks = <&cpufreq_hw 0>;
92 next-level-cache = <&L3_0>;
99 compatible = "qcom,kryo485";
101 enable-method = "psci";
102 capacity-dmips-mhz = <602>;
103 next-level-cache = <&L2_200>;
104 qcom,freq-domain = <&cpufreq_hw 0>;
105 operating-points-v2 = <&cpu0_opp_table>;
106 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
108 power-domains = <&CPU_PD2>;
109 power-domain-names = "psci";
110 #cooling-cells = <2>;
111 clocks = <&cpufreq_hw 0>;
114 compatible = "cache";
117 next-level-cache = <&L3_0>;
123 compatible = "qcom,kryo485";
125 enable-method = "psci";
126 capacity-dmips-mhz = <602>;
127 next-level-cache = <&L2_300>;
128 qcom,freq-domain = <&cpufreq_hw 0>;
129 operating-points-v2 = <&cpu0_opp_table>;
130 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
131 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
132 power-domains = <&CPU_PD3>;
133 power-domain-names = "psci";
134 #cooling-cells = <2>;
135 clocks = <&cpufreq_hw 0>;
138 compatible = "cache";
141 next-level-cache = <&L3_0>;
147 compatible = "qcom,kryo485";
149 enable-method = "psci";
150 capacity-dmips-mhz = <1024>;
151 next-level-cache = <&L2_400>;
152 qcom,freq-domain = <&cpufreq_hw 1>;
153 operating-points-v2 = <&cpu4_opp_table>;
154 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
156 power-domains = <&CPU_PD4>;
157 power-domain-names = "psci";
158 #cooling-cells = <2>;
159 clocks = <&cpufreq_hw 1>;
162 compatible = "cache";
165 next-level-cache = <&L3_0>;
171 compatible = "qcom,kryo485";
173 enable-method = "psci";
174 capacity-dmips-mhz = <1024>;
175 next-level-cache = <&L2_500>;
176 qcom,freq-domain = <&cpufreq_hw 1>;
177 operating-points-v2 = <&cpu4_opp_table>;
178 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
179 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
180 power-domains = <&CPU_PD5>;
181 power-domain-names = "psci";
182 #cooling-cells = <2>;
183 clocks = <&cpufreq_hw 1>;
186 compatible = "cache";
189 next-level-cache = <&L3_0>;
195 compatible = "qcom,kryo485";
197 enable-method = "psci";
198 capacity-dmips-mhz = <1024>;
199 next-level-cache = <&L2_600>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
201 operating-points-v2 = <&cpu4_opp_table>;
202 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
203 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
204 power-domains = <&CPU_PD6>;
205 power-domain-names = "psci";
206 #cooling-cells = <2>;
207 clocks = <&cpufreq_hw 1>;
210 compatible = "cache";
213 next-level-cache = <&L3_0>;
219 compatible = "qcom,kryo485";
221 enable-method = "psci";
222 capacity-dmips-mhz = <1024>;
223 next-level-cache = <&L2_700>;
224 qcom,freq-domain = <&cpufreq_hw 1>;
225 operating-points-v2 = <&cpu4_opp_table>;
226 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>,
227 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
228 power-domains = <&CPU_PD7>;
229 power-domain-names = "psci";
230 #cooling-cells = <2>;
231 clocks = <&cpufreq_hw 1>;
234 compatible = "cache";
237 next-level-cache = <&L3_0>;
278 entry-method = "psci";
280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
281 compatible = "arm,idle-state";
282 arm,psci-suspend-param = <0x40000004>;
283 entry-latency-us = <355>;
284 exit-latency-us = <909>;
285 min-residency-us = <3934>;
289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
290 compatible = "arm,idle-state";
291 arm,psci-suspend-param = <0x40000004>;
292 entry-latency-us = <241>;
293 exit-latency-us = <1461>;
294 min-residency-us = <4488>;
300 CLUSTER_SLEEP_0: cluster-sleep-0 {
301 compatible = "domain-idle-state";
302 arm,psci-suspend-param = <0x4100a344>;
303 entry-latency-us = <3263>;
304 exit-latency-us = <6562>;
305 min-residency-us = <9987>;
310 cpu0_opp_table: opp-table-cpu0 {
311 compatible = "operating-points-v2";
315 opp-hz = /bits/ 64 <300000000>;
316 opp-peak-kBps = <800000 9600000>;
320 opp-hz = /bits/ 64 <422400000>;
321 opp-peak-kBps = <800000 9600000>;
325 opp-hz = /bits/ 64 <537600000>;
326 opp-peak-kBps = <800000 12902400>;
330 opp-hz = /bits/ 64 <652800000>;
331 opp-peak-kBps = <800000 12902400>;
335 opp-hz = /bits/ 64 <768000000>;
336 opp-peak-kBps = <800000 15974400>;
340 opp-hz = /bits/ 64 <883200000>;
341 opp-peak-kBps = <1804000 19660800>;
345 opp-hz = /bits/ 64 <998400000>;
346 opp-peak-kBps = <1804000 19660800>;
350 opp-hz = /bits/ 64 <1113600000>;
351 opp-peak-kBps = <1804000 22732800>;
355 opp-hz = /bits/ 64 <1228800000>;
356 opp-peak-kBps = <1804000 22732800>;
360 opp-hz = /bits/ 64 <1363200000>;
361 opp-peak-kBps = <2188000 25804800>;
365 opp-hz = /bits/ 64 <1478400000>;
366 opp-peak-kBps = <2188000 31948800>;
370 opp-hz = /bits/ 64 <1574400000>;
371 opp-peak-kBps = <3072000 31948800>;
375 opp-hz = /bits/ 64 <1670400000>;
376 opp-peak-kBps = <3072000 31948800>;
380 opp-hz = /bits/ 64 <1766400000>;
381 opp-peak-kBps = <3072000 31948800>;
385 cpu4_opp_table: opp-table-cpu4 {
386 compatible = "operating-points-v2";
390 opp-hz = /bits/ 64 <825600000>;
391 opp-peak-kBps = <1804000 15974400>;
395 opp-hz = /bits/ 64 <940800000>;
396 opp-peak-kBps = <2188000 19660800>;
400 opp-hz = /bits/ 64 <1056000000>;
401 opp-peak-kBps = <2188000 22732800>;
405 opp-hz = /bits/ 64 <1171200000>;
406 opp-peak-kBps = <3072000 25804800>;
410 opp-hz = /bits/ 64 <1286400000>;
411 opp-peak-kBps = <3072000 31948800>;
415 opp-hz = /bits/ 64 <1420800000>;
416 opp-peak-kBps = <4068000 31948800>;
420 opp-hz = /bits/ 64 <1536000000>;
421 opp-peak-kBps = <4068000 31948800>;
425 opp-hz = /bits/ 64 <1651200000>;
426 opp-peak-kBps = <4068000 40550400>;
430 opp-hz = /bits/ 64 <1766400000>;
431 opp-peak-kBps = <4068000 40550400>;
435 opp-hz = /bits/ 64 <1881600000>;
436 opp-peak-kBps = <4068000 43008000>;
440 opp-hz = /bits/ 64 <1996800000>;
441 opp-peak-kBps = <6220000 43008000>;
445 opp-hz = /bits/ 64 <2131200000>;
446 opp-peak-kBps = <6220000 49152000>;
450 opp-hz = /bits/ 64 <2246400000>;
451 opp-peak-kBps = <7216000 49152000>;
455 opp-hz = /bits/ 64 <2361600000>;
456 opp-peak-kBps = <8368000 49152000>;
460 opp-hz = /bits/ 64 <2457600000>;
461 opp-peak-kBps = <8368000 51609600>;
465 opp-hz = /bits/ 64 <2553600000>;
466 opp-peak-kBps = <8368000 51609600>;
470 opp-hz = /bits/ 64 <2649600000>;
471 opp-peak-kBps = <8368000 51609600>;
475 opp-hz = /bits/ 64 <2745600000>;
476 opp-peak-kBps = <8368000 51609600>;
480 opp-hz = /bits/ 64 <2841600000>;
481 opp-peak-kBps = <8368000 51609600>;
485 opp-hz = /bits/ 64 <2918400000>;
486 opp-peak-kBps = <8368000 51609600>;
490 opp-hz = /bits/ 64 <2995200000>;
491 opp-peak-kBps = <8368000 51609600>;
497 compatible = "qcom,scm-sc8180x", "qcom,scm";
501 camnoc_virt: interconnect-camnoc-virt {
502 compatible = "qcom,sc8180x-camnoc-virt";
503 #interconnect-cells = <2>;
504 qcom,bcm-voters = <&apps_bcm_voter>;
507 mc_virt: interconnect-mc-virt {
508 compatible = "qcom,sc8180x-mc-virt";
509 #interconnect-cells = <2>;
510 qcom,bcm-voters = <&apps_bcm_voter>;
513 qup_virt: interconnect-qup-virt {
514 compatible = "qcom,sc8180x-qup-virt";
515 #interconnect-cells = <2>;
516 qcom,bcm-voters = <&apps_bcm_voter>;
520 device_type = "memory";
521 /* We expect the bootloader to fill in the size */
522 reg = <0x0 0x80000000 0x0 0x0>;
526 compatible = "arm,armv8-pmuv3";
527 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
531 compatible = "arm,psci-1.0";
534 CPU_PD0: power-domain-cpu0 {
535 #power-domain-cells = <0>;
536 power-domains = <&CLUSTER_PD>;
537 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
540 CPU_PD1: power-domain-cpu1 {
541 #power-domain-cells = <0>;
542 power-domains = <&CLUSTER_PD>;
543 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
546 CPU_PD2: power-domain-cpu2 {
547 #power-domain-cells = <0>;
548 power-domains = <&CLUSTER_PD>;
549 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
552 CPU_PD3: power-domain-cpu3 {
553 #power-domain-cells = <0>;
554 power-domains = <&CLUSTER_PD>;
555 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
558 CPU_PD4: power-domain-cpu4 {
559 #power-domain-cells = <0>;
560 power-domains = <&CLUSTER_PD>;
561 domain-idle-states = <&BIG_CPU_SLEEP_0>;
564 CPU_PD5: power-domain-cpu5 {
565 #power-domain-cells = <0>;
566 power-domains = <&CLUSTER_PD>;
567 domain-idle-states = <&BIG_CPU_SLEEP_0>;
570 CPU_PD6: power-domain-cpu6 {
571 #power-domain-cells = <0>;
572 power-domains = <&CLUSTER_PD>;
573 domain-idle-states = <&BIG_CPU_SLEEP_0>;
576 CPU_PD7: power-domain-cpu7 {
577 #power-domain-cells = <0>;
578 power-domains = <&CLUSTER_PD>;
579 domain-idle-states = <&BIG_CPU_SLEEP_0>;
582 CLUSTER_PD: power-domain-cpu-cluster0 {
583 #power-domain-cells = <0>;
584 domain-idle-states = <&CLUSTER_SLEEP_0>;
589 #address-cells = <2>;
593 hyp_mem: hyp@85700000 {
594 reg = <0x0 0x85700000 0x0 0x600000>;
598 xbl_mem: xbl@85d00000 {
599 reg = <0x0 0x85d00000 0x0 0x140000>;
603 aop_mem: aop@85f00000 {
604 reg = <0x0 0x85f00000 0x0 0x20000>;
608 aop_cmd_db: cmd-db@85f20000 {
609 compatible = "qcom,cmd-db";
610 reg = <0x0 0x85f20000 0x0 0x20000>;
615 reg = <0x0 0x85f40000 0x0 0x10000>;
619 smem_mem: smem@86000000 {
620 compatible = "qcom,smem";
621 reg = <0x0 0x86000000 0x0 0x200000>;
623 hwlocks = <&tcsr_mutex 3>;
627 reg = <0x0 0x86200000 0x0 0x3900000>;
632 reg = <0x0 0x89b00000 0x0 0x1c00000>;
637 reg = <0x0 0x9d400000 0x0 0x1000000>;
642 reg = <0x0 0x9e400000 0x0 0x1400000>;
647 reg = <0x0 0x9f800000 0x0 0x800000>;
653 compatible = "qcom,smp2p";
654 qcom,smem = <94>, <432>;
656 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
658 mboxes = <&apss_shared 6>;
660 qcom,local-pid = <0>;
661 qcom,remote-pid = <5>;
663 cdsp_smp2p_out: master-kernel {
664 qcom,entry-name = "master-kernel";
665 #qcom,smem-state-cells = <1>;
668 cdsp_smp2p_in: slave-kernel {
669 qcom,entry-name = "slave-kernel";
671 interrupt-controller;
672 #interrupt-cells = <2>;
677 compatible = "qcom,smp2p";
678 qcom,smem = <443>, <429>;
680 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
682 mboxes = <&apss_shared 10>;
684 qcom,local-pid = <0>;
685 qcom,remote-pid = <2>;
687 adsp_smp2p_out: master-kernel {
688 qcom,entry-name = "master-kernel";
689 #qcom,smem-state-cells = <1>;
692 adsp_smp2p_in: slave-kernel {
693 qcom,entry-name = "slave-kernel";
695 interrupt-controller;
696 #interrupt-cells = <2>;
701 compatible = "qcom,smp2p";
702 qcom,smem = <435>, <428>;
704 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
706 mboxes = <&apss_shared 14>;
708 qcom,local-pid = <0>;
709 qcom,remote-pid = <1>;
711 modem_smp2p_out: master-kernel {
712 qcom,entry-name = "master-kernel";
713 #qcom,smem-state-cells = <1>;
716 modem_smp2p_in: slave-kernel {
717 qcom,entry-name = "slave-kernel";
719 interrupt-controller;
720 #interrupt-cells = <2>;
723 modem_smp2p_ipa_out: ipa-ap-to-modem {
724 qcom,entry-name = "ipa";
725 #qcom,smem-state-cells = <1>;
728 modem_smp2p_ipa_in: ipa-modem-to-ap {
729 qcom,entry-name = "ipa";
730 interrupt-controller;
731 #interrupt-cells = <2>;
734 modem_smp2p_wlan_in: wlan-wpss-to-ap {
735 qcom,entry-name = "wlan";
736 interrupt-controller;
737 #interrupt-cells = <2>;
742 compatible = "qcom,smp2p";
743 qcom,smem = <481>, <430>;
745 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
747 mboxes = <&apss_shared 26>;
749 qcom,local-pid = <0>;
750 qcom,remote-pid = <3>;
752 slpi_smp2p_out: master-kernel {
753 qcom,entry-name = "master-kernel";
754 #qcom,smem-state-cells = <1>;
757 slpi_smp2p_in: slave-kernel {
758 qcom,entry-name = "slave-kernel";
760 interrupt-controller;
761 #interrupt-cells = <2>;
766 compatible = "simple-bus";
767 #address-cells = <2>;
769 ranges = <0 0 0 0 0x10 0>;
770 dma-ranges = <0 0 0 0 0x10 0>;
772 gcc: clock-controller@100000 {
773 compatible = "qcom,gcc-sc8180x";
774 reg = <0x0 0x00100000 0x0 0x1f0000>;
777 #power-domain-cells = <1>;
778 clocks = <&rpmhcc RPMH_CXO_CLK>,
779 <&rpmhcc RPMH_CXO_CLK_A>,
781 clock-names = "bi_tcxo",
786 qupv3_id_0: geniqup@8c0000 {
787 compatible = "qcom,geni-se-qup";
788 reg = <0 0x008c0000 0 0x6000>;
789 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
790 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
791 clock-names = "m-ahb", "s-ahb";
792 #address-cells = <2>;
795 iommus = <&apps_smmu 0x4c3 0>;
799 compatible = "qcom,geni-i2c";
800 reg = <0 0x00880000 0 0x4000>;
801 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
803 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
805 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
806 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
807 interconnect-names = "qup-core", "qup-config", "qup-memory";
808 #address-cells = <1>;
814 compatible = "qcom,geni-spi";
815 reg = <0 0x00880000 0 0x4000>;
816 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
820 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
821 interconnect-names = "qup-core", "qup-config";
822 #address-cells = <1>;
827 uart0: serial@880000 {
828 compatible = "qcom,geni-uart";
829 reg = <0 0x00880000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
832 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
834 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
835 interconnect-names = "qup-core", "qup-config";
840 compatible = "qcom,geni-i2c";
841 reg = <0 0x00884000 0 0x4000>;
842 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
844 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
847 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
848 interconnect-names = "qup-core", "qup-config", "qup-memory";
849 #address-cells = <1>;
855 compatible = "qcom,geni-spi";
856 reg = <0 0x00884000 0 0x4000>;
857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
860 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
861 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
862 interconnect-names = "qup-core", "qup-config";
863 #address-cells = <1>;
868 uart1: serial@884000 {
869 compatible = "qcom,geni-uart";
870 reg = <0 0x00884000 0 0x4000>;
871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
873 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
876 interconnect-names = "qup-core", "qup-config";
881 compatible = "qcom,geni-i2c";
882 reg = <0 0x00888000 0 0x4000>;
883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
885 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
886 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
888 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
889 interconnect-names = "qup-core", "qup-config", "qup-memory";
890 #address-cells = <1>;
896 compatible = "qcom,geni-spi";
897 reg = <0 0x00888000 0 0x4000>;
898 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
900 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
901 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
902 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
903 interconnect-names = "qup-core", "qup-config";
904 #address-cells = <1>;
909 uart2: serial@888000 {
910 compatible = "qcom,geni-uart";
911 reg = <0 0x00888000 0 0x4000>;
912 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
915 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
916 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
917 interconnect-names = "qup-core", "qup-config";
922 compatible = "qcom,geni-i2c";
923 reg = <0 0x0088c000 0 0x4000>;
924 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
928 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
929 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
930 interconnect-names = "qup-core", "qup-config", "qup-memory";
931 #address-cells = <1>;
937 compatible = "qcom,geni-spi";
938 reg = <0 0x0088c000 0 0x4000>;
939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
941 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
942 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
943 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
944 interconnect-names = "qup-core", "qup-config";
945 #address-cells = <1>;
950 uart3: serial@88c000 {
951 compatible = "qcom,geni-uart";
952 reg = <0 0x0088c000 0 0x4000>;
953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
955 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
958 interconnect-names = "qup-core", "qup-config";
963 compatible = "qcom,geni-i2c";
964 reg = <0 0x00890000 0 0x4000>;
965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
967 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
968 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
969 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
970 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
971 interconnect-names = "qup-core", "qup-config", "qup-memory";
972 #address-cells = <1>;
978 compatible = "qcom,geni-spi";
979 reg = <0 0x00890000 0 0x4000>;
980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
982 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
983 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
984 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
985 interconnect-names = "qup-core", "qup-config";
986 #address-cells = <1>;
991 uart4: serial@890000 {
992 compatible = "qcom,geni-uart";
993 reg = <0 0x00890000 0 0x4000>;
994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
996 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
998 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
999 interconnect-names = "qup-core", "qup-config";
1000 status = "disabled";
1004 compatible = "qcom,geni-i2c";
1005 reg = <0 0x00894000 0 0x4000>;
1006 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1008 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1011 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1012 interconnect-names = "qup-core", "qup-config", "qup-memory";
1013 #address-cells = <1>;
1015 status = "disabled";
1019 compatible = "qcom,geni-spi";
1020 reg = <0 0x00894000 0 0x4000>;
1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1023 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1026 interconnect-names = "qup-core", "qup-config";
1027 #address-cells = <1>;
1029 status = "disabled";
1032 uart5: serial@894000 {
1033 compatible = "qcom,geni-uart";
1034 reg = <0 0x00894000 0 0x4000>;
1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1039 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1040 interconnect-names = "qup-core", "qup-config";
1041 status = "disabled";
1045 compatible = "qcom,geni-i2c";
1046 reg = <0 0x00898000 0 0x4000>;
1047 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1049 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1050 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1052 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1053 interconnect-names = "qup-core", "qup-config", "qup-memory";
1054 #address-cells = <1>;
1056 status = "disabled";
1060 compatible = "qcom,geni-spi";
1061 reg = <0 0x00898000 0 0x4000>;
1062 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1064 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1067 interconnect-names = "qup-core", "qup-config";
1068 #address-cells = <1>;
1070 status = "disabled";
1073 uart6: serial@898000 {
1074 compatible = "qcom,geni-uart";
1075 reg = <0 0x00898000 0 0x4000>;
1076 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1078 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1081 interconnect-names = "qup-core", "qup-config";
1082 status = "disabled";
1086 compatible = "qcom,geni-i2c";
1087 reg = <0 0x0089c000 0 0x4000>;
1088 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1090 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1092 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
1093 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
1094 interconnect-names = "qup-core", "qup-config", "qup-memory";
1095 #address-cells = <1>;
1097 status = "disabled";
1101 compatible = "qcom,geni-spi";
1102 reg = <0 0x0089c000 0 0x4000>;
1103 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1105 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1108 interconnect-names = "qup-core", "qup-config";
1109 #address-cells = <1>;
1111 status = "disabled";
1114 uart7: serial@89c000 {
1115 compatible = "qcom,geni-uart";
1116 reg = <0 0x0089c000 0 0x4000>;
1117 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1119 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1120 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1121 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
1122 interconnect-names = "qup-core", "qup-config";
1123 status = "disabled";
1127 qupv3_id_1: geniqup@ac0000 {
1128 compatible = "qcom,geni-se-qup";
1129 reg = <0x0 0x00ac0000 0x0 0x6000>;
1130 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1131 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1132 clock-names = "m-ahb", "s-ahb";
1133 #address-cells = <2>;
1136 iommus = <&apps_smmu 0x603 0>;
1137 status = "disabled";
1140 compatible = "qcom,geni-i2c";
1141 reg = <0 0x00a80000 0 0x4000>;
1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1144 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1145 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1147 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1148 interconnect-names = "qup-core", "qup-config", "qup-memory";
1149 #address-cells = <1>;
1151 status = "disabled";
1155 compatible = "qcom,geni-spi";
1156 reg = <0 0x00a80000 0 0x4000>;
1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1159 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1160 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1161 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1162 interconnect-names = "qup-core", "qup-config";
1163 #address-cells = <1>;
1165 status = "disabled";
1168 uart8: serial@a80000 {
1169 compatible = "qcom,geni-uart";
1170 reg = <0 0x00a80000 0 0x4000>;
1171 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1173 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1176 interconnect-names = "qup-core", "qup-config";
1177 status = "disabled";
1181 compatible = "qcom,geni-i2c";
1182 reg = <0 0x00a84000 0 0x4000>;
1183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1185 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1187 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1188 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1189 interconnect-names = "qup-core", "qup-config", "qup-memory";
1190 #address-cells = <1>;
1192 status = "disabled";
1196 compatible = "qcom,geni-spi";
1197 reg = <0 0x00a84000 0 0x4000>;
1198 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1202 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1203 interconnect-names = "qup-core", "qup-config";
1204 #address-cells = <1>;
1206 status = "disabled";
1209 uart9: serial@a84000 {
1210 compatible = "qcom,geni-debug-uart";
1211 reg = <0 0x00a84000 0 0x4000>;
1212 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1214 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1215 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1217 interconnect-names = "qup-core", "qup-config";
1218 status = "disabled";
1222 compatible = "qcom,geni-i2c";
1223 reg = <0 0x00a88000 0 0x4000>;
1224 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1226 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1230 interconnect-names = "qup-core", "qup-config", "qup-memory";
1231 #address-cells = <1>;
1233 status = "disabled";
1237 compatible = "qcom,geni-spi";
1238 reg = <0 0x00a88000 0 0x4000>;
1239 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1241 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1242 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1244 interconnect-names = "qup-core", "qup-config";
1245 #address-cells = <1>;
1247 status = "disabled";
1250 uart10: serial@a88000 {
1251 compatible = "qcom,geni-uart";
1252 reg = <0 0x00a88000 0 0x4000>;
1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1255 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1257 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1258 interconnect-names = "qup-core", "qup-config";
1259 status = "disabled";
1263 compatible = "qcom,geni-i2c";
1264 reg = <0 0x00a8c000 0 0x4000>;
1265 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1267 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1269 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1270 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1271 interconnect-names = "qup-core", "qup-config", "qup-memory";
1272 #address-cells = <1>;
1274 status = "disabled";
1278 compatible = "qcom,geni-spi";
1279 reg = <0 0x00a8c000 0 0x4000>;
1280 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1283 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1284 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1285 interconnect-names = "qup-core", "qup-config";
1286 #address-cells = <1>;
1288 status = "disabled";
1291 uart11: serial@a8c000 {
1292 compatible = "qcom,geni-uart";
1293 reg = <0 0x00a8c000 0 0x4000>;
1294 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1297 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1298 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1299 interconnect-names = "qup-core", "qup-config";
1300 status = "disabled";
1304 compatible = "qcom,geni-i2c";
1305 reg = <0 0x00a90000 0 0x4000>;
1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1312 interconnect-names = "qup-core", "qup-config", "qup-memory";
1313 #address-cells = <1>;
1315 status = "disabled";
1319 compatible = "qcom,geni-spi";
1320 reg = <0 0x00a90000 0 0x4000>;
1321 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1323 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1325 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1326 interconnect-names = "qup-core", "qup-config";
1327 #address-cells = <1>;
1329 status = "disabled";
1332 uart12: serial@a90000 {
1333 compatible = "qcom,geni-uart";
1334 reg = <0 0x00a90000 0 0x4000>;
1335 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1337 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1339 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1340 interconnect-names = "qup-core", "qup-config";
1341 status = "disabled";
1345 compatible = "qcom,geni-i2c";
1346 reg = <0 0x00a94000 0 0x4000>;
1347 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1349 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1350 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1351 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
1352 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
1353 interconnect-names = "qup-core", "qup-config", "qup-memory";
1354 #address-cells = <1>;
1356 status = "disabled";
1360 compatible = "qcom,geni-spi";
1361 reg = <0 0x00a94000 0 0x4000>;
1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1364 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1365 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1366 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1367 interconnect-names = "qup-core", "qup-config";
1368 #address-cells = <1>;
1370 status = "disabled";
1373 uart16: serial@a94000 {
1374 compatible = "qcom,geni-uart";
1375 reg = <0 0x00a94000 0 0x4000>;
1376 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1379 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
1381 interconnect-names = "qup-core", "qup-config";
1382 status = "disabled";
1386 qupv3_id_2: geniqup@cc0000 {
1387 compatible = "qcom,geni-se-qup";
1388 reg = <0x0 0x00cc0000 0x0 0x6000>;
1389 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
1390 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
1391 clock-names = "m-ahb", "s-ahb";
1392 #address-cells = <2>;
1395 iommus = <&apps_smmu 0x7a3 0>;
1396 status = "disabled";
1399 compatible = "qcom,geni-i2c";
1400 reg = <0 0x00c80000 0 0x4000>;
1401 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1403 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1404 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1405 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1406 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1407 interconnect-names = "qup-core", "qup-config", "qup-memory";
1408 #address-cells = <1>;
1410 status = "disabled";
1414 compatible = "qcom,geni-spi";
1415 reg = <0 0x00c80000 0 0x4000>;
1416 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1418 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1419 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1421 interconnect-names = "qup-core", "qup-config";
1422 #address-cells = <1>;
1424 status = "disabled";
1427 uart17: serial@c80000 {
1428 compatible = "qcom,geni-uart";
1429 reg = <0 0x00c80000 0 0x4000>;
1430 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1432 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1433 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1434 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1435 interconnect-names = "qup-core", "qup-config";
1436 status = "disabled";
1440 compatible = "qcom,geni-i2c";
1441 reg = <0 0x00c84000 0 0x4000>;
1442 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1444 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1445 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1446 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1447 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1448 interconnect-names = "qup-core", "qup-config", "qup-memory";
1449 #address-cells = <1>;
1451 status = "disabled";
1455 compatible = "qcom,geni-spi";
1456 reg = <0 0x00c84000 0 0x4000>;
1457 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1459 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1460 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1461 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1462 interconnect-names = "qup-core", "qup-config";
1463 #address-cells = <1>;
1465 status = "disabled";
1468 uart18: serial@c84000 {
1469 compatible = "qcom,geni-uart";
1470 reg = <0 0x00c84000 0 0x4000>;
1471 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1473 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
1474 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1475 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1476 interconnect-names = "qup-core", "qup-config";
1477 status = "disabled";
1481 compatible = "qcom,geni-i2c";
1482 reg = <0 0x00c88000 0 0x4000>;
1483 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1485 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1486 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1488 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1489 interconnect-names = "qup-core", "qup-config", "qup-memory";
1490 #address-cells = <1>;
1492 status = "disabled";
1496 compatible = "qcom,geni-spi";
1497 reg = <0 0x00c88000 0 0x4000>;
1498 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1500 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1501 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1502 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1503 interconnect-names = "qup-core", "qup-config";
1504 #address-cells = <1>;
1506 status = "disabled";
1509 uart19: serial@c88000 {
1510 compatible = "qcom,geni-uart";
1511 reg = <0 0x00c88000 0 0x4000>;
1512 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1514 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
1515 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1516 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1517 interconnect-names = "qup-core", "qup-config";
1518 status = "disabled";
1522 compatible = "qcom,geni-i2c";
1523 reg = <0 0x00c8c000 0 0x4000>;
1524 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1526 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1527 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1529 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1530 interconnect-names = "qup-core", "qup-config", "qup-memory";
1531 #address-cells = <1>;
1533 status = "disabled";
1537 compatible = "qcom,geni-spi";
1538 reg = <0 0x00c8c000 0 0x4000>;
1539 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1541 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1542 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1543 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1544 interconnect-names = "qup-core", "qup-config";
1545 #address-cells = <1>;
1547 status = "disabled";
1550 uart13: serial@c8c000 {
1551 compatible = "qcom,geni-uart";
1552 reg = <0 0x00c8c000 0 0x4000>;
1553 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1555 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1556 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1557 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1558 interconnect-names = "qup-core", "qup-config";
1559 status = "disabled";
1563 compatible = "qcom,geni-i2c";
1564 reg = <0 0x00c90000 0 0x4000>;
1565 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1567 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1568 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1570 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1571 interconnect-names = "qup-core", "qup-config", "qup-memory";
1572 #address-cells = <1>;
1574 status = "disabled";
1578 compatible = "qcom,geni-spi";
1579 reg = <0 0x00c90000 0 0x4000>;
1580 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1582 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1583 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1584 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1585 interconnect-names = "qup-core", "qup-config";
1586 #address-cells = <1>;
1588 status = "disabled";
1591 uart14: serial@c90000 {
1592 compatible = "qcom,geni-uart";
1593 reg = <0 0x00c90000 0 0x4000>;
1594 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1596 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1597 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1598 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1599 interconnect-names = "qup-core", "qup-config";
1600 status = "disabled";
1604 compatible = "qcom,geni-i2c";
1605 reg = <0 0x00c94000 0 0x4000>;
1606 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1608 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1609 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1610 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
1611 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
1612 interconnect-names = "qup-core", "qup-config", "qup-memory";
1613 #address-cells = <1>;
1615 status = "disabled";
1619 compatible = "qcom,geni-spi";
1620 reg = <0 0x00c94000 0 0x4000>;
1621 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1623 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1624 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1625 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1626 interconnect-names = "qup-core", "qup-config";
1627 #address-cells = <1>;
1629 status = "disabled";
1632 uart15: serial@c94000 {
1633 compatible = "qcom,geni-uart";
1634 reg = <0 0x00c94000 0 0x4000>;
1635 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1637 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1638 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
1640 interconnect-names = "qup-core", "qup-config";
1641 status = "disabled";
1645 config_noc: interconnect@1500000 {
1646 compatible = "qcom,sc8180x-config-noc";
1647 reg = <0 0x01500000 0 0x7400>;
1648 #interconnect-cells = <2>;
1649 qcom,bcm-voters = <&apps_bcm_voter>;
1652 system_noc: interconnect@1620000 {
1653 compatible = "qcom,sc8180x-system-noc";
1654 reg = <0 0x01620000 0 0x19400>;
1655 #interconnect-cells = <2>;
1656 qcom,bcm-voters = <&apps_bcm_voter>;
1659 aggre1_noc: interconnect@16e0000 {
1660 compatible = "qcom,sc8180x-aggre1-noc";
1661 reg = <0 0x016e0000 0 0xd080>;
1662 #interconnect-cells = <2>;
1663 qcom,bcm-voters = <&apps_bcm_voter>;
1666 aggre2_noc: interconnect@1700000 {
1667 compatible = "qcom,sc8180x-aggre2-noc";
1668 reg = <0 0x01700000 0 0x20000>;
1669 #interconnect-cells = <2>;
1670 qcom,bcm-voters = <&apps_bcm_voter>;
1673 compute_noc: interconnect@1720000 {
1674 compatible = "qcom,sc8180x-compute-noc";
1675 reg = <0 0x01720000 0 0x7000>;
1676 #interconnect-cells = <2>;
1677 qcom,bcm-voters = <&apps_bcm_voter>;
1680 mmss_noc: interconnect@1740000 {
1681 compatible = "qcom,sc8180x-mmss-noc";
1682 reg = <0 0x01740000 0 0x1c100>;
1683 #interconnect-cells = <2>;
1684 qcom,bcm-voters = <&apps_bcm_voter>;
1687 pcie0: pci@1c00000 {
1688 compatible = "qcom,pcie-sc8180x";
1689 reg = <0 0x01c00000 0 0x3000>,
1690 <0 0x60000000 0 0xf1d>,
1691 <0 0x60000f20 0 0xa8>,
1692 <0 0x60001000 0 0x1000>,
1693 <0 0x60100000 0 0x100000>;
1699 device_type = "pci";
1700 linux,pci-domain = <0>;
1701 bus-range = <0x00 0xff>;
1704 #address-cells = <3>;
1707 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1710 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1711 interrupt-names = "msi";
1712 #interrupt-cells = <1>;
1713 interrupt-map-mask = <0 0 0 0x7>;
1714 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1715 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1716 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1717 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1719 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1720 <&gcc GCC_PCIE_0_AUX_CLK>,
1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1722 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1723 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
1724 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
1725 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1726 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1727 clock-names = "pipe",
1736 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1737 assigned-clock-rates = <19200000>;
1739 iommus = <&apps_smmu 0x1d80 0x7f>;
1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1741 <0x100 &apps_smmu 0x1d81 0x1>;
1743 resets = <&gcc GCC_PCIE_0_BCR>;
1744 reset-names = "pci";
1746 power-domains = <&gcc PCIE_0_GDSC>;
1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1750 interconnect-names = "pcie-mem", "cpu-pcie";
1752 phys = <&pcie0_lane>;
1753 phy-names = "pciephy";
1755 status = "disabled";
1758 pcie0_phy: phy-wrapper@1c06000 {
1759 compatible = "qcom,sc8180x-qmp-pcie-phy";
1760 reg = <0 0x1c06000 0 0x1c0>;
1761 #address-cells = <2>;
1764 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1765 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1766 <&gcc GCC_PCIE_0_CLKREF_CLK>,
1767 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1768 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1770 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1771 reset-names = "phy";
1773 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1774 assigned-clock-rates = <100000000>;
1776 status = "disabled";
1778 pcie0_lane: phy@1c06200 {
1779 reg = <0 0x1c06200 0 0x170>, /* tx0 */
1780 <0 0x1c06400 0 0x200>, /* rx0 */
1781 <0 0x1c06a00 0 0x1f0>, /* pcs */
1782 <0 0x1c06600 0 0x170>, /* tx1 */
1783 <0 0x1c06800 0 0x200>, /* rx1 */
1784 <0 0x1c06e00 0 0xf4>; /* pcs_com */
1785 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1786 clock-names = "pipe0";
1789 clock-output-names = "pcie_0_pipe_clk";
1794 pcie3: pci@1c08000 {
1795 compatible = "qcom,pcie-sc8180x";
1796 reg = <0 0x01c08000 0 0x3000>,
1797 <0 0x40000000 0 0xf1d>,
1798 <0 0x40000f20 0 0xa8>,
1799 <0 0x40001000 0 0x1000>,
1800 <0 0x40100000 0 0x100000>;
1806 device_type = "pci";
1807 linux,pci-domain = <3>;
1808 bus-range = <0x00 0xff>;
1811 #address-cells = <3>;
1814 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
1815 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1817 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
1818 interrupt-names = "msi";
1819 #interrupt-cells = <1>;
1820 interrupt-map-mask = <0 0 0 0x7>;
1821 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1822 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1823 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1824 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1826 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>,
1827 <&gcc GCC_PCIE_3_AUX_CLK>,
1828 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1829 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
1830 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
1831 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
1832 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1833 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1834 clock-names = "pipe",
1843 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1844 assigned-clock-rates = <19200000>;
1846 iommus = <&apps_smmu 0x1e00 0x7f>;
1847 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1848 <0x100 &apps_smmu 0x1e01 0x1>;
1850 resets = <&gcc GCC_PCIE_3_BCR>;
1851 reset-names = "pci";
1853 power-domains = <&gcc PCIE_3_GDSC>;
1855 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>,
1856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1857 interconnect-names = "pcie-mem", "cpu-pcie";
1859 phys = <&pcie3_lane>;
1860 phy-names = "pciephy";
1862 status = "disabled";
1865 pcie3_phy: phy-wrapper@1c0c000 {
1866 compatible = "qcom,sc8180x-qmp-pcie-phy";
1867 reg = <0 0x1c0c000 0 0x1c0>;
1868 #address-cells = <2>;
1871 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1872 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
1873 <&gcc GCC_PCIE_3_CLKREF_CLK>,
1874 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
1875 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1877 resets = <&gcc GCC_PCIE_3_PHY_BCR>;
1878 reset-names = "phy";
1880 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1881 assigned-clock-rates = <100000000>;
1883 status = "disabled";
1885 pcie3_lane: phy@1c0c200 {
1886 reg = <0 0x1c0c200 0 0x170>, /* tx0 */
1887 <0 0x1c0c400 0 0x200>, /* rx0 */
1888 <0 0x1c0ca00 0 0x1f0>, /* pcs */
1889 <0 0x1c0c600 0 0x170>, /* tx1 */
1890 <0 0x1c0c800 0 0x200>, /* rx1 */
1891 <0 0x1c0ce00 0 0xf4>; /* pcs_com */
1892 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>;
1893 clock-names = "pipe0";
1896 clock-output-names = "pcie_3_pipe_clk";
1901 pcie1: pci@1c10000 {
1902 compatible = "qcom,pcie-sc8180x";
1903 reg = <0 0x01c10000 0 0x3000>,
1904 <0 0x68000000 0 0xf1d>,
1905 <0 0x68000f20 0 0xa8>,
1906 <0 0x68001000 0 0x1000>,
1907 <0 0x68100000 0 0x100000>;
1913 device_type = "pci";
1914 linux,pci-domain = <1>;
1915 bus-range = <0x00 0xff>;
1918 #address-cells = <3>;
1921 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
1922 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
1924 interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>;
1925 interrupt-names = "msi";
1926 #interrupt-cells = <1>;
1927 interrupt-map-mask = <0 0 0 0x7>;
1928 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1929 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1930 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1931 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1933 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1934 <&gcc GCC_PCIE_1_AUX_CLK>,
1935 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1936 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1937 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
1938 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
1939 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1940 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
1941 clock-names = "pipe",
1950 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
1951 assigned-clock-rates = <19200000>;
1953 iommus = <&apps_smmu 0x1c80 0x7f>;
1954 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1955 <0x100 &apps_smmu 0x1c81 0x1>;
1957 resets = <&gcc GCC_PCIE_1_BCR>;
1958 reset-names = "pci";
1960 power-domains = <&gcc PCIE_1_GDSC>;
1962 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>,
1963 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
1964 interconnect-names = "pcie-mem", "cpu-pcie";
1966 phys = <&pcie1_lane>;
1967 phy-names = "pciephy";
1969 status = "disabled";
1972 pcie1_phy: phy-wrapper@1c16000 {
1973 compatible = "qcom,sc8180x-qmp-pcie-phy";
1974 reg = <0 0x1c16000 0 0x1c0>;
1975 #address-cells = <2>;
1978 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1979 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1980 <&gcc GCC_PCIE_1_CLKREF_CLK>,
1981 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1982 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1984 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1985 reset-names = "phy";
1987 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
1988 assigned-clock-rates = <100000000>;
1990 status = "disabled";
1992 pcie1_lane: phy@1c0e200 {
1993 reg = <0 0x1c16200 0 0x170>, /* tx0 */
1994 <0 0x1c16400 0 0x200>, /* rx0 */
1995 <0 0x1c16a00 0 0x1f0>, /* pcs */
1996 <0 0x1c16600 0 0x170>, /* tx1 */
1997 <0 0x1c16800 0 0x200>, /* rx1 */
1998 <0 0x1c16e00 0 0xf4>; /* pcs_com */
1999 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2000 clock-names = "pipe0";
2002 clock-output-names = "pcie_1_pipe_clk";
2008 pcie2: pci@1c18000 {
2009 compatible = "qcom,pcie-sc8180x";
2010 reg = <0 0x01c18000 0 0x3000>,
2011 <0 0x70000000 0 0xf1d>,
2012 <0 0x70000f20 0 0xa8>,
2013 <0 0x70001000 0 0x1000>,
2014 <0 0x70100000 0 0x100000>;
2020 device_type = "pci";
2021 linux,pci-domain = <2>;
2022 bus-range = <0x00 0xff>;
2025 #address-cells = <3>;
2028 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>,
2029 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
2031 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>;
2032 interrupt-names = "msi";
2033 #interrupt-cells = <1>;
2034 interrupt-map-mask = <0 0 0 0x7>;
2035 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2036 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
2037 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
2038 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
2040 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
2041 <&gcc GCC_PCIE_2_AUX_CLK>,
2042 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2043 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2044 <&gcc GCC_PCIE_2_SLV_AXI_CLK>,
2045 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
2046 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2047 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
2048 clock-names = "pipe",
2057 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2058 assigned-clock-rates = <19200000>;
2060 iommus = <&apps_smmu 0x1d00 0x7f>;
2061 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2062 <0x100 &apps_smmu 0x1d01 0x1>;
2064 resets = <&gcc GCC_PCIE_2_BCR>;
2065 reset-names = "pci";
2067 power-domains = <&gcc PCIE_2_GDSC>;
2069 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>,
2070 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
2071 interconnect-names = "pcie-mem", "cpu-pcie";
2073 phys = <&pcie2_lane>;
2074 phy-names = "pciephy";
2076 status = "disabled";
2079 pcie2_phy: phy-wrapper@1c1c000 {
2080 compatible = "qcom,sc8180x-qmp-pcie-phy";
2081 reg = <0 0x1c1c000 0 0x1c0>;
2082 #address-cells = <2>;
2085 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
2086 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
2087 <&gcc GCC_PCIE_2_CLKREF_CLK>,
2088 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2089 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2091 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
2092 reset-names = "phy";
2094 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2095 assigned-clock-rates = <100000000>;
2097 status = "disabled";
2099 pcie2_lane: phy@1c0e200 {
2100 reg = <0 0x1c1c200 0 0x170>, /* tx0 */
2101 <0 0x1c1c400 0 0x200>, /* rx0 */
2102 <0 0x1c1ca00 0 0x1f0>, /* pcs */
2103 <0 0x1c1c600 0 0x170>, /* tx1 */
2104 <0 0x1c1c800 0 0x200>, /* rx1 */
2105 <0 0x1c1ce00 0 0xf4>; /* pcs_com */
2106 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
2107 clock-names = "pipe0";
2110 clock-output-names = "pcie_2_pipe_clk";
2116 ufs_mem_hc: ufshc@1d84000 {
2117 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2119 reg = <0 0x01d84000 0 0x2500>;
2120 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2121 phys = <&ufs_mem_phy_lanes>;
2122 phy-names = "ufsphy";
2123 lanes-per-direction = <2>;
2125 resets = <&gcc GCC_UFS_PHY_BCR>;
2126 reset-names = "rst";
2128 iommus = <&apps_smmu 0x300 0>;
2130 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2131 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2132 <&gcc GCC_UFS_PHY_AHB_CLK>,
2133 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2134 <&rpmhcc RPMH_CXO_CLK>,
2135 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2136 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2137 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2138 clock-names = "core_clk",
2143 "tx_lane0_sync_clk",
2144 "rx_lane0_sync_clk",
2145 "rx_lane1_sync_clk";
2146 freq-table-hz = <37500000 300000000>,
2149 <37500000 300000000>,
2155 status = "disabled";
2158 ufs_mem_phy: phy-wrapper@1d87000 {
2159 compatible = "qcom,sc8180x-qmp-ufs-phy";
2160 reg = <0 0x01d87000 0 0x1c0>;
2161 #address-cells = <2>;
2164 clocks = <&rpmhcc RPMH_CXO_CLK>,
2165 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2166 clock-names = "ref",
2169 resets = <&ufs_mem_hc 0>;
2170 reset-names = "ufsphy";
2171 status = "disabled";
2173 ufs_mem_phy_lanes: phy@1d87400 {
2174 reg = <0 0x01d87400 0 0x108>,
2175 <0 0x01d87600 0 0x1e0>,
2176 <0 0x01d87c00 0 0x1dc>,
2177 <0 0x01d87800 0 0x108>,
2178 <0 0x01d87a00 0 0x1e0>;
2183 ipa_virt: interconnect@1e00000 {
2184 compatible = "qcom,sc8180x-ipa-virt";
2185 reg = <0 0x01e00000 0 0x1000>;
2186 #interconnect-cells = <2>;
2187 qcom,bcm-voters = <&apps_bcm_voter>;
2190 tcsr_mutex: hwlock@1f40000 {
2191 compatible = "qcom,tcsr-mutex";
2192 reg = <0x0 0x01f40000 0x0 0x40000>;
2193 #hwlock-cells = <1>;
2197 compatible = "qcom,adreno-680.1", "qcom,adreno";
2198 #stream-id-cells = <16>;
2200 reg = <0 0x02c00000 0 0x40000>;
2201 reg-names = "kgsl_3d0_reg_memory";
2203 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2205 iommus = <&adreno_smmu 0 0xc01>;
2207 operating-points-v2 = <&gpu_opp_table>;
2209 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
2210 interconnect-names = "gfx-mem";
2213 status = "disabled";
2215 gpu_opp_table: opp-table {
2216 compatible = "operating-points-v2";
2219 opp-hz = /bits/ 64 <514000000>;
2220 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2224 opp-hz = /bits/ 64 <500000000>;
2225 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2229 opp-hz = /bits/ 64 <461000000>;
2230 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2234 opp-hz = /bits/ 64 <405000000>;
2235 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2239 opp-hz = /bits/ 64 <315000000>;
2240 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2244 opp-hz = /bits/ 64 <256000000>;
2245 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2249 opp-hz = /bits/ 64 <177000000>;
2250 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2256 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2258 reg = <0 0x02c6a000 0 0x30000>,
2259 <0 0x0b290000 0 0x10000>,
2260 <0 0x0b490000 0 0x10000>;
2265 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2266 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2267 interrupt-names = "hfi", "gmu";
2269 clocks = <&gpucc GPU_CC_AHB_CLK>,
2270 <&gpucc GPU_CC_CX_GMU_CLK>,
2271 <&gpucc GPU_CC_CXO_CLK>,
2272 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2273 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2274 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2276 power-domains = <&gpucc GPU_CX_GDSC>,
2277 <&gpucc GPU_GX_GDSC>;
2278 power-domain-names = "cx", "gx";
2280 iommus = <&adreno_smmu 5 0xc00>;
2282 operating-points-v2 = <&gmu_opp_table>;
2284 gmu_opp_table: opp-table {
2285 compatible = "operating-points-v2";
2288 opp-hz = /bits/ 64 <200000000>;
2289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2293 opp-hz = /bits/ 64 <500000000>;
2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2299 gpucc: clock-controller@2c90000 {
2300 compatible = "qcom,sc8180x-gpucc";
2301 reg = <0 0x02c90000 0 0x9000>;
2302 clocks = <&rpmhcc RPMH_CXO_CLK>,
2303 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2304 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2305 clock-names = "bi_tcxo",
2306 "gcc_gpu_gpll0_clk_src",
2307 "gcc_gpu_gpll0_div_clk_src";
2310 #power-domain-cells = <1>;
2313 adreno_smmu: iommu@2ca0000 {
2314 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2315 "qcom,smmu-500", "arm,mmu-500";
2316 reg = <0 0x02ca0000 0 0x10000>;
2318 #global-interrupts = <1>;
2319 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
2320 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2321 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2322 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2323 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2324 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2325 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2326 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2327 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
2328 clocks = <&gpucc GPU_CC_AHB_CLK>,
2329 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2330 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
2331 clock-names = "ahb", "bus", "iface";
2333 power-domains = <&gpucc GPU_CX_GDSC>;
2336 tlmm: pinctrl@3100000 {
2337 compatible = "qcom,sc8180x-tlmm";
2338 reg = <0 0x03100000 0 0x300000>,
2339 <0 0x03500000 0 0x700000>,
2340 <0 0x03d00000 0 0x300000>;
2341 reg-names = "west", "east", "south";
2342 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
2345 interrupt-controller;
2346 #interrupt-cells = <2>;
2347 gpio-ranges = <&tlmm 0 0 191>;
2348 wakeup-parent = <&pdc>;
2351 remoteproc_mpss: remoteproc@4080000 {
2352 compatible = "qcom,sc8180x-mpss-pas";
2353 reg = <0x0 0x04080000 0x0 0x4040>;
2355 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2356 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2357 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2358 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2359 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2360 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2361 interrupt-names = "wdog", "fatal", "ready", "handover",
2362 "stop-ack", "shutdown-ack";
2364 clocks = <&rpmhcc RPMH_CXO_CLK>;
2367 power-domains = <&rpmhpd SC8180X_CX>,
2368 <&rpmhpd SC8180X_MSS>;
2369 power-domain-names = "cx", "mss";
2371 qcom,qmp = <&aoss_qmp>;
2373 qcom,smem-states = <&modem_smp2p_out 0>;
2374 qcom,smem-state-names = "stop";
2377 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2379 qcom,remote-pid = <1>;
2380 mboxes = <&apss_shared 12>;
2384 remoteproc_cdsp: remoteproc@8300000 {
2385 compatible = "qcom,sc8180x-cdsp-pas";
2386 reg = <0x0 0x08300000 0x0 0x4040>;
2388 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2389 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2390 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2391 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2392 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2393 interrupt-names = "wdog", "fatal", "ready",
2394 "handover", "stop-ack";
2396 clocks = <&rpmhcc RPMH_CXO_CLK>;
2399 power-domains = <&rpmhpd SC8180X_CX>;
2400 power-domain-names = "cx";
2402 qcom,qmp = <&aoss_qmp>;
2404 qcom,smem-states = <&cdsp_smp2p_out 0>;
2405 qcom,smem-state-names = "stop";
2407 status = "disabled";
2410 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
2412 qcom,remote-pid = <5>;
2413 mboxes = <&apss_shared 4>;
2417 usb_prim_hsphy: phy@88e2000 {
2418 compatible = "qcom,sc8180x-usb-hs-phy",
2419 "qcom,usb-snps-hs-7nm-phy";
2420 reg = <0 0x088e2000 0 0x400>;
2421 clocks = <&rpmhcc RPMH_CXO_CLK>;
2422 clock-names = "ref";
2423 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2427 status = "disabled";
2430 usb_sec_hsphy: phy@88e3000 {
2431 compatible = "qcom,sc8180x-usb-hs-phy",
2432 "qcom,usb-snps-hs-7nm-phy";
2433 reg = <0 0x088e3000 0 0x400>;
2434 clocks = <&rpmhcc RPMH_CXO_CLK>;
2435 clock-names = "ref";
2436 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2440 status = "disabled";
2443 usb_prim_qmpphy: phy@88e9000 {
2444 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2445 reg = <0 0x088e9000 0 0x18c>,
2446 <0 0x088e8000 0 0x38>,
2447 <0 0x088ea000 0 0x40>;
2448 reg-names = "reg-base", "dp_com";
2449 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2450 <&rpmhcc RPMH_CXO_CLK>,
2451 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2452 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2453 clock-names = "aux",
2457 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>,
2458 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
2459 reset-names = "phy", "common";
2462 #address-cells = <2>;
2466 status = "disabled";
2469 #address-cells = <1>;
2475 usb_prim_qmpphy_out: endpoint {};
2481 usb_prim_qmpphy_dp_in: endpoint {};
2485 usb_prim_ssphy: usb3-phy@88e9200 {
2486 reg = <0 0x088e9200 0 0x200>,
2487 <0 0x088e9400 0 0x200>,
2488 <0 0x088e9c00 0 0x218>,
2489 <0 0x088e9600 0 0x200>,
2490 <0 0x088e9800 0 0x200>,
2491 <0 0x088e9a00 0 0x100>;
2493 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2494 clock-names = "pipe0";
2495 clock-output-names = "usb3_prim_phy_pipe_clk_src";
2498 usb_prim_dpphy: dp-phy@88ea200 {
2499 reg = <0 0x088ea200 0 0x200>,
2500 <0 0x088ea400 0 0x200>,
2501 <0 0x088eaa00 0 0x200>,
2502 <0 0x088ea600 0 0x200>,
2503 <0 0x088ea800 0 0x200>;
2509 usb_sec_qmpphy: phy@88ee000 {
2510 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2511 reg = <0 0x088ee000 0 0x18c>,
2512 <0 0x088ed000 0 0x10>,
2513 <0 0x088ef000 0 0x40>;
2514 reg-names = "reg-base", "dp_com";
2515 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2516 <&rpmhcc RPMH_CXO_CLK>,
2517 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
2518 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
2519 clock-names = "aux",
2523 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>,
2524 <&gcc GCC_USB3_PHY_SEC_BCR>;
2525 reset-names = "phy", "common";
2528 #address-cells = <2>;
2532 status = "disabled";
2535 #address-cells = <1>;
2541 usb_sec_qmpphy_out: endpoint {};
2547 usb_sec_qmpphy_dp_in: endpoint {};
2551 usb_sec_ssphy: usb3-phy@88e9200 {
2552 reg = <0 0x088ee200 0 0x200>,
2553 <0 0x088ee400 0 0x200>,
2554 <0 0x088eec00 0 0x218>,
2555 <0 0x088ee600 0 0x200>,
2556 <0 0x088ee800 0 0x200>,
2557 <0 0x088eea00 0 0x100>;
2559 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2560 clock-names = "pipe0";
2561 clock-output-names = "usb3_sec_phy_pipe_clk_src";
2564 usb_sec_dpphy: dp-phy@88ef200 {
2565 reg = <0 0x088ef200 0 0x200>,
2566 <0 0x088ef400 0 0x200>,
2567 <0 0x088efa00 0 0x200>,
2568 <0 0x088ef600 0 0x200>,
2569 <0 0x088ef800 0 0x200>;
2572 clock-output-names = "qmp_dptx1_phy_pll_link_clk",
2573 "qmp_dptx1_phy_pll_vco_div_clk";
2577 system-cache-controller@9200000 {
2578 compatible = "qcom,sc8180x-llcc";
2579 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>,
2580 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>,
2581 <0 0x09600000 0 0x50000>;
2582 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2583 "llcc3_base", "llcc_broadcast_base";
2584 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2587 gem_noc: interconnect@9680000 {
2588 compatible = "qcom,sc8180x-gem-noc";
2589 reg = <0 0x09680000 0 0x58200>;
2590 #interconnect-cells = <2>;
2591 qcom,bcm-voters = <&apps_bcm_voter>;
2594 usb_prim: usb@a6f8800 {
2595 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2596 reg = <0 0x0a6f8800 0 0x400>;
2597 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2598 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2599 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2600 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2601 interrupt-names = "hs_phy_irq",
2606 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2607 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2608 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2609 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2610 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2611 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2612 clock-names = "cfg_noc",
2618 resets = <&gcc GCC_USB30_PRIM_BCR>;
2619 power-domains = <&gcc USB30_PRIM_GDSC>;
2621 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>,
2622 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
2623 interconnect-names = "usb-ddr", "apps-usb";
2625 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2626 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2627 assigned-clock-rates = <19200000>, <200000000>;
2629 #address-cells = <2>;
2634 status = "disabled";
2636 usb_prim_dwc3: usb@a600000 {
2637 compatible = "snps,dwc3";
2638 reg = <0 0x0a600000 0 0xcd00>;
2639 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2640 iommus = <&apps_smmu 0x140 0>;
2641 snps,dis_u2_susphy_quirk;
2642 snps,dis_enblslpm_quirk;
2643 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>;
2644 phy-names = "usb2-phy", "usb3-phy";
2647 usb_prim_role_switch: endpoint {
2653 usb_sec: usb@a8f8800 {
2654 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2655 reg = <0 0x0a8f8800 0 0x400>;
2657 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
2658 <&gcc GCC_USB30_SEC_MASTER_CLK>,
2659 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
2660 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2661 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
2662 <&gcc GCC_USB3_SEC_CLKREF_CLK>;
2663 clock-names = "cfg_noc",
2669 resets = <&gcc GCC_USB30_SEC_BCR>;
2670 power-domains = <&gcc USB30_SEC_GDSC>;
2671 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2672 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
2673 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
2674 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
2675 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2676 "dm_hs_phy_irq", "dp_hs_phy_irq";
2678 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2679 <&gcc GCC_USB30_SEC_MASTER_CLK>;
2680 assigned-clock-rates = <19200000>, <200000000>;
2682 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>,
2683 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>;
2684 interconnect-names = "usb-ddr", "apps-usb";
2686 #address-cells = <2>;
2691 status = "disabled";
2693 usb_sec_dwc3: usb@a800000 {
2694 compatible = "snps,dwc3";
2695 reg = <0 0x0a800000 0 0xcd00>;
2696 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2697 iommus = <&apps_smmu 0x160 0>;
2698 snps,dis_u2_susphy_quirk;
2699 snps,dis_enblslpm_quirk;
2700 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>;
2701 phy-names = "usb2-phy", "usb3-phy";
2704 usb_sec_role_switch: endpoint {
2710 mdss: mdss@ae00000 {
2711 compatible = "qcom,sc8180x-mdss";
2712 reg = <0 0x0ae00000 0 0x1000>;
2715 power-domains = <&dispcc MDSS_GDSC>;
2717 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2718 <&gcc GCC_DISP_HF_AXI_CLK>,
2719 <&gcc GCC_DISP_SF_AXI_CLK>,
2720 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2721 clock-names = "iface",
2726 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
2728 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2729 interrupt-controller;
2730 #interrupt-cells = <1>;
2732 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
2733 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
2734 interconnect-names = "mdp0-mem", "mdp1-mem";
2736 iommus = <&apps_smmu 0x800 0x420>;
2738 #address-cells = <2>;
2742 status = "disabled";
2744 mdss_mdp: mdp@ae01000 {
2745 compatible = "qcom,sc8180x-dpu";
2746 reg = <0 0x0ae01000 0 0x8f000>,
2747 <0 0x0aeb0000 0 0x2008>;
2748 reg-names = "mdp", "vbif";
2750 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2751 <&gcc GCC_DISP_HF_AXI_CLK>,
2752 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2753 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2754 clock-names = "iface",
2759 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2760 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2761 assigned-clock-rates = <460000000>,
2764 operating-points-v2 = <&mdp_opp_table>;
2765 power-domains = <&rpmhpd SC8180X_MMCX>;
2767 interrupt-parent = <&mdss>;
2768 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2771 #address-cells = <1>;
2776 dpu_intf0_out: endpoint {
2777 remote-endpoint = <&dp0_in>;
2783 dpu_intf1_out: endpoint {
2784 remote-endpoint = <&mdss_dsi0_in>;
2790 dpu_intf2_out: endpoint {
2791 remote-endpoint = <&mdss_dsi1_in>;
2797 dpu_intf4_out: endpoint {
2798 remote-endpoint = <&dp1_in>;
2804 dpu_intf5_out: endpoint {
2805 remote-endpoint = <&edp_in>;
2810 mdp_opp_table: opp-table {
2811 compatible = "operating-points-v2";
2814 opp-hz = /bits/ 64 <200000000>;
2815 required-opps = <&rpmhpd_opp_low_svs>;
2819 opp-hz = /bits/ 64 <300000000>;
2820 required-opps = <&rpmhpd_opp_svs>;
2824 opp-hz = /bits/ 64 <345000000>;
2825 required-opps = <&rpmhpd_opp_svs_l1>;
2829 opp-hz = /bits/ 64 <460000000>;
2830 required-opps = <&rpmhpd_opp_nom>;
2835 mdss_dsi0: dsi@ae94000 {
2836 compatible = "qcom,mdss-dsi-ctrl";
2837 reg = <0 0x0ae94000 0 0x400>;
2838 reg-names = "dsi_ctrl";
2840 interrupt-parent = <&mdss>;
2841 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
2843 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
2844 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
2845 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
2846 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
2847 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2848 <&gcc GCC_DISP_HF_AXI_CLK>;
2849 clock-names = "byte",
2856 operating-points-v2 = <&dsi_opp_table>;
2857 power-domains = <&rpmhpd SC8180X_MMCX>;
2859 phys = <&mdss_dsi0_phy>;
2862 status = "disabled";
2865 #address-cells = <1>;
2870 mdss_dsi0_in: endpoint {
2871 remote-endpoint = <&dpu_intf1_out>;
2877 mdss_dsi0_out: endpoint {
2882 dsi_opp_table: opp-table {
2883 compatible = "operating-points-v2";
2886 opp-hz = /bits/ 64 <187500000>;
2887 required-opps = <&rpmhpd_opp_low_svs>;
2891 opp-hz = /bits/ 64 <300000000>;
2892 required-opps = <&rpmhpd_opp_svs>;
2896 opp-hz = /bits/ 64 <358000000>;
2897 required-opps = <&rpmhpd_opp_svs_l1>;
2902 mdss_dsi0_phy: dsi-phy@ae94400 {
2903 compatible = "qcom,dsi-phy-7nm";
2904 reg = <0 0x0ae94400 0 0x200>,
2905 <0 0x0ae94600 0 0x280>,
2906 <0 0x0ae94900 0 0x260>;
2907 reg-names = "dsi_phy",
2914 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2915 <&rpmhcc RPMH_CXO_CLK>;
2916 clock-names = "iface", "ref";
2918 status = "disabled";
2921 mdss_dsi1: dsi@ae96000 {
2922 compatible = "qcom,mdss-dsi-ctrl";
2923 reg = <0 0x0ae96000 0 0x400>;
2924 reg-names = "dsi_ctrl";
2926 interrupt-parent = <&mdss>;
2927 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
2929 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
2930 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
2931 <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
2932 <&dispcc DISP_CC_MDSS_ESC1_CLK>,
2933 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2934 <&gcc GCC_DISP_HF_AXI_CLK>;
2935 clock-names = "byte",
2942 operating-points-v2 = <&dsi_opp_table>;
2943 power-domains = <&rpmhpd SC8180X_MMCX>;
2945 phys = <&mdss_dsi1_phy>;
2948 status = "disabled";
2951 #address-cells = <1>;
2956 mdss_dsi1_in: endpoint {
2957 remote-endpoint = <&dpu_intf2_out>;
2963 mdss_dsi1_out: endpoint {
2969 mdss_dsi1_phy: dsi-phy@ae96400 {
2970 compatible = "qcom,dsi-phy-7nm";
2971 reg = <0 0x0ae96400 0 0x200>,
2972 <0 0x0ae96600 0 0x280>,
2973 <0 0x0ae96900 0 0x260>;
2974 reg-names = "dsi_phy",
2981 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2982 <&rpmhcc RPMH_CXO_CLK>;
2983 clock-names = "iface", "ref";
2985 status = "disabled";
2988 mdss_dp0: displayport-controller@ae90000 {
2989 compatible = "qcom,sc8180x-dp";
2990 reg = <0 0xae90000 0 0x200>,
2991 <0 0xae90200 0 0x200>,
2992 <0 0xae90400 0 0x600>,
2993 <0 0xae90a00 0 0x400>;
2994 interrupt-parent = <&mdss>;
2996 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2997 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
2998 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
2999 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3000 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3001 clock-names = "core_iface",
3007 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3008 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3009 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
3011 phys = <&usb_prim_dpphy>;
3014 #sound-dai-cells = <0>;
3016 operating-points-v2 = <&dp0_opp_table>;
3017 power-domains = <&rpmhpd SC8180X_MMCX>;
3019 status = "disabled";
3022 #address-cells = <1>;
3028 remote-endpoint = <&dpu_intf0_out>;
3034 mdss_dp0_out: endpoint {
3039 dp0_opp_table: opp-table {
3040 compatible = "operating-points-v2";
3043 opp-hz = /bits/ 64 <160000000>;
3044 required-opps = <&rpmhpd_opp_low_svs>;
3048 opp-hz = /bits/ 64 <270000000>;
3049 required-opps = <&rpmhpd_opp_svs>;
3053 opp-hz = /bits/ 64 <540000000>;
3054 required-opps = <&rpmhpd_opp_svs_l1>;
3058 opp-hz = /bits/ 64 <810000000>;
3059 required-opps = <&rpmhpd_opp_nom>;
3064 mdss_dp1: displayport-controller@ae98000 {
3065 compatible = "qcom,sc8180x-dp";
3066 reg = <0 0xae98000 0 0x200>,
3067 <0 0xae98200 0 0x200>,
3068 <0 0xae98400 0 0x600>,
3069 <0 0xae98a00 0 0x400>;
3070 interrupt-parent = <&mdss>;
3072 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3073 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
3074 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
3075 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
3076 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
3077 clock-names = "core_iface",
3083 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3084 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
3085 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
3087 phys = <&usb_sec_dpphy>;
3090 #sound-dai-cells = <0>;
3092 operating-points-v2 = <&dp0_opp_table>;
3093 power-domains = <&rpmhpd SC8180X_MMCX>;
3095 status = "disabled";
3098 #address-cells = <1>;
3104 remote-endpoint = <&dpu_intf4_out>;
3110 mdss_dp1_out: endpoint {
3115 dp1_opp_table: opp-table {
3116 compatible = "operating-points-v2";
3119 opp-hz = /bits/ 64 <160000000>;
3120 required-opps = <&rpmhpd_opp_low_svs>;
3124 opp-hz = /bits/ 64 <270000000>;
3125 required-opps = <&rpmhpd_opp_svs>;
3129 opp-hz = /bits/ 64 <540000000>;
3130 required-opps = <&rpmhpd_opp_svs_l1>;
3134 opp-hz = /bits/ 64 <810000000>;
3135 required-opps = <&rpmhpd_opp_nom>;
3140 mdss_edp: displayport-controller@ae9a000 {
3141 compatible = "qcom,sc8180x-edp";
3142 reg = <0 0xae9a000 0 0x200>,
3143 <0 0xae9a200 0 0x200>,
3144 <0 0xae9a400 0 0x600>,
3145 <0 0xae9aa00 0 0x400>;
3146 interrupt-parent = <&mdss>;
3148 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3149 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3150 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3151 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3152 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3153 clock-names = "core_iface",
3159 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3160 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3161 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3166 #sound-dai-cells = <0>;
3168 operating-points-v2 = <&edp_opp_table>;
3169 power-domains = <&rpmhpd SC8180X_MMCX>;
3171 status = "disabled";
3174 #address-cells = <1>;
3180 remote-endpoint = <&dpu_intf5_out>;
3185 edp_opp_table: opp-table {
3186 compatible = "operating-points-v2";
3189 opp-hz = /bits/ 64 <160000000>;
3190 required-opps = <&rpmhpd_opp_low_svs>;
3194 opp-hz = /bits/ 64 <270000000>;
3195 required-opps = <&rpmhpd_opp_svs>;
3199 opp-hz = /bits/ 64 <540000000>;
3200 required-opps = <&rpmhpd_opp_svs_l1>;
3204 opp-hz = /bits/ 64 <810000000>;
3205 required-opps = <&rpmhpd_opp_nom>;
3211 edp_phy: phy@aec2a00 {
3212 compatible = "qcom,sc8180x-edp-phy";
3213 reg = <0 0x0aec2a00 0 0x1c0>,
3214 <0 0x0aec2200 0 0xa0>,
3215 <0 0x0aec2600 0 0xa0>,
3216 <0 0x0aec2000 0 0x19c>;
3218 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3219 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3220 clock-names = "aux", "cfg_ahb";
3222 power-domains = <&dispcc MDSS_GDSC>;
3228 dispcc: clock-controller@af00000 {
3229 compatible = "qcom,sc8180x-dispcc";
3230 reg = <0 0x0af00000 0 0x20000>;
3231 clocks = <&rpmhcc RPMH_CXO_CLK>,
3233 <&usb_prim_dpphy 0>,
3234 <&usb_prim_dpphy 1>,
3239 clock-names = "bi_tcxo",
3241 "dp_phy_pll_link_clk",
3242 "dp_phy_pll_vco_div_clk",
3243 "dptx1_phy_pll_link_clk",
3244 "dptx1_phy_pll_vco_div_clk",
3245 "edp_phy_pll_link_clk",
3246 "edp_phy_pll_vco_div_clk";
3247 power-domains = <&rpmhpd SC8180X_MMCX>;
3250 #power-domain-cells = <1>;
3253 pdc: interrupt-controller@b220000 {
3254 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3255 reg = <0 0x0b220000 0 0x30000>;
3256 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3257 #interrupt-cells = <2>;
3258 interrupt-parent = <&intc>;
3259 interrupt-controller;
3262 tsens0: thermal-sensor@c263000 {
3263 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3264 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3265 <0 0x0c222000 0 0x1ff>; /* SROT */
3266 #qcom,sensors = <16>;
3267 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3268 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3269 interrupt-names = "uplow", "critical";
3270 #thermal-sensor-cells = <1>;
3273 tsens1: thermal-sensor@c265000 {
3274 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3275 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3276 <0 0x0c223000 0 0x1ff>; /* SROT */
3277 #qcom,sensors = <9>;
3278 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3279 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3280 interrupt-names = "uplow", "critical";
3281 #thermal-sensor-cells = <1>;
3284 aoss_qmp: power-controller@c300000 {
3285 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3286 reg = <0x0 0x0c300000 0x0 0x100000>;
3287 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3288 mboxes = <&apss_shared 0>;
3291 #power-domain-cells = <1>;
3294 spmi_bus: spmi@c440000 {
3295 compatible = "qcom,spmi-pmic-arb";
3296 reg = <0x0 0x0c440000 0x0 0x0001100>,
3297 <0x0 0x0c600000 0x0 0x2000000>,
3298 <0x0 0x0e600000 0x0 0x0100000>,
3299 <0x0 0x0e700000 0x0 0x00a0000>,
3300 <0x0 0x0c40a000 0x0 0x0026000>;
3301 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3302 interrupt-names = "periph_irq";
3303 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
3306 #address-cells = <2>;
3308 interrupt-controller;
3309 #interrupt-cells = <4>;
3313 apps_smmu: iommu@15000000 {
3314 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3315 reg = <0 0x15000000 0 0x100000>;
3317 #global-interrupts = <1>;
3318 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3319 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3321 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3322 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3323 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3324 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3325 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3326 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3327 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3328 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3329 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3330 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3332 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3333 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3334 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3335 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3336 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3337 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3338 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3339 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3340 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3341 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3343 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3344 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3345 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3346 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3347 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3348 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3349 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3350 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3351 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3352 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3353 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3354 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3355 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3356 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3357 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3358 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3359 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3360 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3361 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3362 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3363 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3364 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3365 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3366 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3367 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3368 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3369 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3370 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3371 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3372 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3373 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3374 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3375 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3376 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3377 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3378 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3379 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3380 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3381 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3382 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3383 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3384 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
3385 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
3386 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
3387 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
3388 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
3389 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
3390 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3391 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3392 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3393 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3394 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3395 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3396 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3397 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3398 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3399 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3400 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
3402 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3403 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
3404 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
3405 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
3406 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
3407 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
3408 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
3409 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
3410 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
3411 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
3412 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
3413 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>,
3414 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>,
3415 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3416 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3417 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
3418 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
3419 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
3420 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
3421 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
3422 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
3423 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
3424 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>;
3428 remoteproc_adsp: remoteproc@17300000 {
3429 compatible = "qcom,sc8180x-adsp-pas";
3430 reg = <0x0 0x17300000 0x0 0x4040>;
3432 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3433 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3434 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3435 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3436 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3437 interrupt-names = "wdog", "fatal", "ready",
3438 "handover", "stop-ack";
3440 clocks = <&rpmhcc RPMH_CXO_CLK>;
3443 power-domains = <&rpmhpd SC8180X_CX>;
3444 power-domain-names = "cx";
3446 qcom,qmp = <&aoss_qmp>;
3448 qcom,smem-states = <&adsp_smp2p_out 0>;
3449 qcom,smem-state-names = "stop";
3451 status = "disabled";
3453 remoteproc_adsp_glink: glink-edge {
3454 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
3456 qcom,remote-pid = <2>;
3457 mboxes = <&apss_shared 8>;
3461 intc: interrupt-controller@17a00000 {
3462 compatible = "arm,gic-v3";
3463 interrupt-controller;
3464 #interrupt-cells = <3>;
3465 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
3466 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
3467 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3470 apss_shared: mailbox@17c00000 {
3471 compatible = "qcom,sc8180x-apss-shared";
3472 reg = <0x0 0x17c00000 0x0 0x1000>;
3477 compatible = "arm,armv7-timer-mem";
3478 reg = <0x0 0x17c20000 0x0 0x1000>;
3480 #address-cells = <1>;
3482 ranges = <0 0 0 0x20000000>;
3485 reg = <0x17c21000 0x1000>,
3486 <0x17c22000 0x1000>;
3488 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3489 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3493 reg = <0x17c23000 0x1000>;
3495 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3496 status = "disabled";
3500 reg = <0x17c25000 0x1000>;
3502 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3503 status = "disabled";
3507 reg = <0x17c26000 0x1000>;
3509 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3510 status = "disabled";
3514 reg = <0x17c29000 0x1000>;
3516 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3517 status = "disabled";
3521 reg = <0x17c2b000 0x1000>;
3523 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3524 status = "disabled";
3528 reg = <0x17c2d000 0x1000>;
3530 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3531 status = "disabled";
3535 apps_rsc: rsc@18200000 {
3536 compatible = "qcom,rpmh-rsc";
3537 reg = <0x0 0x18200000 0x0 0x10000>,
3538 <0x0 0x18210000 0x0 0x10000>,
3539 <0x0 0x18220000 0x0 0x10000>;
3540 reg-names = "drv-0", "drv-1", "drv-2";
3541 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3542 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3543 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3544 qcom,tcs-offset = <0xd00>;
3546 qcom,tcs-config = <ACTIVE_TCS 2>,
3551 power-domains = <&CLUSTER_PD>;
3553 apps_bcm_voter: bcm-voter {
3554 compatible = "qcom,bcm-voter";
3557 rpmhcc: clock-controller {
3558 compatible = "qcom,sc8180x-rpmh-clk";
3561 clocks = <&xo_board_clk>;
3564 rpmhpd: power-controller {
3565 compatible = "qcom,sc8180x-rpmhpd";
3566 #power-domain-cells = <1>;
3567 operating-points-v2 = <&rpmhpd_opp_table>;
3569 rpmhpd_opp_table: opp-table {
3570 compatible = "operating-points-v2";
3572 rpmhpd_opp_ret: opp1 {
3573 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3576 rpmhpd_opp_min_svs: opp2 {
3577 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3580 rpmhpd_opp_low_svs: opp3 {
3581 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3584 rpmhpd_opp_svs: opp4 {
3585 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3588 rpmhpd_opp_svs_l1: opp5 {
3589 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3592 rpmhpd_opp_nom: opp6 {
3593 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3596 rpmhpd_opp_nom_l1: opp7 {
3597 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3600 rpmhpd_opp_nom_l2: opp8 {
3601 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3604 rpmhpd_opp_turbo: opp9 {
3605 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3608 rpmhpd_opp_turbo_l1: opp10 {
3609 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3615 osm_l3: interconnect@18321000 {
3616 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3617 reg = <0 0x18321000 0 0x1400>;
3619 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3620 clock-names = "xo", "alternate";
3622 #interconnect-cells = <1>;
3626 compatible = "qcom,sc8180x-lmh";
3627 reg = <0 0x18350800 0 0x400>;
3628 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
3630 qcom,lmh-temp-arm-millicelsius = <65000>;
3631 qcom,lmh-temp-low-millicelsius = <94500>;
3632 qcom,lmh-temp-high-millicelsius = <95000>;
3633 interrupt-controller;
3634 #interrupt-cells = <1>;
3638 compatible = "qcom,sc8180x-lmh";
3639 reg = <0 0x18358800 0 0x400>;
3640 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
3642 qcom,lmh-temp-arm-millicelsius = <65000>;
3643 qcom,lmh-temp-low-millicelsius = <94500>;
3644 qcom,lmh-temp-high-millicelsius = <95000>;
3645 interrupt-controller;
3646 #interrupt-cells = <1>;
3649 cpufreq_hw: cpufreq@18323000 {
3650 compatible = "qcom,cpufreq-hw";
3651 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3652 reg-names = "freq-domain0", "freq-domain1";
3654 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3655 clock-names = "xo", "alternate";
3657 #freq-domain-cells = <1>;
3661 wifi: wifi@18800000 {
3662 compatible = "qcom,wcn3990-wifi";
3663 reg = <0 0x18800000 0 0x800000>;
3664 reg-names = "membase";
3665 clock-names = "cxo_ref_clk_pin";
3666 clocks = <&rpmhcc RPMH_RF_CLK2>;
3667 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3668 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3669 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3670 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3671 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3672 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
3673 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3675 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3676 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3677 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3678 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3679 iommus = <&apps_smmu 0x0640 0x1>;
3680 qcom,msa-fixed-perm;
3681 status = "disabled";
3687 polling-delay-passive = <250>;
3688 polling-delay = <1000>;
3690 thermal-sensors = <&tsens0 1>;
3694 temperature = <110000>;
3695 hysteresis = <1000>;
3702 polling-delay-passive = <250>;
3703 polling-delay = <1000>;
3705 thermal-sensors = <&tsens0 2>;
3709 temperature = <110000>;
3710 hysteresis = <1000>;
3717 polling-delay-passive = <250>;
3718 polling-delay = <1000>;
3720 thermal-sensors = <&tsens0 3>;
3724 temperature = <110000>;
3725 hysteresis = <1000>;
3732 polling-delay-passive = <250>;
3733 polling-delay = <1000>;
3735 thermal-sensors = <&tsens0 4>;
3739 temperature = <110000>;
3740 hysteresis = <1000>;
3747 polling-delay-passive = <250>;
3748 polling-delay = <1000>;
3750 thermal-sensors = <&tsens0 7>;
3754 temperature = <110000>;
3755 hysteresis = <1000>;
3762 polling-delay-passive = <250>;
3763 polling-delay = <1000>;
3765 thermal-sensors = <&tsens0 8>;
3769 temperature = <110000>;
3770 hysteresis = <1000>;
3777 polling-delay-passive = <250>;
3778 polling-delay = <1000>;
3780 thermal-sensors = <&tsens0 9>;
3784 temperature = <110000>;
3785 hysteresis = <1000>;
3792 polling-delay-passive = <250>;
3793 polling-delay = <1000>;
3795 thermal-sensors = <&tsens0 10>;
3799 temperature = <110000>;
3800 hysteresis = <1000>;
3806 cpu4-bottom-thermal {
3807 polling-delay-passive = <250>;
3808 polling-delay = <1000>;
3810 thermal-sensors = <&tsens0 11>;
3814 temperature = <110000>;
3815 hysteresis = <1000>;
3821 cpu5-bottom-thermal {
3822 polling-delay-passive = <250>;
3823 polling-delay = <1000>;
3825 thermal-sensors = <&tsens0 12>;
3829 temperature = <110000>;
3830 hysteresis = <1000>;
3836 cpu6-bottom-thermal {
3837 polling-delay-passive = <250>;
3838 polling-delay = <1000>;
3840 thermal-sensors = <&tsens0 13>;
3844 temperature = <110000>;
3845 hysteresis = <1000>;
3851 cpu7-bottom-thermal {
3852 polling-delay-passive = <250>;
3853 polling-delay = <1000>;
3855 thermal-sensors = <&tsens0 14>;
3859 temperature = <110000>;
3860 hysteresis = <1000>;
3867 polling-delay-passive = <250>;
3868 polling-delay = <1000>;
3870 thermal-sensors = <&tsens0 0>;
3874 temperature = <90000>;
3875 hysteresis = <2000>;
3882 polling-delay-passive = <250>;
3883 polling-delay = <1000>;
3885 thermal-sensors = <&tsens0 5>;
3889 temperature = <110000>;
3890 hysteresis = <2000>;
3897 polling-delay-passive = <250>;
3898 polling-delay = <1000>;
3900 thermal-sensors = <&tsens0 6>;
3904 temperature = <110000>;
3905 hysteresis = <2000>;
3912 polling-delay-passive = <250>;
3913 polling-delay = <1000>;
3915 thermal-sensors = <&tsens0 15>;
3919 temperature = <90000>;
3920 hysteresis = <2000>;
3927 polling-delay-passive = <250>;
3928 polling-delay = <1000>;
3930 thermal-sensors = <&tsens1 0>;
3934 temperature = <90000>;
3935 hysteresis = <2000>;
3942 polling-delay-passive = <250>;
3943 polling-delay = <1000>;
3945 thermal-sensors = <&tsens1 1>;
3949 temperature = <90000>;
3950 hysteresis = <2000>;
3957 polling-delay-passive = <250>;
3958 polling-delay = <1000>;
3960 thermal-sensors = <&tsens1 2>;
3964 temperature = <90000>;
3965 hysteresis = <2000>;
3972 polling-delay-passive = <250>;
3973 polling-delay = <1000>;
3975 thermal-sensors = <&tsens1 3>;
3979 temperature = <90000>;
3980 hysteresis = <2000>;
3987 polling-delay-passive = <250>;
3988 polling-delay = <1000>;
3990 thermal-sensors = <&tsens1 4>;
3994 temperature = <90000>;
3995 hysteresis = <2000>;
4002 polling-delay-passive = <250>;
4003 polling-delay = <1000>;
4005 thermal-sensors = <&tsens1 5>;
4009 temperature = <90000>;
4010 hysteresis = <2000>;
4017 polling-delay-passive = <250>;
4018 polling-delay = <1000>;
4020 thermal-sensors = <&tsens1 6>;
4024 temperature = <90000>;
4025 hysteresis = <2000>;
4032 polling-delay-passive = <250>;
4033 polling-delay = <1000>;
4035 thermal-sensors = <&tsens1 7>;
4039 temperature = <90000>;
4040 hysteresis = <2000>;
4047 polling-delay-passive = <250>;
4048 polling-delay = <1000>;
4050 thermal-sensors = <&tsens1 8>;
4054 temperature = <90000>;
4055 hysteresis = <2000>;
4061 gpu-bottom-thermal {
4062 polling-delay-passive = <250>;
4063 polling-delay = <1000>;
4065 thermal-sensors = <&tsens1 11>;
4069 temperature = <90000>;
4070 hysteresis = <2000>;
4078 compatible = "arm,armv8-timer";
4079 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4080 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4081 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4082 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;