arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
  11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
  12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
  15 #include <dt-bindings/dma/qcom-gpi.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sc7280.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/mailbox/qcom-ipcc.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/sound/qcom,lpass.h>
  26 #include <dt-bindings/thermal/thermal.h>
  27
  28 / {
  29         interrupt-parent = <&intc>;
  30
  31         #address-cells = <2>;
  32         #size-cells = <2>;
  33
  34         chosen { };
  35
  36         aliases {
  37                 i2c0 = &i2c0;
  38                 i2c1 = &i2c1;
  39                 i2c2 = &i2c2;
  40                 i2c3 = &i2c3;
  41                 i2c4 = &i2c4;
  42                 i2c5 = &i2c5;
  43                 i2c6 = &i2c6;
  44                 i2c7 = &i2c7;
  45                 i2c8 = &i2c8;
  46                 i2c9 = &i2c9;
  47                 i2c10 = &i2c10;
  48                 i2c11 = &i2c11;
  49                 i2c12 = &i2c12;
  50                 i2c13 = &i2c13;
  51                 i2c14 = &i2c14;
  52                 i2c15 = &i2c15;
  53                 mmc1 = &sdhc_1;
  54                 mmc2 = &sdhc_2;
  55                 spi0 = &spi0;
  56                 spi1 = &spi1;
  57                 spi2 = &spi2;
  58                 spi3 = &spi3;
  59                 spi4 = &spi4;
  60                 spi5 = &spi5;
  61                 spi6 = &spi6;
  62                 spi7 = &spi7;
  63                 spi8 = &spi8;
  64                 spi9 = &spi9;
  65                 spi10 = &spi10;
  66                 spi11 = &spi11;
  67                 spi12 = &spi12;
  68                 spi13 = &spi13;
  69                 spi14 = &spi14;
  70                 spi15 = &spi15;
  71         };
  72
  73         clocks {
  74                 xo_board: xo-board {
  75                         compatible = "fixed-clock";
  76                         clock-frequency = <76800000>;
  77                         #clock-cells = <0>;
  78                 };
  79
  80                 sleep_clk: sleep-clk {
  81                         compatible = "fixed-clock";
  82                         clock-frequency = <32000>;
  83                         #clock-cells = <0>;
  84                 };
  85         };
  86
  87         reserved-memory {
  88                 #address-cells = <2>;
  89                 #size-cells = <2>;
  90                 ranges;
  91
  92                 wlan_ce_mem: memory@4cd000 {
  93                         no-map;
  94                         reg = <0x0 0x004cd000 0x0 0x1000>;
  95                 };
  96
  97                 hyp_mem: memory@80000000 {
  98                         reg = <0x0 0x80000000 0x0 0x600000>;
  99                         no-map;
 100                 };
 101
 102                 xbl_mem: memory@80600000 {
 103                         reg = <0x0 0x80600000 0x0 0x200000>;
 104                         no-map;
 105                 };
 106
 107                 aop_mem: memory@80800000 {
 108                         reg = <0x0 0x80800000 0x0 0x60000>;
 109                         no-map;
 110                 };
 111
 112                 aop_cmd_db_mem: memory@80860000 {
 113                         reg = <0x0 0x80860000 0x0 0x20000>;
 114                         compatible = "qcom,cmd-db";
 115                         no-map;
 116                 };
 117
 118                 reserved_xbl_uefi_log: memory@80880000 {
 119                         reg = <0x0 0x80884000 0x0 0x10000>;
 120                         no-map;
 121                 };
 122
 123                 sec_apps_mem: memory@808ff000 {
 124                         reg = <0x0 0x808ff000 0x0 0x1000>;
 125                         no-map;
 126                 };
 127
 128                 smem_mem: memory@80900000 {
 129                         reg = <0x0 0x80900000 0x0 0x200000>;
 130                         no-map;
 131                 };
 132
 133                 cpucp_mem: memory@80b00000 {
 134                         no-map;
 135                         reg = <0x0 0x80b00000 0x0 0x100000>;
 136                 };
 137
 138                 wlan_fw_mem: memory@80c00000 {
 139                         reg = <0x0 0x80c00000 0x0 0xc00000>;
 140                         no-map;
 141                 };
 142
 143                 video_mem: memory@8b200000 {
 144                         reg = <0x0 0x8b200000 0x0 0x500000>;
 145                         no-map;
 146                 };
 147
 148                 ipa_fw_mem: memory@8b700000 {
 149                         reg = <0 0x8b700000 0 0x10000>;
 150                         no-map;
 151                 };
 152
 153                 rmtfs_mem: memory@9c900000 {
 154                         compatible = "qcom,rmtfs-mem";
 155                         reg = <0x0 0x9c900000 0x0 0x280000>;
 156                         no-map;
 157
 158                         qcom,client-id = <1>;
 159                         qcom,vmid = <15>;
 160                 };
 161         };
 162
 163         cpus {
 164                 #address-cells = <2>;
 165                 #size-cells = <0>;
 166
 167                 CPU0: cpu@0 {
 168                         device_type = "cpu";
 169                         compatible = "arm,kryo";
 170                         reg = <0x0 0x0>;
 171                         enable-method = "psci";
 172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 173                                            &LITTLE_CPU_SLEEP_1
 174                                            &CLUSTER_SLEEP_0>;
 175                         next-level-cache = <&L2_0>;
 176                         operating-points-v2 = <&cpu0_opp_table>;
 177                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 178                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 179                         qcom,freq-domain = <&cpufreq_hw 0>;
 180                         #cooling-cells = <2>;
 181                         L2_0: l2-cache {
 182                                 compatible = "cache";
 183                                 next-level-cache = <&L3_0>;
 184                                 L3_0: l3-cache {
 185                                         compatible = "cache";
 186                                 };
 187                         };
 188                 };
 189
 190                 CPU1: cpu@100 {
 191                         device_type = "cpu";
 192                         compatible = "arm,kryo";
 193                         reg = <0x0 0x100>;
 194                         enable-method = "psci";
 195                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 196                                            &LITTLE_CPU_SLEEP_1
 197                                            &CLUSTER_SLEEP_0>;
 198                         next-level-cache = <&L2_100>;
 199                         operating-points-v2 = <&cpu0_opp_table>;
 200                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 201                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 202                         qcom,freq-domain = <&cpufreq_hw 0>;
 203                         #cooling-cells = <2>;
 204                         L2_100: l2-cache {
 205                                 compatible = "cache";
 206                                 next-level-cache = <&L3_0>;
 207                         };
 208                 };
 209
 210                 CPU2: cpu@200 {
 211                         device_type = "cpu";
 212                         compatible = "arm,kryo";
 213                         reg = <0x0 0x200>;
 214                         enable-method = "psci";
 215                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 216                                            &LITTLE_CPU_SLEEP_1
 217                                            &CLUSTER_SLEEP_0>;
 218                         next-level-cache = <&L2_200>;
 219                         operating-points-v2 = <&cpu0_opp_table>;
 220                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 221                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 222                         qcom,freq-domain = <&cpufreq_hw 0>;
 223                         #cooling-cells = <2>;
 224                         L2_200: l2-cache {
 225                                 compatible = "cache";
 226                                 next-level-cache = <&L3_0>;
 227                         };
 228                 };
 229
 230                 CPU3: cpu@300 {
 231                         device_type = "cpu";
 232                         compatible = "arm,kryo";
 233                         reg = <0x0 0x300>;
 234                         enable-method = "psci";
 235                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 236                                            &LITTLE_CPU_SLEEP_1
 237                                            &CLUSTER_SLEEP_0>;
 238                         next-level-cache = <&L2_300>;
 239                         operating-points-v2 = <&cpu0_opp_table>;
 240                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 241                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 242                         qcom,freq-domain = <&cpufreq_hw 0>;
 243                         #cooling-cells = <2>;
 244                         L2_300: l2-cache {
 245                                 compatible = "cache";
 246                                 next-level-cache = <&L3_0>;
 247                         };
 248                 };
 249
 250                 CPU4: cpu@400 {
 251                         device_type = "cpu";
 252                         compatible = "arm,kryo";
 253                         reg = <0x0 0x400>;
 254                         enable-method = "psci";
 255                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 256                                            &BIG_CPU_SLEEP_1
 257                                            &CLUSTER_SLEEP_0>;
 258                         next-level-cache = <&L2_400>;
 259                         operating-points-v2 = <&cpu4_opp_table>;
 260                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 261                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 262                         qcom,freq-domain = <&cpufreq_hw 1>;
 263                         #cooling-cells = <2>;
 264                         L2_400: l2-cache {
 265                                 compatible = "cache";
 266                                 next-level-cache = <&L3_0>;
 267                         };
 268                 };
 269
 270                 CPU5: cpu@500 {
 271                         device_type = "cpu";
 272                         compatible = "arm,kryo";
 273                         reg = <0x0 0x500>;
 274                         enable-method = "psci";
 275                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 276                                            &BIG_CPU_SLEEP_1
 277                                            &CLUSTER_SLEEP_0>;
 278                         next-level-cache = <&L2_500>;
 279                         operating-points-v2 = <&cpu4_opp_table>;
 280                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 281                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 282                         qcom,freq-domain = <&cpufreq_hw 1>;
 283                         #cooling-cells = <2>;
 284                         L2_500: l2-cache {
 285                                 compatible = "cache";
 286                                 next-level-cache = <&L3_0>;
 287                         };
 288                 };
 289
 290                 CPU6: cpu@600 {
 291                         device_type = "cpu";
 292                         compatible = "arm,kryo";
 293                         reg = <0x0 0x600>;
 294                         enable-method = "psci";
 295                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 296                                            &BIG_CPU_SLEEP_1
 297                                            &CLUSTER_SLEEP_0>;
 298                         next-level-cache = <&L2_600>;
 299                         operating-points-v2 = <&cpu4_opp_table>;
 300                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 301                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 302                         qcom,freq-domain = <&cpufreq_hw 1>;
 303                         #cooling-cells = <2>;
 304                         L2_600: l2-cache {
 305                                 compatible = "cache";
 306                                 next-level-cache = <&L3_0>;
 307                         };
 308                 };
 309
 310                 CPU7: cpu@700 {
 311                         device_type = "cpu";
 312                         compatible = "arm,kryo";
 313                         reg = <0x0 0x700>;
 314                         enable-method = "psci";
 315                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 316                                            &BIG_CPU_SLEEP_1
 317                                            &CLUSTER_SLEEP_0>;
 318                         next-level-cache = <&L2_700>;
 319                         operating-points-v2 = <&cpu7_opp_table>;
 320                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 321                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 322                         qcom,freq-domain = <&cpufreq_hw 2>;
 323                         #cooling-cells = <2>;
 324                         L2_700: l2-cache {
 325                                 compatible = "cache";
 326                                 next-level-cache = <&L3_0>;
 327                         };
 328                 };
 329
 330                 cpu-map {
 331                         cluster0 {
 332                                 core0 {
 333                                         cpu = <&CPU0>;
 334                                 };
 335
 336                                 core1 {
 337                                         cpu = <&CPU1>;
 338                                 };
 339
 340                                 core2 {
 341                                         cpu = <&CPU2>;
 342                                 };
 343
 344                                 core3 {
 345                                         cpu = <&CPU3>;
 346                                 };
 347
 348                                 core4 {
 349                                         cpu = <&CPU4>;
 350                                 };
 351
 352                                 core5 {
 353                                         cpu = <&CPU5>;
 354                                 };
 355
 356                                 core6 {
 357                                         cpu = <&CPU6>;
 358                                 };
 359
 360                                 core7 {
 361                                         cpu = <&CPU7>;
 362                                 };
 363                         };
 364                 };
 365
 366                 idle-states {
 367                         entry-method = "psci";
 368
 369                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 370                                 compatible = "arm,idle-state";
 371                                 idle-state-name = "little-power-down";
 372                                 arm,psci-suspend-param = <0x40000003>;
 373                                 entry-latency-us = <549>;
 374                                 exit-latency-us = <901>;
 375                                 min-residency-us = <1774>;
 376                                 local-timer-stop;
 377                         };
 378
 379                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 380                                 compatible = "arm,idle-state";
 381                                 idle-state-name = "little-rail-power-down";
 382                                 arm,psci-suspend-param = <0x40000004>;
 383                                 entry-latency-us = <702>;
 384                                 exit-latency-us = <915>;
 385                                 min-residency-us = <4001>;
 386                                 local-timer-stop;
 387                         };
 388
 389                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 390                                 compatible = "arm,idle-state";
 391                                 idle-state-name = "big-power-down";
 392                                 arm,psci-suspend-param = <0x40000003>;
 393                                 entry-latency-us = <523>;
 394                                 exit-latency-us = <1244>;
 395                                 min-residency-us = <2207>;
 396                                 local-timer-stop;
 397                         };
 398
 399                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 400                                 compatible = "arm,idle-state";
 401                                 idle-state-name = "big-rail-power-down";
 402                                 arm,psci-suspend-param = <0x40000004>;
 403                                 entry-latency-us = <526>;
 404                                 exit-latency-us = <1854>;
 405                                 min-residency-us = <5555>;
 406                                 local-timer-stop;
 407                         };
 408
 409                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 410                                 compatible = "arm,idle-state";
 411                                 idle-state-name = "cluster-power-down";
 412                                 arm,psci-suspend-param = <0x40003444>;
 413                                 entry-latency-us = <3263>;
 414                                 exit-latency-us = <6562>;
 415                                 min-residency-us = <9926>;
 416                                 local-timer-stop;
 417                         };
 418                 };
 419         };
 420
 421         cpu0_opp_table: opp-table-cpu0 {
 422                 compatible = "operating-points-v2";
 423                 opp-shared;
 424
 425                 cpu0_opp_300mhz: opp-300000000 {
 426                         opp-hz = /bits/ 64 <300000000>;
 427                         opp-peak-kBps = <800000 9600000>;
 428                 };
 429
 430                 cpu0_opp_691mhz: opp-691200000 {
 431                         opp-hz = /bits/ 64 <691200000>;
 432                         opp-peak-kBps = <800000 17817600>;
 433                 };
 434
 435                 cpu0_opp_806mhz: opp-806400000 {
 436                         opp-hz = /bits/ 64 <806400000>;
 437                         opp-peak-kBps = <800000 20889600>;
 438                 };
 439
 440                 cpu0_opp_941mhz: opp-940800000 {
 441                         opp-hz = /bits/ 64 <940800000>;
 442                         opp-peak-kBps = <1804000 24576000>;
 443                 };
 444
 445                 cpu0_opp_1152mhz: opp-1152000000 {
 446                         opp-hz = /bits/ 64 <1152000000>;
 447                         opp-peak-kBps = <2188000 27033600>;
 448                 };
 449
 450                 cpu0_opp_1325mhz: opp-1324800000 {
 451                         opp-hz = /bits/ 64 <1324800000>;
 452                         opp-peak-kBps = <2188000 33792000>;
 453                 };
 454
 455                 cpu0_opp_1517mhz: opp-1516800000 {
 456                         opp-hz = /bits/ 64 <1516800000>;
 457                         opp-peak-kBps = <3072000 38092800>;
 458                 };
 459
 460                 cpu0_opp_1651mhz: opp-1651200000 {
 461                         opp-hz = /bits/ 64 <1651200000>;
 462                         opp-peak-kBps = <3072000 41779200>;
 463                 };
 464
 465                 cpu0_opp_1805mhz: opp-1804800000 {
 466                         opp-hz = /bits/ 64 <1804800000>;
 467                         opp-peak-kBps = <4068000 48537600>;
 468                 };
 469
 470                 cpu0_opp_1958mhz: opp-1958400000 {
 471                         opp-hz = /bits/ 64 <1958400000>;
 472                         opp-peak-kBps = <4068000 48537600>;
 473                 };
 474
 475                 cpu0_opp_2016mhz: opp-2016000000 {
 476                         opp-hz = /bits/ 64 <2016000000>;
 477                         opp-peak-kBps = <6220000 48537600>;
 478                 };
 479         };
 480
 481         cpu4_opp_table: opp-table-cpu4 {
 482                 compatible = "operating-points-v2";
 483                 opp-shared;
 484
 485                 cpu4_opp_691mhz: opp-691200000 {
 486                         opp-hz = /bits/ 64 <691200000>;
 487                         opp-peak-kBps = <1804000 9600000>;
 488                 };
 489
 490                 cpu4_opp_941mhz: opp-940800000 {
 491                         opp-hz = /bits/ 64 <940800000>;
 492                         opp-peak-kBps = <2188000 17817600>;
 493                 };
 494
 495                 cpu4_opp_1229mhz: opp-1228800000 {
 496                         opp-hz = /bits/ 64 <1228800000>;
 497                         opp-peak-kBps = <4068000 24576000>;
 498                 };
 499
 500                 cpu4_opp_1344mhz: opp-1344000000 {
 501                         opp-hz = /bits/ 64 <1344000000>;
 502                         opp-peak-kBps = <4068000 24576000>;
 503                 };
 504
 505                 cpu4_opp_1517mhz: opp-1516800000 {
 506                         opp-hz = /bits/ 64 <1516800000>;
 507                         opp-peak-kBps = <4068000 24576000>;
 508                 };
 509
 510                 cpu4_opp_1651mhz: opp-1651200000 {
 511                         opp-hz = /bits/ 64 <1651200000>;
 512                         opp-peak-kBps = <6220000 38092800>;
 513                 };
 514
 515                 cpu4_opp_1901mhz: opp-1900800000 {
 516                         opp-hz = /bits/ 64 <1900800000>;
 517                         opp-peak-kBps = <6220000 44851200>;
 518                 };
 519
 520                 cpu4_opp_2054mhz: opp-2054400000 {
 521                         opp-hz = /bits/ 64 <2054400000>;
 522                         opp-peak-kBps = <6220000 44851200>;
 523                 };
 524
 525                 cpu4_opp_2112mhz: opp-2112000000 {
 526                         opp-hz = /bits/ 64 <2112000000>;
 527                         opp-peak-kBps = <6220000 44851200>;
 528                 };
 529
 530                 cpu4_opp_2131mhz: opp-2131200000 {
 531                         opp-hz = /bits/ 64 <2131200000>;
 532                         opp-peak-kBps = <6220000 44851200>;
 533                 };
 534
 535                 cpu4_opp_2208mhz: opp-2208000000 {
 536                         opp-hz = /bits/ 64 <2208000000>;
 537                         opp-peak-kBps = <6220000 44851200>;
 538                 };
 539
 540                 cpu4_opp_2400mhz: opp-2400000000 {
 541                         opp-hz = /bits/ 64 <2400000000>;
 542                         opp-peak-kBps = <8532000 48537600>;
 543                 };
 544
 545                 cpu4_opp_2611mhz: opp-2611200000 {
 546                         opp-hz = /bits/ 64 <2611200000>;
 547                         opp-peak-kBps = <8532000 48537600>;
 548                 };
 549         };
 550
 551         cpu7_opp_table: opp-table-cpu7 {
 552                 compatible = "operating-points-v2";
 553                 opp-shared;
 554
 555                 cpu7_opp_806mhz: opp-806400000 {
 556                         opp-hz = /bits/ 64 <806400000>;
 557                         opp-peak-kBps = <1804000 9600000>;
 558                 };
 559
 560                 cpu7_opp_1056mhz: opp-1056000000 {
 561                         opp-hz = /bits/ 64 <1056000000>;
 562                         opp-peak-kBps = <2188000 17817600>;
 563                 };
 564
 565                 cpu7_opp_1325mhz: opp-1324800000 {
 566                         opp-hz = /bits/ 64 <1324800000>;
 567                         opp-peak-kBps = <4068000 24576000>;
 568                 };
 569
 570                 cpu7_opp_1517mhz: opp-1516800000 {
 571                         opp-hz = /bits/ 64 <1516800000>;
 572                         opp-peak-kBps = <4068000 24576000>;
 573                 };
 574
 575                 cpu7_opp_1766mhz: opp-1766400000 {
 576                         opp-hz = /bits/ 64 <1766400000>;
 577                         opp-peak-kBps = <6220000 38092800>;
 578                 };
 579
 580                 cpu7_opp_1862mhz: opp-1862400000 {
 581                         opp-hz = /bits/ 64 <1862400000>;
 582                         opp-peak-kBps = <6220000 38092800>;
 583                 };
 584
 585                 cpu7_opp_2035mhz: opp-2035200000 {
 586                         opp-hz = /bits/ 64 <2035200000>;
 587                         opp-peak-kBps = <6220000 38092800>;
 588                 };
 589
 590                 cpu7_opp_2112mhz: opp-2112000000 {
 591                         opp-hz = /bits/ 64 <2112000000>;
 592                         opp-peak-kBps = <6220000 44851200>;
 593                 };
 594
 595                 cpu7_opp_2208mhz: opp-2208000000 {
 596                         opp-hz = /bits/ 64 <2208000000>;
 597                         opp-peak-kBps = <6220000 44851200>;
 598                 };
 599
 600                 cpu7_opp_2381mhz: opp-2380800000 {
 601                         opp-hz = /bits/ 64 <2380800000>;
 602                         opp-peak-kBps = <6832000 44851200>;
 603                 };
 604
 605                 cpu7_opp_2400mhz: opp-2400000000 {
 606                         opp-hz = /bits/ 64 <2400000000>;
 607                         opp-peak-kBps = <8532000 48537600>;
 608                 };
 609
 610                 cpu7_opp_2515mhz: opp-2515200000 {
 611                         opp-hz = /bits/ 64 <2515200000>;
 612                         opp-peak-kBps = <8532000 48537600>;
 613                 };
 614
 615                 cpu7_opp_2707mhz: opp-2707200000 {
 616                         opp-hz = /bits/ 64 <2707200000>;
 617                         opp-peak-kBps = <8532000 48537600>;
 618                 };
 619
 620                 cpu7_opp_3014mhz: opp-3014400000 {
 621                         opp-hz = /bits/ 64 <3014400000>;
 622                         opp-peak-kBps = <8532000 48537600>;
 623                 };
 624         };
 625
 626         memory@80000000 {
 627                 device_type = "memory";
 628                 /* We expect the bootloader to fill in the size */
 629                 reg = <0 0x80000000 0 0>;
 630         };
 631
 632         firmware {
 633                 scm {
 634                         compatible = "qcom,scm-sc7280", "qcom,scm";
 635                 };
 636         };
 637
 638         clk_virt: interconnect {
 639                 compatible = "qcom,sc7280-clk-virt";
 640                 #interconnect-cells = <2>;
 641                 qcom,bcm-voters = <&apps_bcm_voter>;
 642         };
 643
 644         smem {
 645                 compatible = "qcom,smem";
 646                 memory-region = <&smem_mem>;
 647                 hwlocks = <&tcsr_mutex 3>;
 648         };
 649
 650         smp2p-adsp {
 651                 compatible = "qcom,smp2p";
 652                 qcom,smem = <443>, <429>;
 653                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 654                                              IPCC_MPROC_SIGNAL_SMP2P
 655                                              IRQ_TYPE_EDGE_RISING>;
 656                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 657                                 IPCC_MPROC_SIGNAL_SMP2P>;
 658
 659                 qcom,local-pid = <0>;
 660                 qcom,remote-pid = <2>;
 661
 662                 adsp_smp2p_out: master-kernel {
 663                         qcom,entry-name = "master-kernel";
 664                         #qcom,smem-state-cells = <1>;
 665                 };
 666
 667                 adsp_smp2p_in: slave-kernel {
 668                         qcom,entry-name = "slave-kernel";
 669                         interrupt-controller;
 670                         #interrupt-cells = <2>;
 671                 };
 672         };
 673
 674         smp2p-cdsp {
 675                 compatible = "qcom,smp2p";
 676                 qcom,smem = <94>, <432>;
 677                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 678                                              IPCC_MPROC_SIGNAL_SMP2P
 679                                              IRQ_TYPE_EDGE_RISING>;
 680                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 681                                 IPCC_MPROC_SIGNAL_SMP2P>;
 682
 683                 qcom,local-pid = <0>;
 684                 qcom,remote-pid = <5>;
 685
 686                 cdsp_smp2p_out: master-kernel {
 687                         qcom,entry-name = "master-kernel";
 688                         #qcom,smem-state-cells = <1>;
 689                 };
 690
 691                 cdsp_smp2p_in: slave-kernel {
 692                         qcom,entry-name = "slave-kernel";
 693                         interrupt-controller;
 694                         #interrupt-cells = <2>;
 695                 };
 696         };
 697
 698         smp2p-mpss {
 699                 compatible = "qcom,smp2p";
 700                 qcom,smem = <435>, <428>;
 701                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 702                                              IPCC_MPROC_SIGNAL_SMP2P
 703                                              IRQ_TYPE_EDGE_RISING>;
 704                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 705                                 IPCC_MPROC_SIGNAL_SMP2P>;
 706
 707                 qcom,local-pid = <0>;
 708                 qcom,remote-pid = <1>;
 709
 710                 modem_smp2p_out: master-kernel {
 711                         qcom,entry-name = "master-kernel";
 712                         #qcom,smem-state-cells = <1>;
 713                 };
 714
 715                 modem_smp2p_in: slave-kernel {
 716                         qcom,entry-name = "slave-kernel";
 717                         interrupt-controller;
 718                         #interrupt-cells = <2>;
 719                 };
 720
 721                 ipa_smp2p_out: ipa-ap-to-modem {
 722                         qcom,entry-name = "ipa";
 723                         #qcom,smem-state-cells = <1>;
 724                 };
 725
 726                 ipa_smp2p_in: ipa-modem-to-ap {
 727                         qcom,entry-name = "ipa";
 728                         interrupt-controller;
 729                         #interrupt-cells = <2>;
 730                 };
 731         };
 732
 733         smp2p-wpss {
 734                 compatible = "qcom,smp2p";
 735                 qcom,smem = <617>, <616>;
 736                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 737                                              IPCC_MPROC_SIGNAL_SMP2P
 738                                              IRQ_TYPE_EDGE_RISING>;
 739                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 740                                 IPCC_MPROC_SIGNAL_SMP2P>;
 741
 742                 qcom,local-pid = <0>;
 743                 qcom,remote-pid = <13>;
 744
 745                 wpss_smp2p_out: master-kernel {
 746                         qcom,entry-name = "master-kernel";
 747                         #qcom,smem-state-cells = <1>;
 748                 };
 749
 750                 wpss_smp2p_in: slave-kernel {
 751                         qcom,entry-name = "slave-kernel";
 752                         interrupt-controller;
 753                         #interrupt-cells = <2>;
 754                 };
 755         };
 756
 757         pmu {
 758                 compatible = "arm,armv8-pmuv3";
 759                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 760         };
 761
 762         psci {
 763                 compatible = "arm,psci-1.0";
 764                 method = "smc";
 765         };
 766
 767         qspi_opp_table: opp-table-qspi {
 768                 compatible = "operating-points-v2";
 769
 770                 opp-75000000 {
 771                         opp-hz = /bits/ 64 <75000000>;
 772                         required-opps = <&rpmhpd_opp_low_svs>;
 773                 };
 774
 775                 opp-150000000 {
 776                         opp-hz = /bits/ 64 <150000000>;
 777                         required-opps = <&rpmhpd_opp_svs>;
 778                 };
 779
 780                 opp-200000000 {
 781                         opp-hz = /bits/ 64 <200000000>;
 782                         required-opps = <&rpmhpd_opp_svs_l1>;
 783                 };
 784
 785                 opp-300000000 {
 786                         opp-hz = /bits/ 64 <300000000>;
 787                         required-opps = <&rpmhpd_opp_nom>;
 788                 };
 789         };
 790
 791         qup_opp_table: opp-table-qup {
 792                 compatible = "operating-points-v2";
 793
 794                 opp-75000000 {
 795                         opp-hz = /bits/ 64 <75000000>;
 796                         required-opps = <&rpmhpd_opp_low_svs>;
 797                 };
 798
 799                 opp-100000000 {
 800                         opp-hz = /bits/ 64 <100000000>;
 801                         required-opps = <&rpmhpd_opp_svs>;
 802                 };
 803
 804                 opp-128000000 {
 805                         opp-hz = /bits/ 64 <128000000>;
 806                         required-opps = <&rpmhpd_opp_nom>;
 807                 };
 808         };
 809
 810         soc: soc@0 {
 811                 #address-cells = <2>;
 812                 #size-cells = <2>;
 813                 ranges = <0 0 0 0 0x10 0>;
 814                 dma-ranges = <0 0 0 0 0x10 0>;
 815                 compatible = "simple-bus";
 816
 817                 gcc: clock-controller@100000 {
 818                         compatible = "qcom,gcc-sc7280";
 819                         reg = <0 0x00100000 0 0x1f0000>;
 820                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 821                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 822                                  <0>, <&pcie1_lane>,
 823                                  <0>, <0>, <0>,
 824                                  <&usb_1_ssphy>;
 825                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 826                                       "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 827                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 828                                       "ufs_phy_tx_symbol_0_clk",
 829                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 830                         #clock-cells = <1>;
 831                         #reset-cells = <1>;
 832                         #power-domain-cells = <1>;
 833                         power-domains = <&rpmhpd SC7280_CX>;
 834                 };
 835
 836                 ipcc: mailbox@408000 {
 837                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 838                         reg = <0 0x00408000 0 0x1000>;
 839                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 840                         interrupt-controller;
 841                         #interrupt-cells = <3>;
 842                         #mbox-cells = <2>;
 843                 };
 844
 845                 qfprom: efuse@784000 {
 846                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
 847                         reg = <0 0x00784000 0 0xa20>,
 848                               <0 0x00780000 0 0xa20>,
 849                               <0 0x00782000 0 0x120>,
 850                               <0 0x00786000 0 0x1fff>;
 851                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 852                         clock-names = "core";
 853                         power-domains = <&rpmhpd SC7280_MX>;
 854                         #address-cells = <1>;
 855                         #size-cells = <1>;
 856
 857                         gpu_speed_bin: gpu_speed_bin@1e9 {
 858                                 reg = <0x1e9 0x2>;
 859                                 bits = <5 8>;
 860                         };
 861                 };
 862
 863                 sdhc_1: mmc@7c4000 {
 864                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 865                         pinctrl-names = "default", "sleep";
 866                         pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
 867                         pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
 868                         status = "disabled";
 869
 870                         reg = <0 0x007c4000 0 0x1000>,
 871                               <0 0x007c5000 0 0x1000>;
 872                         reg-names = "hc", "cqhci";
 873
 874                         iommus = <&apps_smmu 0xc0 0x0>;
 875                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 876                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 877                         interrupt-names = "hc_irq", "pwr_irq";
 878
 879                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 880                                  <&gcc GCC_SDCC1_APPS_CLK>,
 881                                  <&rpmhcc RPMH_CXO_CLK>;
 882                         clock-names = "iface", "core", "xo";
 883                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 884                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 885                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 886                         power-domains = <&rpmhpd SC7280_CX>;
 887                         operating-points-v2 = <&sdhc1_opp_table>;
 888
 889                         bus-width = <8>;
 890                         supports-cqe;
 891
 892                         qcom,dll-config = <0x0007642c>;
 893                         qcom,ddr-config = <0x80040868>;
 894
 895                         mmc-ddr-1_8v;
 896                         mmc-hs200-1_8v;
 897                         mmc-hs400-1_8v;
 898                         mmc-hs400-enhanced-strobe;
 899
 900                         resets = <&gcc GCC_SDCC1_BCR>;
 901
 902                         sdhc1_opp_table: opp-table {
 903                                 compatible = "operating-points-v2";
 904
 905                                 opp-100000000 {
 906                                         opp-hz = /bits/ 64 <100000000>;
 907                                         required-opps = <&rpmhpd_opp_low_svs>;
 908                                         opp-peak-kBps = <1800000 400000>;
 909                                         opp-avg-kBps = <100000 0>;
 910                                 };
 911
 912                                 opp-384000000 {
 913                                         opp-hz = /bits/ 64 <384000000>;
 914                                         required-opps = <&rpmhpd_opp_nom>;
 915                                         opp-peak-kBps = <5400000 1600000>;
 916                                         opp-avg-kBps = <390000 0>;
 917                                 };
 918                         };
 919
 920                 };
 921
 922                 gpi_dma0: dma-controller@900000 {
 923                         #dma-cells = <3>;
 924                         compatible = "qcom,sc7280-gpi-dma";
 925                         reg = <0 0x00900000 0 0x60000>;
 926                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 935                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 936                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 937                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 938                         dma-channels = <12>;
 939                         dma-channel-mask = <0x7f>;
 940                         iommus = <&apps_smmu 0x0136 0x0>;
 941                         status = "disabled";
 942                 };
 943
 944                 qupv3_id_0: geniqup@9c0000 {
 945                         compatible = "qcom,geni-se-qup";
 946                         reg = <0 0x009c0000 0 0x2000>;
 947                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 948                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 949                         clock-names = "m-ahb", "s-ahb";
 950                         #address-cells = <2>;
 951                         #size-cells = <2>;
 952                         ranges;
 953                         iommus = <&apps_smmu 0x123 0x0>;
 954                         status = "disabled";
 955
 956                         i2c0: i2c@980000 {
 957                                 compatible = "qcom,geni-i2c";
 958                                 reg = <0 0x00980000 0 0x4000>;
 959                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 960                                 clock-names = "se";
 961                                 pinctrl-names = "default";
 962                                 pinctrl-0 = <&qup_i2c0_data_clk>;
 963                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 964                                 #address-cells = <1>;
 965                                 #size-cells = <0>;
 966                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 967                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 968                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 969                                 interconnect-names = "qup-core", "qup-config",
 970                                                         "qup-memory";
 971                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 972                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 973                                 dma-names = "tx", "rx";
 974                                 status = "disabled";
 975                         };
 976
 977                         spi0: spi@980000 {
 978                                 compatible = "qcom,geni-spi";
 979                                 reg = <0 0x00980000 0 0x4000>;
 980                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 981                                 clock-names = "se";
 982                                 pinctrl-names = "default";
 983                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
 984                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 985                                 #address-cells = <1>;
 986                                 #size-cells = <0>;
 987                                 power-domains = <&rpmhpd SC7280_CX>;
 988                                 operating-points-v2 = <&qup_opp_table>;
 989                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 990                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 991                                 interconnect-names = "qup-core", "qup-config";
 992                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 993                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 994                                 dma-names = "tx", "rx";
 995                                 status = "disabled";
 996                         };
 997
 998                         uart0: serial@980000 {
 999                                 compatible = "qcom,geni-uart";
1000                                 reg = <0 0x00980000 0 0x4000>;
1001                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1002                                 clock-names = "se";
1003                                 pinctrl-names = "default";
1004                                 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1005                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1006                                 power-domains = <&rpmhpd SC7280_CX>;
1007                                 operating-points-v2 = <&qup_opp_table>;
1008                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1009                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1010                                 interconnect-names = "qup-core", "qup-config";
1011                                 status = "disabled";
1012                         };
1013
1014                         i2c1: i2c@984000 {
1015                                 compatible = "qcom,geni-i2c";
1016                                 reg = <0 0x00984000 0 0x4000>;
1017                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1018                                 clock-names = "se";
1019                                 pinctrl-names = "default";
1020                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1021                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1022                                 #address-cells = <1>;
1023                                 #size-cells = <0>;
1024                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1025                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1026                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1027                                 interconnect-names = "qup-core", "qup-config",
1028                                                         "qup-memory";
1029                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031                                 dma-names = "tx", "rx";
1032                                 status = "disabled";
1033                         };
1034
1035                         spi1: spi@984000 {
1036                                 compatible = "qcom,geni-spi";
1037                                 reg = <0 0x00984000 0 0x4000>;
1038                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1039                                 clock-names = "se";
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1042                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 power-domains = <&rpmhpd SC7280_CX>;
1046                                 operating-points-v2 = <&qup_opp_table>;
1047                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1048                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1049                                 interconnect-names = "qup-core", "qup-config";
1050                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1051                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1052                                 dma-names = "tx", "rx";
1053                                 status = "disabled";
1054                         };
1055
1056                         uart1: serial@984000 {
1057                                 compatible = "qcom,geni-uart";
1058                                 reg = <0 0x00984000 0 0x4000>;
1059                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1060                                 clock-names = "se";
1061                                 pinctrl-names = "default";
1062                                 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1063                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1064                                 power-domains = <&rpmhpd SC7280_CX>;
1065                                 operating-points-v2 = <&qup_opp_table>;
1066                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1067                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1068                                 interconnect-names = "qup-core", "qup-config";
1069                                 status = "disabled";
1070                         };
1071
1072                         i2c2: i2c@988000 {
1073                                 compatible = "qcom,geni-i2c";
1074                                 reg = <0 0x00988000 0 0x4000>;
1075                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1076                                 clock-names = "se";
1077                                 pinctrl-names = "default";
1078                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1079                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1080                                 #address-cells = <1>;
1081                                 #size-cells = <0>;
1082                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1083                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1084                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1085                                 interconnect-names = "qup-core", "qup-config",
1086                                                         "qup-memory";
1087                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1088                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1089                                 dma-names = "tx", "rx";
1090                                 status = "disabled";
1091                         };
1092
1093                         spi2: spi@988000 {
1094                                 compatible = "qcom,geni-spi";
1095                                 reg = <0 0x00988000 0 0x4000>;
1096                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1097                                 clock-names = "se";
1098                                 pinctrl-names = "default";
1099                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1100                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103                                 power-domains = <&rpmhpd SC7280_CX>;
1104                                 operating-points-v2 = <&qup_opp_table>;
1105                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1106                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1107                                 interconnect-names = "qup-core", "qup-config";
1108                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1109                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1110                                 dma-names = "tx", "rx";
1111                                 status = "disabled";
1112                         };
1113
1114                         uart2: serial@988000 {
1115                                 compatible = "qcom,geni-uart";
1116                                 reg = <0 0x00988000 0 0x4000>;
1117                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1118                                 clock-names = "se";
1119                                 pinctrl-names = "default";
1120                                 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1121                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1122                                 power-domains = <&rpmhpd SC7280_CX>;
1123                                 operating-points-v2 = <&qup_opp_table>;
1124                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1125                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1126                                 interconnect-names = "qup-core", "qup-config";
1127                                 status = "disabled";
1128                         };
1129
1130                         i2c3: i2c@98c000 {
1131                                 compatible = "qcom,geni-i2c";
1132                                 reg = <0 0x0098c000 0 0x4000>;
1133                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1134                                 clock-names = "se";
1135                                 pinctrl-names = "default";
1136                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1137                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1141                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1142                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1143                                 interconnect-names = "qup-core", "qup-config",
1144                                                         "qup-memory";
1145                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1146                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1147                                 dma-names = "tx", "rx";
1148                                 status = "disabled";
1149                         };
1150
1151                         spi3: spi@98c000 {
1152                                 compatible = "qcom,geni-spi";
1153                                 reg = <0 0x0098c000 0 0x4000>;
1154                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1155                                 clock-names = "se";
1156                                 pinctrl-names = "default";
1157                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1158                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1159                                 #address-cells = <1>;
1160                                 #size-cells = <0>;
1161                                 power-domains = <&rpmhpd SC7280_CX>;
1162                                 operating-points-v2 = <&qup_opp_table>;
1163                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1165                                 interconnect-names = "qup-core", "qup-config";
1166                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1167                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1168                                 dma-names = "tx", "rx";
1169                                 status = "disabled";
1170                         };
1171
1172                         uart3: serial@98c000 {
1173                                 compatible = "qcom,geni-uart";
1174                                 reg = <0 0x0098c000 0 0x4000>;
1175                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1176                                 clock-names = "se";
1177                                 pinctrl-names = "default";
1178                                 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1179                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1180                                 power-domains = <&rpmhpd SC7280_CX>;
1181                                 operating-points-v2 = <&qup_opp_table>;
1182                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1183                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1184                                 interconnect-names = "qup-core", "qup-config";
1185                                 status = "disabled";
1186                         };
1187
1188                         i2c4: i2c@990000 {
1189                                 compatible = "qcom,geni-i2c";
1190                                 reg = <0 0x00990000 0 0x4000>;
1191                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1192                                 clock-names = "se";
1193                                 pinctrl-names = "default";
1194                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1195                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1196                                 #address-cells = <1>;
1197                                 #size-cells = <0>;
1198                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1199                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1200                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1201                                 interconnect-names = "qup-core", "qup-config",
1202                                                         "qup-memory";
1203                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1204                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1205                                 dma-names = "tx", "rx";
1206                                 status = "disabled";
1207                         };
1208
1209                         spi4: spi@990000 {
1210                                 compatible = "qcom,geni-spi";
1211                                 reg = <0 0x00990000 0 0x4000>;
1212                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1213                                 clock-names = "se";
1214                                 pinctrl-names = "default";
1215                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1216                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1217                                 #address-cells = <1>;
1218                                 #size-cells = <0>;
1219                                 power-domains = <&rpmhpd SC7280_CX>;
1220                                 operating-points-v2 = <&qup_opp_table>;
1221                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1223                                 interconnect-names = "qup-core", "qup-config";
1224                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1225                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1226                                 dma-names = "tx", "rx";
1227                                 status = "disabled";
1228                         };
1229
1230                         uart4: serial@990000 {
1231                                 compatible = "qcom,geni-uart";
1232                                 reg = <0 0x00990000 0 0x4000>;
1233                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1234                                 clock-names = "se";
1235                                 pinctrl-names = "default";
1236                                 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1237                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1238                                 power-domains = <&rpmhpd SC7280_CX>;
1239                                 operating-points-v2 = <&qup_opp_table>;
1240                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1241                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1242                                 interconnect-names = "qup-core", "qup-config";
1243                                 status = "disabled";
1244                         };
1245
1246                         i2c5: i2c@994000 {
1247                                 compatible = "qcom,geni-i2c";
1248                                 reg = <0 0x00994000 0 0x4000>;
1249                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1250                                 clock-names = "se";
1251                                 pinctrl-names = "default";
1252                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1253                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1254                                 #address-cells = <1>;
1255                                 #size-cells = <0>;
1256                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1257                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1258                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1259                                 interconnect-names = "qup-core", "qup-config",
1260                                                         "qup-memory";
1261                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1262                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1263                                 dma-names = "tx", "rx";
1264                                 status = "disabled";
1265                         };
1266
1267                         spi5: spi@994000 {
1268                                 compatible = "qcom,geni-spi";
1269                                 reg = <0 0x00994000 0 0x4000>;
1270                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1271                                 clock-names = "se";
1272                                 pinctrl-names = "default";
1273                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1274                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1275                                 #address-cells = <1>;
1276                                 #size-cells = <0>;
1277                                 power-domains = <&rpmhpd SC7280_CX>;
1278                                 operating-points-v2 = <&qup_opp_table>;
1279                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1280                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1281                                 interconnect-names = "qup-core", "qup-config";
1282                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1283                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1284                                 dma-names = "tx", "rx";
1285                                 status = "disabled";
1286                         };
1287
1288                         uart5: serial@994000 {
1289                                 compatible = "qcom,geni-uart";
1290                                 reg = <0 0x00994000 0 0x4000>;
1291                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1292                                 clock-names = "se";
1293                                 pinctrl-names = "default";
1294                                 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1295                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1296                                 power-domains = <&rpmhpd SC7280_CX>;
1297                                 operating-points-v2 = <&qup_opp_table>;
1298                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1299                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1300                                 interconnect-names = "qup-core", "qup-config";
1301                                 status = "disabled";
1302                         };
1303
1304                         i2c6: i2c@998000 {
1305                                 compatible = "qcom,geni-i2c";
1306                                 reg = <0 0x00998000 0 0x4000>;
1307                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1308                                 clock-names = "se";
1309                                 pinctrl-names = "default";
1310                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1311                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1315                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1316                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1317                                 interconnect-names = "qup-core", "qup-config",
1318                                                         "qup-memory";
1319                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1320                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1321                                 dma-names = "tx", "rx";
1322                                 status = "disabled";
1323                         };
1324
1325                         spi6: spi@998000 {
1326                                 compatible = "qcom,geni-spi";
1327                                 reg = <0 0x00998000 0 0x4000>;
1328                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1329                                 clock-names = "se";
1330                                 pinctrl-names = "default";
1331                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1332                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1333                                 #address-cells = <1>;
1334                                 #size-cells = <0>;
1335                                 power-domains = <&rpmhpd SC7280_CX>;
1336                                 operating-points-v2 = <&qup_opp_table>;
1337                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1338                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1339                                 interconnect-names = "qup-core", "qup-config";
1340                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1341                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1342                                 dma-names = "tx", "rx";
1343                                 status = "disabled";
1344                         };
1345
1346                         uart6: serial@998000 {
1347                                 compatible = "qcom,geni-uart";
1348                                 reg = <0 0x00998000 0 0x4000>;
1349                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1350                                 clock-names = "se";
1351                                 pinctrl-names = "default";
1352                                 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1353                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1354                                 power-domains = <&rpmhpd SC7280_CX>;
1355                                 operating-points-v2 = <&qup_opp_table>;
1356                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1357                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1358                                 interconnect-names = "qup-core", "qup-config";
1359                                 status = "disabled";
1360                         };
1361
1362                         i2c7: i2c@99c000 {
1363                                 compatible = "qcom,geni-i2c";
1364                                 reg = <0 0x0099c000 0 0x4000>;
1365                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1366                                 clock-names = "se";
1367                                 pinctrl-names = "default";
1368                                 pinctrl-0 = <&qup_i2c7_data_clk>;
1369                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1370                                 #address-cells = <1>;
1371                                 #size-cells = <0>;
1372                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1373                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1374                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1375                                 interconnect-names = "qup-core", "qup-config",
1376                                                         "qup-memory";
1377                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1378                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1379                                 dma-names = "tx", "rx";
1380                                 status = "disabled";
1381                         };
1382
1383                         spi7: spi@99c000 {
1384                                 compatible = "qcom,geni-spi";
1385                                 reg = <0 0x0099c000 0 0x4000>;
1386                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1387                                 clock-names = "se";
1388                                 pinctrl-names = "default";
1389                                 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1390                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1391                                 #address-cells = <1>;
1392                                 #size-cells = <0>;
1393                                 power-domains = <&rpmhpd SC7280_CX>;
1394                                 operating-points-v2 = <&qup_opp_table>;
1395                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1397                                 interconnect-names = "qup-core", "qup-config";
1398                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1399                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1400                                 dma-names = "tx", "rx";
1401                                 status = "disabled";
1402                         };
1403
1404                         uart7: serial@99c000 {
1405                                 compatible = "qcom,geni-uart";
1406                                 reg = <0 0x0099c000 0 0x4000>;
1407                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1408                                 clock-names = "se";
1409                                 pinctrl-names = "default";
1410                                 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1411                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1412                                 power-domains = <&rpmhpd SC7280_CX>;
1413                                 operating-points-v2 = <&qup_opp_table>;
1414                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1415                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1416                                 interconnect-names = "qup-core", "qup-config";
1417                                 status = "disabled";
1418                         };
1419                 };
1420
1421                 gpi_dma1: dma-controller@a00000 {
1422                         #dma-cells = <3>;
1423                         compatible = "qcom,sc7280-gpi-dma";
1424                         reg = <0 0x00a00000 0 0x60000>;
1425                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1426                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1427                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1428                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1434                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1435                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1436                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1437                         dma-channels = <12>;
1438                         dma-channel-mask = <0x1e>;
1439                         iommus = <&apps_smmu 0x56 0x0>;
1440                         status = "disabled";
1441                 };
1442
1443                 qupv3_id_1: geniqup@ac0000 {
1444                         compatible = "qcom,geni-se-qup";
1445                         reg = <0 0x00ac0000 0 0x2000>;
1446                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1447                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1448                         clock-names = "m-ahb", "s-ahb";
1449                         #address-cells = <2>;
1450                         #size-cells = <2>;
1451                         ranges;
1452                         iommus = <&apps_smmu 0x43 0x0>;
1453                         status = "disabled";
1454
1455                         i2c8: i2c@a80000 {
1456                                 compatible = "qcom,geni-i2c";
1457                                 reg = <0 0x00a80000 0 0x4000>;
1458                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1459                                 clock-names = "se";
1460                                 pinctrl-names = "default";
1461                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1462                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1463                                 #address-cells = <1>;
1464                                 #size-cells = <0>;
1465                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1466                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1467                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1468                                 interconnect-names = "qup-core", "qup-config",
1469                                                         "qup-memory";
1470                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1471                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1472                                 dma-names = "tx", "rx";
1473                                 status = "disabled";
1474                         };
1475
1476                         spi8: spi@a80000 {
1477                                 compatible = "qcom,geni-spi";
1478                                 reg = <0 0x00a80000 0 0x4000>;
1479                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1480                                 clock-names = "se";
1481                                 pinctrl-names = "default";
1482                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1483                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1484                                 #address-cells = <1>;
1485                                 #size-cells = <0>;
1486                                 power-domains = <&rpmhpd SC7280_CX>;
1487                                 operating-points-v2 = <&qup_opp_table>;
1488                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1489                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1490                                 interconnect-names = "qup-core", "qup-config";
1491                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1492                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1493                                 dma-names = "tx", "rx";
1494                                 status = "disabled";
1495                         };
1496
1497                         uart8: serial@a80000 {
1498                                 compatible = "qcom,geni-uart";
1499                                 reg = <0 0x00a80000 0 0x4000>;
1500                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1501                                 clock-names = "se";
1502                                 pinctrl-names = "default";
1503                                 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1504                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1505                                 power-domains = <&rpmhpd SC7280_CX>;
1506                                 operating-points-v2 = <&qup_opp_table>;
1507                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1508                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1509                                 interconnect-names = "qup-core", "qup-config";
1510                                 status = "disabled";
1511                         };
1512
1513                         i2c9: i2c@a84000 {
1514                                 compatible = "qcom,geni-i2c";
1515                                 reg = <0 0x00a84000 0 0x4000>;
1516                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1517                                 clock-names = "se";
1518                                 pinctrl-names = "default";
1519                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1520                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1521                                 #address-cells = <1>;
1522                                 #size-cells = <0>;
1523                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1524                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1525                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1526                                 interconnect-names = "qup-core", "qup-config",
1527                                                         "qup-memory";
1528                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1529                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1530                                 dma-names = "tx", "rx";
1531                                 status = "disabled";
1532                         };
1533
1534                         spi9: spi@a84000 {
1535                                 compatible = "qcom,geni-spi";
1536                                 reg = <0 0x00a84000 0 0x4000>;
1537                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1538                                 clock-names = "se";
1539                                 pinctrl-names = "default";
1540                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1541                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1542                                 #address-cells = <1>;
1543                                 #size-cells = <0>;
1544                                 power-domains = <&rpmhpd SC7280_CX>;
1545                                 operating-points-v2 = <&qup_opp_table>;
1546                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1547                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1548                                 interconnect-names = "qup-core", "qup-config";
1549                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1550                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1551                                 dma-names = "tx", "rx";
1552                                 status = "disabled";
1553                         };
1554
1555                         uart9: serial@a84000 {
1556                                 compatible = "qcom,geni-uart";
1557                                 reg = <0 0x00a84000 0 0x4000>;
1558                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1559                                 clock-names = "se";
1560                                 pinctrl-names = "default";
1561                                 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1562                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1563                                 power-domains = <&rpmhpd SC7280_CX>;
1564                                 operating-points-v2 = <&qup_opp_table>;
1565                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1567                                 interconnect-names = "qup-core", "qup-config";
1568                                 status = "disabled";
1569                         };
1570
1571                         i2c10: i2c@a88000 {
1572                                 compatible = "qcom,geni-i2c";
1573                                 reg = <0 0x00a88000 0 0x4000>;
1574                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1575                                 clock-names = "se";
1576                                 pinctrl-names = "default";
1577                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1578                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579                                 #address-cells = <1>;
1580                                 #size-cells = <0>;
1581                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1582                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1583                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1584                                 interconnect-names = "qup-core", "qup-config",
1585                                                         "qup-memory";
1586                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1587                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1588                                 dma-names = "tx", "rx";
1589                                 status = "disabled";
1590                         };
1591
1592                         spi10: spi@a88000 {
1593                                 compatible = "qcom,geni-spi";
1594                                 reg = <0 0x00a88000 0 0x4000>;
1595                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1596                                 clock-names = "se";
1597                                 pinctrl-names = "default";
1598                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1599                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1600                                 #address-cells = <1>;
1601                                 #size-cells = <0>;
1602                                 power-domains = <&rpmhpd SC7280_CX>;
1603                                 operating-points-v2 = <&qup_opp_table>;
1604                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1606                                 interconnect-names = "qup-core", "qup-config";
1607                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1608                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1609                                 dma-names = "tx", "rx";
1610                                 status = "disabled";
1611                         };
1612
1613                         uart10: serial@a88000 {
1614                                 compatible = "qcom,geni-uart";
1615                                 reg = <0 0x00a88000 0 0x4000>;
1616                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1617                                 clock-names = "se";
1618                                 pinctrl-names = "default";
1619                                 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1620                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1621                                 power-domains = <&rpmhpd SC7280_CX>;
1622                                 operating-points-v2 = <&qup_opp_table>;
1623                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1625                                 interconnect-names = "qup-core", "qup-config";
1626                                 status = "disabled";
1627                         };
1628
1629                         i2c11: i2c@a8c000 {
1630                                 compatible = "qcom,geni-i2c";
1631                                 reg = <0 0x00a8c000 0 0x4000>;
1632                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1633                                 clock-names = "se";
1634                                 pinctrl-names = "default";
1635                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1636                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1637                                 #address-cells = <1>;
1638                                 #size-cells = <0>;
1639                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1641                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642                                 interconnect-names = "qup-core", "qup-config",
1643                                                         "qup-memory";
1644                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1645                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1646                                 dma-names = "tx", "rx";
1647                                 status = "disabled";
1648                         };
1649
1650                         spi11: spi@a8c000 {
1651                                 compatible = "qcom,geni-spi";
1652                                 reg = <0 0x00a8c000 0 0x4000>;
1653                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1654                                 clock-names = "se";
1655                                 pinctrl-names = "default";
1656                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1657                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1658                                 #address-cells = <1>;
1659                                 #size-cells = <0>;
1660                                 power-domains = <&rpmhpd SC7280_CX>;
1661                                 operating-points-v2 = <&qup_opp_table>;
1662                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1663                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1664                                 interconnect-names = "qup-core", "qup-config";
1665                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1666                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1667                                 dma-names = "tx", "rx";
1668                                 status = "disabled";
1669                         };
1670
1671                         uart11: serial@a8c000 {
1672                                 compatible = "qcom,geni-uart";
1673                                 reg = <0 0x00a8c000 0 0x4000>;
1674                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1675                                 clock-names = "se";
1676                                 pinctrl-names = "default";
1677                                 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1678                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1679                                 power-domains = <&rpmhpd SC7280_CX>;
1680                                 operating-points-v2 = <&qup_opp_table>;
1681                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1682                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1683                                 interconnect-names = "qup-core", "qup-config";
1684                                 status = "disabled";
1685                         };
1686
1687                         i2c12: i2c@a90000 {
1688                                 compatible = "qcom,geni-i2c";
1689                                 reg = <0 0x00a90000 0 0x4000>;
1690                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1691                                 clock-names = "se";
1692                                 pinctrl-names = "default";
1693                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1694                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1695                                 #address-cells = <1>;
1696                                 #size-cells = <0>;
1697                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1698                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1699                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1700                                 interconnect-names = "qup-core", "qup-config",
1701                                                         "qup-memory";
1702                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1703                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1704                                 dma-names = "tx", "rx";
1705                                 status = "disabled";
1706                         };
1707
1708                         spi12: spi@a90000 {
1709                                 compatible = "qcom,geni-spi";
1710                                 reg = <0 0x00a90000 0 0x4000>;
1711                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1712                                 clock-names = "se";
1713                                 pinctrl-names = "default";
1714                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1715                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1716                                 #address-cells = <1>;
1717                                 #size-cells = <0>;
1718                                 power-domains = <&rpmhpd SC7280_CX>;
1719                                 operating-points-v2 = <&qup_opp_table>;
1720                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1721                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1722                                 interconnect-names = "qup-core", "qup-config";
1723                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1724                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1725                                 dma-names = "tx", "rx";
1726                                 status = "disabled";
1727                         };
1728
1729                         uart12: serial@a90000 {
1730                                 compatible = "qcom,geni-uart";
1731                                 reg = <0 0x00a90000 0 0x4000>;
1732                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1733                                 clock-names = "se";
1734                                 pinctrl-names = "default";
1735                                 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1736                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1737                                 power-domains = <&rpmhpd SC7280_CX>;
1738                                 operating-points-v2 = <&qup_opp_table>;
1739                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1740                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1741                                 interconnect-names = "qup-core", "qup-config";
1742                                 status = "disabled";
1743                         };
1744
1745                         i2c13: i2c@a94000 {
1746                                 compatible = "qcom,geni-i2c";
1747                                 reg = <0 0x00a94000 0 0x4000>;
1748                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1749                                 clock-names = "se";
1750                                 pinctrl-names = "default";
1751                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1752                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1753                                 #address-cells = <1>;
1754                                 #size-cells = <0>;
1755                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1756                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1757                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1758                                 interconnect-names = "qup-core", "qup-config",
1759                                                         "qup-memory";
1760                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1761                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1762                                 dma-names = "tx", "rx";
1763                                 status = "disabled";
1764                         };
1765
1766                         spi13: spi@a94000 {
1767                                 compatible = "qcom,geni-spi";
1768                                 reg = <0 0x00a94000 0 0x4000>;
1769                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1770                                 clock-names = "se";
1771                                 pinctrl-names = "default";
1772                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1773                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1774                                 #address-cells = <1>;
1775                                 #size-cells = <0>;
1776                                 power-domains = <&rpmhpd SC7280_CX>;
1777                                 operating-points-v2 = <&qup_opp_table>;
1778                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1779                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1780                                 interconnect-names = "qup-core", "qup-config";
1781                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1782                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1783                                 dma-names = "tx", "rx";
1784                                 status = "disabled";
1785                         };
1786
1787                         uart13: serial@a94000 {
1788                                 compatible = "qcom,geni-uart";
1789                                 reg = <0 0x00a94000 0 0x4000>;
1790                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1791                                 clock-names = "se";
1792                                 pinctrl-names = "default";
1793                                 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1794                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1795                                 power-domains = <&rpmhpd SC7280_CX>;
1796                                 operating-points-v2 = <&qup_opp_table>;
1797                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1798                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1799                                 interconnect-names = "qup-core", "qup-config";
1800                                 status = "disabled";
1801                         };
1802
1803                         i2c14: i2c@a98000 {
1804                                 compatible = "qcom,geni-i2c";
1805                                 reg = <0 0x00a98000 0 0x4000>;
1806                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1807                                 clock-names = "se";
1808                                 pinctrl-names = "default";
1809                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1810                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1811                                 #address-cells = <1>;
1812                                 #size-cells = <0>;
1813                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1814                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1815                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1816                                 interconnect-names = "qup-core", "qup-config",
1817                                                         "qup-memory";
1818                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1819                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1820                                 dma-names = "tx", "rx";
1821                                 status = "disabled";
1822                         };
1823
1824                         spi14: spi@a98000 {
1825                                 compatible = "qcom,geni-spi";
1826                                 reg = <0 0x00a98000 0 0x4000>;
1827                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1828                                 clock-names = "se";
1829                                 pinctrl-names = "default";
1830                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1831                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1832                                 #address-cells = <1>;
1833                                 #size-cells = <0>;
1834                                 power-domains = <&rpmhpd SC7280_CX>;
1835                                 operating-points-v2 = <&qup_opp_table>;
1836                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1837                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1838                                 interconnect-names = "qup-core", "qup-config";
1839                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1840                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1841                                 dma-names = "tx", "rx";
1842                                 status = "disabled";
1843                         };
1844
1845                         uart14: serial@a98000 {
1846                                 compatible = "qcom,geni-uart";
1847                                 reg = <0 0x00a98000 0 0x4000>;
1848                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1849                                 clock-names = "se";
1850                                 pinctrl-names = "default";
1851                                 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1852                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1853                                 power-domains = <&rpmhpd SC7280_CX>;
1854                                 operating-points-v2 = <&qup_opp_table>;
1855                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1856                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1857                                 interconnect-names = "qup-core", "qup-config";
1858                                 status = "disabled";
1859                         };
1860
1861                         i2c15: i2c@a9c000 {
1862                                 compatible = "qcom,geni-i2c";
1863                                 reg = <0 0x00a9c000 0 0x4000>;
1864                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1865                                 clock-names = "se";
1866                                 pinctrl-names = "default";
1867                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1868                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1869                                 #address-cells = <1>;
1870                                 #size-cells = <0>;
1871                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1872                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1873                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1874                                 interconnect-names = "qup-core", "qup-config",
1875                                                         "qup-memory";
1876                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1877                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1878                                 dma-names = "tx", "rx";
1879                                 status = "disabled";
1880                         };
1881
1882                         spi15: spi@a9c000 {
1883                                 compatible = "qcom,geni-spi";
1884                                 reg = <0 0x00a9c000 0 0x4000>;
1885                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1886                                 clock-names = "se";
1887                                 pinctrl-names = "default";
1888                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1889                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1890                                 #address-cells = <1>;
1891                                 #size-cells = <0>;
1892                                 power-domains = <&rpmhpd SC7280_CX>;
1893                                 operating-points-v2 = <&qup_opp_table>;
1894                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1895                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1896                                 interconnect-names = "qup-core", "qup-config";
1897                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1898                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1899                                 dma-names = "tx", "rx";
1900                                 status = "disabled";
1901                         };
1902
1903                         uart15: serial@a9c000 {
1904                                 compatible = "qcom,geni-uart";
1905                                 reg = <0 0x00a9c000 0 0x4000>;
1906                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1907                                 clock-names = "se";
1908                                 pinctrl-names = "default";
1909                                 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1910                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1911                                 power-domains = <&rpmhpd SC7280_CX>;
1912                                 operating-points-v2 = <&qup_opp_table>;
1913                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1914                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1915                                 interconnect-names = "qup-core", "qup-config";
1916                                 status = "disabled";
1917                         };
1918                 };
1919
1920                 cnoc2: interconnect@1500000 {
1921                         reg = <0 0x01500000 0 0x1000>;
1922                         compatible = "qcom,sc7280-cnoc2";
1923                         #interconnect-cells = <2>;
1924                         qcom,bcm-voters = <&apps_bcm_voter>;
1925                 };
1926
1927                 cnoc3: interconnect@1502000 {
1928                         reg = <0 0x01502000 0 0x1000>;
1929                         compatible = "qcom,sc7280-cnoc3";
1930                         #interconnect-cells = <2>;
1931                         qcom,bcm-voters = <&apps_bcm_voter>;
1932                 };
1933
1934                 mc_virt: interconnect@1580000 {
1935                         reg = <0 0x01580000 0 0x4>;
1936                         compatible = "qcom,sc7280-mc-virt";
1937                         #interconnect-cells = <2>;
1938                         qcom,bcm-voters = <&apps_bcm_voter>;
1939                 };
1940
1941                 system_noc: interconnect@1680000 {
1942                         reg = <0 0x01680000 0 0x15480>;
1943                         compatible = "qcom,sc7280-system-noc";
1944                         #interconnect-cells = <2>;
1945                         qcom,bcm-voters = <&apps_bcm_voter>;
1946                 };
1947
1948                 aggre1_noc: interconnect@16e0000 {
1949                         compatible = "qcom,sc7280-aggre1-noc";
1950                         reg = <0 0x016e0000 0 0x1c080>;
1951                         #interconnect-cells = <2>;
1952                         qcom,bcm-voters = <&apps_bcm_voter>;
1953                 };
1954
1955                 aggre2_noc: interconnect@1700000 {
1956                         reg = <0 0x01700000 0 0x2b080>;
1957                         compatible = "qcom,sc7280-aggre2-noc";
1958                         #interconnect-cells = <2>;
1959                         qcom,bcm-voters = <&apps_bcm_voter>;
1960                 };
1961
1962                 mmss_noc: interconnect@1740000 {
1963                         reg = <0 0x01740000 0 0x1e080>;
1964                         compatible = "qcom,sc7280-mmss-noc";
1965                         #interconnect-cells = <2>;
1966                         qcom,bcm-voters = <&apps_bcm_voter>;
1967                 };
1968
1969                 wifi: wifi@17a10040 {
1970                         compatible = "qcom,wcn6750-wifi";
1971                         reg = <0 0x17a10040 0 0x0>;
1972                         iommus = <&apps_smmu 0x1c00 0x1>;
1973                         interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
1974                                      <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
1975                                      <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
1976                                      <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
1977                                      <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
1978                                      <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
1979                                      <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
1980                                      <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
1981                                      <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
1982                                      <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
1983                                      <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
1984                                      <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
1985                                      <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
1986                                      <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
1987                                      <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
1988                                      <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
1989                                      <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
1990                                      <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
1991                                      <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
1992                                      <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
1993                                      <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
1994                                      <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
1995                                      <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
1996                                      <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
1997                                      <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
1998                                      <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
1999                                      <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2000                                      <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2001                                      <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2002                                      <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2003                                      <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2004                                      <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2005                         qcom,rproc = <&remoteproc_wpss>;
2006                         memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2007                         status = "disabled";
2008                 };
2009
2010                 pcie1: pci@1c08000 {
2011                         compatible = "qcom,pcie-sc7280";
2012                         reg = <0 0x01c08000 0 0x3000>,
2013                               <0 0x40000000 0 0xf1d>,
2014                               <0 0x40000f20 0 0xa8>,
2015                               <0 0x40001000 0 0x1000>,
2016                               <0 0x40100000 0 0x100000>;
2017
2018                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2019                         device_type = "pci";
2020                         linux,pci-domain = <1>;
2021                         bus-range = <0x00 0xff>;
2022                         num-lanes = <2>;
2023
2024                         #address-cells = <3>;
2025                         #size-cells = <2>;
2026
2027                         ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2028                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2029
2030                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2031                         interrupt-names = "msi";
2032                         #interrupt-cells = <1>;
2033                         interrupt-map-mask = <0 0 0 0x7>;
2034                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2035                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2036                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2037                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2038
2039                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2040                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2041                                  <&pcie1_lane>,
2042                                  <&rpmhcc RPMH_CXO_CLK>,
2043                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2044                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2045                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2046                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2047                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2048                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2049                                  <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2050                                  <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2051                                  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2052
2053                         clock-names = "pipe",
2054                                       "pipe_mux",
2055                                       "phy_pipe",
2056                                       "ref",
2057                                       "aux",
2058                                       "cfg",
2059                                       "bus_master",
2060                                       "bus_slave",
2061                                       "slave_q2a",
2062                                       "tbu",
2063                                       "ddrss_sf_tbu",
2064                                       "aggre0",
2065                                       "aggre1";
2066
2067                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2068                         assigned-clock-rates = <19200000>;
2069
2070                         resets = <&gcc GCC_PCIE_1_BCR>;
2071                         reset-names = "pci";
2072
2073                         power-domains = <&gcc GCC_PCIE_1_GDSC>;
2074
2075                         phys = <&pcie1_lane>;
2076                         phy-names = "pciephy";
2077
2078                         pinctrl-names = "default";
2079                         pinctrl-0 = <&pcie1_clkreq_n>;
2080
2081                         dma-coherent;
2082
2083                         iommus = <&apps_smmu 0x1c80 0x1>;
2084
2085                         iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2086                                     <0x100 &apps_smmu 0x1c81 0x1>;
2087
2088                         status = "disabled";
2089                 };
2090
2091                 pcie1_phy: phy@1c0e000 {
2092                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2093                         reg = <0 0x01c0e000 0 0x1c0>;
2094                         #address-cells = <2>;
2095                         #size-cells = <2>;
2096                         ranges;
2097                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2098                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2099                                  <&gcc GCC_PCIE_CLKREF_EN>,
2100                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2101                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2102
2103                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2104                         reset-names = "phy";
2105
2106                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2107                         assigned-clock-rates = <100000000>;
2108
2109                         status = "disabled";
2110
2111                         pcie1_lane: phy@1c0e200 {
2112                                 reg = <0 0x01c0e200 0 0x170>,
2113                                       <0 0x01c0e400 0 0x200>,
2114                                       <0 0x01c0ea00 0 0x1f0>,
2115                                       <0 0x01c0e600 0 0x170>,
2116                                       <0 0x01c0e800 0 0x200>,
2117                                       <0 0x01c0ee00 0 0xf4>;
2118                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2119                                 clock-names = "pipe0";
2120
2121                                 #phy-cells = <0>;
2122                                 #clock-cells = <0>;
2123                                 clock-output-names = "pcie_1_pipe_clk";
2124                         };
2125                 };
2126
2127                 ipa: ipa@1e40000 {
2128                         compatible = "qcom,sc7280-ipa";
2129
2130                         iommus = <&apps_smmu 0x480 0x0>,
2131                                  <&apps_smmu 0x482 0x0>;
2132                         reg = <0 0x1e40000 0 0x8000>,
2133                               <0 0x1e50000 0 0x4ad0>,
2134                               <0 0x1e04000 0 0x23000>;
2135                         reg-names = "ipa-reg",
2136                                     "ipa-shared",
2137                                     "gsi";
2138
2139                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2140                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2141                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2142                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2143                         interrupt-names = "ipa",
2144                                           "gsi",
2145                                           "ipa-clock-query",
2146                                           "ipa-setup-ready";
2147
2148                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2149                         clock-names = "core";
2150
2151                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2152                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2153                         interconnect-names = "memory",
2154                                              "config";
2155
2156                         qcom,qmp = <&aoss_qmp>;
2157
2158                         qcom,smem-states = <&ipa_smp2p_out 0>,
2159                                            <&ipa_smp2p_out 1>;
2160                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2161                                                 "ipa-clock-enabled";
2162
2163                         status = "disabled";
2164                 };
2165
2166                 tcsr_mutex: hwlock@1f40000 {
2167                         compatible = "qcom,tcsr-mutex";
2168                         reg = <0 0x01f40000 0 0x20000>;
2169                         #hwlock-cells = <1>;
2170                 };
2171
2172                 tcsr_1: syscon@1f60000 {
2173                         compatible = "qcom,sc7280-tcsr", "syscon";
2174                         reg = <0 0x01f60000 0 0x20000>;
2175                 };
2176
2177                 tcsr_2: syscon@1fc0000 {
2178                         compatible = "qcom,sc7280-tcsr", "syscon";
2179                         reg = <0 0x01fc0000 0 0x30000>;
2180                 };
2181
2182                 lpasscc: lpasscc@3000000 {
2183                         compatible = "qcom,sc7280-lpasscc";
2184                         reg = <0 0x03000000 0 0x40>,
2185                               <0 0x03c04000 0 0x4>;
2186                         reg-names = "qdsp6ss", "top_cc";
2187                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2188                         clock-names = "iface";
2189                         #clock-cells = <1>;
2190                 };
2191
2192                 lpass_rx_macro: codec@3200000 {
2193                         compatible = "qcom,sc7280-lpass-rx-macro";
2194                         reg = <0 0x03200000 0 0x1000>;
2195
2196                         pinctrl-names = "default";
2197                         pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2198
2199                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2200                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2201                                  <&lpass_va_macro>;
2202                         clock-names = "mclk", "npl", "fsgen";
2203
2204                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2205                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2206                         power-domain-names = "macro", "dcodec";
2207
2208                         #clock-cells = <0>;
2209                         #sound-dai-cells = <1>;
2210
2211                         status = "disabled";
2212                 };
2213
2214                 swr0: soundwire@3210000 {
2215                         compatible = "qcom,soundwire-v1.6.0";
2216                         reg = <0 0x03210000 0 0x2000>;
2217
2218                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2219                         clocks = <&lpass_rx_macro>;
2220                         clock-names = "iface";
2221
2222                         qcom,din-ports = <0>;
2223                         qcom,dout-ports = <5>;
2224
2225                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2226                         reset-names = "swr_audio_cgcr";
2227
2228                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2229                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2230                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2231                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2232                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2233                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2234                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2235                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2236                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2237
2238                         #sound-dai-cells = <1>;
2239                         #address-cells = <2>;
2240                         #size-cells = <0>;
2241
2242                         status = "disabled";
2243                 };
2244
2245                 lpass_tx_macro: codec@3220000 {
2246                         compatible = "qcom,sc7280-lpass-tx-macro";
2247                         reg = <0 0x03220000 0 0x1000>;
2248
2249                         pinctrl-names = "default";
2250                         pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2251
2252                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2253                                  <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2254                                  <&lpass_va_macro>;
2255                         clock-names = "mclk", "npl", "fsgen";
2256
2257                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2258                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2259                         power-domain-names = "macro", "dcodec";
2260
2261                         #clock-cells = <0>;
2262                         #sound-dai-cells = <1>;
2263
2264                         status = "disabled";
2265                 };
2266
2267                 swr1: soundwire@3230000 {
2268                         compatible = "qcom,soundwire-v1.6.0";
2269                         reg = <0 0x03230000 0 0x2000>;
2270
2271                         interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2272                                               <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2273                         clocks = <&lpass_tx_macro>;
2274                         clock-names = "iface";
2275
2276                         qcom,din-ports = <3>;
2277                         qcom,dout-ports = <0>;
2278
2279                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2280                         reset-names = "swr_audio_cgcr";
2281
2282                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x03 0x03>;
2283                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02>;
2284                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00>;
2285                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff>;
2286                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff>;
2287                         qcom,ports-word-length =        /bits/ 8 <0xff 0x00 0xff>;
2288                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff>;
2289                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff>;
2290                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00>;
2291                         qcom,port-offset = <1>;
2292
2293                         #sound-dai-cells = <1>;
2294                         #address-cells = <2>;
2295                         #size-cells = <0>;
2296
2297                         status = "disabled";
2298                 };
2299
2300                 lpass_audiocc: clock-controller@3300000 {
2301                         compatible = "qcom,sc7280-lpassaudiocc";
2302                         reg = <0 0x03300000 0 0x30000>,
2303                               <0 0x032a9000 0 0x1000>;
2304                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2305                                <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2306                         clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2307                         power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2308                         #clock-cells = <1>;
2309                         #power-domain-cells = <1>;
2310                         #reset-cells = <1>;
2311                 };
2312
2313                 lpass_va_macro: codec@3370000 {
2314                         compatible = "qcom,sc7280-lpass-va-macro";
2315                         reg = <0 0x03370000 0 0x1000>;
2316
2317                         pinctrl-names = "default";
2318                         pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2319
2320                         clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2321                         clock-names = "mclk";
2322
2323                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2324                                         <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2325                         power-domain-names = "macro", "dcodec";
2326
2327                         #clock-cells = <0>;
2328                         #sound-dai-cells = <1>;
2329
2330                         status = "disabled";
2331                 };
2332
2333                 lpass_aon: clock-controller@3380000 {
2334                         compatible = "qcom,sc7280-lpassaoncc";
2335                         reg = <0 0x03380000 0 0x30000>;
2336                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2337                                <&rpmhcc RPMH_CXO_CLK_A>,
2338                                <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2339                         clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2340                         #clock-cells = <1>;
2341                         #power-domain-cells = <1>;
2342                 };
2343
2344                 lpass_core: clock-controller@3900000 {
2345                         compatible = "qcom,sc7280-lpasscorecc";
2346                         reg = <0 0x03900000 0 0x50000>;
2347                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2348                         clock-names = "bi_tcxo";
2349                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2350                         #clock-cells = <1>;
2351                         #power-domain-cells = <1>;
2352                 };
2353
2354                 lpass_cpu: audio@3987000 {
2355                         compatible = "qcom,sc7280-lpass-cpu";
2356
2357                         reg = <0 0x03987000 0 0x68000>,
2358                               <0 0x03b00000 0 0x29000>,
2359                               <0 0x03260000 0 0xc000>,
2360                               <0 0x03280000 0 0x29000>,
2361                               <0 0x03340000 0 0x29000>,
2362                               <0 0x0336c000 0 0x3000>;
2363                         reg-names = "lpass-hdmiif",
2364                                     "lpass-lpaif",
2365                                     "lpass-rxtx-cdc-dma-lpm",
2366                                     "lpass-rxtx-lpaif",
2367                                     "lpass-va-lpaif",
2368                                     "lpass-va-cdc-dma-lpm";
2369
2370                         iommus = <&apps_smmu 0x1820 0>,
2371                                  <&apps_smmu 0x1821 0>,
2372                                  <&apps_smmu 0x1832 0>;
2373
2374                         power-domains = <&rpmhpd SC7280_LCX>;
2375                         power-domain-names = "lcx";
2376                         required-opps = <&rpmhpd_opp_nom>;
2377
2378                         clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2379                                  <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2380                                  <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2381                                  <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2382                                  <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2383                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2384                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2385                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2386                                  <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2387                                  <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2388                         clock-names = "aon_cc_audio_hm_h",
2389                                       "audio_cc_ext_mclk0",
2390                                       "core_cc_sysnoc_mport_core",
2391                                       "core_cc_ext_if0_ibit",
2392                                       "core_cc_ext_if1_ibit",
2393                                       "audio_cc_codec_mem",
2394                                       "audio_cc_codec_mem0",
2395                                       "audio_cc_codec_mem1",
2396                                       "audio_cc_codec_mem2",
2397                                       "aon_cc_va_mem0";
2398
2399                         #sound-dai-cells = <1>;
2400                         #address-cells = <1>;
2401                         #size-cells = <0>;
2402
2403                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2404                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2405                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2406                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2407                         interrupt-names = "lpass-irq-lpaif",
2408                                           "lpass-irq-hdmi",
2409                                           "lpass-irq-vaif",
2410                                           "lpass-irq-rxtxif";
2411
2412                         status = "disabled";
2413                 };
2414
2415                 lpass_hm: clock-controller@3c00000 {
2416                         compatible = "qcom,sc7280-lpasshm";
2417                         reg = <0 0x3c00000 0 0x28>;
2418                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2419                         clock-names = "bi_tcxo";
2420                         #clock-cells = <1>;
2421                         #power-domain-cells = <1>;
2422                 };
2423
2424                 lpass_ag_noc: interconnect@3c40000 {
2425                         reg = <0 0x03c40000 0 0xf080>;
2426                         compatible = "qcom,sc7280-lpass-ag-noc";
2427                         #interconnect-cells = <2>;
2428                         qcom,bcm-voters = <&apps_bcm_voter>;
2429                 };
2430
2431                 lpass_tlmm: pinctrl@33c0000 {
2432                         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2433                         reg = <0 0x033c0000 0x0 0x20000>,
2434                                 <0 0x03550000 0x0 0x10000>;
2435                         qcom,adsp-bypass-mode;
2436                         gpio-controller;
2437                         #gpio-cells = <2>;
2438                         gpio-ranges = <&lpass_tlmm 0 0 15>;
2439
2440                         #clock-cells = <1>;
2441
2442                         lpass_dmic01_clk: dmic01-clk {
2443                                 pins = "gpio6";
2444                                 function = "dmic1_clk";
2445                         };
2446
2447                         lpass_dmic01_clk_sleep: dmic01-clk-sleep {
2448                                 pins = "gpio6";
2449                                 function = "dmic1_clk";
2450                         };
2451
2452                         lpass_dmic01_data: dmic01-data {
2453                                 pins = "gpio7";
2454                                 function = "dmic1_data";
2455                         };
2456
2457                         lpass_dmic01_data_sleep: dmic01-data-sleep {
2458                                 pins = "gpio7";
2459                                 function = "dmic1_data";
2460                         };
2461
2462                         lpass_dmic23_clk: dmic23-clk {
2463                                 pins = "gpio8";
2464                                 function = "dmic2_clk";
2465                         };
2466
2467                         lpass_dmic23_clk_sleep: dmic23-clk-sleep {
2468                                 pins = "gpio8";
2469                                 function = "dmic2_clk";
2470                         };
2471
2472                         lpass_dmic23_data: dmic23-data {
2473                                 pins = "gpio9";
2474                                 function = "dmic2_data";
2475                         };
2476
2477                         lpass_dmic23_data_sleep: dmic23-data-sleep {
2478                                 pins = "gpio9";
2479                                 function = "dmic2_data";
2480                         };
2481
2482                         lpass_rx_swr_clk: rx-swr-clk {
2483                                 pins = "gpio3";
2484                                 function = "swr_rx_clk";
2485                         };
2486
2487                         lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
2488                                 pins = "gpio3";
2489                                 function = "swr_rx_clk";
2490                         };
2491
2492                         lpass_rx_swr_data: rx-swr-data {
2493                                 pins = "gpio4", "gpio5";
2494                                 function = "swr_rx_data";
2495                         };
2496
2497                         lpass_rx_swr_data_sleep: rx-swr-data-sleep {
2498                                 pins = "gpio4", "gpio5";
2499                                 function = "swr_rx_data";
2500                         };
2501
2502                         lpass_tx_swr_clk: tx-swr-clk {
2503                                 pins = "gpio0";
2504                                 function = "swr_tx_clk";
2505                         };
2506
2507                         lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
2508                                 pins = "gpio0";
2509                                 function = "swr_tx_clk";
2510                         };
2511
2512                         lpass_tx_swr_data: tx-swr-data {
2513                                 pins = "gpio1", "gpio2", "gpio14";
2514                                 function = "swr_tx_data";
2515                         };
2516
2517                         lpass_tx_swr_data_sleep: tx-swr-data-sleep {
2518                                 pins = "gpio1", "gpio2", "gpio14";
2519                                 function = "swr_tx_data";
2520                         };
2521                 };
2522
2523                 gpu: gpu@3d00000 {
2524                         compatible = "qcom,adreno-635.0", "qcom,adreno";
2525                         reg = <0 0x03d00000 0 0x40000>,
2526                               <0 0x03d9e000 0 0x1000>,
2527                               <0 0x03d61000 0 0x800>;
2528                         reg-names = "kgsl_3d0_reg_memory",
2529                                     "cx_mem",
2530                                     "cx_dbgc";
2531                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2532                         iommus = <&adreno_smmu 0 0x401>;
2533                         operating-points-v2 = <&gpu_opp_table>;
2534                         qcom,gmu = <&gmu>;
2535                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2536                         interconnect-names = "gfx-mem";
2537                         #cooling-cells = <2>;
2538
2539                         nvmem-cells = <&gpu_speed_bin>;
2540                         nvmem-cell-names = "speed_bin";
2541
2542                         gpu_opp_table: opp-table {
2543                                 compatible = "operating-points-v2";
2544
2545                                 opp-315000000 {
2546                                         opp-hz = /bits/ 64 <315000000>;
2547                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2548                                         opp-peak-kBps = <1804000>;
2549                                         opp-supported-hw = <0x03>;
2550                                 };
2551
2552                                 opp-450000000 {
2553                                         opp-hz = /bits/ 64 <450000000>;
2554                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2555                                         opp-peak-kBps = <4068000>;
2556                                         opp-supported-hw = <0x03>;
2557                                 };
2558
2559                                 /* Only applicable for SKUs which has 550Mhz as Fmax */
2560                                 opp-550000000-0 {
2561                                         opp-hz = /bits/ 64 <550000000>;
2562                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2563                                         opp-peak-kBps = <8368000>;
2564                                         opp-supported-hw = <0x01>;
2565                                 };
2566
2567                                 opp-550000000-1 {
2568                                         opp-hz = /bits/ 64 <550000000>;
2569                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2570                                         opp-peak-kBps = <6832000>;
2571                                         opp-supported-hw = <0x02>;
2572                                 };
2573
2574                                 opp-608000000 {
2575                                         opp-hz = /bits/ 64 <608000000>;
2576                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2577                                         opp-peak-kBps = <8368000>;
2578                                         opp-supported-hw = <0x02>;
2579                                 };
2580
2581                                 opp-700000000 {
2582                                         opp-hz = /bits/ 64 <700000000>;
2583                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2584                                         opp-peak-kBps = <8532000>;
2585                                         opp-supported-hw = <0x02>;
2586                                 };
2587
2588                                 opp-812000000 {
2589                                         opp-hz = /bits/ 64 <812000000>;
2590                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2591                                         opp-peak-kBps = <8532000>;
2592                                         opp-supported-hw = <0x02>;
2593                                 };
2594
2595                                 opp-840000000 {
2596                                         opp-hz = /bits/ 64 <840000000>;
2597                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2598                                         opp-peak-kBps = <8532000>;
2599                                         opp-supported-hw = <0x02>;
2600                                 };
2601
2602                                 opp-900000000 {
2603                                         opp-hz = /bits/ 64 <900000000>;
2604                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2605                                         opp-peak-kBps = <8532000>;
2606                                         opp-supported-hw = <0x02>;
2607                                 };
2608                         };
2609                 };
2610
2611                 gmu: gmu@3d6a000 {
2612                         compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2613                         reg = <0 0x03d6a000 0 0x34000>,
2614                                 <0 0x3de0000 0 0x10000>,
2615                                 <0 0x0b290000 0 0x10000>;
2616                         reg-names = "gmu", "rscc", "gmu_pdc";
2617                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2618                                         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2619                         interrupt-names = "hfi", "gmu";
2620                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2621                                  <&gpucc GPU_CC_CXO_CLK>,
2622                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2623                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2624                                  <&gpucc GPU_CC_AHB_CLK>,
2625                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2626                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2627                         clock-names = "gmu",
2628                                       "cxo",
2629                                       "axi",
2630                                       "memnoc",
2631                                       "ahb",
2632                                       "hub",
2633                                       "smmu_vote";
2634                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2635                                         <&gpucc GPU_CC_GX_GDSC>;
2636                         power-domain-names = "cx",
2637                                              "gx";
2638                         iommus = <&adreno_smmu 5 0x400>;
2639                         operating-points-v2 = <&gmu_opp_table>;
2640
2641                         gmu_opp_table: opp-table {
2642                                 compatible = "operating-points-v2";
2643
2644                                 opp-200000000 {
2645                                         opp-hz = /bits/ 64 <200000000>;
2646                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2647                                 };
2648                         };
2649                 };
2650
2651                 gpucc: clock-controller@3d90000 {
2652                         compatible = "qcom,sc7280-gpucc";
2653                         reg = <0 0x03d90000 0 0x9000>;
2654                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2655                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2656                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2657                         clock-names = "bi_tcxo",
2658                                       "gcc_gpu_gpll0_clk_src",
2659                                       "gcc_gpu_gpll0_div_clk_src";
2660                         #clock-cells = <1>;
2661                         #reset-cells = <1>;
2662                         #power-domain-cells = <1>;
2663                 };
2664
2665                 adreno_smmu: iommu@3da0000 {
2666                         compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2667                         reg = <0 0x03da0000 0 0x20000>;
2668                         #iommu-cells = <2>;
2669                         #global-interrupts = <2>;
2670                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2671                                         <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2672                                         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2673                                         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2674                                         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2675                                         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2676                                         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2677                                         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2678                                         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2679                                         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2680                                         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2681                                         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2682
2683                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2684                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2685                                  <&gpucc GPU_CC_AHB_CLK>,
2686                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2687                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2688                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2689                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2690                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2691                                         "gcc_gpu_snoc_dvm_gfx_clk",
2692                                         "gpu_cc_ahb_clk",
2693                                         "gpu_cc_hlos1_vote_gpu_smmu_clk",
2694                                         "gpu_cc_cx_gmu_clk",
2695                                         "gpu_cc_hub_cx_int_clk",
2696                                         "gpu_cc_hub_aon_clk";
2697
2698                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2699                 };
2700
2701                 remoteproc_mpss: remoteproc@4080000 {
2702                         compatible = "qcom,sc7280-mpss-pas";
2703                         reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2704                         reg-names = "qdsp6", "rmb";
2705
2706                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2707                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2708                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2709                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2710                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2711                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2712                         interrupt-names = "wdog", "fatal", "ready", "handover",
2713                                           "stop-ack", "shutdown-ack";
2714
2715                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2716                                  <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
2717                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2718                                  <&rpmhcc RPMH_PKA_CLK>,
2719                                  <&rpmhcc RPMH_CXO_CLK>;
2720                         clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
2721
2722                         power-domains = <&rpmhpd SC7280_CX>,
2723                                         <&rpmhpd SC7280_MSS>;
2724                         power-domain-names = "cx", "mss";
2725
2726                         memory-region = <&mpss_mem>;
2727
2728                         qcom,qmp = <&aoss_qmp>;
2729
2730                         qcom,smem-states = <&modem_smp2p_out 0>;
2731                         qcom,smem-state-names = "stop";
2732
2733                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2734                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2735                         reset-names = "mss_restart", "pdc_reset";
2736
2737                         qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
2738                         qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
2739                         qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
2740
2741                         status = "disabled";
2742
2743                         glink-edge {
2744                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2745                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2746                                                              IRQ_TYPE_EDGE_RISING>;
2747                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2748                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2749                                 label = "modem";
2750                                 qcom,remote-pid = <1>;
2751                         };
2752                 };
2753
2754                 stm@6002000 {
2755                         compatible = "arm,coresight-stm", "arm,primecell";
2756                         reg = <0 0x06002000 0 0x1000>,
2757                               <0 0x16280000 0 0x180000>;
2758                         reg-names = "stm-base", "stm-stimulus-base";
2759
2760                         clocks = <&aoss_qmp>;
2761                         clock-names = "apb_pclk";
2762
2763                         out-ports {
2764                                 port {
2765                                         stm_out: endpoint {
2766                                                 remote-endpoint = <&funnel0_in7>;
2767                                         };
2768                                 };
2769                         };
2770                 };
2771
2772                 funnel@6041000 {
2773                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2774                         reg = <0 0x06041000 0 0x1000>;
2775
2776                         clocks = <&aoss_qmp>;
2777                         clock-names = "apb_pclk";
2778
2779                         out-ports {
2780                                 port {
2781                                         funnel0_out: endpoint {
2782                                                 remote-endpoint = <&merge_funnel_in0>;
2783                                         };
2784                                 };
2785                         };
2786
2787                         in-ports {
2788                                 #address-cells = <1>;
2789                                 #size-cells = <0>;
2790
2791                                 port@7 {
2792                                         reg = <7>;
2793                                         funnel0_in7: endpoint {
2794                                                 remote-endpoint = <&stm_out>;
2795                                         };
2796                                 };
2797                         };
2798                 };
2799
2800                 funnel@6042000 {
2801                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2802                         reg = <0 0x06042000 0 0x1000>;
2803
2804                         clocks = <&aoss_qmp>;
2805                         clock-names = "apb_pclk";
2806
2807                         out-ports {
2808                                 port {
2809                                         funnel1_out: endpoint {
2810                                                 remote-endpoint = <&merge_funnel_in1>;
2811                                         };
2812                                 };
2813                         };
2814
2815                         in-ports {
2816                                 #address-cells = <1>;
2817                                 #size-cells = <0>;
2818
2819                                 port@4 {
2820                                         reg = <4>;
2821                                         funnel1_in4: endpoint {
2822                                                 remote-endpoint = <&apss_merge_funnel_out>;
2823                                         };
2824                                 };
2825                         };
2826                 };
2827
2828                 funnel@6045000 {
2829                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2830                         reg = <0 0x06045000 0 0x1000>;
2831
2832                         clocks = <&aoss_qmp>;
2833                         clock-names = "apb_pclk";
2834
2835                         out-ports {
2836                                 port {
2837                                         merge_funnel_out: endpoint {
2838                                                 remote-endpoint = <&swao_funnel_in>;
2839                                         };
2840                                 };
2841                         };
2842
2843                         in-ports {
2844                                 #address-cells = <1>;
2845                                 #size-cells = <0>;
2846
2847                                 port@0 {
2848                                         reg = <0>;
2849                                         merge_funnel_in0: endpoint {
2850                                                 remote-endpoint = <&funnel0_out>;
2851                                         };
2852                                 };
2853
2854                                 port@1 {
2855                                         reg = <1>;
2856                                         merge_funnel_in1: endpoint {
2857                                                 remote-endpoint = <&funnel1_out>;
2858                                         };
2859                                 };
2860                         };
2861                 };
2862
2863                 replicator@6046000 {
2864                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2865                         reg = <0 0x06046000 0 0x1000>;
2866
2867                         clocks = <&aoss_qmp>;
2868                         clock-names = "apb_pclk";
2869
2870                         out-ports {
2871                                 port {
2872                                         replicator_out: endpoint {
2873                                                 remote-endpoint = <&etr_in>;
2874                                         };
2875                                 };
2876                         };
2877
2878                         in-ports {
2879                                 port {
2880                                         replicator_in: endpoint {
2881                                                 remote-endpoint = <&swao_replicator_out>;
2882                                         };
2883                                 };
2884                         };
2885                 };
2886
2887                 etr@6048000 {
2888                         compatible = "arm,coresight-tmc", "arm,primecell";
2889                         reg = <0 0x06048000 0 0x1000>;
2890                         iommus = <&apps_smmu 0x04c0 0>;
2891
2892                         clocks = <&aoss_qmp>;
2893                         clock-names = "apb_pclk";
2894                         arm,scatter-gather;
2895
2896                         in-ports {
2897                                 port {
2898                                         etr_in: endpoint {
2899                                                 remote-endpoint = <&replicator_out>;
2900                                         };
2901                                 };
2902                         };
2903                 };
2904
2905                 funnel@6b04000 {
2906                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2907                         reg = <0 0x06b04000 0 0x1000>;
2908
2909                         clocks = <&aoss_qmp>;
2910                         clock-names = "apb_pclk";
2911
2912                         out-ports {
2913                                 port {
2914                                         swao_funnel_out: endpoint {
2915                                                 remote-endpoint = <&etf_in>;
2916                                         };
2917                                 };
2918                         };
2919
2920                         in-ports {
2921                                 #address-cells = <1>;
2922                                 #size-cells = <0>;
2923
2924                                 port@7 {
2925                                         reg = <7>;
2926                                         swao_funnel_in: endpoint {
2927                                                 remote-endpoint = <&merge_funnel_out>;
2928                                         };
2929                                 };
2930                         };
2931                 };
2932
2933                 etf@6b05000 {
2934                         compatible = "arm,coresight-tmc", "arm,primecell";
2935                         reg = <0 0x06b05000 0 0x1000>;
2936
2937                         clocks = <&aoss_qmp>;
2938                         clock-names = "apb_pclk";
2939
2940                         out-ports {
2941                                 port {
2942                                         etf_out: endpoint {
2943                                                 remote-endpoint = <&swao_replicator_in>;
2944                                         };
2945                                 };
2946                         };
2947
2948                         in-ports {
2949                                 port {
2950                                         etf_in: endpoint {
2951                                                 remote-endpoint = <&swao_funnel_out>;
2952                                         };
2953                                 };
2954                         };
2955                 };
2956
2957                 replicator@6b06000 {
2958                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2959                         reg = <0 0x06b06000 0 0x1000>;
2960
2961                         clocks = <&aoss_qmp>;
2962                         clock-names = "apb_pclk";
2963                         qcom,replicator-loses-context;
2964
2965                         out-ports {
2966                                 port {
2967                                         swao_replicator_out: endpoint {
2968                                                 remote-endpoint = <&replicator_in>;
2969                                         };
2970                                 };
2971                         };
2972
2973                         in-ports {
2974                                 port {
2975                                         swao_replicator_in: endpoint {
2976                                                 remote-endpoint = <&etf_out>;
2977                                         };
2978                                 };
2979                         };
2980                 };
2981
2982                 etm@7040000 {
2983                         compatible = "arm,coresight-etm4x", "arm,primecell";
2984                         reg = <0 0x07040000 0 0x1000>;
2985
2986                         cpu = <&CPU0>;
2987
2988                         clocks = <&aoss_qmp>;
2989                         clock-names = "apb_pclk";
2990                         arm,coresight-loses-context-with-cpu;
2991                         qcom,skip-power-up;
2992
2993                         out-ports {
2994                                 port {
2995                                         etm0_out: endpoint {
2996                                                 remote-endpoint = <&apss_funnel_in0>;
2997                                         };
2998                                 };
2999                         };
3000                 };
3001
3002                 etm@7140000 {
3003                         compatible = "arm,coresight-etm4x", "arm,primecell";
3004                         reg = <0 0x07140000 0 0x1000>;
3005
3006                         cpu = <&CPU1>;
3007
3008                         clocks = <&aoss_qmp>;
3009                         clock-names = "apb_pclk";
3010                         arm,coresight-loses-context-with-cpu;
3011                         qcom,skip-power-up;
3012
3013                         out-ports {
3014                                 port {
3015                                         etm1_out: endpoint {
3016                                                 remote-endpoint = <&apss_funnel_in1>;
3017                                         };
3018                                 };
3019                         };
3020                 };
3021
3022                 etm@7240000 {
3023                         compatible = "arm,coresight-etm4x", "arm,primecell";
3024                         reg = <0 0x07240000 0 0x1000>;
3025
3026                         cpu = <&CPU2>;
3027
3028                         clocks = <&aoss_qmp>;
3029                         clock-names = "apb_pclk";
3030                         arm,coresight-loses-context-with-cpu;
3031                         qcom,skip-power-up;
3032
3033                         out-ports {
3034                                 port {
3035                                         etm2_out: endpoint {
3036                                                 remote-endpoint = <&apss_funnel_in2>;
3037                                         };
3038                                 };
3039                         };
3040                 };
3041
3042                 etm@7340000 {
3043                         compatible = "arm,coresight-etm4x", "arm,primecell";
3044                         reg = <0 0x07340000 0 0x1000>;
3045
3046                         cpu = <&CPU3>;
3047
3048                         clocks = <&aoss_qmp>;
3049                         clock-names = "apb_pclk";
3050                         arm,coresight-loses-context-with-cpu;
3051                         qcom,skip-power-up;
3052
3053                         out-ports {
3054                                 port {
3055                                         etm3_out: endpoint {
3056                                                 remote-endpoint = <&apss_funnel_in3>;
3057                                         };
3058                                 };
3059                         };
3060                 };
3061
3062                 etm@7440000 {
3063                         compatible = "arm,coresight-etm4x", "arm,primecell";
3064                         reg = <0 0x07440000 0 0x1000>;
3065
3066                         cpu = <&CPU4>;
3067
3068                         clocks = <&aoss_qmp>;
3069                         clock-names = "apb_pclk";
3070                         arm,coresight-loses-context-with-cpu;
3071                         qcom,skip-power-up;
3072
3073                         out-ports {
3074                                 port {
3075                                         etm4_out: endpoint {
3076                                                 remote-endpoint = <&apss_funnel_in4>;
3077                                         };
3078                                 };
3079                         };
3080                 };
3081
3082                 etm@7540000 {
3083                         compatible = "arm,coresight-etm4x", "arm,primecell";
3084                         reg = <0 0x07540000 0 0x1000>;
3085
3086                         cpu = <&CPU5>;
3087
3088                         clocks = <&aoss_qmp>;
3089                         clock-names = "apb_pclk";
3090                         arm,coresight-loses-context-with-cpu;
3091                         qcom,skip-power-up;
3092
3093                         out-ports {
3094                                 port {
3095                                         etm5_out: endpoint {
3096                                                 remote-endpoint = <&apss_funnel_in5>;
3097                                         };
3098                                 };
3099                         };
3100                 };
3101
3102                 etm@7640000 {
3103                         compatible = "arm,coresight-etm4x", "arm,primecell";
3104                         reg = <0 0x07640000 0 0x1000>;
3105
3106                         cpu = <&CPU6>;
3107
3108                         clocks = <&aoss_qmp>;
3109                         clock-names = "apb_pclk";
3110                         arm,coresight-loses-context-with-cpu;
3111                         qcom,skip-power-up;
3112
3113                         out-ports {
3114                                 port {
3115                                         etm6_out: endpoint {
3116                                                 remote-endpoint = <&apss_funnel_in6>;
3117                                         };
3118                                 };
3119                         };
3120                 };
3121
3122                 etm@7740000 {
3123                         compatible = "arm,coresight-etm4x", "arm,primecell";
3124                         reg = <0 0x07740000 0 0x1000>;
3125
3126                         cpu = <&CPU7>;
3127
3128                         clocks = <&aoss_qmp>;
3129                         clock-names = "apb_pclk";
3130                         arm,coresight-loses-context-with-cpu;
3131                         qcom,skip-power-up;
3132
3133                         out-ports {
3134                                 port {
3135                                         etm7_out: endpoint {
3136                                                 remote-endpoint = <&apss_funnel_in7>;
3137                                         };
3138                                 };
3139                         };
3140                 };
3141
3142                 funnel@7800000 { /* APSS Funnel */
3143                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3144                         reg = <0 0x07800000 0 0x1000>;
3145
3146                         clocks = <&aoss_qmp>;
3147                         clock-names = "apb_pclk";
3148
3149                         out-ports {
3150                                 port {
3151                                         apss_funnel_out: endpoint {
3152                                                 remote-endpoint = <&apss_merge_funnel_in>;
3153                                         };
3154                                 };
3155                         };
3156
3157                         in-ports {
3158                                 #address-cells = <1>;
3159                                 #size-cells = <0>;
3160
3161                                 port@0 {
3162                                         reg = <0>;
3163                                         apss_funnel_in0: endpoint {
3164                                                 remote-endpoint = <&etm0_out>;
3165                                         };
3166                                 };
3167
3168                                 port@1 {
3169                                         reg = <1>;
3170                                         apss_funnel_in1: endpoint {
3171                                                 remote-endpoint = <&etm1_out>;
3172                                         };
3173                                 };
3174
3175                                 port@2 {
3176                                         reg = <2>;
3177                                         apss_funnel_in2: endpoint {
3178                                                 remote-endpoint = <&etm2_out>;
3179                                         };
3180                                 };
3181
3182                                 port@3 {
3183                                         reg = <3>;
3184                                         apss_funnel_in3: endpoint {
3185                                                 remote-endpoint = <&etm3_out>;
3186                                         };
3187                                 };
3188
3189                                 port@4 {
3190                                         reg = <4>;
3191                                         apss_funnel_in4: endpoint {
3192                                                 remote-endpoint = <&etm4_out>;
3193                                         };
3194                                 };
3195
3196                                 port@5 {
3197                                         reg = <5>;
3198                                         apss_funnel_in5: endpoint {
3199                                                 remote-endpoint = <&etm5_out>;
3200                                         };
3201                                 };
3202
3203                                 port@6 {
3204                                         reg = <6>;
3205                                         apss_funnel_in6: endpoint {
3206                                                 remote-endpoint = <&etm6_out>;
3207                                         };
3208                                 };
3209
3210                                 port@7 {
3211                                         reg = <7>;
3212                                         apss_funnel_in7: endpoint {
3213                                                 remote-endpoint = <&etm7_out>;
3214                                         };
3215                                 };
3216                         };
3217                 };
3218
3219                 funnel@7810000 {
3220                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3221                         reg = <0 0x07810000 0 0x1000>;
3222
3223                         clocks = <&aoss_qmp>;
3224                         clock-names = "apb_pclk";
3225
3226                         out-ports {
3227                                 port {
3228                                         apss_merge_funnel_out: endpoint {
3229                                                 remote-endpoint = <&funnel1_in4>;
3230                                         };
3231                                 };
3232                         };
3233
3234                         in-ports {
3235                                 port {
3236                                         apss_merge_funnel_in: endpoint {
3237                                                 remote-endpoint = <&apss_funnel_out>;
3238                                         };
3239                                 };
3240                         };
3241                 };
3242
3243                 sdhc_2: mmc@8804000 {
3244                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3245                         pinctrl-names = "default", "sleep";
3246                         pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3247                         pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3248                         status = "disabled";
3249
3250                         reg = <0 0x08804000 0 0x1000>;
3251
3252                         iommus = <&apps_smmu 0x100 0x0>;
3253                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3254                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3255                         interrupt-names = "hc_irq", "pwr_irq";
3256
3257                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3258                                  <&gcc GCC_SDCC2_APPS_CLK>,
3259                                  <&rpmhcc RPMH_CXO_CLK>;
3260                         clock-names = "iface", "core", "xo";
3261                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3262                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3263                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3264                         power-domains = <&rpmhpd SC7280_CX>;
3265                         operating-points-v2 = <&sdhc2_opp_table>;
3266
3267                         bus-width = <4>;
3268
3269                         qcom,dll-config = <0x0007642c>;
3270
3271                         resets = <&gcc GCC_SDCC2_BCR>;
3272
3273                         sdhc2_opp_table: opp-table {
3274                                 compatible = "operating-points-v2";
3275
3276                                 opp-100000000 {
3277                                         opp-hz = /bits/ 64 <100000000>;
3278                                         required-opps = <&rpmhpd_opp_low_svs>;
3279                                         opp-peak-kBps = <1800000 400000>;
3280                                         opp-avg-kBps = <100000 0>;
3281                                 };
3282
3283                                 opp-202000000 {
3284                                         opp-hz = /bits/ 64 <202000000>;
3285                                         required-opps = <&rpmhpd_opp_nom>;
3286                                         opp-peak-kBps = <5400000 1600000>;
3287                                         opp-avg-kBps = <200000 0>;
3288                                 };
3289                         };
3290
3291                 };
3292
3293                 usb_1_hsphy: phy@88e3000 {
3294                         compatible = "qcom,sc7280-usb-hs-phy",
3295                                      "qcom,usb-snps-hs-7nm-phy";
3296                         reg = <0 0x088e3000 0 0x400>;
3297                         status = "disabled";
3298                         #phy-cells = <0>;
3299
3300                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3301                         clock-names = "ref";
3302
3303                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3304                 };
3305
3306                 usb_2_hsphy: phy@88e4000 {
3307                         compatible = "qcom,sc7280-usb-hs-phy",
3308                                      "qcom,usb-snps-hs-7nm-phy";
3309                         reg = <0 0x088e4000 0 0x400>;
3310                         status = "disabled";
3311                         #phy-cells = <0>;
3312
3313                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3314                         clock-names = "ref";
3315
3316                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3317                 };
3318
3319                 usb_1_qmpphy: phy-wrapper@88e9000 {
3320                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3321                                      "qcom,sm8250-qmp-usb3-dp-phy";
3322                         reg = <0 0x088e9000 0 0x200>,
3323                               <0 0x088e8000 0 0x40>,
3324                               <0 0x088ea000 0 0x200>;
3325                         status = "disabled";
3326                         #address-cells = <2>;
3327                         #size-cells = <2>;
3328                         ranges;
3329
3330                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3331                                  <&rpmhcc RPMH_CXO_CLK>,
3332                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3333                         clock-names = "aux", "ref_clk_src", "com_aux";
3334
3335                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3336                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3337                         reset-names = "phy", "common";
3338
3339                         usb_1_ssphy: usb3-phy@88e9200 {
3340                                 reg = <0 0x088e9200 0 0x200>,
3341                                       <0 0x088e9400 0 0x200>,
3342                                       <0 0x088e9c00 0 0x400>,
3343                                       <0 0x088e9600 0 0x200>,
3344                                       <0 0x088e9800 0 0x200>,
3345                                       <0 0x088e9a00 0 0x100>;
3346                                 #clock-cells = <0>;
3347                                 #phy-cells = <0>;
3348                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3349                                 clock-names = "pipe0";
3350                                 clock-output-names = "usb3_phy_pipe_clk_src";
3351                         };
3352
3353                         dp_phy: dp-phy@88ea200 {
3354                                 reg = <0 0x088ea200 0 0x200>,
3355                                       <0 0x088ea400 0 0x200>,
3356                                       <0 0x088eaa00 0 0x200>,
3357                                       <0 0x088ea600 0 0x200>,
3358                                       <0 0x088ea800 0 0x200>;
3359                                 #phy-cells = <0>;
3360                                 #clock-cells = <1>;
3361                         };
3362                 };
3363
3364                 usb_2: usb@8cf8800 {
3365                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3366                         reg = <0 0x08cf8800 0 0x400>;
3367                         status = "disabled";
3368                         #address-cells = <2>;
3369                         #size-cells = <2>;
3370                         ranges;
3371                         dma-ranges;
3372
3373                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3374                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3375                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3376                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3377                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3378                         clock-names = "cfg_noc",
3379                                       "core",
3380                                       "iface",
3381                                       "sleep",
3382                                       "mock_utmi";
3383
3384                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3385                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3386                         assigned-clock-rates = <19200000>, <200000000>;
3387
3388                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3389                                               <&pdc 12 IRQ_TYPE_EDGE_RISING>,
3390                                               <&pdc 13 IRQ_TYPE_EDGE_RISING>;
3391                         interrupt-names = "hs_phy_irq",
3392                                           "dp_hs_phy_irq",
3393                                           "dm_hs_phy_irq";
3394
3395                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3396                         required-opps = <&rpmhpd_opp_nom>;
3397
3398                         resets = <&gcc GCC_USB30_SEC_BCR>;
3399
3400                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3401                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3402                         interconnect-names = "usb-ddr", "apps-usb";
3403
3404                         usb_2_dwc3: usb@8c00000 {
3405                                 compatible = "snps,dwc3";
3406                                 reg = <0 0x08c00000 0 0xe000>;
3407                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3408                                 iommus = <&apps_smmu 0xa0 0x0>;
3409                                 snps,dis_u2_susphy_quirk;
3410                                 snps,dis_enblslpm_quirk;
3411                                 phys = <&usb_2_hsphy>;
3412                                 phy-names = "usb2-phy";
3413                                 maximum-speed = "high-speed";
3414                                 usb-role-switch;
3415                                 port {
3416                                         usb2_role_switch: endpoint {
3417                                                 remote-endpoint = <&eud_ep>;
3418                                         };
3419                                 };
3420                         };
3421                 };
3422
3423                 qspi: spi@88dc000 {
3424                         compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3425                         reg = <0 0x088dc000 0 0x1000>;
3426                         #address-cells = <1>;
3427                         #size-cells = <0>;
3428                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3429                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3430                                  <&gcc GCC_QSPI_CORE_CLK>;
3431                         clock-names = "iface", "core";
3432                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
3433                                         &cnoc2 SLAVE_QSPI_0 0>;
3434                         interconnect-names = "qspi-config";
3435                         power-domains = <&rpmhpd SC7280_CX>;
3436                         operating-points-v2 = <&qspi_opp_table>;
3437                         status = "disabled";
3438                 };
3439
3440                 remoteproc_wpss: remoteproc@8a00000 {
3441                         compatible = "qcom,sc7280-wpss-pil";
3442                         reg = <0 0x08a00000 0 0x10000>;
3443
3444                         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3445                                               <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3446                                               <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3447                                               <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3448                                               <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3449                                               <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3450                         interrupt-names = "wdog", "fatal", "ready", "handover",
3451                                           "stop-ack", "shutdown-ack";
3452
3453                         clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3454                                  <&gcc GCC_WPSS_AHB_CLK>,
3455                                  <&gcc GCC_WPSS_RSCP_CLK>,
3456                                  <&rpmhcc RPMH_CXO_CLK>;
3457                         clock-names = "ahb_bdg", "ahb",
3458                                       "rscp", "xo";
3459
3460                         power-domains = <&rpmhpd SC7280_CX>,
3461                                         <&rpmhpd SC7280_MX>;
3462                         power-domain-names = "cx", "mx";
3463
3464                         memory-region = <&wpss_mem>;
3465
3466                         qcom,qmp = <&aoss_qmp>;
3467
3468                         qcom,smem-states = <&wpss_smp2p_out 0>;
3469                         qcom,smem-state-names = "stop";
3470
3471                         resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3472                                  <&pdc_reset PDC_WPSS_SYNC_RESET>;
3473                         reset-names = "restart", "pdc_sync";
3474
3475                         qcom,halt-regs = <&tcsr_1 0x17000>;
3476
3477                         status = "disabled";
3478
3479                         glink-edge {
3480                                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3481                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3482                                                              IRQ_TYPE_EDGE_RISING>;
3483                                 mboxes = <&ipcc IPCC_CLIENT_WPSS
3484                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3485
3486                                 label = "wpss";
3487                                 qcom,remote-pid = <13>;
3488                         };
3489                 };
3490
3491                 pmu@9091000 {
3492                         compatible = "qcom,sc7280-llcc-bwmon";
3493                         reg = <0 0x9091000 0 0x1000>;
3494
3495                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3496
3497                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3498
3499                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3500
3501                         llcc_bwmon_opp_table: opp-table {
3502                                 compatible = "operating-points-v2";
3503
3504                                 opp-0 {
3505                                         opp-peak-kBps = <800000>;
3506                                 };
3507                                 opp-1 {
3508                                         opp-peak-kBps = <1804000>;
3509                                 };
3510                                 opp-2 {
3511                                         opp-peak-kBps = <2188000>;
3512                                 };
3513                                 opp-3 {
3514                                         opp-peak-kBps = <3072000>;
3515                                 };
3516                                 opp-4 {
3517                                         opp-peak-kBps = <4068000>;
3518                                 };
3519                                 opp-5 {
3520                                         opp-peak-kBps = <6220000>;
3521                                 };
3522                                 opp-6 {
3523                                         opp-peak-kBps = <6832000>;
3524                                 };
3525                                 opp-7 {
3526                                         opp-peak-kBps = <8532000>;
3527                                 };
3528                         };
3529                 };
3530
3531                 pmu@90b6400 {
3532                         compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3533                         reg = <0 0x090b6400 0 0x600>;
3534
3535                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3536
3537                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3538                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3539
3540                         cpu_bwmon_opp_table: opp-table {
3541                                 compatible = "operating-points-v2";
3542
3543                                 opp-0 {
3544                                         opp-peak-kBps = <2400000>;
3545                                 };
3546                                 opp-1 {
3547                                         opp-peak-kBps = <4800000>;
3548                                 };
3549                                 opp-2 {
3550                                         opp-peak-kBps = <7456000>;
3551                                 };
3552                                 opp-3 {
3553                                         opp-peak-kBps = <9600000>;
3554                                 };
3555                                 opp-4 {
3556                                         opp-peak-kBps = <12896000>;
3557                                 };
3558                                 opp-5 {
3559                                         opp-peak-kBps = <14928000>;
3560                                 };
3561                                 opp-6 {
3562                                         opp-peak-kBps = <17056000>;
3563                                 };
3564                         };
3565                 };
3566
3567                 dc_noc: interconnect@90e0000 {
3568                         reg = <0 0x090e0000 0 0x5080>;
3569                         compatible = "qcom,sc7280-dc-noc";
3570                         #interconnect-cells = <2>;
3571                         qcom,bcm-voters = <&apps_bcm_voter>;
3572                 };
3573
3574                 gem_noc: interconnect@9100000 {
3575                         reg = <0 0x9100000 0 0xe2200>;
3576                         compatible = "qcom,sc7280-gem-noc";
3577                         #interconnect-cells = <2>;
3578                         qcom,bcm-voters = <&apps_bcm_voter>;
3579                 };
3580
3581                 system-cache-controller@9200000 {
3582                         compatible = "qcom,sc7280-llcc";
3583                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3584                         reg-names = "llcc_base", "llcc_broadcast_base";
3585                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3586                 };
3587
3588                 eud: eud@88e0000 {
3589                         compatible = "qcom,sc7280-eud","qcom,eud";
3590                         reg = <0 0x88e0000 0 0x2000>,
3591                               <0 0x88e2000 0 0x1000>;
3592                         interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3593                         ports {
3594                                 #address-cells = <1>;
3595                                 #size-cells = <0>;
3596
3597                                 port@0 {
3598                                         reg = <0>;
3599                                         eud_ep: endpoint {
3600                                                 remote-endpoint = <&usb2_role_switch>;
3601                                         };
3602                                 };
3603                                 port@1 {
3604                                         reg = <1>;
3605                                         eud_con: endpoint {
3606                                                 remote-endpoint = <&con_eud>;
3607                                         };
3608                                 };
3609                         };
3610                 };
3611
3612                 eud_typec: connector {
3613                         compatible = "usb-c-connector";
3614                         ports {
3615                                 #address-cells = <1>;
3616                                 #size-cells = <0>;
3617
3618                                 port@0 {
3619                                         reg = <0>;
3620                                         con_eud: endpoint {
3621                                                 remote-endpoint = <&eud_con>;
3622                                         };
3623                                 };
3624                         };
3625                 };
3626
3627                 nsp_noc: interconnect@a0c0000 {
3628                         reg = <0 0x0a0c0000 0 0x10000>;
3629                         compatible = "qcom,sc7280-nsp-noc";
3630                         #interconnect-cells = <2>;
3631                         qcom,bcm-voters = <&apps_bcm_voter>;
3632                 };
3633
3634                 usb_1: usb@a6f8800 {
3635                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3636                         reg = <0 0x0a6f8800 0 0x400>;
3637                         status = "disabled";
3638                         #address-cells = <2>;
3639                         #size-cells = <2>;
3640                         ranges;
3641                         dma-ranges;
3642
3643                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3644                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3645                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3646                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3647                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3648                         clock-names = "cfg_noc",
3649                                       "core",
3650                                       "iface",
3651                                       "sleep",
3652                                       "mock_utmi";
3653
3654                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3655                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3656                         assigned-clock-rates = <19200000>, <200000000>;
3657
3658                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3659                                               <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
3660                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3661                                               <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
3662                         interrupt-names = "hs_phy_irq",
3663                                           "dp_hs_phy_irq",
3664                                           "dm_hs_phy_irq",
3665                                           "ss_phy_irq";
3666
3667                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3668                         required-opps = <&rpmhpd_opp_nom>;
3669
3670                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3671
3672                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3673                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3674                         interconnect-names = "usb-ddr", "apps-usb";
3675
3676                         wakeup-source;
3677
3678                         usb_1_dwc3: usb@a600000 {
3679                                 compatible = "snps,dwc3";
3680                                 reg = <0 0x0a600000 0 0xe000>;
3681                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3682                                 iommus = <&apps_smmu 0xe0 0x0>;
3683                                 snps,dis_u2_susphy_quirk;
3684                                 snps,dis_enblslpm_quirk;
3685                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3686                                 phy-names = "usb2-phy", "usb3-phy";
3687                                 maximum-speed = "super-speed";
3688                         };
3689                 };
3690
3691                 venus: video-codec@aa00000 {
3692                         compatible = "qcom,sc7280-venus";
3693                         reg = <0 0x0aa00000 0 0xd0600>;
3694                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3695
3696                         clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3697                                  <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3698                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3699                                  <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3700                                  <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3701                         clock-names = "core", "bus", "iface",
3702                                       "vcodec_core", "vcodec_bus";
3703
3704                         power-domains = <&videocc MVSC_GDSC>,
3705                                         <&videocc MVS0_GDSC>,
3706                                         <&rpmhpd SC7280_CX>;
3707                         power-domain-names = "venus", "vcodec0", "cx";
3708                         operating-points-v2 = <&venus_opp_table>;
3709
3710                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3711                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3712                         interconnect-names = "cpu-cfg", "video-mem";
3713
3714                         iommus = <&apps_smmu 0x2180 0x20>,
3715                                  <&apps_smmu 0x2184 0x20>;
3716                         memory-region = <&video_mem>;
3717
3718                         video-decoder {
3719                                 compatible = "venus-decoder";
3720                         };
3721
3722                         video-encoder {
3723                                 compatible = "venus-encoder";
3724                         };
3725
3726                         video-firmware {
3727                                 iommus = <&apps_smmu 0x21a2 0x0>;
3728                         };
3729
3730                         venus_opp_table: opp-table {
3731                                 compatible = "operating-points-v2";
3732
3733                                 opp-133330000 {
3734                                         opp-hz = /bits/ 64 <133330000>;
3735                                         required-opps = <&rpmhpd_opp_low_svs>;
3736                                 };
3737
3738                                 opp-240000000 {
3739                                         opp-hz = /bits/ 64 <240000000>;
3740                                         required-opps = <&rpmhpd_opp_svs>;
3741                                 };
3742
3743                                 opp-335000000 {
3744                                         opp-hz = /bits/ 64 <335000000>;
3745                                         required-opps = <&rpmhpd_opp_svs_l1>;
3746                                 };
3747
3748                                 opp-424000000 {
3749                                         opp-hz = /bits/ 64 <424000000>;
3750                                         required-opps = <&rpmhpd_opp_nom>;
3751                                 };
3752
3753                                 opp-460000048 {
3754                                         opp-hz = /bits/ 64 <460000048>;
3755                                         required-opps = <&rpmhpd_opp_turbo>;
3756                                 };
3757                         };
3758
3759                 };
3760
3761                 videocc: clock-controller@aaf0000 {
3762                         compatible = "qcom,sc7280-videocc";
3763                         reg = <0 0xaaf0000 0 0x10000>;
3764                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3765                                 <&rpmhcc RPMH_CXO_CLK_A>;
3766                         clock-names = "bi_tcxo", "bi_tcxo_ao";
3767                         #clock-cells = <1>;
3768                         #reset-cells = <1>;
3769                         #power-domain-cells = <1>;
3770                 };
3771
3772                 camcc: clock-controller@ad00000 {
3773                         compatible = "qcom,sc7280-camcc";
3774                         reg = <0 0x0ad00000 0 0x10000>;
3775                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3776                                 <&rpmhcc RPMH_CXO_CLK_A>,
3777                                 <&sleep_clk>;
3778                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3779                         #clock-cells = <1>;
3780                         #reset-cells = <1>;
3781                         #power-domain-cells = <1>;
3782                 };
3783
3784                 dispcc: clock-controller@af00000 {
3785                         compatible = "qcom,sc7280-dispcc";
3786                         reg = <0 0xaf00000 0 0x20000>;
3787                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3788                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3789                                  <&mdss_dsi_phy 0>,
3790                                  <&mdss_dsi_phy 1>,
3791                                  <&dp_phy 0>,
3792                                  <&dp_phy 1>,
3793                                  <&mdss_edp_phy 0>,
3794                                  <&mdss_edp_phy 1>;
3795                         clock-names = "bi_tcxo",
3796                                       "gcc_disp_gpll0_clk",
3797                                       "dsi0_phy_pll_out_byteclk",
3798                                       "dsi0_phy_pll_out_dsiclk",
3799                                       "dp_phy_pll_link_clk",
3800                                       "dp_phy_pll_vco_div_clk",
3801                                       "edp_phy_pll_link_clk",
3802                                       "edp_phy_pll_vco_div_clk";
3803                         #clock-cells = <1>;
3804                         #reset-cells = <1>;
3805                         #power-domain-cells = <1>;
3806                 };
3807
3808                 mdss: display-subsystem@ae00000 {
3809                         compatible = "qcom,sc7280-mdss";
3810                         reg = <0 0x0ae00000 0 0x1000>;
3811                         reg-names = "mdss";
3812
3813                         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3814
3815                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3816                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3817                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3818                         clock-names = "iface",
3819                                       "ahb",
3820                                       "core";
3821
3822                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3823                         interrupt-controller;
3824                         #interrupt-cells = <1>;
3825
3826                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3827                         interconnect-names = "mdp0-mem";
3828
3829                         iommus = <&apps_smmu 0x900 0x402>;
3830
3831                         #address-cells = <2>;
3832                         #size-cells = <2>;
3833                         ranges;
3834
3835                         status = "disabled";
3836
3837                         mdss_mdp: display-controller@ae01000 {
3838                                 compatible = "qcom,sc7280-dpu";
3839                                 reg = <0 0x0ae01000 0 0x8f030>,
3840                                         <0 0x0aeb0000 0 0x2008>;
3841                                 reg-names = "mdp", "vbif";
3842
3843                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3844                                         <&gcc GCC_DISP_SF_AXI_CLK>,
3845                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
3846                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3847                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
3848                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3849                                 clock-names = "bus",
3850                                               "nrt_bus",
3851                                               "iface",
3852                                               "lut",
3853                                               "core",
3854                                               "vsync";
3855                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3856                                                 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3857                                 assigned-clock-rates = <19200000>,
3858                                                         <19200000>;
3859                                 operating-points-v2 = <&mdp_opp_table>;
3860                                 power-domains = <&rpmhpd SC7280_CX>;
3861
3862                                 interrupt-parent = <&mdss>;
3863                                 interrupts = <0>;
3864
3865                                 status = "disabled";
3866
3867                                 ports {
3868                                         #address-cells = <1>;
3869                                         #size-cells = <0>;
3870
3871                                         port@0 {
3872                                                 reg = <0>;
3873                                                 dpu_intf1_out: endpoint {
3874                                                         remote-endpoint = <&dsi0_in>;
3875                                                 };
3876                                         };
3877
3878                                         port@1 {
3879                                                 reg = <1>;
3880                                                 dpu_intf5_out: endpoint {
3881                                                         remote-endpoint = <&edp_in>;
3882                                                 };
3883                                         };
3884
3885                                         port@2 {
3886                                                 reg = <2>;
3887                                                 dpu_intf0_out: endpoint {
3888                                                         remote-endpoint = <&dp_in>;
3889                                                 };
3890                                         };
3891                                 };
3892
3893                                 mdp_opp_table: opp-table {
3894                                         compatible = "operating-points-v2";
3895
3896                                         opp-200000000 {
3897                                                 opp-hz = /bits/ 64 <200000000>;
3898                                                 required-opps = <&rpmhpd_opp_low_svs>;
3899                                         };
3900
3901                                         opp-300000000 {
3902                                                 opp-hz = /bits/ 64 <300000000>;
3903                                                 required-opps = <&rpmhpd_opp_svs>;
3904                                         };
3905
3906                                         opp-380000000 {
3907                                                 opp-hz = /bits/ 64 <380000000>;
3908                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3909                                         };
3910
3911                                         opp-506666667 {
3912                                                 opp-hz = /bits/ 64 <506666667>;
3913                                                 required-opps = <&rpmhpd_opp_nom>;
3914                                         };
3915                                 };
3916                         };
3917
3918                         mdss_dsi: dsi@ae94000 {
3919                                 compatible = "qcom,mdss-dsi-ctrl";
3920                                 reg = <0 0x0ae94000 0 0x400>;
3921                                 reg-names = "dsi_ctrl";
3922
3923                                 interrupt-parent = <&mdss>;
3924                                 interrupts = <4>;
3925
3926                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3927                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3928                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3929                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3930                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3931                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3932                                 clock-names = "byte",
3933                                               "byte_intf",
3934                                               "pixel",
3935                                               "core",
3936                                               "iface",
3937                                               "bus";
3938
3939                                 operating-points-v2 = <&dsi_opp_table>;
3940                                 power-domains = <&rpmhpd SC7280_CX>;
3941
3942                                 phys = <&mdss_dsi_phy>;
3943                                 phy-names = "dsi";
3944
3945                                 #address-cells = <1>;
3946                                 #size-cells = <0>;
3947
3948                                 status = "disabled";
3949
3950                                 ports {
3951                                         #address-cells = <1>;
3952                                         #size-cells = <0>;
3953
3954                                         port@0 {
3955                                                 reg = <0>;
3956                                                 dsi0_in: endpoint {
3957                                                         remote-endpoint = <&dpu_intf1_out>;
3958                                                 };
3959                                         };
3960
3961                                         port@1 {
3962                                                 reg = <1>;
3963                                                 dsi0_out: endpoint {
3964                                                 };
3965                                         };
3966                                 };
3967
3968                                 dsi_opp_table: opp-table {
3969                                         compatible = "operating-points-v2";
3970
3971                                         opp-187500000 {
3972                                                 opp-hz = /bits/ 64 <187500000>;
3973                                                 required-opps = <&rpmhpd_opp_low_svs>;
3974                                         };
3975
3976                                         opp-300000000 {
3977                                                 opp-hz = /bits/ 64 <300000000>;
3978                                                 required-opps = <&rpmhpd_opp_svs>;
3979                                         };
3980
3981                                         opp-358000000 {
3982                                                 opp-hz = /bits/ 64 <358000000>;
3983                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3984                                         };
3985                                 };
3986                         };
3987
3988                         mdss_dsi_phy: phy@ae94400 {
3989                                 compatible = "qcom,sc7280-dsi-phy-7nm";
3990                                 reg = <0 0x0ae94400 0 0x200>,
3991                                       <0 0x0ae94600 0 0x280>,
3992                                       <0 0x0ae94900 0 0x280>;
3993                                 reg-names = "dsi_phy",
3994                                             "dsi_phy_lane",
3995                                             "dsi_pll";
3996
3997                                 #clock-cells = <1>;
3998                                 #phy-cells = <0>;
3999
4000                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4001                                          <&rpmhcc RPMH_CXO_CLK>;
4002                                 clock-names = "iface", "ref";
4003
4004                                 status = "disabled";
4005                         };
4006
4007                         mdss_edp: edp@aea0000 {
4008                                 compatible = "qcom,sc7280-edp";
4009                                 pinctrl-names = "default";
4010                                 pinctrl-0 = <&edp_hot_plug_det>;
4011
4012                                 reg = <0 0xaea0000 0 0x200>,
4013                                       <0 0xaea0200 0 0x200>,
4014                                       <0 0xaea0400 0 0xc00>,
4015                                       <0 0xaea1000 0 0x400>;
4016
4017                                 interrupt-parent = <&mdss>;
4018                                 interrupts = <14>;
4019
4020                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4021                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4022                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4023                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4024                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4025                                 clock-names = "core_iface",
4026                                               "core_aux",
4027                                               "ctrl_link",
4028                                               "ctrl_link_iface",
4029                                               "stream_pixel";
4030                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4031                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4032                                 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4033
4034                                 phys = <&mdss_edp_phy>;
4035                                 phy-names = "dp";
4036
4037                                 operating-points-v2 = <&edp_opp_table>;
4038                                 power-domains = <&rpmhpd SC7280_CX>;
4039
4040                                 status = "disabled";
4041
4042                                 ports {
4043                                         #address-cells = <1>;
4044                                         #size-cells = <0>;
4045
4046                                         port@0 {
4047                                                 reg = <0>;
4048                                                 edp_in: endpoint {
4049                                                         remote-endpoint = <&dpu_intf5_out>;
4050                                                 };
4051                                         };
4052
4053                                         port@1 {
4054                                                 reg = <1>;
4055                                                 mdss_edp_out: endpoint { };
4056                                         };
4057                                 };
4058
4059                                 edp_opp_table: opp-table {
4060                                         compatible = "operating-points-v2";
4061
4062                                         opp-160000000 {
4063                                                 opp-hz = /bits/ 64 <160000000>;
4064                                                 required-opps = <&rpmhpd_opp_low_svs>;
4065                                         };
4066
4067                                         opp-270000000 {
4068                                                 opp-hz = /bits/ 64 <270000000>;
4069                                                 required-opps = <&rpmhpd_opp_svs>;
4070                                         };
4071
4072                                         opp-540000000 {
4073                                                 opp-hz = /bits/ 64 <540000000>;
4074                                                 required-opps = <&rpmhpd_opp_nom>;
4075                                         };
4076
4077                                         opp-810000000 {
4078                                                 opp-hz = /bits/ 64 <810000000>;
4079                                                 required-opps = <&rpmhpd_opp_nom>;
4080                                         };
4081                                 };
4082                         };
4083
4084                         mdss_edp_phy: phy@aec2a00 {
4085                                 compatible = "qcom,sc7280-edp-phy";
4086
4087                                 reg = <0 0xaec2a00 0 0x19c>,
4088                                       <0 0xaec2200 0 0xa0>,
4089                                       <0 0xaec2600 0 0xa0>,
4090                                       <0 0xaec2000 0 0x1c0>;
4091
4092                                 clocks = <&rpmhcc RPMH_CXO_CLK>,
4093                                          <&gcc GCC_EDP_CLKREF_EN>;
4094                                 clock-names = "aux",
4095                                               "cfg_ahb";
4096
4097                                 #clock-cells = <1>;
4098                                 #phy-cells = <0>;
4099
4100                                 status = "disabled";
4101                         };
4102
4103                         mdss_dp: displayport-controller@ae90000 {
4104                                 compatible = "qcom,sc7280-dp";
4105
4106                                 reg = <0 0xae90000 0 0x200>,
4107                                       <0 0xae90200 0 0x200>,
4108                                       <0 0xae90400 0 0xc00>,
4109                                       <0 0xae91000 0 0x400>,
4110                                       <0 0xae91400 0 0x400>;
4111
4112                                 interrupt-parent = <&mdss>;
4113                                 interrupts = <12>;
4114
4115                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4116                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4117                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4118                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4119                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4120                                 clock-names = "core_iface",
4121                                                 "core_aux",
4122                                                 "ctrl_link",
4123                                                 "ctrl_link_iface",
4124                                                 "stream_pixel";
4125                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4126                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4127                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4128                                 phys = <&dp_phy>;
4129                                 phy-names = "dp";
4130
4131                                 operating-points-v2 = <&dp_opp_table>;
4132                                 power-domains = <&rpmhpd SC7280_CX>;
4133
4134                                 #sound-dai-cells = <0>;
4135
4136                                 status = "disabled";
4137
4138                                 ports {
4139                                         #address-cells = <1>;
4140                                         #size-cells = <0>;
4141
4142                                         port@0 {
4143                                                 reg = <0>;
4144                                                 dp_in: endpoint {
4145                                                         remote-endpoint = <&dpu_intf0_out>;
4146                                                 };
4147                                         };
4148
4149                                         port@1 {
4150                                                 reg = <1>;
4151                                                 dp_out: endpoint { };
4152                                         };
4153                                 };
4154
4155                                 dp_opp_table: opp-table {
4156                                         compatible = "operating-points-v2";
4157
4158                                         opp-160000000 {
4159                                                 opp-hz = /bits/ 64 <160000000>;
4160                                                 required-opps = <&rpmhpd_opp_low_svs>;
4161                                         };
4162
4163                                         opp-270000000 {
4164                                                 opp-hz = /bits/ 64 <270000000>;
4165                                                 required-opps = <&rpmhpd_opp_svs>;
4166                                         };
4167
4168                                         opp-540000000 {
4169                                                 opp-hz = /bits/ 64 <540000000>;
4170                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4171                                         };
4172
4173                                         opp-810000000 {
4174                                                 opp-hz = /bits/ 64 <810000000>;
4175                                                 required-opps = <&rpmhpd_opp_nom>;
4176                                         };
4177                                 };
4178                         };
4179                 };
4180
4181                 pdc: interrupt-controller@b220000 {
4182                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
4183                         reg = <0 0x0b220000 0 0x30000>;
4184                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4185                                           <55 306 4>, <59 312 3>, <62 374 2>,
4186                                           <64 434 2>, <66 438 3>, <69 86 1>,
4187                                           <70 520 54>, <124 609 31>, <155 63 1>,
4188                                           <156 716 12>;
4189                         #interrupt-cells = <2>;
4190                         interrupt-parent = <&intc>;
4191                         interrupt-controller;
4192                 };
4193
4194                 pdc_reset: reset-controller@b5e0000 {
4195                         compatible = "qcom,sc7280-pdc-global";
4196                         reg = <0 0x0b5e0000 0 0x20000>;
4197                         #reset-cells = <1>;
4198                 };
4199
4200                 tsens0: thermal-sensor@c263000 {
4201                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4202                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4203                                 <0 0x0c222000 0 0x1ff>; /* SROT */
4204                         #qcom,sensors = <15>;
4205                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4206                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4207                         interrupt-names = "uplow","critical";
4208                         #thermal-sensor-cells = <1>;
4209                 };
4210
4211                 tsens1: thermal-sensor@c265000 {
4212                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4213                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4214                                 <0 0x0c223000 0 0x1ff>; /* SROT */
4215                         #qcom,sensors = <12>;
4216                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4217                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4218                         interrupt-names = "uplow","critical";
4219                         #thermal-sensor-cells = <1>;
4220                 };
4221
4222                 aoss_reset: reset-controller@c2a0000 {
4223                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4224                         reg = <0 0x0c2a0000 0 0x31000>;
4225                         #reset-cells = <1>;
4226                 };
4227
4228                 aoss_qmp: power-controller@c300000 {
4229                         compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4230                         reg = <0 0x0c300000 0 0x400>;
4231                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4232                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
4233                                                      IRQ_TYPE_EDGE_RISING>;
4234                         mboxes = <&ipcc IPCC_CLIENT_AOP
4235                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
4236
4237                         #clock-cells = <0>;
4238                 };
4239
4240                 sram@c3f0000 {
4241                         compatible = "qcom,rpmh-stats";
4242                         reg = <0 0x0c3f0000 0 0x400>;
4243                 };
4244
4245                 spmi_bus: spmi@c440000 {
4246                         compatible = "qcom,spmi-pmic-arb";
4247                         reg = <0 0x0c440000 0 0x1100>,
4248                               <0 0x0c600000 0 0x2000000>,
4249                               <0 0x0e600000 0 0x100000>,
4250                               <0 0x0e700000 0 0xa0000>,
4251                               <0 0x0c40a000 0 0x26000>;
4252                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4253                         interrupt-names = "periph_irq";
4254                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4255                         qcom,ee = <0>;
4256                         qcom,channel = <0>;
4257                         #address-cells = <2>;
4258                         #size-cells = <0>;
4259                         interrupt-controller;
4260                         #interrupt-cells = <4>;
4261                 };
4262
4263                 tlmm: pinctrl@f100000 {
4264                         compatible = "qcom,sc7280-pinctrl";
4265                         reg = <0 0x0f100000 0 0x300000>;
4266                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4267                         gpio-controller;
4268                         #gpio-cells = <2>;
4269                         interrupt-controller;
4270                         #interrupt-cells = <2>;
4271                         gpio-ranges = <&tlmm 0 0 175>;
4272                         wakeup-parent = <&pdc>;
4273
4274                         dp_hot_plug_det: dp-hot-plug-det-pins {
4275                                 pins = "gpio47";
4276                                 function = "dp_hot";
4277                         };
4278
4279                         edp_hot_plug_det: edp-hot-plug-det-pins {
4280                                 pins = "gpio60";
4281                                 function = "edp_hot";
4282                         };
4283
4284                         mi2s0_data0: mi2s0-data0-pins {
4285                                 pins = "gpio98";
4286                                 function = "mi2s0_data0";
4287                         };
4288
4289                         mi2s0_data1: mi2s0-data1-pins {
4290                                 pins = "gpio99";
4291                                 function = "mi2s0_data1";
4292                         };
4293
4294                         mi2s0_mclk: mi2s0-mclk-pins {
4295                                 pins = "gpio96";
4296                                 function = "pri_mi2s";
4297                         };
4298
4299                         mi2s0_sclk: mi2s0-sclk-pins {
4300                                 pins = "gpio97";
4301                                 function = "mi2s0_sck";
4302                         };
4303
4304                         mi2s0_ws: mi2s0-ws-pins {
4305                                 pins = "gpio100";
4306                                 function = "mi2s0_ws";
4307                         };
4308
4309                         mi2s1_data0: mi2s1-data0-pins {
4310                                 pins = "gpio107";
4311                                 function = "mi2s1_data0";
4312                         };
4313
4314                         mi2s1_sclk: mi2s1-sclk-pins {
4315                                 pins = "gpio106";
4316                                 function = "mi2s1_sck";
4317                         };
4318
4319                         mi2s1_ws: mi2s1-ws-pins {
4320                                 pins = "gpio108";
4321                                 function = "mi2s1_ws";
4322                         };
4323
4324                         pcie1_clkreq_n: pcie1-clkreq-n-pins {
4325                                 pins = "gpio79";
4326                                 function = "pcie1_clkreqn";
4327                         };
4328
4329                         qspi_clk: qspi-clk-pins {
4330                                 pins = "gpio14";
4331                                 function = "qspi_clk";
4332                         };
4333
4334                         qspi_cs0: qspi-cs0-pins {
4335                                 pins = "gpio15";
4336                                 function = "qspi_cs";
4337                         };
4338
4339                         qspi_cs1: qspi-cs1-pins {
4340                                 pins = "gpio19";
4341                                 function = "qspi_cs";
4342                         };
4343
4344                         qspi_data01: qspi-data01-pins {
4345                                 pins = "gpio12", "gpio13";
4346                                 function = "qspi_data";
4347                         };
4348
4349                         qspi_data23: qspi-data23-pins {
4350                                 pins = "gpio16", "gpio17";
4351                                 function = "qspi_data";
4352                         };
4353
4354                         qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
4355                                 pins = "gpio0", "gpio1";
4356                                 function = "qup00";
4357                         };
4358
4359                         qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
4360                                 pins = "gpio4", "gpio5";
4361                                 function = "qup01";
4362                         };
4363
4364                         qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
4365                                 pins = "gpio8", "gpio9";
4366                                 function = "qup02";
4367                         };
4368
4369                         qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
4370                                 pins = "gpio12", "gpio13";
4371                                 function = "qup03";
4372                         };
4373
4374                         qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
4375                                 pins = "gpio16", "gpio17";
4376                                 function = "qup04";
4377                         };
4378
4379                         qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
4380                                 pins = "gpio20", "gpio21";
4381                                 function = "qup05";
4382                         };
4383
4384                         qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
4385                                 pins = "gpio24", "gpio25";
4386                                 function = "qup06";
4387                         };
4388
4389                         qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
4390                                 pins = "gpio28", "gpio29";
4391                                 function = "qup07";
4392                         };
4393
4394                         qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
4395                                 pins = "gpio32", "gpio33";
4396                                 function = "qup10";
4397                         };
4398
4399                         qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
4400                                 pins = "gpio36", "gpio37";
4401                                 function = "qup11";
4402                         };
4403
4404                         qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
4405                                 pins = "gpio40", "gpio41";
4406                                 function = "qup12";
4407                         };
4408
4409                         qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
4410                                 pins = "gpio44", "gpio45";
4411                                 function = "qup13";
4412                         };
4413
4414                         qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
4415                                 pins = "gpio48", "gpio49";
4416                                 function = "qup14";
4417                         };
4418
4419                         qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
4420                                 pins = "gpio52", "gpio53";
4421                                 function = "qup15";
4422                         };
4423
4424                         qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
4425                                 pins = "gpio56", "gpio57";
4426                                 function = "qup16";
4427                         };
4428
4429                         qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
4430                                 pins = "gpio60", "gpio61";
4431                                 function = "qup17";
4432                         };
4433
4434                         qup_spi0_data_clk: qup-spi0-data-clk-pins {
4435                                 pins = "gpio0", "gpio1", "gpio2";
4436                                 function = "qup00";
4437                         };
4438
4439                         qup_spi0_cs: qup-spi0-cs-pins {
4440                                 pins = "gpio3";
4441                                 function = "qup00";
4442                         };
4443
4444                         qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
4445                                 pins = "gpio3";
4446                                 function = "gpio";
4447                         };
4448
4449                         qup_spi1_data_clk: qup-spi1-data-clk-pins {
4450                                 pins = "gpio4", "gpio5", "gpio6";
4451                                 function = "qup01";
4452                         };
4453
4454                         qup_spi1_cs: qup-spi1-cs-pins {
4455                                 pins = "gpio7";
4456                                 function = "qup01";
4457                         };
4458
4459                         qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
4460                                 pins = "gpio7";
4461                                 function = "gpio";
4462                         };
4463
4464                         qup_spi2_data_clk: qup-spi2-data-clk-pins {
4465                                 pins = "gpio8", "gpio9", "gpio10";
4466                                 function = "qup02";
4467                         };
4468
4469                         qup_spi2_cs: qup-spi2-cs-pins {
4470                                 pins = "gpio11";
4471                                 function = "qup02";
4472                         };
4473
4474                         qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
4475                                 pins = "gpio11";
4476                                 function = "gpio";
4477                         };
4478
4479                         qup_spi3_data_clk: qup-spi3-data-clk-pins {
4480                                 pins = "gpio12", "gpio13", "gpio14";
4481                                 function = "qup03";
4482                         };
4483
4484                         qup_spi3_cs: qup-spi3-cs-pins {
4485                                 pins = "gpio15";
4486                                 function = "qup03";
4487                         };
4488
4489                         qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
4490                                 pins = "gpio15";
4491                                 function = "gpio";
4492                         };
4493
4494                         qup_spi4_data_clk: qup-spi4-data-clk-pins {
4495                                 pins = "gpio16", "gpio17", "gpio18";
4496                                 function = "qup04";
4497                         };
4498
4499                         qup_spi4_cs: qup-spi4-cs-pins {
4500                                 pins = "gpio19";
4501                                 function = "qup04";
4502                         };
4503
4504                         qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
4505                                 pins = "gpio19";
4506                                 function = "gpio";
4507                         };
4508
4509                         qup_spi5_data_clk: qup-spi5-data-clk-pins {
4510                                 pins = "gpio20", "gpio21", "gpio22";
4511                                 function = "qup05";
4512                         };
4513
4514                         qup_spi5_cs: qup-spi5-cs-pins {
4515                                 pins = "gpio23";
4516                                 function = "qup05";
4517                         };
4518
4519                         qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
4520                                 pins = "gpio23";
4521                                 function = "gpio";
4522                         };
4523
4524                         qup_spi6_data_clk: qup-spi6-data-clk-pins {
4525                                 pins = "gpio24", "gpio25", "gpio26";
4526                                 function = "qup06";
4527                         };
4528
4529                         qup_spi6_cs: qup-spi6-cs-pins {
4530                                 pins = "gpio27";
4531                                 function = "qup06";
4532                         };
4533
4534                         qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
4535                                 pins = "gpio27";
4536                                 function = "gpio";
4537                         };
4538
4539                         qup_spi7_data_clk: qup-spi7-data-clk-pins {
4540                                 pins = "gpio28", "gpio29", "gpio30";
4541                                 function = "qup07";
4542                         };
4543
4544                         qup_spi7_cs: qup-spi7-cs-pins {
4545                                 pins = "gpio31";
4546                                 function = "qup07";
4547                         };
4548
4549                         qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
4550                                 pins = "gpio31";
4551                                 function = "gpio";
4552                         };
4553
4554                         qup_spi8_data_clk: qup-spi8-data-clk-pins {
4555                                 pins = "gpio32", "gpio33", "gpio34";
4556                                 function = "qup10";
4557                         };
4558
4559                         qup_spi8_cs: qup-spi8-cs-pins {
4560                                 pins = "gpio35";
4561                                 function = "qup10";
4562                         };
4563
4564                         qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
4565                                 pins = "gpio35";
4566                                 function = "gpio";
4567                         };
4568
4569                         qup_spi9_data_clk: qup-spi9-data-clk-pins {
4570                                 pins = "gpio36", "gpio37", "gpio38";
4571                                 function = "qup11";
4572                         };
4573
4574                         qup_spi9_cs: qup-spi9-cs-pins {
4575                                 pins = "gpio39";
4576                                 function = "qup11";
4577                         };
4578
4579                         qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
4580                                 pins = "gpio39";
4581                                 function = "gpio";
4582                         };
4583
4584                         qup_spi10_data_clk: qup-spi10-data-clk-pins {
4585                                 pins = "gpio40", "gpio41", "gpio42";
4586                                 function = "qup12";
4587                         };
4588
4589                         qup_spi10_cs: qup-spi10-cs-pins {
4590                                 pins = "gpio43";
4591                                 function = "qup12";
4592                         };
4593
4594                         qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
4595                                 pins = "gpio43";
4596                                 function = "gpio";
4597                         };
4598
4599                         qup_spi11_data_clk: qup-spi11-data-clk-pins {
4600                                 pins = "gpio44", "gpio45", "gpio46";
4601                                 function = "qup13";
4602                         };
4603
4604                         qup_spi11_cs: qup-spi11-cs-pins {
4605                                 pins = "gpio47";
4606                                 function = "qup13";
4607                         };
4608
4609                         qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
4610                                 pins = "gpio47";
4611                                 function = "gpio";
4612                         };
4613
4614                         qup_spi12_data_clk: qup-spi12-data-clk-pins {
4615                                 pins = "gpio48", "gpio49", "gpio50";
4616                                 function = "qup14";
4617                         };
4618
4619                         qup_spi12_cs: qup-spi12-cs-pins {
4620                                 pins = "gpio51";
4621                                 function = "qup14";
4622                         };
4623
4624                         qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
4625                                 pins = "gpio51";
4626                                 function = "gpio";
4627                         };
4628
4629                         qup_spi13_data_clk: qup-spi13-data-clk-pins {
4630                                 pins = "gpio52", "gpio53", "gpio54";
4631                                 function = "qup15";
4632                         };
4633
4634                         qup_spi13_cs: qup-spi13-cs-pins {
4635                                 pins = "gpio55";
4636                                 function = "qup15";
4637                         };
4638
4639                         qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
4640                                 pins = "gpio55";
4641                                 function = "gpio";
4642                         };
4643
4644                         qup_spi14_data_clk: qup-spi14-data-clk-pins {
4645                                 pins = "gpio56", "gpio57", "gpio58";
4646                                 function = "qup16";
4647                         };
4648
4649                         qup_spi14_cs: qup-spi14-cs-pins {
4650                                 pins = "gpio59";
4651                                 function = "qup16";
4652                         };
4653
4654                         qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
4655                                 pins = "gpio59";
4656                                 function = "gpio";
4657                         };
4658
4659                         qup_spi15_data_clk: qup-spi15-data-clk-pins {
4660                                 pins = "gpio60", "gpio61", "gpio62";
4661                                 function = "qup17";
4662                         };
4663
4664                         qup_spi15_cs: qup-spi15-cs-pins {
4665                                 pins = "gpio63";
4666                                 function = "qup17";
4667                         };
4668
4669                         qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
4670                                 pins = "gpio63";
4671                                 function = "gpio";
4672                         };
4673
4674                         qup_uart0_cts: qup-uart0-cts-pins {
4675                                 pins = "gpio0";
4676                                 function = "qup00";
4677                         };
4678
4679                         qup_uart0_rts: qup-uart0-rts-pins {
4680                                 pins = "gpio1";
4681                                 function = "qup00";
4682                         };
4683
4684                         qup_uart0_tx: qup-uart0-tx-pins {
4685                                 pins = "gpio2";
4686                                 function = "qup00";
4687                         };
4688
4689                         qup_uart0_rx: qup-uart0-rx-pins {
4690                                 pins = "gpio3";
4691                                 function = "qup00";
4692                         };
4693
4694                         qup_uart1_cts: qup-uart1-cts-pins {
4695                                 pins = "gpio4";
4696                                 function = "qup01";
4697                         };
4698
4699                         qup_uart1_rts: qup-uart1-rts-pins {
4700                                 pins = "gpio5";
4701                                 function = "qup01";
4702                         };
4703
4704                         qup_uart1_tx: qup-uart1-tx-pins {
4705                                 pins = "gpio6";
4706                                 function = "qup01";
4707                         };
4708
4709                         qup_uart1_rx: qup-uart1-rx-pins {
4710                                 pins = "gpio7";
4711                                 function = "qup01";
4712                         };
4713
4714                         qup_uart2_cts: qup-uart2-cts-pins {
4715                                 pins = "gpio8";
4716                                 function = "qup02";
4717                         };
4718
4719                         qup_uart2_rts: qup-uart2-rts-pins {
4720                                 pins = "gpio9";
4721                                 function = "qup02";
4722                         };
4723
4724                         qup_uart2_tx: qup-uart2-tx-pins {
4725                                 pins = "gpio10";
4726                                 function = "qup02";
4727                         };
4728
4729                         qup_uart2_rx: qup-uart2-rx-pins {
4730                                 pins = "gpio11";
4731                                 function = "qup02";
4732                         };
4733
4734                         qup_uart3_cts: qup-uart3-cts-pins {
4735                                 pins = "gpio12";
4736                                 function = "qup03";
4737                         };
4738
4739                         qup_uart3_rts: qup-uart3-rts-pins {
4740                                 pins = "gpio13";
4741                                 function = "qup03";
4742                         };
4743
4744                         qup_uart3_tx: qup-uart3-tx-pins {
4745                                 pins = "gpio14";
4746                                 function = "qup03";
4747                         };
4748
4749                         qup_uart3_rx: qup-uart3-rx-pins {
4750                                 pins = "gpio15";
4751                                 function = "qup03";
4752                         };
4753
4754                         qup_uart4_cts: qup-uart4-cts-pins {
4755                                 pins = "gpio16";
4756                                 function = "qup04";
4757                         };
4758
4759                         qup_uart4_rts: qup-uart4-rts-pins {
4760                                 pins = "gpio17";
4761                                 function = "qup04";
4762                         };
4763
4764                         qup_uart4_tx: qup-uart4-tx-pins {
4765                                 pins = "gpio18";
4766                                 function = "qup04";
4767                         };
4768
4769                         qup_uart4_rx: qup-uart4-rx-pins {
4770                                 pins = "gpio19";
4771                                 function = "qup04";
4772                         };
4773
4774                         qup_uart5_cts: qup-uart5-cts-pins {
4775                                 pins = "gpio20";
4776                                 function = "qup05";
4777                         };
4778
4779                         qup_uart5_rts: qup-uart5-rts-pins {
4780                                 pins = "gpio21";
4781                                 function = "qup05";
4782                         };
4783
4784                         qup_uart5_tx: qup-uart5-tx-pins {
4785                                 pins = "gpio22";
4786                                 function = "qup05";
4787                         };
4788
4789                         qup_uart5_rx: qup-uart5-rx-pins {
4790                                 pins = "gpio23";
4791                                 function = "qup05";
4792                         };
4793
4794                         qup_uart6_cts: qup-uart6-cts-pins {
4795                                 pins = "gpio24";
4796                                 function = "qup06";
4797                         };
4798
4799                         qup_uart6_rts: qup-uart6-rts-pins {
4800                                 pins = "gpio25";
4801                                 function = "qup06";
4802                         };
4803
4804                         qup_uart6_tx: qup-uart6-tx-pins {
4805                                 pins = "gpio26";
4806                                 function = "qup06";
4807                         };
4808
4809                         qup_uart6_rx: qup-uart6-rx-pins {
4810                                 pins = "gpio27";
4811                                 function = "qup06";
4812                         };
4813
4814                         qup_uart7_cts: qup-uart7-cts-pins {
4815                                 pins = "gpio28";
4816                                 function = "qup07";
4817                         };
4818
4819                         qup_uart7_rts: qup-uart7-rts-pins {
4820                                 pins = "gpio29";
4821                                 function = "qup07";
4822                         };
4823
4824                         qup_uart7_tx: qup-uart7-tx-pins {
4825                                 pins = "gpio30";
4826                                 function = "qup07";
4827                         };
4828
4829                         qup_uart7_rx: qup-uart7-rx-pins {
4830                                 pins = "gpio31";
4831                                 function = "qup07";
4832                         };
4833
4834                         qup_uart8_cts: qup-uart8-cts-pins {
4835                                 pins = "gpio32";
4836                                 function = "qup10";
4837                         };
4838
4839                         qup_uart8_rts: qup-uart8-rts-pins {
4840                                 pins = "gpio33";
4841                                 function = "qup10";
4842                         };
4843
4844                         qup_uart8_tx: qup-uart8-tx-pins {
4845                                 pins = "gpio34";
4846                                 function = "qup10";
4847                         };
4848
4849                         qup_uart8_rx: qup-uart8-rx-pins {
4850                                 pins = "gpio35";
4851                                 function = "qup10";
4852                         };
4853
4854                         qup_uart9_cts: qup-uart9-cts-pins {
4855                                 pins = "gpio36";
4856                                 function = "qup11";
4857                         };
4858
4859                         qup_uart9_rts: qup-uart9-rts-pins {
4860                                 pins = "gpio37";
4861                                 function = "qup11";
4862                         };
4863
4864                         qup_uart9_tx: qup-uart9-tx-pins {
4865                                 pins = "gpio38";
4866                                 function = "qup11";
4867                         };
4868
4869                         qup_uart9_rx: qup-uart9-rx-pins {
4870                                 pins = "gpio39";
4871                                 function = "qup11";
4872                         };
4873
4874                         qup_uart10_cts: qup-uart10-cts-pins {
4875                                 pins = "gpio40";
4876                                 function = "qup12";
4877                         };
4878
4879                         qup_uart10_rts: qup-uart10-rts-pins {
4880                                 pins = "gpio41";
4881                                 function = "qup12";
4882                         };
4883
4884                         qup_uart10_tx: qup-uart10-tx-pins {
4885                                 pins = "gpio42";
4886                                 function = "qup12";
4887                         };
4888
4889                         qup_uart10_rx: qup-uart10-rx-pins {
4890                                 pins = "gpio43";
4891                                 function = "qup12";
4892                         };
4893
4894                         qup_uart11_cts: qup-uart11-cts-pins {
4895                                 pins = "gpio44";
4896                                 function = "qup13";
4897                         };
4898
4899                         qup_uart11_rts: qup-uart11-rts-pins {
4900                                 pins = "gpio45";
4901                                 function = "qup13";
4902                         };
4903
4904                         qup_uart11_tx: qup-uart11-tx-pins {
4905                                 pins = "gpio46";
4906                                 function = "qup13";
4907                         };
4908
4909                         qup_uart11_rx: qup-uart11-rx-pins {
4910                                 pins = "gpio47";
4911                                 function = "qup13";
4912                         };
4913
4914                         qup_uart12_cts: qup-uart12-cts-pins {
4915                                 pins = "gpio48";
4916                                 function = "qup14";
4917                         };
4918
4919                         qup_uart12_rts: qup-uart12-rts-pins {
4920                                 pins = "gpio49";
4921                                 function = "qup14";
4922                         };
4923
4924                         qup_uart12_tx: qup-uart12-tx-pins {
4925                                 pins = "gpio50";
4926                                 function = "qup14";
4927                         };
4928
4929                         qup_uart12_rx: qup-uart12-rx-pins {
4930                                 pins = "gpio51";
4931                                 function = "qup14";
4932                         };
4933
4934                         qup_uart13_cts: qup-uart13-cts-pins {
4935                                 pins = "gpio52";
4936                                 function = "qup15";
4937                         };
4938
4939                         qup_uart13_rts: qup-uart13-rts-pins {
4940                                 pins = "gpio53";
4941                                 function = "qup15";
4942                         };
4943
4944                         qup_uart13_tx: qup-uart13-tx-pins {
4945                                 pins = "gpio54";
4946                                 function = "qup15";
4947                         };
4948
4949                         qup_uart13_rx: qup-uart13-rx-pins {
4950                                 pins = "gpio55";
4951                                 function = "qup15";
4952                         };
4953
4954                         qup_uart14_cts: qup-uart14-cts-pins {
4955                                 pins = "gpio56";
4956                                 function = "qup16";
4957                         };
4958
4959                         qup_uart14_rts: qup-uart14-rts-pins {
4960                                 pins = "gpio57";
4961                                 function = "qup16";
4962                         };
4963
4964                         qup_uart14_tx: qup-uart14-tx-pins {
4965                                 pins = "gpio58";
4966                                 function = "qup16";
4967                         };
4968
4969                         qup_uart14_rx: qup-uart14-rx-pins {
4970                                 pins = "gpio59";
4971                                 function = "qup16";
4972                         };
4973
4974                         qup_uart15_cts: qup-uart15-cts-pins {
4975                                 pins = "gpio60";
4976                                 function = "qup17";
4977                         };
4978
4979                         qup_uart15_rts: qup-uart15-rts-pins {
4980                                 pins = "gpio61";
4981                                 function = "qup17";
4982                         };
4983
4984                         qup_uart15_tx: qup-uart15-tx-pins {
4985                                 pins = "gpio62";
4986                                 function = "qup17";
4987                         };
4988
4989                         qup_uart15_rx: qup-uart15-rx-pins {
4990                                 pins = "gpio63";
4991                                 function = "qup17";
4992                         };
4993
4994                         sdc1_clk: sdc1-clk-pins {
4995                                 pins = "sdc1_clk";
4996                         };
4997
4998                         sdc1_cmd: sdc1-cmd-pins {
4999                                 pins = "sdc1_cmd";
5000                         };
5001
5002                         sdc1_data: sdc1-data-pins {
5003                                 pins = "sdc1_data";
5004                         };
5005
5006                         sdc1_rclk: sdc1-rclk-pins {
5007                                 pins = "sdc1_rclk";
5008                         };
5009
5010                         sdc1_clk_sleep: sdc1-clk-sleep-pins {
5011                                 pins = "sdc1_clk";
5012                                 drive-strength = <2>;
5013                                 bias-bus-hold;
5014                         };
5015
5016                         sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
5017                                 pins = "sdc1_cmd";
5018                                 drive-strength = <2>;
5019                                 bias-bus-hold;
5020                         };
5021
5022                         sdc1_data_sleep: sdc1-data-sleep-pins {
5023                                 pins = "sdc1_data";
5024                                 drive-strength = <2>;
5025                                 bias-bus-hold;
5026                         };
5027
5028                         sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
5029                                 pins = "sdc1_rclk";
5030                                 drive-strength = <2>;
5031                                 bias-bus-hold;
5032                         };
5033
5034                         sdc2_clk: sdc2-clk-pins {
5035                                 pins = "sdc2_clk";
5036                         };
5037
5038                         sdc2_cmd: sdc2-cmd-pins {
5039                                 pins = "sdc2_cmd";
5040                         };
5041
5042                         sdc2_data: sdc2-data-pins {
5043                                 pins = "sdc2_data";
5044                         };
5045
5046                         sdc2_clk_sleep: sdc2-clk-sleep-pins {
5047                                 pins = "sdc2_clk";
5048                                 drive-strength = <2>;
5049                                 bias-bus-hold;
5050                         };
5051
5052                         sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
5053                                 pins = "sdc2_cmd";
5054                                 drive-strength = <2>;
5055                                 bias-bus-hold;
5056                         };
5057
5058                         sdc2_data_sleep: sdc2-data-sleep-pins {
5059                                 pins = "sdc2_data";
5060                                 drive-strength = <2>;
5061                                 bias-bus-hold;
5062                         };
5063                 };
5064
5065                 sram@146a5000 {
5066                         compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5067                         reg = <0 0x146a5000 0 0x6000>;
5068
5069                         #address-cells = <1>;
5070                         #size-cells = <1>;
5071
5072                         ranges = <0 0 0x146a5000 0x6000>;
5073
5074                         pil-reloc@594c {
5075                                 compatible = "qcom,pil-reloc-info";
5076                                 reg = <0x594c 0xc8>;
5077                         };
5078                 };
5079
5080                 apps_smmu: iommu@15000000 {
5081                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5082                         reg = <0 0x15000000 0 0x100000>;
5083                         #iommu-cells = <2>;
5084                         #global-interrupts = <1>;
5085                         dma-coherent;
5086                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5087                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5088                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5089                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5090                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5091                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5092                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5093                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5094                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5095                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5096                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5097                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5098                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5099                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5100                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5101                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5102                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5103                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5104                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5105                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5106                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5107                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5108                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5109                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5110                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5111                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5112                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5113                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5114                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5115                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5116                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5117                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5118                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5119                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5120                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5121                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5122                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5123                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5124                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5125                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5126                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5127                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5128                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5129                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5130                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5131                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5132                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5133                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5134                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5135                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5136                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5137                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5138                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5139                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5140                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5141                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5142                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5143                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5144                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5145                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5146                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5147                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5148                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5149                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5150                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5151                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5152                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5153                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5154                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5155                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5156                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5157                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5158                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5159                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5160                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5161                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5162                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5163                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5164                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5165                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5166                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5167                 };
5168
5169                 intc: interrupt-controller@17a00000 {
5170                         compatible = "arm,gic-v3";
5171                         #address-cells = <2>;
5172                         #size-cells = <2>;
5173                         ranges;
5174                         #interrupt-cells = <3>;
5175                         interrupt-controller;
5176                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
5177                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
5178                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5179
5180                         gic-its@17a40000 {
5181                                 compatible = "arm,gic-v3-its";
5182                                 msi-controller;
5183                                 #msi-cells = <1>;
5184                                 reg = <0 0x17a40000 0 0x20000>;
5185                                 status = "disabled";
5186                         };
5187                 };
5188
5189                 watchdog@17c10000 {
5190                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5191                         reg = <0 0x17c10000 0 0x1000>;
5192                         clocks = <&sleep_clk>;
5193                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5194                 };
5195
5196                 timer@17c20000 {
5197                         #address-cells = <1>;
5198                         #size-cells = <1>;
5199                         ranges = <0 0 0 0x20000000>;
5200                         compatible = "arm,armv7-timer-mem";
5201                         reg = <0 0x17c20000 0 0x1000>;
5202
5203                         frame@17c21000 {
5204                                 frame-number = <0>;
5205                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5206                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5207                                 reg = <0x17c21000 0x1000>,
5208                                       <0x17c22000 0x1000>;
5209                         };
5210
5211                         frame@17c23000 {
5212                                 frame-number = <1>;
5213                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5214                                 reg = <0x17c23000 0x1000>;
5215                                 status = "disabled";
5216                         };
5217
5218                         frame@17c25000 {
5219                                 frame-number = <2>;
5220                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5221                                 reg = <0x17c25000 0x1000>;
5222                                 status = "disabled";
5223                         };
5224
5225                         frame@17c27000 {
5226                                 frame-number = <3>;
5227                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5228                                 reg = <0x17c27000 0x1000>;
5229                                 status = "disabled";
5230                         };
5231
5232                         frame@17c29000 {
5233                                 frame-number = <4>;
5234                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5235                                 reg = <0x17c29000 0x1000>;
5236                                 status = "disabled";
5237                         };
5238
5239                         frame@17c2b000 {
5240                                 frame-number = <5>;
5241                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5242                                 reg = <0x17c2b000 0x1000>;
5243                                 status = "disabled";
5244                         };
5245
5246                         frame@17c2d000 {
5247                                 frame-number = <6>;
5248                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5249                                 reg = <0x17c2d000 0x1000>;
5250                                 status = "disabled";
5251                         };
5252                 };
5253
5254                 apps_rsc: rsc@18200000 {
5255                         compatible = "qcom,rpmh-rsc";
5256                         reg = <0 0x18200000 0 0x10000>,
5257                               <0 0x18210000 0 0x10000>,
5258                               <0 0x18220000 0 0x10000>;
5259                         reg-names = "drv-0", "drv-1", "drv-2";
5260                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5261                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5262                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5263                         qcom,tcs-offset = <0xd00>;
5264                         qcom,drv-id = <2>;
5265                         qcom,tcs-config = <ACTIVE_TCS  2>,
5266                                           <SLEEP_TCS   3>,
5267                                           <WAKE_TCS    3>,
5268                                           <CONTROL_TCS 1>;
5269
5270                         apps_bcm_voter: bcm-voter {
5271                                 compatible = "qcom,bcm-voter";
5272                         };
5273
5274                         rpmhpd: power-controller {
5275                                 compatible = "qcom,sc7280-rpmhpd";
5276                                 #power-domain-cells = <1>;
5277                                 operating-points-v2 = <&rpmhpd_opp_table>;
5278
5279                                 rpmhpd_opp_table: opp-table {
5280                                         compatible = "operating-points-v2";
5281
5282                                         rpmhpd_opp_ret: opp1 {
5283                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5284                                         };
5285
5286                                         rpmhpd_opp_low_svs: opp2 {
5287                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5288                                         };
5289
5290                                         rpmhpd_opp_svs: opp3 {
5291                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5292                                         };
5293
5294                                         rpmhpd_opp_svs_l1: opp4 {
5295                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5296                                         };
5297
5298                                         rpmhpd_opp_svs_l2: opp5 {
5299                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5300                                         };
5301
5302                                         rpmhpd_opp_nom: opp6 {
5303                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5304                                         };
5305
5306                                         rpmhpd_opp_nom_l1: opp7 {
5307                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5308                                         };
5309
5310                                         rpmhpd_opp_turbo: opp8 {
5311                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5312                                         };
5313
5314                                         rpmhpd_opp_turbo_l1: opp9 {
5315                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5316                                         };
5317                                 };
5318                         };
5319
5320                         rpmhcc: clock-controller {
5321                                 compatible = "qcom,sc7280-rpmh-clk";
5322                                 clocks = <&xo_board>;
5323                                 clock-names = "xo";
5324                                 #clock-cells = <1>;
5325                         };
5326                 };
5327
5328                 epss_l3: interconnect@18590000 {
5329                         compatible = "qcom,sc7280-epss-l3";
5330                         reg = <0 0x18590000 0 0x1000>;
5331                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5332                         clock-names = "xo", "alternate";
5333                         #interconnect-cells = <1>;
5334                 };
5335
5336                 cpufreq_hw: cpufreq@18591000 {
5337                         compatible = "qcom,cpufreq-epss";
5338                         reg = <0 0x18591000 0 0x1000>,
5339                               <0 0x18592000 0 0x1000>,
5340                               <0 0x18593000 0 0x1000>;
5341
5342                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
5343                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
5344                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
5345                         interrupt-names = "dcvsh-irq-0",
5346                                           "dcvsh-irq-1",
5347                                           "dcvsh-irq-2";
5348
5349                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5350                         clock-names = "xo", "alternate";
5351                         #freq-domain-cells = <1>;
5352                 };
5353         };
5354
5355         thermal_zones: thermal-zones {
5356                 cpu0-thermal {
5357                         polling-delay-passive = <250>;
5358                         polling-delay = <0>;
5359
5360                         thermal-sensors = <&tsens0 1>;
5361
5362                         trips {
5363                                 cpu0_alert0: trip-point0 {
5364                                         temperature = <90000>;
5365                                         hysteresis = <2000>;
5366                                         type = "passive";
5367                                 };
5368
5369                                 cpu0_alert1: trip-point1 {
5370                                         temperature = <95000>;
5371                                         hysteresis = <2000>;
5372                                         type = "passive";
5373                                 };
5374
5375                                 cpu0_crit: cpu-crit {
5376                                         temperature = <110000>;
5377                                         hysteresis = <0>;
5378                                         type = "critical";
5379                                 };
5380                         };
5381
5382                         cooling-maps {
5383                                 map0 {
5384                                         trip = <&cpu0_alert0>;
5385                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5386                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5387                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5388                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5389                                 };
5390                                 map1 {
5391                                         trip = <&cpu0_alert1>;
5392                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5393                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5394                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5395                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5396                                 };
5397                         };
5398                 };
5399
5400                 cpu1-thermal {
5401                         polling-delay-passive = <250>;
5402                         polling-delay = <0>;
5403
5404                         thermal-sensors = <&tsens0 2>;
5405
5406                         trips {
5407                                 cpu1_alert0: trip-point0 {
5408                                         temperature = <90000>;
5409                                         hysteresis = <2000>;
5410                                         type = "passive";
5411                                 };
5412
5413                                 cpu1_alert1: trip-point1 {
5414                                         temperature = <95000>;
5415                                         hysteresis = <2000>;
5416                                         type = "passive";
5417                                 };
5418
5419                                 cpu1_crit: cpu-crit {
5420                                         temperature = <110000>;
5421                                         hysteresis = <0>;
5422                                         type = "critical";
5423                                 };
5424                         };
5425
5426                         cooling-maps {
5427                                 map0 {
5428                                         trip = <&cpu1_alert0>;
5429                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5430                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5431                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5432                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5433                                 };
5434                                 map1 {
5435                                         trip = <&cpu1_alert1>;
5436                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5437                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5438                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5439                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5440                                 };
5441                         };
5442                 };
5443
5444                 cpu2-thermal {
5445                         polling-delay-passive = <250>;
5446                         polling-delay = <0>;
5447
5448                         thermal-sensors = <&tsens0 3>;
5449
5450                         trips {
5451                                 cpu2_alert0: trip-point0 {
5452                                         temperature = <90000>;
5453                                         hysteresis = <2000>;
5454                                         type = "passive";
5455                                 };
5456
5457                                 cpu2_alert1: trip-point1 {
5458                                         temperature = <95000>;
5459                                         hysteresis = <2000>;
5460                                         type = "passive";
5461                                 };
5462
5463                                 cpu2_crit: cpu-crit {
5464                                         temperature = <110000>;
5465                                         hysteresis = <0>;
5466                                         type = "critical";
5467                                 };
5468                         };
5469
5470                         cooling-maps {
5471                                 map0 {
5472                                         trip = <&cpu2_alert0>;
5473                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5474                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5475                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5476                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5477                                 };
5478                                 map1 {
5479                                         trip = <&cpu2_alert1>;
5480                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5481                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5482                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5483                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5484                                 };
5485                         };
5486                 };
5487
5488                 cpu3-thermal {
5489                         polling-delay-passive = <250>;
5490                         polling-delay = <0>;
5491
5492                         thermal-sensors = <&tsens0 4>;
5493
5494                         trips {
5495                                 cpu3_alert0: trip-point0 {
5496                                         temperature = <90000>;
5497                                         hysteresis = <2000>;
5498                                         type = "passive";
5499                                 };
5500
5501                                 cpu3_alert1: trip-point1 {
5502                                         temperature = <95000>;
5503                                         hysteresis = <2000>;
5504                                         type = "passive";
5505                                 };
5506
5507                                 cpu3_crit: cpu-crit {
5508                                         temperature = <110000>;
5509                                         hysteresis = <0>;
5510                                         type = "critical";
5511                                 };
5512                         };
5513
5514                         cooling-maps {
5515                                 map0 {
5516                                         trip = <&cpu3_alert0>;
5517                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5518                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5519                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5520                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5521                                 };
5522                                 map1 {
5523                                         trip = <&cpu3_alert1>;
5524                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5525                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5526                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5527                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5528                                 };
5529                         };
5530                 };
5531
5532                 cpu4-thermal {
5533                         polling-delay-passive = <250>;
5534                         polling-delay = <0>;
5535
5536                         thermal-sensors = <&tsens0 7>;
5537
5538                         trips {
5539                                 cpu4_alert0: trip-point0 {
5540                                         temperature = <90000>;
5541                                         hysteresis = <2000>;
5542                                         type = "passive";
5543                                 };
5544
5545                                 cpu4_alert1: trip-point1 {
5546                                         temperature = <95000>;
5547                                         hysteresis = <2000>;
5548                                         type = "passive";
5549                                 };
5550
5551                                 cpu4_crit: cpu-crit {
5552                                         temperature = <110000>;
5553                                         hysteresis = <0>;
5554                                         type = "critical";
5555                                 };
5556                         };
5557
5558                         cooling-maps {
5559                                 map0 {
5560                                         trip = <&cpu4_alert0>;
5561                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5562                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5563                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5564                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5565                                 };
5566                                 map1 {
5567                                         trip = <&cpu4_alert1>;
5568                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5569                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5570                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5571                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5572                                 };
5573                         };
5574                 };
5575
5576                 cpu5-thermal {
5577                         polling-delay-passive = <250>;
5578                         polling-delay = <0>;
5579
5580                         thermal-sensors = <&tsens0 8>;
5581
5582                         trips {
5583                                 cpu5_alert0: trip-point0 {
5584                                         temperature = <90000>;
5585                                         hysteresis = <2000>;
5586                                         type = "passive";
5587                                 };
5588
5589                                 cpu5_alert1: trip-point1 {
5590                                         temperature = <95000>;
5591                                         hysteresis = <2000>;
5592                                         type = "passive";
5593                                 };
5594
5595                                 cpu5_crit: cpu-crit {
5596                                         temperature = <110000>;
5597                                         hysteresis = <0>;
5598                                         type = "critical";
5599                                 };
5600                         };
5601
5602                         cooling-maps {
5603                                 map0 {
5604                                         trip = <&cpu5_alert0>;
5605                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5606                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5607                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5608                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5609                                 };
5610                                 map1 {
5611                                         trip = <&cpu5_alert1>;
5612                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5613                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5614                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5615                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5616                                 };
5617                         };
5618                 };
5619
5620                 cpu6-thermal {
5621                         polling-delay-passive = <250>;
5622                         polling-delay = <0>;
5623
5624                         thermal-sensors = <&tsens0 9>;
5625
5626                         trips {
5627                                 cpu6_alert0: trip-point0 {
5628                                         temperature = <90000>;
5629                                         hysteresis = <2000>;
5630                                         type = "passive";
5631                                 };
5632
5633                                 cpu6_alert1: trip-point1 {
5634                                         temperature = <95000>;
5635                                         hysteresis = <2000>;
5636                                         type = "passive";
5637                                 };
5638
5639                                 cpu6_crit: cpu-crit {
5640                                         temperature = <110000>;
5641                                         hysteresis = <0>;
5642                                         type = "critical";
5643                                 };
5644                         };
5645
5646                         cooling-maps {
5647                                 map0 {
5648                                         trip = <&cpu6_alert0>;
5649                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5650                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5651                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5652                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5653                                 };
5654                                 map1 {
5655                                         trip = <&cpu6_alert1>;
5656                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5657                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5658                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5659                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5660                                 };
5661                         };
5662                 };
5663
5664                 cpu7-thermal {
5665                         polling-delay-passive = <250>;
5666                         polling-delay = <0>;
5667
5668                         thermal-sensors = <&tsens0 10>;
5669
5670                         trips {
5671                                 cpu7_alert0: trip-point0 {
5672                                         temperature = <90000>;
5673                                         hysteresis = <2000>;
5674                                         type = "passive";
5675                                 };
5676
5677                                 cpu7_alert1: trip-point1 {
5678                                         temperature = <95000>;
5679                                         hysteresis = <2000>;
5680                                         type = "passive";
5681                                 };
5682
5683                                 cpu7_crit: cpu-crit {
5684                                         temperature = <110000>;
5685                                         hysteresis = <0>;
5686                                         type = "critical";
5687                                 };
5688                         };
5689
5690                         cooling-maps {
5691                                 map0 {
5692                                         trip = <&cpu7_alert0>;
5693                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5694                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5695                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5696                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5697                                 };
5698                                 map1 {
5699                                         trip = <&cpu7_alert1>;
5700                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5701                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5702                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5703                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5704                                 };
5705                         };
5706                 };
5707
5708                 cpu8-thermal {
5709                         polling-delay-passive = <250>;
5710                         polling-delay = <0>;
5711
5712                         thermal-sensors = <&tsens0 11>;
5713
5714                         trips {
5715                                 cpu8_alert0: trip-point0 {
5716                                         temperature = <90000>;
5717                                         hysteresis = <2000>;
5718                                         type = "passive";
5719                                 };
5720
5721                                 cpu8_alert1: trip-point1 {
5722                                         temperature = <95000>;
5723                                         hysteresis = <2000>;
5724                                         type = "passive";
5725                                 };
5726
5727                                 cpu8_crit: cpu-crit {
5728                                         temperature = <110000>;
5729                                         hysteresis = <0>;
5730                                         type = "critical";
5731                                 };
5732                         };
5733
5734                         cooling-maps {
5735                                 map0 {
5736                                         trip = <&cpu8_alert0>;
5737                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5738                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5739                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5740                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5741                                 };
5742                                 map1 {
5743                                         trip = <&cpu8_alert1>;
5744                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5745                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5746                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5747                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5748                                 };
5749                         };
5750                 };
5751
5752                 cpu9-thermal {
5753                         polling-delay-passive = <250>;
5754                         polling-delay = <0>;
5755
5756                         thermal-sensors = <&tsens0 12>;
5757
5758                         trips {
5759                                 cpu9_alert0: trip-point0 {
5760                                         temperature = <90000>;
5761                                         hysteresis = <2000>;
5762                                         type = "passive";
5763                                 };
5764
5765                                 cpu9_alert1: trip-point1 {
5766                                         temperature = <95000>;
5767                                         hysteresis = <2000>;
5768                                         type = "passive";
5769                                 };
5770
5771                                 cpu9_crit: cpu-crit {
5772                                         temperature = <110000>;
5773                                         hysteresis = <0>;
5774                                         type = "critical";
5775                                 };
5776                         };
5777
5778                         cooling-maps {
5779                                 map0 {
5780                                         trip = <&cpu9_alert0>;
5781                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5782                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5783                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5784                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5785                                 };
5786                                 map1 {
5787                                         trip = <&cpu9_alert1>;
5788                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5789                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5790                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5791                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5792                                 };
5793                         };
5794                 };
5795
5796                 cpu10-thermal {
5797                         polling-delay-passive = <250>;
5798                         polling-delay = <0>;
5799
5800                         thermal-sensors = <&tsens0 13>;
5801
5802                         trips {
5803                                 cpu10_alert0: trip-point0 {
5804                                         temperature = <90000>;
5805                                         hysteresis = <2000>;
5806                                         type = "passive";
5807                                 };
5808
5809                                 cpu10_alert1: trip-point1 {
5810                                         temperature = <95000>;
5811                                         hysteresis = <2000>;
5812                                         type = "passive";
5813                                 };
5814
5815                                 cpu10_crit: cpu-crit {
5816                                         temperature = <110000>;
5817                                         hysteresis = <0>;
5818                                         type = "critical";
5819                                 };
5820                         };
5821
5822                         cooling-maps {
5823                                 map0 {
5824                                         trip = <&cpu10_alert0>;
5825                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5826                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5827                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5828                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5829                                 };
5830                                 map1 {
5831                                         trip = <&cpu10_alert1>;
5832                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5833                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5834                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5835                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5836                                 };
5837                         };
5838                 };
5839
5840                 cpu11-thermal {
5841                         polling-delay-passive = <250>;
5842                         polling-delay = <0>;
5843
5844                         thermal-sensors = <&tsens0 14>;
5845
5846                         trips {
5847                                 cpu11_alert0: trip-point0 {
5848                                         temperature = <90000>;
5849                                         hysteresis = <2000>;
5850                                         type = "passive";
5851                                 };
5852
5853                                 cpu11_alert1: trip-point1 {
5854                                         temperature = <95000>;
5855                                         hysteresis = <2000>;
5856                                         type = "passive";
5857                                 };
5858
5859                                 cpu11_crit: cpu-crit {
5860                                         temperature = <110000>;
5861                                         hysteresis = <0>;
5862                                         type = "critical";
5863                                 };
5864                         };
5865
5866                         cooling-maps {
5867                                 map0 {
5868                                         trip = <&cpu11_alert0>;
5869                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5870                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5871                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5872                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5873                                 };
5874                                 map1 {
5875                                         trip = <&cpu11_alert1>;
5876                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5877                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5878                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5879                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5880                                 };
5881                         };
5882                 };
5883
5884                 aoss0-thermal {
5885                         polling-delay-passive = <0>;
5886                         polling-delay = <0>;
5887
5888                         thermal-sensors = <&tsens0 0>;
5889
5890                         trips {
5891                                 aoss0_alert0: trip-point0 {
5892                                         temperature = <90000>;
5893                                         hysteresis = <2000>;
5894                                         type = "hot";
5895                                 };
5896
5897                                 aoss0_crit: aoss0-crit {
5898                                         temperature = <110000>;
5899                                         hysteresis = <0>;
5900                                         type = "critical";
5901                                 };
5902                         };
5903                 };
5904
5905                 aoss1-thermal {
5906                         polling-delay-passive = <0>;
5907                         polling-delay = <0>;
5908
5909                         thermal-sensors = <&tsens1 0>;
5910
5911                         trips {
5912                                 aoss1_alert0: trip-point0 {
5913                                         temperature = <90000>;
5914                                         hysteresis = <2000>;
5915                                         type = "hot";
5916                                 };
5917
5918                                 aoss1_crit: aoss1-crit {
5919                                         temperature = <110000>;
5920                                         hysteresis = <0>;
5921                                         type = "critical";
5922                                 };
5923                         };
5924                 };
5925
5926                 cpuss0-thermal {
5927                         polling-delay-passive = <0>;
5928                         polling-delay = <0>;
5929
5930                         thermal-sensors = <&tsens0 5>;
5931
5932                         trips {
5933                                 cpuss0_alert0: trip-point0 {
5934                                         temperature = <90000>;
5935                                         hysteresis = <2000>;
5936                                         type = "hot";
5937                                 };
5938                                 cpuss0_crit: cluster0-crit {
5939                                         temperature = <110000>;
5940                                         hysteresis = <0>;
5941                                         type = "critical";
5942                                 };
5943                         };
5944                 };
5945
5946                 cpuss1-thermal {
5947                         polling-delay-passive = <0>;
5948                         polling-delay = <0>;
5949
5950                         thermal-sensors = <&tsens0 6>;
5951
5952                         trips {
5953                                 cpuss1_alert0: trip-point0 {
5954                                         temperature = <90000>;
5955                                         hysteresis = <2000>;
5956                                         type = "hot";
5957                                 };
5958                                 cpuss1_crit: cluster0-crit {
5959                                         temperature = <110000>;
5960                                         hysteresis = <0>;
5961                                         type = "critical";
5962                                 };
5963                         };
5964                 };
5965
5966                 gpuss0-thermal {
5967                         polling-delay-passive = <100>;
5968                         polling-delay = <0>;
5969
5970                         thermal-sensors = <&tsens1 1>;
5971
5972                         trips {
5973                                 gpuss0_alert0: trip-point0 {
5974                                         temperature = <95000>;
5975                                         hysteresis = <2000>;
5976                                         type = "passive";
5977                                 };
5978
5979                                 gpuss0_crit: gpuss0-crit {
5980                                         temperature = <110000>;
5981                                         hysteresis = <0>;
5982                                         type = "critical";
5983                                 };
5984                         };
5985
5986                         cooling-maps {
5987                                 map0 {
5988                                         trip = <&gpuss0_alert0>;
5989                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5990                                 };
5991                         };
5992                 };
5993
5994                 gpuss1-thermal {
5995                         polling-delay-passive = <100>;
5996                         polling-delay = <0>;
5997
5998                         thermal-sensors = <&tsens1 2>;
5999
6000                         trips {
6001                                 gpuss1_alert0: trip-point0 {
6002                                         temperature = <95000>;
6003                                         hysteresis = <2000>;
6004                                         type = "passive";
6005                                 };
6006
6007                                 gpuss1_crit: gpuss1-crit {
6008                                         temperature = <110000>;
6009                                         hysteresis = <0>;
6010                                         type = "critical";
6011                                 };
6012                         };
6013
6014                         cooling-maps {
6015                                 map0 {
6016                                         trip = <&gpuss1_alert0>;
6017                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6018                                 };
6019                         };
6020                 };
6021
6022                 nspss0-thermal {
6023                         polling-delay-passive = <0>;
6024                         polling-delay = <0>;
6025
6026                         thermal-sensors = <&tsens1 3>;
6027
6028                         trips {
6029                                 nspss0_alert0: trip-point0 {
6030                                         temperature = <90000>;
6031                                         hysteresis = <2000>;
6032                                         type = "hot";
6033                                 };
6034
6035                                 nspss0_crit: nspss0-crit {
6036                                         temperature = <110000>;
6037                                         hysteresis = <0>;
6038                                         type = "critical";
6039                                 };
6040                         };
6041                 };
6042
6043                 nspss1-thermal {
6044                         polling-delay-passive = <0>;
6045                         polling-delay = <0>;
6046
6047                         thermal-sensors = <&tsens1 4>;
6048
6049                         trips {
6050                                 nspss1_alert0: trip-point0 {
6051                                         temperature = <90000>;
6052                                         hysteresis = <2000>;
6053                                         type = "hot";
6054                                 };
6055
6056                                 nspss1_crit: nspss1-crit {
6057                                         temperature = <110000>;
6058                                         hysteresis = <0>;
6059                                         type = "critical";
6060                                 };
6061                         };
6062                 };
6063
6064                 video-thermal {
6065                         polling-delay-passive = <0>;
6066                         polling-delay = <0>;
6067
6068                         thermal-sensors = <&tsens1 5>;
6069
6070                         trips {
6071                                 video_alert0: trip-point0 {
6072                                         temperature = <90000>;
6073                                         hysteresis = <2000>;
6074                                         type = "hot";
6075                                 };
6076
6077                                 video_crit: video-crit {
6078                                         temperature = <110000>;
6079                                         hysteresis = <0>;
6080                                         type = "critical";
6081                                 };
6082                         };
6083                 };
6084
6085                 ddr-thermal {
6086                         polling-delay-passive = <0>;
6087                         polling-delay = <0>;
6088
6089                         thermal-sensors = <&tsens1 6>;
6090
6091                         trips {
6092                                 ddr_alert0: trip-point0 {
6093                                         temperature = <90000>;
6094                                         hysteresis = <2000>;
6095                                         type = "hot";
6096                                 };
6097
6098                                 ddr_crit: ddr-crit {
6099                                         temperature = <110000>;
6100                                         hysteresis = <0>;
6101                                         type = "critical";
6102                                 };
6103                         };
6104                 };
6105
6106                 mdmss0-thermal {
6107                         polling-delay-passive = <0>;
6108                         polling-delay = <0>;
6109
6110                         thermal-sensors = <&tsens1 7>;
6111
6112                         trips {
6113                                 mdmss0_alert0: trip-point0 {
6114                                         temperature = <90000>;
6115                                         hysteresis = <2000>;
6116                                         type = "hot";
6117                                 };
6118
6119                                 mdmss0_crit: mdmss0-crit {
6120                                         temperature = <110000>;
6121                                         hysteresis = <0>;
6122                                         type = "critical";
6123                                 };
6124                         };
6125                 };
6126
6127                 mdmss1-thermal {
6128                         polling-delay-passive = <0>;
6129                         polling-delay = <0>;
6130
6131                         thermal-sensors = <&tsens1 8>;
6132
6133                         trips {
6134                                 mdmss1_alert0: trip-point0 {
6135                                         temperature = <90000>;
6136                                         hysteresis = <2000>;
6137                                         type = "hot";
6138                                 };
6139
6140                                 mdmss1_crit: mdmss1-crit {
6141                                         temperature = <110000>;
6142                                         hysteresis = <0>;
6143                                         type = "critical";
6144                                 };
6145                         };
6146                 };
6147
6148                 mdmss2-thermal {
6149                         polling-delay-passive = <0>;
6150                         polling-delay = <0>;
6151
6152                         thermal-sensors = <&tsens1 9>;
6153
6154                         trips {
6155                                 mdmss2_alert0: trip-point0 {
6156                                         temperature = <90000>;
6157                                         hysteresis = <2000>;
6158                                         type = "hot";
6159                                 };
6160
6161                                 mdmss2_crit: mdmss2-crit {
6162                                         temperature = <110000>;
6163                                         hysteresis = <0>;
6164                                         type = "critical";
6165                                 };
6166                         };
6167                 };
6168
6169                 mdmss3-thermal {
6170                         polling-delay-passive = <0>;
6171                         polling-delay = <0>;
6172
6173                         thermal-sensors = <&tsens1 10>;
6174
6175                         trips {
6176                                 mdmss3_alert0: trip-point0 {
6177                                         temperature = <90000>;
6178                                         hysteresis = <2000>;
6179                                         type = "hot";
6180                                 };
6181
6182                                 mdmss3_crit: mdmss3-crit {
6183                                         temperature = <110000>;
6184                                         hysteresis = <0>;
6185                                         type = "critical";
6186                                 };
6187                         };
6188                 };
6189
6190                 camera0-thermal {
6191                         polling-delay-passive = <0>;
6192                         polling-delay = <0>;
6193
6194                         thermal-sensors = <&tsens1 11>;
6195
6196                         trips {
6197                                 camera0_alert0: trip-point0 {
6198                                         temperature = <90000>;
6199                                         hysteresis = <2000>;
6200                                         type = "hot";
6201                                 };
6202
6203                                 camera0_crit: camera0-crit {
6204                                         temperature = <110000>;
6205                                         hysteresis = <0>;
6206                                         type = "critical";
6207                                 };
6208                         };
6209                 };
6210         };
6211
6212         timer {
6213                 compatible = "arm,armv8-timer";
6214                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6215                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6216                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6217                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
6218         };
6219 };