1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 SoC device tree source
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7280.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 #include <dt-bindings/sound/qcom,lpass.h>
26 #include <dt-bindings/thermal/thermal.h>
29 interrupt-parent = <&intc>;
75 compatible = "fixed-clock";
76 clock-frequency = <76800000>;
80 sleep_clk: sleep-clk {
81 compatible = "fixed-clock";
82 clock-frequency = <32000>;
92 wlan_ce_mem: memory@4cd000 {
94 reg = <0x0 0x004cd000 0x0 0x1000>;
97 hyp_mem: memory@80000000 {
98 reg = <0x0 0x80000000 0x0 0x600000>;
102 xbl_mem: memory@80600000 {
103 reg = <0x0 0x80600000 0x0 0x200000>;
107 aop_mem: memory@80800000 {
108 reg = <0x0 0x80800000 0x0 0x60000>;
112 aop_cmd_db_mem: memory@80860000 {
113 reg = <0x0 0x80860000 0x0 0x20000>;
114 compatible = "qcom,cmd-db";
118 reserved_xbl_uefi_log: memory@80880000 {
119 reg = <0x0 0x80884000 0x0 0x10000>;
123 sec_apps_mem: memory@808ff000 {
124 reg = <0x0 0x808ff000 0x0 0x1000>;
128 smem_mem: memory@80900000 {
129 reg = <0x0 0x80900000 0x0 0x200000>;
133 cpucp_mem: memory@80b00000 {
135 reg = <0x0 0x80b00000 0x0 0x100000>;
138 wlan_fw_mem: memory@80c00000 {
139 reg = <0x0 0x80c00000 0x0 0xc00000>;
143 video_mem: memory@8b200000 {
144 reg = <0x0 0x8b200000 0x0 0x500000>;
148 ipa_fw_mem: memory@8b700000 {
149 reg = <0 0x8b700000 0 0x10000>;
153 rmtfs_mem: memory@9c900000 {
154 compatible = "qcom,rmtfs-mem";
155 reg = <0x0 0x9c900000 0x0 0x280000>;
158 qcom,client-id = <1>;
164 #address-cells = <2>;
169 compatible = "arm,kryo";
171 enable-method = "psci";
172 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
175 next-level-cache = <&L2_0>;
176 operating-points-v2 = <&cpu0_opp_table>;
177 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
178 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
179 qcom,freq-domain = <&cpufreq_hw 0>;
180 #cooling-cells = <2>;
182 compatible = "cache";
183 next-level-cache = <&L3_0>;
185 compatible = "cache";
192 compatible = "arm,kryo";
194 enable-method = "psci";
195 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
198 next-level-cache = <&L2_100>;
199 operating-points-v2 = <&cpu0_opp_table>;
200 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
201 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
202 qcom,freq-domain = <&cpufreq_hw 0>;
203 #cooling-cells = <2>;
205 compatible = "cache";
206 next-level-cache = <&L3_0>;
212 compatible = "arm,kryo";
214 enable-method = "psci";
215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
218 next-level-cache = <&L2_200>;
219 operating-points-v2 = <&cpu0_opp_table>;
220 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
221 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
222 qcom,freq-domain = <&cpufreq_hw 0>;
223 #cooling-cells = <2>;
225 compatible = "cache";
226 next-level-cache = <&L3_0>;
232 compatible = "arm,kryo";
234 enable-method = "psci";
235 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
238 next-level-cache = <&L2_300>;
239 operating-points-v2 = <&cpu0_opp_table>;
240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
242 qcom,freq-domain = <&cpufreq_hw 0>;
243 #cooling-cells = <2>;
245 compatible = "cache";
246 next-level-cache = <&L3_0>;
252 compatible = "arm,kryo";
254 enable-method = "psci";
255 cpu-idle-states = <&BIG_CPU_SLEEP_0
258 next-level-cache = <&L2_400>;
259 operating-points-v2 = <&cpu4_opp_table>;
260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
262 qcom,freq-domain = <&cpufreq_hw 1>;
263 #cooling-cells = <2>;
265 compatible = "cache";
266 next-level-cache = <&L3_0>;
272 compatible = "arm,kryo";
274 enable-method = "psci";
275 cpu-idle-states = <&BIG_CPU_SLEEP_0
278 next-level-cache = <&L2_500>;
279 operating-points-v2 = <&cpu4_opp_table>;
280 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
281 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
283 #cooling-cells = <2>;
285 compatible = "cache";
286 next-level-cache = <&L3_0>;
292 compatible = "arm,kryo";
294 enable-method = "psci";
295 cpu-idle-states = <&BIG_CPU_SLEEP_0
298 next-level-cache = <&L2_600>;
299 operating-points-v2 = <&cpu4_opp_table>;
300 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
301 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
302 qcom,freq-domain = <&cpufreq_hw 1>;
303 #cooling-cells = <2>;
305 compatible = "cache";
306 next-level-cache = <&L3_0>;
312 compatible = "arm,kryo";
314 enable-method = "psci";
315 cpu-idle-states = <&BIG_CPU_SLEEP_0
318 next-level-cache = <&L2_700>;
319 operating-points-v2 = <&cpu7_opp_table>;
320 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
321 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
322 qcom,freq-domain = <&cpufreq_hw 2>;
323 #cooling-cells = <2>;
325 compatible = "cache";
326 next-level-cache = <&L3_0>;
367 entry-method = "psci";
369 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
370 compatible = "arm,idle-state";
371 idle-state-name = "little-power-down";
372 arm,psci-suspend-param = <0x40000003>;
373 entry-latency-us = <549>;
374 exit-latency-us = <901>;
375 min-residency-us = <1774>;
379 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
380 compatible = "arm,idle-state";
381 idle-state-name = "little-rail-power-down";
382 arm,psci-suspend-param = <0x40000004>;
383 entry-latency-us = <702>;
384 exit-latency-us = <915>;
385 min-residency-us = <4001>;
389 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
390 compatible = "arm,idle-state";
391 idle-state-name = "big-power-down";
392 arm,psci-suspend-param = <0x40000003>;
393 entry-latency-us = <523>;
394 exit-latency-us = <1244>;
395 min-residency-us = <2207>;
399 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
400 compatible = "arm,idle-state";
401 idle-state-name = "big-rail-power-down";
402 arm,psci-suspend-param = <0x40000004>;
403 entry-latency-us = <526>;
404 exit-latency-us = <1854>;
405 min-residency-us = <5555>;
409 CLUSTER_SLEEP_0: cluster-sleep-0 {
410 compatible = "arm,idle-state";
411 idle-state-name = "cluster-power-down";
412 arm,psci-suspend-param = <0x40003444>;
413 entry-latency-us = <3263>;
414 exit-latency-us = <6562>;
415 min-residency-us = <9926>;
421 cpu0_opp_table: opp-table-cpu0 {
422 compatible = "operating-points-v2";
425 cpu0_opp_300mhz: opp-300000000 {
426 opp-hz = /bits/ 64 <300000000>;
427 opp-peak-kBps = <800000 9600000>;
430 cpu0_opp_691mhz: opp-691200000 {
431 opp-hz = /bits/ 64 <691200000>;
432 opp-peak-kBps = <800000 17817600>;
435 cpu0_opp_806mhz: opp-806400000 {
436 opp-hz = /bits/ 64 <806400000>;
437 opp-peak-kBps = <800000 20889600>;
440 cpu0_opp_941mhz: opp-940800000 {
441 opp-hz = /bits/ 64 <940800000>;
442 opp-peak-kBps = <1804000 24576000>;
445 cpu0_opp_1152mhz: opp-1152000000 {
446 opp-hz = /bits/ 64 <1152000000>;
447 opp-peak-kBps = <2188000 27033600>;
450 cpu0_opp_1325mhz: opp-1324800000 {
451 opp-hz = /bits/ 64 <1324800000>;
452 opp-peak-kBps = <2188000 33792000>;
455 cpu0_opp_1517mhz: opp-1516800000 {
456 opp-hz = /bits/ 64 <1516800000>;
457 opp-peak-kBps = <3072000 38092800>;
460 cpu0_opp_1651mhz: opp-1651200000 {
461 opp-hz = /bits/ 64 <1651200000>;
462 opp-peak-kBps = <3072000 41779200>;
465 cpu0_opp_1805mhz: opp-1804800000 {
466 opp-hz = /bits/ 64 <1804800000>;
467 opp-peak-kBps = <4068000 48537600>;
470 cpu0_opp_1958mhz: opp-1958400000 {
471 opp-hz = /bits/ 64 <1958400000>;
472 opp-peak-kBps = <4068000 48537600>;
475 cpu0_opp_2016mhz: opp-2016000000 {
476 opp-hz = /bits/ 64 <2016000000>;
477 opp-peak-kBps = <6220000 48537600>;
481 cpu4_opp_table: opp-table-cpu4 {
482 compatible = "operating-points-v2";
485 cpu4_opp_691mhz: opp-691200000 {
486 opp-hz = /bits/ 64 <691200000>;
487 opp-peak-kBps = <1804000 9600000>;
490 cpu4_opp_941mhz: opp-940800000 {
491 opp-hz = /bits/ 64 <940800000>;
492 opp-peak-kBps = <2188000 17817600>;
495 cpu4_opp_1229mhz: opp-1228800000 {
496 opp-hz = /bits/ 64 <1228800000>;
497 opp-peak-kBps = <4068000 24576000>;
500 cpu4_opp_1344mhz: opp-1344000000 {
501 opp-hz = /bits/ 64 <1344000000>;
502 opp-peak-kBps = <4068000 24576000>;
505 cpu4_opp_1517mhz: opp-1516800000 {
506 opp-hz = /bits/ 64 <1516800000>;
507 opp-peak-kBps = <4068000 24576000>;
510 cpu4_opp_1651mhz: opp-1651200000 {
511 opp-hz = /bits/ 64 <1651200000>;
512 opp-peak-kBps = <6220000 38092800>;
515 cpu4_opp_1901mhz: opp-1900800000 {
516 opp-hz = /bits/ 64 <1900800000>;
517 opp-peak-kBps = <6220000 44851200>;
520 cpu4_opp_2054mhz: opp-2054400000 {
521 opp-hz = /bits/ 64 <2054400000>;
522 opp-peak-kBps = <6220000 44851200>;
525 cpu4_opp_2112mhz: opp-2112000000 {
526 opp-hz = /bits/ 64 <2112000000>;
527 opp-peak-kBps = <6220000 44851200>;
530 cpu4_opp_2131mhz: opp-2131200000 {
531 opp-hz = /bits/ 64 <2131200000>;
532 opp-peak-kBps = <6220000 44851200>;
535 cpu4_opp_2208mhz: opp-2208000000 {
536 opp-hz = /bits/ 64 <2208000000>;
537 opp-peak-kBps = <6220000 44851200>;
540 cpu4_opp_2400mhz: opp-2400000000 {
541 opp-hz = /bits/ 64 <2400000000>;
542 opp-peak-kBps = <8532000 48537600>;
545 cpu4_opp_2611mhz: opp-2611200000 {
546 opp-hz = /bits/ 64 <2611200000>;
547 opp-peak-kBps = <8532000 48537600>;
551 cpu7_opp_table: opp-table-cpu7 {
552 compatible = "operating-points-v2";
555 cpu7_opp_806mhz: opp-806400000 {
556 opp-hz = /bits/ 64 <806400000>;
557 opp-peak-kBps = <1804000 9600000>;
560 cpu7_opp_1056mhz: opp-1056000000 {
561 opp-hz = /bits/ 64 <1056000000>;
562 opp-peak-kBps = <2188000 17817600>;
565 cpu7_opp_1325mhz: opp-1324800000 {
566 opp-hz = /bits/ 64 <1324800000>;
567 opp-peak-kBps = <4068000 24576000>;
570 cpu7_opp_1517mhz: opp-1516800000 {
571 opp-hz = /bits/ 64 <1516800000>;
572 opp-peak-kBps = <4068000 24576000>;
575 cpu7_opp_1766mhz: opp-1766400000 {
576 opp-hz = /bits/ 64 <1766400000>;
577 opp-peak-kBps = <6220000 38092800>;
580 cpu7_opp_1862mhz: opp-1862400000 {
581 opp-hz = /bits/ 64 <1862400000>;
582 opp-peak-kBps = <6220000 38092800>;
585 cpu7_opp_2035mhz: opp-2035200000 {
586 opp-hz = /bits/ 64 <2035200000>;
587 opp-peak-kBps = <6220000 38092800>;
590 cpu7_opp_2112mhz: opp-2112000000 {
591 opp-hz = /bits/ 64 <2112000000>;
592 opp-peak-kBps = <6220000 44851200>;
595 cpu7_opp_2208mhz: opp-2208000000 {
596 opp-hz = /bits/ 64 <2208000000>;
597 opp-peak-kBps = <6220000 44851200>;
600 cpu7_opp_2381mhz: opp-2380800000 {
601 opp-hz = /bits/ 64 <2380800000>;
602 opp-peak-kBps = <6832000 44851200>;
605 cpu7_opp_2400mhz: opp-2400000000 {
606 opp-hz = /bits/ 64 <2400000000>;
607 opp-peak-kBps = <8532000 48537600>;
610 cpu7_opp_2515mhz: opp-2515200000 {
611 opp-hz = /bits/ 64 <2515200000>;
612 opp-peak-kBps = <8532000 48537600>;
615 cpu7_opp_2707mhz: opp-2707200000 {
616 opp-hz = /bits/ 64 <2707200000>;
617 opp-peak-kBps = <8532000 48537600>;
620 cpu7_opp_3014mhz: opp-3014400000 {
621 opp-hz = /bits/ 64 <3014400000>;
622 opp-peak-kBps = <8532000 48537600>;
627 device_type = "memory";
628 /* We expect the bootloader to fill in the size */
629 reg = <0 0x80000000 0 0>;
634 compatible = "qcom,scm-sc7280", "qcom,scm";
638 clk_virt: interconnect {
639 compatible = "qcom,sc7280-clk-virt";
640 #interconnect-cells = <2>;
641 qcom,bcm-voters = <&apps_bcm_voter>;
645 compatible = "qcom,smem";
646 memory-region = <&smem_mem>;
647 hwlocks = <&tcsr_mutex 3>;
651 compatible = "qcom,smp2p";
652 qcom,smem = <443>, <429>;
653 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
654 IPCC_MPROC_SIGNAL_SMP2P
655 IRQ_TYPE_EDGE_RISING>;
656 mboxes = <&ipcc IPCC_CLIENT_LPASS
657 IPCC_MPROC_SIGNAL_SMP2P>;
659 qcom,local-pid = <0>;
660 qcom,remote-pid = <2>;
662 adsp_smp2p_out: master-kernel {
663 qcom,entry-name = "master-kernel";
664 #qcom,smem-state-cells = <1>;
667 adsp_smp2p_in: slave-kernel {
668 qcom,entry-name = "slave-kernel";
669 interrupt-controller;
670 #interrupt-cells = <2>;
675 compatible = "qcom,smp2p";
676 qcom,smem = <94>, <432>;
677 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
678 IPCC_MPROC_SIGNAL_SMP2P
679 IRQ_TYPE_EDGE_RISING>;
680 mboxes = <&ipcc IPCC_CLIENT_CDSP
681 IPCC_MPROC_SIGNAL_SMP2P>;
683 qcom,local-pid = <0>;
684 qcom,remote-pid = <5>;
686 cdsp_smp2p_out: master-kernel {
687 qcom,entry-name = "master-kernel";
688 #qcom,smem-state-cells = <1>;
691 cdsp_smp2p_in: slave-kernel {
692 qcom,entry-name = "slave-kernel";
693 interrupt-controller;
694 #interrupt-cells = <2>;
699 compatible = "qcom,smp2p";
700 qcom,smem = <435>, <428>;
701 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
702 IPCC_MPROC_SIGNAL_SMP2P
703 IRQ_TYPE_EDGE_RISING>;
704 mboxes = <&ipcc IPCC_CLIENT_MPSS
705 IPCC_MPROC_SIGNAL_SMP2P>;
707 qcom,local-pid = <0>;
708 qcom,remote-pid = <1>;
710 modem_smp2p_out: master-kernel {
711 qcom,entry-name = "master-kernel";
712 #qcom,smem-state-cells = <1>;
715 modem_smp2p_in: slave-kernel {
716 qcom,entry-name = "slave-kernel";
717 interrupt-controller;
718 #interrupt-cells = <2>;
721 ipa_smp2p_out: ipa-ap-to-modem {
722 qcom,entry-name = "ipa";
723 #qcom,smem-state-cells = <1>;
726 ipa_smp2p_in: ipa-modem-to-ap {
727 qcom,entry-name = "ipa";
728 interrupt-controller;
729 #interrupt-cells = <2>;
734 compatible = "qcom,smp2p";
735 qcom,smem = <617>, <616>;
736 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
737 IPCC_MPROC_SIGNAL_SMP2P
738 IRQ_TYPE_EDGE_RISING>;
739 mboxes = <&ipcc IPCC_CLIENT_WPSS
740 IPCC_MPROC_SIGNAL_SMP2P>;
742 qcom,local-pid = <0>;
743 qcom,remote-pid = <13>;
745 wpss_smp2p_out: master-kernel {
746 qcom,entry-name = "master-kernel";
747 #qcom,smem-state-cells = <1>;
750 wpss_smp2p_in: slave-kernel {
751 qcom,entry-name = "slave-kernel";
752 interrupt-controller;
753 #interrupt-cells = <2>;
758 compatible = "arm,armv8-pmuv3";
759 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
763 compatible = "arm,psci-1.0";
767 qspi_opp_table: opp-table-qspi {
768 compatible = "operating-points-v2";
771 opp-hz = /bits/ 64 <75000000>;
772 required-opps = <&rpmhpd_opp_low_svs>;
776 opp-hz = /bits/ 64 <150000000>;
777 required-opps = <&rpmhpd_opp_svs>;
781 opp-hz = /bits/ 64 <200000000>;
782 required-opps = <&rpmhpd_opp_svs_l1>;
786 opp-hz = /bits/ 64 <300000000>;
787 required-opps = <&rpmhpd_opp_nom>;
791 qup_opp_table: opp-table-qup {
792 compatible = "operating-points-v2";
795 opp-hz = /bits/ 64 <75000000>;
796 required-opps = <&rpmhpd_opp_low_svs>;
800 opp-hz = /bits/ 64 <100000000>;
801 required-opps = <&rpmhpd_opp_svs>;
805 opp-hz = /bits/ 64 <128000000>;
806 required-opps = <&rpmhpd_opp_nom>;
811 #address-cells = <2>;
813 ranges = <0 0 0 0 0x10 0>;
814 dma-ranges = <0 0 0 0 0x10 0>;
815 compatible = "simple-bus";
817 gcc: clock-controller@100000 {
818 compatible = "qcom,gcc-sc7280";
819 reg = <0 0x00100000 0 0x1f0000>;
820 clocks = <&rpmhcc RPMH_CXO_CLK>,
821 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
825 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
826 "pcie_0_pipe_clk", "pcie_1_pipe_clk",
827 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
828 "ufs_phy_tx_symbol_0_clk",
829 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
832 #power-domain-cells = <1>;
833 power-domains = <&rpmhpd SC7280_CX>;
836 ipcc: mailbox@408000 {
837 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
838 reg = <0 0x00408000 0 0x1000>;
839 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
840 interrupt-controller;
841 #interrupt-cells = <3>;
845 qfprom: efuse@784000 {
846 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
847 reg = <0 0x00784000 0 0xa20>,
848 <0 0x00780000 0 0xa20>,
849 <0 0x00782000 0 0x120>,
850 <0 0x00786000 0 0x1fff>;
851 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
852 clock-names = "core";
853 power-domains = <&rpmhpd SC7280_MX>;
854 #address-cells = <1>;
857 gpu_speed_bin: gpu_speed_bin@1e9 {
864 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
865 pinctrl-names = "default", "sleep";
866 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
867 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
870 reg = <0 0x007c4000 0 0x1000>,
871 <0 0x007c5000 0 0x1000>;
872 reg-names = "hc", "cqhci";
874 iommus = <&apps_smmu 0xc0 0x0>;
875 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
877 interrupt-names = "hc_irq", "pwr_irq";
879 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
880 <&gcc GCC_SDCC1_APPS_CLK>,
881 <&rpmhcc RPMH_CXO_CLK>;
882 clock-names = "iface", "core", "xo";
883 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
884 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
885 interconnect-names = "sdhc-ddr","cpu-sdhc";
886 power-domains = <&rpmhpd SC7280_CX>;
887 operating-points-v2 = <&sdhc1_opp_table>;
892 qcom,dll-config = <0x0007642c>;
893 qcom,ddr-config = <0x80040868>;
898 mmc-hs400-enhanced-strobe;
900 resets = <&gcc GCC_SDCC1_BCR>;
902 sdhc1_opp_table: opp-table {
903 compatible = "operating-points-v2";
906 opp-hz = /bits/ 64 <100000000>;
907 required-opps = <&rpmhpd_opp_low_svs>;
908 opp-peak-kBps = <1800000 400000>;
909 opp-avg-kBps = <100000 0>;
913 opp-hz = /bits/ 64 <384000000>;
914 required-opps = <&rpmhpd_opp_nom>;
915 opp-peak-kBps = <5400000 1600000>;
916 opp-avg-kBps = <390000 0>;
922 gpi_dma0: dma-controller@900000 {
924 compatible = "qcom,sc7280-gpi-dma";
925 reg = <0 0x00900000 0 0x60000>;
926 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
939 dma-channel-mask = <0x7f>;
940 iommus = <&apps_smmu 0x0136 0x0>;
944 qupv3_id_0: geniqup@9c0000 {
945 compatible = "qcom,geni-se-qup";
946 reg = <0 0x009c0000 0 0x2000>;
947 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
948 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
949 clock-names = "m-ahb", "s-ahb";
950 #address-cells = <2>;
953 iommus = <&apps_smmu 0x123 0x0>;
957 compatible = "qcom,geni-i2c";
958 reg = <0 0x00980000 0 0x4000>;
959 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
961 pinctrl-names = "default";
962 pinctrl-0 = <&qup_i2c0_data_clk>;
963 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
964 #address-cells = <1>;
966 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
967 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
968 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
969 interconnect-names = "qup-core", "qup-config",
971 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
972 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
973 dma-names = "tx", "rx";
978 compatible = "qcom,geni-spi";
979 reg = <0 0x00980000 0 0x4000>;
980 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
984 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
985 #address-cells = <1>;
987 power-domains = <&rpmhpd SC7280_CX>;
988 operating-points-v2 = <&qup_opp_table>;
989 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
990 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
991 interconnect-names = "qup-core", "qup-config";
992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
993 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
994 dma-names = "tx", "rx";
998 uart0: serial@980000 {
999 compatible = "qcom,geni-uart";
1000 reg = <0 0x00980000 0 0x4000>;
1001 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1003 pinctrl-names = "default";
1004 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1005 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1006 power-domains = <&rpmhpd SC7280_CX>;
1007 operating-points-v2 = <&qup_opp_table>;
1008 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1009 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1010 interconnect-names = "qup-core", "qup-config";
1011 status = "disabled";
1015 compatible = "qcom,geni-i2c";
1016 reg = <0 0x00984000 0 0x4000>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1019 pinctrl-names = "default";
1020 pinctrl-0 = <&qup_i2c1_data_clk>;
1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1022 #address-cells = <1>;
1024 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1025 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1026 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1027 interconnect-names = "qup-core", "qup-config",
1029 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1030 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1031 dma-names = "tx", "rx";
1032 status = "disabled";
1036 compatible = "qcom,geni-spi";
1037 reg = <0 0x00984000 0 0x4000>;
1038 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1042 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1043 #address-cells = <1>;
1045 power-domains = <&rpmhpd SC7280_CX>;
1046 operating-points-v2 = <&qup_opp_table>;
1047 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1048 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1049 interconnect-names = "qup-core", "qup-config";
1050 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1051 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1052 dma-names = "tx", "rx";
1053 status = "disabled";
1056 uart1: serial@984000 {
1057 compatible = "qcom,geni-uart";
1058 reg = <0 0x00984000 0 0x4000>;
1059 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1061 pinctrl-names = "default";
1062 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1063 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1064 power-domains = <&rpmhpd SC7280_CX>;
1065 operating-points-v2 = <&qup_opp_table>;
1066 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1067 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1068 interconnect-names = "qup-core", "qup-config";
1069 status = "disabled";
1073 compatible = "qcom,geni-i2c";
1074 reg = <0 0x00988000 0 0x4000>;
1075 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_i2c2_data_clk>;
1079 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cells = <1>;
1082 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1083 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1084 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1085 interconnect-names = "qup-core", "qup-config",
1087 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1088 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1089 dma-names = "tx", "rx";
1090 status = "disabled";
1094 compatible = "qcom,geni-spi";
1095 reg = <0 0x00988000 0 0x4000>;
1096 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1100 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1101 #address-cells = <1>;
1103 power-domains = <&rpmhpd SC7280_CX>;
1104 operating-points-v2 = <&qup_opp_table>;
1105 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1106 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1107 interconnect-names = "qup-core", "qup-config";
1108 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1109 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1110 dma-names = "tx", "rx";
1111 status = "disabled";
1114 uart2: serial@988000 {
1115 compatible = "qcom,geni-uart";
1116 reg = <0 0x00988000 0 0x4000>;
1117 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1121 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1122 power-domains = <&rpmhpd SC7280_CX>;
1123 operating-points-v2 = <&qup_opp_table>;
1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1125 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1126 interconnect-names = "qup-core", "qup-config";
1127 status = "disabled";
1131 compatible = "qcom,geni-i2c";
1132 reg = <0 0x0098c000 0 0x4000>;
1133 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&qup_i2c3_data_clk>;
1137 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1138 #address-cells = <1>;
1140 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1142 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1143 interconnect-names = "qup-core", "qup-config",
1145 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1146 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1147 dma-names = "tx", "rx";
1148 status = "disabled";
1152 compatible = "qcom,geni-spi";
1153 reg = <0 0x0098c000 0 0x4000>;
1154 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1156 pinctrl-names = "default";
1157 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1158 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1159 #address-cells = <1>;
1161 power-domains = <&rpmhpd SC7280_CX>;
1162 operating-points-v2 = <&qup_opp_table>;
1163 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1164 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1165 interconnect-names = "qup-core", "qup-config";
1166 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1167 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1168 dma-names = "tx", "rx";
1169 status = "disabled";
1172 uart3: serial@98c000 {
1173 compatible = "qcom,geni-uart";
1174 reg = <0 0x0098c000 0 0x4000>;
1175 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1177 pinctrl-names = "default";
1178 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1179 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1180 power-domains = <&rpmhpd SC7280_CX>;
1181 operating-points-v2 = <&qup_opp_table>;
1182 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1183 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1184 interconnect-names = "qup-core", "qup-config";
1185 status = "disabled";
1189 compatible = "qcom,geni-i2c";
1190 reg = <0 0x00990000 0 0x4000>;
1191 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1193 pinctrl-names = "default";
1194 pinctrl-0 = <&qup_i2c4_data_clk>;
1195 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1196 #address-cells = <1>;
1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1199 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1200 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1201 interconnect-names = "qup-core", "qup-config",
1203 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1204 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1205 dma-names = "tx", "rx";
1206 status = "disabled";
1210 compatible = "qcom,geni-spi";
1211 reg = <0 0x00990000 0 0x4000>;
1212 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1216 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1217 #address-cells = <1>;
1219 power-domains = <&rpmhpd SC7280_CX>;
1220 operating-points-v2 = <&qup_opp_table>;
1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1223 interconnect-names = "qup-core", "qup-config";
1224 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1225 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1226 dma-names = "tx", "rx";
1227 status = "disabled";
1230 uart4: serial@990000 {
1231 compatible = "qcom,geni-uart";
1232 reg = <0 0x00990000 0 0x4000>;
1233 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1235 pinctrl-names = "default";
1236 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1237 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1238 power-domains = <&rpmhpd SC7280_CX>;
1239 operating-points-v2 = <&qup_opp_table>;
1240 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1241 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1242 interconnect-names = "qup-core", "qup-config";
1243 status = "disabled";
1247 compatible = "qcom,geni-i2c";
1248 reg = <0 0x00994000 0 0x4000>;
1249 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1251 pinctrl-names = "default";
1252 pinctrl-0 = <&qup_i2c5_data_clk>;
1253 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1254 #address-cells = <1>;
1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1257 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1258 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1259 interconnect-names = "qup-core", "qup-config",
1261 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1262 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1263 dma-names = "tx", "rx";
1264 status = "disabled";
1268 compatible = "qcom,geni-spi";
1269 reg = <0 0x00994000 0 0x4000>;
1270 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1274 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1275 #address-cells = <1>;
1277 power-domains = <&rpmhpd SC7280_CX>;
1278 operating-points-v2 = <&qup_opp_table>;
1279 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1280 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1281 interconnect-names = "qup-core", "qup-config";
1282 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1283 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1284 dma-names = "tx", "rx";
1285 status = "disabled";
1288 uart5: serial@994000 {
1289 compatible = "qcom,geni-uart";
1290 reg = <0 0x00994000 0 0x4000>;
1291 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1293 pinctrl-names = "default";
1294 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1295 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1296 power-domains = <&rpmhpd SC7280_CX>;
1297 operating-points-v2 = <&qup_opp_table>;
1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1299 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1300 interconnect-names = "qup-core", "qup-config";
1301 status = "disabled";
1305 compatible = "qcom,geni-i2c";
1306 reg = <0 0x00998000 0 0x4000>;
1307 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1309 pinctrl-names = "default";
1310 pinctrl-0 = <&qup_i2c6_data_clk>;
1311 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1312 #address-cells = <1>;
1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1315 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1316 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1317 interconnect-names = "qup-core", "qup-config",
1319 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1320 <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1321 dma-names = "tx", "rx";
1322 status = "disabled";
1326 compatible = "qcom,geni-spi";
1327 reg = <0 0x00998000 0 0x4000>;
1328 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1330 pinctrl-names = "default";
1331 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1332 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1333 #address-cells = <1>;
1335 power-domains = <&rpmhpd SC7280_CX>;
1336 operating-points-v2 = <&qup_opp_table>;
1337 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1338 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1339 interconnect-names = "qup-core", "qup-config";
1340 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1341 <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1342 dma-names = "tx", "rx";
1343 status = "disabled";
1346 uart6: serial@998000 {
1347 compatible = "qcom,geni-uart";
1348 reg = <0 0x00998000 0 0x4000>;
1349 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1351 pinctrl-names = "default";
1352 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1353 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1354 power-domains = <&rpmhpd SC7280_CX>;
1355 operating-points-v2 = <&qup_opp_table>;
1356 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1357 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1358 interconnect-names = "qup-core", "qup-config";
1359 status = "disabled";
1363 compatible = "qcom,geni-i2c";
1364 reg = <0 0x0099c000 0 0x4000>;
1365 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1367 pinctrl-names = "default";
1368 pinctrl-0 = <&qup_i2c7_data_clk>;
1369 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1370 #address-cells = <1>;
1372 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1373 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1374 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1375 interconnect-names = "qup-core", "qup-config",
1377 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1378 <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1379 dma-names = "tx", "rx";
1380 status = "disabled";
1384 compatible = "qcom,geni-spi";
1385 reg = <0 0x0099c000 0 0x4000>;
1386 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1388 pinctrl-names = "default";
1389 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1390 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1391 #address-cells = <1>;
1393 power-domains = <&rpmhpd SC7280_CX>;
1394 operating-points-v2 = <&qup_opp_table>;
1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1397 interconnect-names = "qup-core", "qup-config";
1398 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1399 <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1400 dma-names = "tx", "rx";
1401 status = "disabled";
1404 uart7: serial@99c000 {
1405 compatible = "qcom,geni-uart";
1406 reg = <0 0x0099c000 0 0x4000>;
1407 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1409 pinctrl-names = "default";
1410 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1411 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1412 power-domains = <&rpmhpd SC7280_CX>;
1413 operating-points-v2 = <&qup_opp_table>;
1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1415 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1416 interconnect-names = "qup-core", "qup-config";
1417 status = "disabled";
1421 gpi_dma1: dma-controller@a00000 {
1423 compatible = "qcom,sc7280-gpi-dma";
1424 reg = <0 0x00a00000 0 0x60000>;
1425 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1429 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1432 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1433 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1434 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1435 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1436 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1437 dma-channels = <12>;
1438 dma-channel-mask = <0x1e>;
1439 iommus = <&apps_smmu 0x56 0x0>;
1440 status = "disabled";
1443 qupv3_id_1: geniqup@ac0000 {
1444 compatible = "qcom,geni-se-qup";
1445 reg = <0 0x00ac0000 0 0x2000>;
1446 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1447 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1448 clock-names = "m-ahb", "s-ahb";
1449 #address-cells = <2>;
1452 iommus = <&apps_smmu 0x43 0x0>;
1453 status = "disabled";
1456 compatible = "qcom,geni-i2c";
1457 reg = <0 0x00a80000 0 0x4000>;
1458 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1460 pinctrl-names = "default";
1461 pinctrl-0 = <&qup_i2c8_data_clk>;
1462 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1463 #address-cells = <1>;
1465 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1466 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1467 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1468 interconnect-names = "qup-core", "qup-config",
1470 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1471 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1472 dma-names = "tx", "rx";
1473 status = "disabled";
1477 compatible = "qcom,geni-spi";
1478 reg = <0 0x00a80000 0 0x4000>;
1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1481 pinctrl-names = "default";
1482 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1483 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1484 #address-cells = <1>;
1486 power-domains = <&rpmhpd SC7280_CX>;
1487 operating-points-v2 = <&qup_opp_table>;
1488 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1489 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1490 interconnect-names = "qup-core", "qup-config";
1491 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1492 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1493 dma-names = "tx", "rx";
1494 status = "disabled";
1497 uart8: serial@a80000 {
1498 compatible = "qcom,geni-uart";
1499 reg = <0 0x00a80000 0 0x4000>;
1500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1502 pinctrl-names = "default";
1503 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1504 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1505 power-domains = <&rpmhpd SC7280_CX>;
1506 operating-points-v2 = <&qup_opp_table>;
1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1508 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1509 interconnect-names = "qup-core", "qup-config";
1510 status = "disabled";
1514 compatible = "qcom,geni-i2c";
1515 reg = <0 0x00a84000 0 0x4000>;
1516 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1518 pinctrl-names = "default";
1519 pinctrl-0 = <&qup_i2c9_data_clk>;
1520 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1521 #address-cells = <1>;
1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1524 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1525 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1526 interconnect-names = "qup-core", "qup-config",
1528 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1529 <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1530 dma-names = "tx", "rx";
1531 status = "disabled";
1535 compatible = "qcom,geni-spi";
1536 reg = <0 0x00a84000 0 0x4000>;
1537 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1541 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1542 #address-cells = <1>;
1544 power-domains = <&rpmhpd SC7280_CX>;
1545 operating-points-v2 = <&qup_opp_table>;
1546 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1547 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1548 interconnect-names = "qup-core", "qup-config";
1549 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1550 <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1551 dma-names = "tx", "rx";
1552 status = "disabled";
1555 uart9: serial@a84000 {
1556 compatible = "qcom,geni-uart";
1557 reg = <0 0x00a84000 0 0x4000>;
1558 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1562 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1563 power-domains = <&rpmhpd SC7280_CX>;
1564 operating-points-v2 = <&qup_opp_table>;
1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1566 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1567 interconnect-names = "qup-core", "qup-config";
1568 status = "disabled";
1572 compatible = "qcom,geni-i2c";
1573 reg = <0 0x00a88000 0 0x4000>;
1574 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1576 pinctrl-names = "default";
1577 pinctrl-0 = <&qup_i2c10_data_clk>;
1578 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1579 #address-cells = <1>;
1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1582 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1583 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1584 interconnect-names = "qup-core", "qup-config",
1586 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1587 <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1588 dma-names = "tx", "rx";
1589 status = "disabled";
1593 compatible = "qcom,geni-spi";
1594 reg = <0 0x00a88000 0 0x4000>;
1595 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1599 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1600 #address-cells = <1>;
1602 power-domains = <&rpmhpd SC7280_CX>;
1603 operating-points-v2 = <&qup_opp_table>;
1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1606 interconnect-names = "qup-core", "qup-config";
1607 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1608 <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1609 dma-names = "tx", "rx";
1610 status = "disabled";
1613 uart10: serial@a88000 {
1614 compatible = "qcom,geni-uart";
1615 reg = <0 0x00a88000 0 0x4000>;
1616 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1620 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1621 power-domains = <&rpmhpd SC7280_CX>;
1622 operating-points-v2 = <&qup_opp_table>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1625 interconnect-names = "qup-core", "qup-config";
1626 status = "disabled";
1630 compatible = "qcom,geni-i2c";
1631 reg = <0 0x00a8c000 0 0x4000>;
1632 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1634 pinctrl-names = "default";
1635 pinctrl-0 = <&qup_i2c11_data_clk>;
1636 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1637 #address-cells = <1>;
1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1641 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1642 interconnect-names = "qup-core", "qup-config",
1644 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1645 <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1646 dma-names = "tx", "rx";
1647 status = "disabled";
1651 compatible = "qcom,geni-spi";
1652 reg = <0 0x00a8c000 0 0x4000>;
1653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1655 pinctrl-names = "default";
1656 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1657 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1658 #address-cells = <1>;
1660 power-domains = <&rpmhpd SC7280_CX>;
1661 operating-points-v2 = <&qup_opp_table>;
1662 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1663 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1664 interconnect-names = "qup-core", "qup-config";
1665 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1666 <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1667 dma-names = "tx", "rx";
1668 status = "disabled";
1671 uart11: serial@a8c000 {
1672 compatible = "qcom,geni-uart";
1673 reg = <0 0x00a8c000 0 0x4000>;
1674 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1676 pinctrl-names = "default";
1677 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1678 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1679 power-domains = <&rpmhpd SC7280_CX>;
1680 operating-points-v2 = <&qup_opp_table>;
1681 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1682 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1683 interconnect-names = "qup-core", "qup-config";
1684 status = "disabled";
1688 compatible = "qcom,geni-i2c";
1689 reg = <0 0x00a90000 0 0x4000>;
1690 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1692 pinctrl-names = "default";
1693 pinctrl-0 = <&qup_i2c12_data_clk>;
1694 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1695 #address-cells = <1>;
1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1699 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1700 interconnect-names = "qup-core", "qup-config",
1702 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1703 <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1704 dma-names = "tx", "rx";
1705 status = "disabled";
1709 compatible = "qcom,geni-spi";
1710 reg = <0 0x00a90000 0 0x4000>;
1711 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1713 pinctrl-names = "default";
1714 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1715 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1716 #address-cells = <1>;
1718 power-domains = <&rpmhpd SC7280_CX>;
1719 operating-points-v2 = <&qup_opp_table>;
1720 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1721 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1722 interconnect-names = "qup-core", "qup-config";
1723 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1724 <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1725 dma-names = "tx", "rx";
1726 status = "disabled";
1729 uart12: serial@a90000 {
1730 compatible = "qcom,geni-uart";
1731 reg = <0 0x00a90000 0 0x4000>;
1732 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1734 pinctrl-names = "default";
1735 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1736 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1737 power-domains = <&rpmhpd SC7280_CX>;
1738 operating-points-v2 = <&qup_opp_table>;
1739 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1740 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1741 interconnect-names = "qup-core", "qup-config";
1742 status = "disabled";
1746 compatible = "qcom,geni-i2c";
1747 reg = <0 0x00a94000 0 0x4000>;
1748 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1750 pinctrl-names = "default";
1751 pinctrl-0 = <&qup_i2c13_data_clk>;
1752 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1753 #address-cells = <1>;
1755 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1756 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1757 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1758 interconnect-names = "qup-core", "qup-config",
1760 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1761 <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1762 dma-names = "tx", "rx";
1763 status = "disabled";
1767 compatible = "qcom,geni-spi";
1768 reg = <0 0x00a94000 0 0x4000>;
1769 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1771 pinctrl-names = "default";
1772 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1773 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1774 #address-cells = <1>;
1776 power-domains = <&rpmhpd SC7280_CX>;
1777 operating-points-v2 = <&qup_opp_table>;
1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1779 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1780 interconnect-names = "qup-core", "qup-config";
1781 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1782 <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1783 dma-names = "tx", "rx";
1784 status = "disabled";
1787 uart13: serial@a94000 {
1788 compatible = "qcom,geni-uart";
1789 reg = <0 0x00a94000 0 0x4000>;
1790 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1792 pinctrl-names = "default";
1793 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1794 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1795 power-domains = <&rpmhpd SC7280_CX>;
1796 operating-points-v2 = <&qup_opp_table>;
1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1799 interconnect-names = "qup-core", "qup-config";
1800 status = "disabled";
1804 compatible = "qcom,geni-i2c";
1805 reg = <0 0x00a98000 0 0x4000>;
1806 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1808 pinctrl-names = "default";
1809 pinctrl-0 = <&qup_i2c14_data_clk>;
1810 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1811 #address-cells = <1>;
1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1814 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1815 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1816 interconnect-names = "qup-core", "qup-config",
1818 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1819 <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1820 dma-names = "tx", "rx";
1821 status = "disabled";
1825 compatible = "qcom,geni-spi";
1826 reg = <0 0x00a98000 0 0x4000>;
1827 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1829 pinctrl-names = "default";
1830 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1831 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1832 #address-cells = <1>;
1834 power-domains = <&rpmhpd SC7280_CX>;
1835 operating-points-v2 = <&qup_opp_table>;
1836 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1837 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1838 interconnect-names = "qup-core", "qup-config";
1839 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1840 <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1841 dma-names = "tx", "rx";
1842 status = "disabled";
1845 uart14: serial@a98000 {
1846 compatible = "qcom,geni-uart";
1847 reg = <0 0x00a98000 0 0x4000>;
1848 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1850 pinctrl-names = "default";
1851 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1852 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1853 power-domains = <&rpmhpd SC7280_CX>;
1854 operating-points-v2 = <&qup_opp_table>;
1855 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1856 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1857 interconnect-names = "qup-core", "qup-config";
1858 status = "disabled";
1862 compatible = "qcom,geni-i2c";
1863 reg = <0 0x00a9c000 0 0x4000>;
1864 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1866 pinctrl-names = "default";
1867 pinctrl-0 = <&qup_i2c15_data_clk>;
1868 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1869 #address-cells = <1>;
1871 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1872 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1873 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1874 interconnect-names = "qup-core", "qup-config",
1876 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1877 <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1878 dma-names = "tx", "rx";
1879 status = "disabled";
1883 compatible = "qcom,geni-spi";
1884 reg = <0 0x00a9c000 0 0x4000>;
1885 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1887 pinctrl-names = "default";
1888 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1889 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1890 #address-cells = <1>;
1892 power-domains = <&rpmhpd SC7280_CX>;
1893 operating-points-v2 = <&qup_opp_table>;
1894 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1895 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1896 interconnect-names = "qup-core", "qup-config";
1897 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1898 <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1899 dma-names = "tx", "rx";
1900 status = "disabled";
1903 uart15: serial@a9c000 {
1904 compatible = "qcom,geni-uart";
1905 reg = <0 0x00a9c000 0 0x4000>;
1906 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1908 pinctrl-names = "default";
1909 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1910 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1911 power-domains = <&rpmhpd SC7280_CX>;
1912 operating-points-v2 = <&qup_opp_table>;
1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1914 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1915 interconnect-names = "qup-core", "qup-config";
1916 status = "disabled";
1920 cnoc2: interconnect@1500000 {
1921 reg = <0 0x01500000 0 0x1000>;
1922 compatible = "qcom,sc7280-cnoc2";
1923 #interconnect-cells = <2>;
1924 qcom,bcm-voters = <&apps_bcm_voter>;
1927 cnoc3: interconnect@1502000 {
1928 reg = <0 0x01502000 0 0x1000>;
1929 compatible = "qcom,sc7280-cnoc3";
1930 #interconnect-cells = <2>;
1931 qcom,bcm-voters = <&apps_bcm_voter>;
1934 mc_virt: interconnect@1580000 {
1935 reg = <0 0x01580000 0 0x4>;
1936 compatible = "qcom,sc7280-mc-virt";
1937 #interconnect-cells = <2>;
1938 qcom,bcm-voters = <&apps_bcm_voter>;
1941 system_noc: interconnect@1680000 {
1942 reg = <0 0x01680000 0 0x15480>;
1943 compatible = "qcom,sc7280-system-noc";
1944 #interconnect-cells = <2>;
1945 qcom,bcm-voters = <&apps_bcm_voter>;
1948 aggre1_noc: interconnect@16e0000 {
1949 compatible = "qcom,sc7280-aggre1-noc";
1950 reg = <0 0x016e0000 0 0x1c080>;
1951 #interconnect-cells = <2>;
1952 qcom,bcm-voters = <&apps_bcm_voter>;
1955 aggre2_noc: interconnect@1700000 {
1956 reg = <0 0x01700000 0 0x2b080>;
1957 compatible = "qcom,sc7280-aggre2-noc";
1958 #interconnect-cells = <2>;
1959 qcom,bcm-voters = <&apps_bcm_voter>;
1962 mmss_noc: interconnect@1740000 {
1963 reg = <0 0x01740000 0 0x1e080>;
1964 compatible = "qcom,sc7280-mmss-noc";
1965 #interconnect-cells = <2>;
1966 qcom,bcm-voters = <&apps_bcm_voter>;
1969 wifi: wifi@17a10040 {
1970 compatible = "qcom,wcn6750-wifi";
1971 reg = <0 0x17a10040 0 0x0>;
1972 iommus = <&apps_smmu 0x1c00 0x1>;
1973 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
1974 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
1975 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
1976 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
1977 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
1978 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
1979 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
1980 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
1981 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
1982 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
1983 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
1984 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
1985 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
1986 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
1987 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
1988 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
1989 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
1990 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
1991 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
1992 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
1993 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
1994 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
1995 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
1996 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
1997 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
1998 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
1999 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
2000 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
2001 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
2002 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2003 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2004 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2005 qcom,rproc = <&remoteproc_wpss>;
2006 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2007 status = "disabled";
2010 pcie1: pci@1c08000 {
2011 compatible = "qcom,pcie-sc7280";
2012 reg = <0 0x01c08000 0 0x3000>,
2013 <0 0x40000000 0 0xf1d>,
2014 <0 0x40000f20 0 0xa8>,
2015 <0 0x40001000 0 0x1000>,
2016 <0 0x40100000 0 0x100000>;
2018 reg-names = "parf", "dbi", "elbi", "atu", "config";
2019 device_type = "pci";
2020 linux,pci-domain = <1>;
2021 bus-range = <0x00 0xff>;
2024 #address-cells = <3>;
2027 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2028 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2030 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2031 interrupt-names = "msi";
2032 #interrupt-cells = <1>;
2033 interrupt-map-mask = <0 0 0 0x7>;
2034 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2035 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2036 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2037 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2039 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2040 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2042 <&rpmhcc RPMH_CXO_CLK>,
2043 <&gcc GCC_PCIE_1_AUX_CLK>,
2044 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2045 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2046 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2047 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2048 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2049 <&gcc GCC_DDRSS_PCIE_SF_CLK>,
2050 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
2051 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
2053 clock-names = "pipe",
2067 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2068 assigned-clock-rates = <19200000>;
2070 resets = <&gcc GCC_PCIE_1_BCR>;
2071 reset-names = "pci";
2073 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2075 phys = <&pcie1_lane>;
2076 phy-names = "pciephy";
2078 pinctrl-names = "default";
2079 pinctrl-0 = <&pcie1_clkreq_n>;
2083 iommus = <&apps_smmu 0x1c80 0x1>;
2085 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2086 <0x100 &apps_smmu 0x1c81 0x1>;
2088 status = "disabled";
2091 pcie1_phy: phy@1c0e000 {
2092 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2093 reg = <0 0x01c0e000 0 0x1c0>;
2094 #address-cells = <2>;
2097 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2098 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2099 <&gcc GCC_PCIE_CLKREF_EN>,
2100 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2101 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2103 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2104 reset-names = "phy";
2106 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2107 assigned-clock-rates = <100000000>;
2109 status = "disabled";
2111 pcie1_lane: phy@1c0e200 {
2112 reg = <0 0x01c0e200 0 0x170>,
2113 <0 0x01c0e400 0 0x200>,
2114 <0 0x01c0ea00 0 0x1f0>,
2115 <0 0x01c0e600 0 0x170>,
2116 <0 0x01c0e800 0 0x200>,
2117 <0 0x01c0ee00 0 0xf4>;
2118 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2119 clock-names = "pipe0";
2123 clock-output-names = "pcie_1_pipe_clk";
2128 compatible = "qcom,sc7280-ipa";
2130 iommus = <&apps_smmu 0x480 0x0>,
2131 <&apps_smmu 0x482 0x0>;
2132 reg = <0 0x1e40000 0 0x8000>,
2133 <0 0x1e50000 0 0x4ad0>,
2134 <0 0x1e04000 0 0x23000>;
2135 reg-names = "ipa-reg",
2139 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2140 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2141 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2142 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2143 interrupt-names = "ipa",
2148 clocks = <&rpmhcc RPMH_IPA_CLK>;
2149 clock-names = "core";
2151 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2152 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2153 interconnect-names = "memory",
2156 qcom,qmp = <&aoss_qmp>;
2158 qcom,smem-states = <&ipa_smp2p_out 0>,
2160 qcom,smem-state-names = "ipa-clock-enabled-valid",
2161 "ipa-clock-enabled";
2163 status = "disabled";
2166 tcsr_mutex: hwlock@1f40000 {
2167 compatible = "qcom,tcsr-mutex";
2168 reg = <0 0x01f40000 0 0x20000>;
2169 #hwlock-cells = <1>;
2172 tcsr_1: syscon@1f60000 {
2173 compatible = "qcom,sc7280-tcsr", "syscon";
2174 reg = <0 0x01f60000 0 0x20000>;
2177 tcsr_2: syscon@1fc0000 {
2178 compatible = "qcom,sc7280-tcsr", "syscon";
2179 reg = <0 0x01fc0000 0 0x30000>;
2182 lpasscc: lpasscc@3000000 {
2183 compatible = "qcom,sc7280-lpasscc";
2184 reg = <0 0x03000000 0 0x40>,
2185 <0 0x03c04000 0 0x4>;
2186 reg-names = "qdsp6ss", "top_cc";
2187 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2188 clock-names = "iface";
2192 lpass_rx_macro: codec@3200000 {
2193 compatible = "qcom,sc7280-lpass-rx-macro";
2194 reg = <0 0x03200000 0 0x1000>;
2196 pinctrl-names = "default";
2197 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2199 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2200 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2202 clock-names = "mclk", "npl", "fsgen";
2204 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2205 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2206 power-domain-names = "macro", "dcodec";
2209 #sound-dai-cells = <1>;
2211 status = "disabled";
2214 swr0: soundwire@3210000 {
2215 compatible = "qcom,soundwire-v1.6.0";
2216 reg = <0 0x03210000 0 0x2000>;
2218 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2219 clocks = <&lpass_rx_macro>;
2220 clock-names = "iface";
2222 qcom,din-ports = <0>;
2223 qcom,dout-ports = <5>;
2225 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2226 reset-names = "swr_audio_cgcr";
2228 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2229 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2230 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2231 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2232 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2233 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2234 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2235 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2236 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2238 #sound-dai-cells = <1>;
2239 #address-cells = <2>;
2242 status = "disabled";
2245 lpass_tx_macro: codec@3220000 {
2246 compatible = "qcom,sc7280-lpass-tx-macro";
2247 reg = <0 0x03220000 0 0x1000>;
2249 pinctrl-names = "default";
2250 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2252 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
2253 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
2255 clock-names = "mclk", "npl", "fsgen";
2257 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2258 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2259 power-domain-names = "macro", "dcodec";
2262 #sound-dai-cells = <1>;
2264 status = "disabled";
2267 swr1: soundwire@3230000 {
2268 compatible = "qcom,soundwire-v1.6.0";
2269 reg = <0 0x03230000 0 0x2000>;
2271 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2272 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>;
2273 clocks = <&lpass_tx_macro>;
2274 clock-names = "iface";
2276 qcom,din-ports = <3>;
2277 qcom,dout-ports = <0>;
2279 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2280 reset-names = "swr_audio_cgcr";
2282 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2283 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2284 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2285 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2286 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2287 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2288 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2289 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2290 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2291 qcom,port-offset = <1>;
2293 #sound-dai-cells = <1>;
2294 #address-cells = <2>;
2297 status = "disabled";
2300 lpass_audiocc: clock-controller@3300000 {
2301 compatible = "qcom,sc7280-lpassaudiocc";
2302 reg = <0 0x03300000 0 0x30000>,
2303 <0 0x032a9000 0 0x1000>;
2304 clocks = <&rpmhcc RPMH_CXO_CLK>,
2305 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2306 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2307 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2309 #power-domain-cells = <1>;
2313 lpass_va_macro: codec@3370000 {
2314 compatible = "qcom,sc7280-lpass-va-macro";
2315 reg = <0 0x03370000 0 0x1000>;
2317 pinctrl-names = "default";
2318 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2320 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>;
2321 clock-names = "mclk";
2323 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2324 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2325 power-domain-names = "macro", "dcodec";
2328 #sound-dai-cells = <1>;
2330 status = "disabled";
2333 lpass_aon: clock-controller@3380000 {
2334 compatible = "qcom,sc7280-lpassaoncc";
2335 reg = <0 0x03380000 0 0x30000>;
2336 clocks = <&rpmhcc RPMH_CXO_CLK>,
2337 <&rpmhcc RPMH_CXO_CLK_A>,
2338 <&lpass_core LPASS_CORE_CC_CORE_CLK>;
2339 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2341 #power-domain-cells = <1>;
2344 lpass_core: clock-controller@3900000 {
2345 compatible = "qcom,sc7280-lpasscorecc";
2346 reg = <0 0x03900000 0 0x50000>;
2347 clocks = <&rpmhcc RPMH_CXO_CLK>;
2348 clock-names = "bi_tcxo";
2349 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2351 #power-domain-cells = <1>;
2354 lpass_cpu: audio@3987000 {
2355 compatible = "qcom,sc7280-lpass-cpu";
2357 reg = <0 0x03987000 0 0x68000>,
2358 <0 0x03b00000 0 0x29000>,
2359 <0 0x03260000 0 0xc000>,
2360 <0 0x03280000 0 0x29000>,
2361 <0 0x03340000 0 0x29000>,
2362 <0 0x0336c000 0 0x3000>;
2363 reg-names = "lpass-hdmiif",
2365 "lpass-rxtx-cdc-dma-lpm",
2368 "lpass-va-cdc-dma-lpm";
2370 iommus = <&apps_smmu 0x1820 0>,
2371 <&apps_smmu 0x1821 0>,
2372 <&apps_smmu 0x1832 0>;
2374 power-domains = <&rpmhpd SC7280_LCX>;
2375 power-domain-names = "lcx";
2376 required-opps = <&rpmhpd_opp_nom>;
2378 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>,
2379 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>,
2380 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>,
2381 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>,
2382 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>,
2383 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2384 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2385 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2386 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
2387 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>;
2388 clock-names = "aon_cc_audio_hm_h",
2389 "audio_cc_ext_mclk0",
2390 "core_cc_sysnoc_mport_core",
2391 "core_cc_ext_if0_ibit",
2392 "core_cc_ext_if1_ibit",
2393 "audio_cc_codec_mem",
2394 "audio_cc_codec_mem0",
2395 "audio_cc_codec_mem1",
2396 "audio_cc_codec_mem2",
2399 #sound-dai-cells = <1>;
2400 #address-cells = <1>;
2403 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2404 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2405 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
2406 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
2407 interrupt-names = "lpass-irq-lpaif",
2412 status = "disabled";
2415 lpass_hm: clock-controller@3c00000 {
2416 compatible = "qcom,sc7280-lpasshm";
2417 reg = <0 0x3c00000 0 0x28>;
2418 clocks = <&rpmhcc RPMH_CXO_CLK>;
2419 clock-names = "bi_tcxo";
2421 #power-domain-cells = <1>;
2424 lpass_ag_noc: interconnect@3c40000 {
2425 reg = <0 0x03c40000 0 0xf080>;
2426 compatible = "qcom,sc7280-lpass-ag-noc";
2427 #interconnect-cells = <2>;
2428 qcom,bcm-voters = <&apps_bcm_voter>;
2431 lpass_tlmm: pinctrl@33c0000 {
2432 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2433 reg = <0 0x033c0000 0x0 0x20000>,
2434 <0 0x03550000 0x0 0x10000>;
2435 qcom,adsp-bypass-mode;
2438 gpio-ranges = <&lpass_tlmm 0 0 15>;
2442 lpass_dmic01_clk: dmic01-clk {
2444 function = "dmic1_clk";
2447 lpass_dmic01_clk_sleep: dmic01-clk-sleep {
2449 function = "dmic1_clk";
2452 lpass_dmic01_data: dmic01-data {
2454 function = "dmic1_data";
2457 lpass_dmic01_data_sleep: dmic01-data-sleep {
2459 function = "dmic1_data";
2462 lpass_dmic23_clk: dmic23-clk {
2464 function = "dmic2_clk";
2467 lpass_dmic23_clk_sleep: dmic23-clk-sleep {
2469 function = "dmic2_clk";
2472 lpass_dmic23_data: dmic23-data {
2474 function = "dmic2_data";
2477 lpass_dmic23_data_sleep: dmic23-data-sleep {
2479 function = "dmic2_data";
2482 lpass_rx_swr_clk: rx-swr-clk {
2484 function = "swr_rx_clk";
2487 lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
2489 function = "swr_rx_clk";
2492 lpass_rx_swr_data: rx-swr-data {
2493 pins = "gpio4", "gpio5";
2494 function = "swr_rx_data";
2497 lpass_rx_swr_data_sleep: rx-swr-data-sleep {
2498 pins = "gpio4", "gpio5";
2499 function = "swr_rx_data";
2502 lpass_tx_swr_clk: tx-swr-clk {
2504 function = "swr_tx_clk";
2507 lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
2509 function = "swr_tx_clk";
2512 lpass_tx_swr_data: tx-swr-data {
2513 pins = "gpio1", "gpio2", "gpio14";
2514 function = "swr_tx_data";
2517 lpass_tx_swr_data_sleep: tx-swr-data-sleep {
2518 pins = "gpio1", "gpio2", "gpio14";
2519 function = "swr_tx_data";
2524 compatible = "qcom,adreno-635.0", "qcom,adreno";
2525 reg = <0 0x03d00000 0 0x40000>,
2526 <0 0x03d9e000 0 0x1000>,
2527 <0 0x03d61000 0 0x800>;
2528 reg-names = "kgsl_3d0_reg_memory",
2531 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2532 iommus = <&adreno_smmu 0 0x401>;
2533 operating-points-v2 = <&gpu_opp_table>;
2535 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2536 interconnect-names = "gfx-mem";
2537 #cooling-cells = <2>;
2539 nvmem-cells = <&gpu_speed_bin>;
2540 nvmem-cell-names = "speed_bin";
2542 gpu_opp_table: opp-table {
2543 compatible = "operating-points-v2";
2546 opp-hz = /bits/ 64 <315000000>;
2547 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2548 opp-peak-kBps = <1804000>;
2549 opp-supported-hw = <0x03>;
2553 opp-hz = /bits/ 64 <450000000>;
2554 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2555 opp-peak-kBps = <4068000>;
2556 opp-supported-hw = <0x03>;
2559 /* Only applicable for SKUs which has 550Mhz as Fmax */
2561 opp-hz = /bits/ 64 <550000000>;
2562 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2563 opp-peak-kBps = <8368000>;
2564 opp-supported-hw = <0x01>;
2568 opp-hz = /bits/ 64 <550000000>;
2569 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2570 opp-peak-kBps = <6832000>;
2571 opp-supported-hw = <0x02>;
2575 opp-hz = /bits/ 64 <608000000>;
2576 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2577 opp-peak-kBps = <8368000>;
2578 opp-supported-hw = <0x02>;
2582 opp-hz = /bits/ 64 <700000000>;
2583 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2584 opp-peak-kBps = <8532000>;
2585 opp-supported-hw = <0x02>;
2589 opp-hz = /bits/ 64 <812000000>;
2590 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2591 opp-peak-kBps = <8532000>;
2592 opp-supported-hw = <0x02>;
2596 opp-hz = /bits/ 64 <840000000>;
2597 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2598 opp-peak-kBps = <8532000>;
2599 opp-supported-hw = <0x02>;
2603 opp-hz = /bits/ 64 <900000000>;
2604 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2605 opp-peak-kBps = <8532000>;
2606 opp-supported-hw = <0x02>;
2612 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2613 reg = <0 0x03d6a000 0 0x34000>,
2614 <0 0x3de0000 0 0x10000>,
2615 <0 0x0b290000 0 0x10000>;
2616 reg-names = "gmu", "rscc", "gmu_pdc";
2617 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2618 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2619 interrupt-names = "hfi", "gmu";
2620 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2621 <&gpucc GPU_CC_CXO_CLK>,
2622 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2623 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2624 <&gpucc GPU_CC_AHB_CLK>,
2625 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2626 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2627 clock-names = "gmu",
2634 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2635 <&gpucc GPU_CC_GX_GDSC>;
2636 power-domain-names = "cx",
2638 iommus = <&adreno_smmu 5 0x400>;
2639 operating-points-v2 = <&gmu_opp_table>;
2641 gmu_opp_table: opp-table {
2642 compatible = "operating-points-v2";
2645 opp-hz = /bits/ 64 <200000000>;
2646 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2651 gpucc: clock-controller@3d90000 {
2652 compatible = "qcom,sc7280-gpucc";
2653 reg = <0 0x03d90000 0 0x9000>;
2654 clocks = <&rpmhcc RPMH_CXO_CLK>,
2655 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2656 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2657 clock-names = "bi_tcxo",
2658 "gcc_gpu_gpll0_clk_src",
2659 "gcc_gpu_gpll0_div_clk_src";
2662 #power-domain-cells = <1>;
2665 adreno_smmu: iommu@3da0000 {
2666 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2667 reg = <0 0x03da0000 0 0x20000>;
2669 #global-interrupts = <2>;
2670 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2671 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2672 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2673 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2674 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2675 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2676 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2677 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2678 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2679 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2680 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2681 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2683 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2684 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2685 <&gpucc GPU_CC_AHB_CLK>,
2686 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2687 <&gpucc GPU_CC_CX_GMU_CLK>,
2688 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2689 <&gpucc GPU_CC_HUB_AON_CLK>;
2690 clock-names = "gcc_gpu_memnoc_gfx_clk",
2691 "gcc_gpu_snoc_dvm_gfx_clk",
2693 "gpu_cc_hlos1_vote_gpu_smmu_clk",
2694 "gpu_cc_cx_gmu_clk",
2695 "gpu_cc_hub_cx_int_clk",
2696 "gpu_cc_hub_aon_clk";
2698 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2701 remoteproc_mpss: remoteproc@4080000 {
2702 compatible = "qcom,sc7280-mpss-pas";
2703 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2704 reg-names = "qdsp6", "rmb";
2706 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2707 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2708 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2709 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2710 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2711 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2712 interrupt-names = "wdog", "fatal", "ready", "handover",
2713 "stop-ack", "shutdown-ack";
2715 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2716 <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
2717 <&gcc GCC_MSS_SNOC_AXI_CLK>,
2718 <&rpmhcc RPMH_PKA_CLK>,
2719 <&rpmhcc RPMH_CXO_CLK>;
2720 clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
2722 power-domains = <&rpmhpd SC7280_CX>,
2723 <&rpmhpd SC7280_MSS>;
2724 power-domain-names = "cx", "mss";
2726 memory-region = <&mpss_mem>;
2728 qcom,qmp = <&aoss_qmp>;
2730 qcom,smem-states = <&modem_smp2p_out 0>;
2731 qcom,smem-state-names = "stop";
2733 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2734 <&pdc_reset PDC_MODEM_SYNC_RESET>;
2735 reset-names = "mss_restart", "pdc_reset";
2737 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x8000 0x13000>;
2738 qcom,ext-regs = <&tcsr_2 0x10000 0x10004 &tcsr_1 0x6004 0x6008>;
2739 qcom,qaccept-regs = <&tcsr_1 0x3030 0x3040 0x3020>;
2741 status = "disabled";
2744 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2745 IPCC_MPROC_SIGNAL_GLINK_QMP
2746 IRQ_TYPE_EDGE_RISING>;
2747 mboxes = <&ipcc IPCC_CLIENT_MPSS
2748 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2750 qcom,remote-pid = <1>;
2755 compatible = "arm,coresight-stm", "arm,primecell";
2756 reg = <0 0x06002000 0 0x1000>,
2757 <0 0x16280000 0 0x180000>;
2758 reg-names = "stm-base", "stm-stimulus-base";
2760 clocks = <&aoss_qmp>;
2761 clock-names = "apb_pclk";
2766 remote-endpoint = <&funnel0_in7>;
2773 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2774 reg = <0 0x06041000 0 0x1000>;
2776 clocks = <&aoss_qmp>;
2777 clock-names = "apb_pclk";
2781 funnel0_out: endpoint {
2782 remote-endpoint = <&merge_funnel_in0>;
2788 #address-cells = <1>;
2793 funnel0_in7: endpoint {
2794 remote-endpoint = <&stm_out>;
2801 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2802 reg = <0 0x06042000 0 0x1000>;
2804 clocks = <&aoss_qmp>;
2805 clock-names = "apb_pclk";
2809 funnel1_out: endpoint {
2810 remote-endpoint = <&merge_funnel_in1>;
2816 #address-cells = <1>;
2821 funnel1_in4: endpoint {
2822 remote-endpoint = <&apss_merge_funnel_out>;
2829 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2830 reg = <0 0x06045000 0 0x1000>;
2832 clocks = <&aoss_qmp>;
2833 clock-names = "apb_pclk";
2837 merge_funnel_out: endpoint {
2838 remote-endpoint = <&swao_funnel_in>;
2844 #address-cells = <1>;
2849 merge_funnel_in0: endpoint {
2850 remote-endpoint = <&funnel0_out>;
2856 merge_funnel_in1: endpoint {
2857 remote-endpoint = <&funnel1_out>;
2863 replicator@6046000 {
2864 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2865 reg = <0 0x06046000 0 0x1000>;
2867 clocks = <&aoss_qmp>;
2868 clock-names = "apb_pclk";
2872 replicator_out: endpoint {
2873 remote-endpoint = <&etr_in>;
2880 replicator_in: endpoint {
2881 remote-endpoint = <&swao_replicator_out>;
2888 compatible = "arm,coresight-tmc", "arm,primecell";
2889 reg = <0 0x06048000 0 0x1000>;
2890 iommus = <&apps_smmu 0x04c0 0>;
2892 clocks = <&aoss_qmp>;
2893 clock-names = "apb_pclk";
2899 remote-endpoint = <&replicator_out>;
2906 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2907 reg = <0 0x06b04000 0 0x1000>;
2909 clocks = <&aoss_qmp>;
2910 clock-names = "apb_pclk";
2914 swao_funnel_out: endpoint {
2915 remote-endpoint = <&etf_in>;
2921 #address-cells = <1>;
2926 swao_funnel_in: endpoint {
2927 remote-endpoint = <&merge_funnel_out>;
2934 compatible = "arm,coresight-tmc", "arm,primecell";
2935 reg = <0 0x06b05000 0 0x1000>;
2937 clocks = <&aoss_qmp>;
2938 clock-names = "apb_pclk";
2943 remote-endpoint = <&swao_replicator_in>;
2951 remote-endpoint = <&swao_funnel_out>;
2957 replicator@6b06000 {
2958 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2959 reg = <0 0x06b06000 0 0x1000>;
2961 clocks = <&aoss_qmp>;
2962 clock-names = "apb_pclk";
2963 qcom,replicator-loses-context;
2967 swao_replicator_out: endpoint {
2968 remote-endpoint = <&replicator_in>;
2975 swao_replicator_in: endpoint {
2976 remote-endpoint = <&etf_out>;
2983 compatible = "arm,coresight-etm4x", "arm,primecell";
2984 reg = <0 0x07040000 0 0x1000>;
2988 clocks = <&aoss_qmp>;
2989 clock-names = "apb_pclk";
2990 arm,coresight-loses-context-with-cpu;
2995 etm0_out: endpoint {
2996 remote-endpoint = <&apss_funnel_in0>;
3003 compatible = "arm,coresight-etm4x", "arm,primecell";
3004 reg = <0 0x07140000 0 0x1000>;
3008 clocks = <&aoss_qmp>;
3009 clock-names = "apb_pclk";
3010 arm,coresight-loses-context-with-cpu;
3015 etm1_out: endpoint {
3016 remote-endpoint = <&apss_funnel_in1>;
3023 compatible = "arm,coresight-etm4x", "arm,primecell";
3024 reg = <0 0x07240000 0 0x1000>;
3028 clocks = <&aoss_qmp>;
3029 clock-names = "apb_pclk";
3030 arm,coresight-loses-context-with-cpu;
3035 etm2_out: endpoint {
3036 remote-endpoint = <&apss_funnel_in2>;
3043 compatible = "arm,coresight-etm4x", "arm,primecell";
3044 reg = <0 0x07340000 0 0x1000>;
3048 clocks = <&aoss_qmp>;
3049 clock-names = "apb_pclk";
3050 arm,coresight-loses-context-with-cpu;
3055 etm3_out: endpoint {
3056 remote-endpoint = <&apss_funnel_in3>;
3063 compatible = "arm,coresight-etm4x", "arm,primecell";
3064 reg = <0 0x07440000 0 0x1000>;
3068 clocks = <&aoss_qmp>;
3069 clock-names = "apb_pclk";
3070 arm,coresight-loses-context-with-cpu;
3075 etm4_out: endpoint {
3076 remote-endpoint = <&apss_funnel_in4>;
3083 compatible = "arm,coresight-etm4x", "arm,primecell";
3084 reg = <0 0x07540000 0 0x1000>;
3088 clocks = <&aoss_qmp>;
3089 clock-names = "apb_pclk";
3090 arm,coresight-loses-context-with-cpu;
3095 etm5_out: endpoint {
3096 remote-endpoint = <&apss_funnel_in5>;
3103 compatible = "arm,coresight-etm4x", "arm,primecell";
3104 reg = <0 0x07640000 0 0x1000>;
3108 clocks = <&aoss_qmp>;
3109 clock-names = "apb_pclk";
3110 arm,coresight-loses-context-with-cpu;
3115 etm6_out: endpoint {
3116 remote-endpoint = <&apss_funnel_in6>;
3123 compatible = "arm,coresight-etm4x", "arm,primecell";
3124 reg = <0 0x07740000 0 0x1000>;
3128 clocks = <&aoss_qmp>;
3129 clock-names = "apb_pclk";
3130 arm,coresight-loses-context-with-cpu;
3135 etm7_out: endpoint {
3136 remote-endpoint = <&apss_funnel_in7>;
3142 funnel@7800000 { /* APSS Funnel */
3143 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3144 reg = <0 0x07800000 0 0x1000>;
3146 clocks = <&aoss_qmp>;
3147 clock-names = "apb_pclk";
3151 apss_funnel_out: endpoint {
3152 remote-endpoint = <&apss_merge_funnel_in>;
3158 #address-cells = <1>;
3163 apss_funnel_in0: endpoint {
3164 remote-endpoint = <&etm0_out>;
3170 apss_funnel_in1: endpoint {
3171 remote-endpoint = <&etm1_out>;
3177 apss_funnel_in2: endpoint {
3178 remote-endpoint = <&etm2_out>;
3184 apss_funnel_in3: endpoint {
3185 remote-endpoint = <&etm3_out>;
3191 apss_funnel_in4: endpoint {
3192 remote-endpoint = <&etm4_out>;
3198 apss_funnel_in5: endpoint {
3199 remote-endpoint = <&etm5_out>;
3205 apss_funnel_in6: endpoint {
3206 remote-endpoint = <&etm6_out>;
3212 apss_funnel_in7: endpoint {
3213 remote-endpoint = <&etm7_out>;
3220 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3221 reg = <0 0x07810000 0 0x1000>;
3223 clocks = <&aoss_qmp>;
3224 clock-names = "apb_pclk";
3228 apss_merge_funnel_out: endpoint {
3229 remote-endpoint = <&funnel1_in4>;
3236 apss_merge_funnel_in: endpoint {
3237 remote-endpoint = <&apss_funnel_out>;
3243 sdhc_2: mmc@8804000 {
3244 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3245 pinctrl-names = "default", "sleep";
3246 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3247 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3248 status = "disabled";
3250 reg = <0 0x08804000 0 0x1000>;
3252 iommus = <&apps_smmu 0x100 0x0>;
3253 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3254 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3255 interrupt-names = "hc_irq", "pwr_irq";
3257 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3258 <&gcc GCC_SDCC2_APPS_CLK>,
3259 <&rpmhcc RPMH_CXO_CLK>;
3260 clock-names = "iface", "core", "xo";
3261 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3262 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3263 interconnect-names = "sdhc-ddr","cpu-sdhc";
3264 power-domains = <&rpmhpd SC7280_CX>;
3265 operating-points-v2 = <&sdhc2_opp_table>;
3269 qcom,dll-config = <0x0007642c>;
3271 resets = <&gcc GCC_SDCC2_BCR>;
3273 sdhc2_opp_table: opp-table {
3274 compatible = "operating-points-v2";
3277 opp-hz = /bits/ 64 <100000000>;
3278 required-opps = <&rpmhpd_opp_low_svs>;
3279 opp-peak-kBps = <1800000 400000>;
3280 opp-avg-kBps = <100000 0>;
3284 opp-hz = /bits/ 64 <202000000>;
3285 required-opps = <&rpmhpd_opp_nom>;
3286 opp-peak-kBps = <5400000 1600000>;
3287 opp-avg-kBps = <200000 0>;
3293 usb_1_hsphy: phy@88e3000 {
3294 compatible = "qcom,sc7280-usb-hs-phy",
3295 "qcom,usb-snps-hs-7nm-phy";
3296 reg = <0 0x088e3000 0 0x400>;
3297 status = "disabled";
3300 clocks = <&rpmhcc RPMH_CXO_CLK>;
3301 clock-names = "ref";
3303 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3306 usb_2_hsphy: phy@88e4000 {
3307 compatible = "qcom,sc7280-usb-hs-phy",
3308 "qcom,usb-snps-hs-7nm-phy";
3309 reg = <0 0x088e4000 0 0x400>;
3310 status = "disabled";
3313 clocks = <&rpmhcc RPMH_CXO_CLK>;
3314 clock-names = "ref";
3316 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3319 usb_1_qmpphy: phy-wrapper@88e9000 {
3320 compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3321 "qcom,sm8250-qmp-usb3-dp-phy";
3322 reg = <0 0x088e9000 0 0x200>,
3323 <0 0x088e8000 0 0x40>,
3324 <0 0x088ea000 0 0x200>;
3325 status = "disabled";
3326 #address-cells = <2>;
3330 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3331 <&rpmhcc RPMH_CXO_CLK>,
3332 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3333 clock-names = "aux", "ref_clk_src", "com_aux";
3335 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3336 <&gcc GCC_USB3_PHY_PRIM_BCR>;
3337 reset-names = "phy", "common";
3339 usb_1_ssphy: usb3-phy@88e9200 {
3340 reg = <0 0x088e9200 0 0x200>,
3341 <0 0x088e9400 0 0x200>,
3342 <0 0x088e9c00 0 0x400>,
3343 <0 0x088e9600 0 0x200>,
3344 <0 0x088e9800 0 0x200>,
3345 <0 0x088e9a00 0 0x100>;
3348 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3349 clock-names = "pipe0";
3350 clock-output-names = "usb3_phy_pipe_clk_src";
3353 dp_phy: dp-phy@88ea200 {
3354 reg = <0 0x088ea200 0 0x200>,
3355 <0 0x088ea400 0 0x200>,
3356 <0 0x088eaa00 0 0x200>,
3357 <0 0x088ea600 0 0x200>,
3358 <0 0x088ea800 0 0x200>;
3364 usb_2: usb@8cf8800 {
3365 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3366 reg = <0 0x08cf8800 0 0x400>;
3367 status = "disabled";
3368 #address-cells = <2>;
3373 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3374 <&gcc GCC_USB30_SEC_MASTER_CLK>,
3375 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3376 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3377 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3378 clock-names = "cfg_noc",
3384 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3385 <&gcc GCC_USB30_SEC_MASTER_CLK>;
3386 assigned-clock-rates = <19200000>, <200000000>;
3388 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3389 <&pdc 12 IRQ_TYPE_EDGE_RISING>,
3390 <&pdc 13 IRQ_TYPE_EDGE_RISING>;
3391 interrupt-names = "hs_phy_irq",
3395 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3396 required-opps = <&rpmhpd_opp_nom>;
3398 resets = <&gcc GCC_USB30_SEC_BCR>;
3400 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3401 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3402 interconnect-names = "usb-ddr", "apps-usb";
3404 usb_2_dwc3: usb@8c00000 {
3405 compatible = "snps,dwc3";
3406 reg = <0 0x08c00000 0 0xe000>;
3407 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3408 iommus = <&apps_smmu 0xa0 0x0>;
3409 snps,dis_u2_susphy_quirk;
3410 snps,dis_enblslpm_quirk;
3411 phys = <&usb_2_hsphy>;
3412 phy-names = "usb2-phy";
3413 maximum-speed = "high-speed";
3416 usb2_role_switch: endpoint {
3417 remote-endpoint = <&eud_ep>;
3424 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3425 reg = <0 0x088dc000 0 0x1000>;
3426 #address-cells = <1>;
3428 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3429 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3430 <&gcc GCC_QSPI_CORE_CLK>;
3431 clock-names = "iface", "core";
3432 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3433 &cnoc2 SLAVE_QSPI_0 0>;
3434 interconnect-names = "qspi-config";
3435 power-domains = <&rpmhpd SC7280_CX>;
3436 operating-points-v2 = <&qspi_opp_table>;
3437 status = "disabled";
3440 remoteproc_wpss: remoteproc@8a00000 {
3441 compatible = "qcom,sc7280-wpss-pil";
3442 reg = <0 0x08a00000 0 0x10000>;
3444 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3445 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3446 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3447 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3448 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3449 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3450 interrupt-names = "wdog", "fatal", "ready", "handover",
3451 "stop-ack", "shutdown-ack";
3453 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3454 <&gcc GCC_WPSS_AHB_CLK>,
3455 <&gcc GCC_WPSS_RSCP_CLK>,
3456 <&rpmhcc RPMH_CXO_CLK>;
3457 clock-names = "ahb_bdg", "ahb",
3460 power-domains = <&rpmhpd SC7280_CX>,
3461 <&rpmhpd SC7280_MX>;
3462 power-domain-names = "cx", "mx";
3464 memory-region = <&wpss_mem>;
3466 qcom,qmp = <&aoss_qmp>;
3468 qcom,smem-states = <&wpss_smp2p_out 0>;
3469 qcom,smem-state-names = "stop";
3471 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3472 <&pdc_reset PDC_WPSS_SYNC_RESET>;
3473 reset-names = "restart", "pdc_sync";
3475 qcom,halt-regs = <&tcsr_1 0x17000>;
3477 status = "disabled";
3480 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3481 IPCC_MPROC_SIGNAL_GLINK_QMP
3482 IRQ_TYPE_EDGE_RISING>;
3483 mboxes = <&ipcc IPCC_CLIENT_WPSS
3484 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3487 qcom,remote-pid = <13>;
3492 compatible = "qcom,sc7280-llcc-bwmon";
3493 reg = <0 0x9091000 0 0x1000>;
3495 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3497 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3499 operating-points-v2 = <&llcc_bwmon_opp_table>;
3501 llcc_bwmon_opp_table: opp-table {
3502 compatible = "operating-points-v2";
3505 opp-peak-kBps = <800000>;
3508 opp-peak-kBps = <1804000>;
3511 opp-peak-kBps = <2188000>;
3514 opp-peak-kBps = <3072000>;
3517 opp-peak-kBps = <4068000>;
3520 opp-peak-kBps = <6220000>;
3523 opp-peak-kBps = <6832000>;
3526 opp-peak-kBps = <8532000>;
3532 compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
3533 reg = <0 0x090b6400 0 0x600>;
3535 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3537 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3538 operating-points-v2 = <&cpu_bwmon_opp_table>;
3540 cpu_bwmon_opp_table: opp-table {
3541 compatible = "operating-points-v2";
3544 opp-peak-kBps = <2400000>;
3547 opp-peak-kBps = <4800000>;
3550 opp-peak-kBps = <7456000>;
3553 opp-peak-kBps = <9600000>;
3556 opp-peak-kBps = <12896000>;
3559 opp-peak-kBps = <14928000>;
3562 opp-peak-kBps = <17056000>;
3567 dc_noc: interconnect@90e0000 {
3568 reg = <0 0x090e0000 0 0x5080>;
3569 compatible = "qcom,sc7280-dc-noc";
3570 #interconnect-cells = <2>;
3571 qcom,bcm-voters = <&apps_bcm_voter>;
3574 gem_noc: interconnect@9100000 {
3575 reg = <0 0x9100000 0 0xe2200>;
3576 compatible = "qcom,sc7280-gem-noc";
3577 #interconnect-cells = <2>;
3578 qcom,bcm-voters = <&apps_bcm_voter>;
3581 system-cache-controller@9200000 {
3582 compatible = "qcom,sc7280-llcc";
3583 reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3584 reg-names = "llcc_base", "llcc_broadcast_base";
3585 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3589 compatible = "qcom,sc7280-eud","qcom,eud";
3590 reg = <0 0x88e0000 0 0x2000>,
3591 <0 0x88e2000 0 0x1000>;
3592 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3594 #address-cells = <1>;
3600 remote-endpoint = <&usb2_role_switch>;
3606 remote-endpoint = <&con_eud>;
3612 eud_typec: connector {
3613 compatible = "usb-c-connector";
3615 #address-cells = <1>;
3621 remote-endpoint = <&eud_con>;
3627 nsp_noc: interconnect@a0c0000 {
3628 reg = <0 0x0a0c0000 0 0x10000>;
3629 compatible = "qcom,sc7280-nsp-noc";
3630 #interconnect-cells = <2>;
3631 qcom,bcm-voters = <&apps_bcm_voter>;
3634 usb_1: usb@a6f8800 {
3635 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3636 reg = <0 0x0a6f8800 0 0x400>;
3637 status = "disabled";
3638 #address-cells = <2>;
3643 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3644 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3645 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3646 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3647 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3648 clock-names = "cfg_noc",
3654 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3655 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3656 assigned-clock-rates = <19200000>, <200000000>;
3658 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3659 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
3660 <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3661 <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
3662 interrupt-names = "hs_phy_irq",
3667 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3668 required-opps = <&rpmhpd_opp_nom>;
3670 resets = <&gcc GCC_USB30_PRIM_BCR>;
3672 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3673 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3674 interconnect-names = "usb-ddr", "apps-usb";
3678 usb_1_dwc3: usb@a600000 {
3679 compatible = "snps,dwc3";
3680 reg = <0 0x0a600000 0 0xe000>;
3681 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3682 iommus = <&apps_smmu 0xe0 0x0>;
3683 snps,dis_u2_susphy_quirk;
3684 snps,dis_enblslpm_quirk;
3685 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3686 phy-names = "usb2-phy", "usb3-phy";
3687 maximum-speed = "super-speed";
3691 venus: video-codec@aa00000 {
3692 compatible = "qcom,sc7280-venus";
3693 reg = <0 0x0aa00000 0 0xd0600>;
3694 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3696 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3697 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3698 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3699 <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3700 <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3701 clock-names = "core", "bus", "iface",
3702 "vcodec_core", "vcodec_bus";
3704 power-domains = <&videocc MVSC_GDSC>,
3705 <&videocc MVS0_GDSC>,
3706 <&rpmhpd SC7280_CX>;
3707 power-domain-names = "venus", "vcodec0", "cx";
3708 operating-points-v2 = <&venus_opp_table>;
3710 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3711 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3712 interconnect-names = "cpu-cfg", "video-mem";
3714 iommus = <&apps_smmu 0x2180 0x20>,
3715 <&apps_smmu 0x2184 0x20>;
3716 memory-region = <&video_mem>;
3719 compatible = "venus-decoder";
3723 compatible = "venus-encoder";
3727 iommus = <&apps_smmu 0x21a2 0x0>;
3730 venus_opp_table: opp-table {
3731 compatible = "operating-points-v2";
3734 opp-hz = /bits/ 64 <133330000>;
3735 required-opps = <&rpmhpd_opp_low_svs>;
3739 opp-hz = /bits/ 64 <240000000>;
3740 required-opps = <&rpmhpd_opp_svs>;
3744 opp-hz = /bits/ 64 <335000000>;
3745 required-opps = <&rpmhpd_opp_svs_l1>;
3749 opp-hz = /bits/ 64 <424000000>;
3750 required-opps = <&rpmhpd_opp_nom>;
3754 opp-hz = /bits/ 64 <460000048>;
3755 required-opps = <&rpmhpd_opp_turbo>;
3761 videocc: clock-controller@aaf0000 {
3762 compatible = "qcom,sc7280-videocc";
3763 reg = <0 0xaaf0000 0 0x10000>;
3764 clocks = <&rpmhcc RPMH_CXO_CLK>,
3765 <&rpmhcc RPMH_CXO_CLK_A>;
3766 clock-names = "bi_tcxo", "bi_tcxo_ao";
3769 #power-domain-cells = <1>;
3772 camcc: clock-controller@ad00000 {
3773 compatible = "qcom,sc7280-camcc";
3774 reg = <0 0x0ad00000 0 0x10000>;
3775 clocks = <&rpmhcc RPMH_CXO_CLK>,
3776 <&rpmhcc RPMH_CXO_CLK_A>,
3778 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3781 #power-domain-cells = <1>;
3784 dispcc: clock-controller@af00000 {
3785 compatible = "qcom,sc7280-dispcc";
3786 reg = <0 0xaf00000 0 0x20000>;
3787 clocks = <&rpmhcc RPMH_CXO_CLK>,
3788 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3795 clock-names = "bi_tcxo",
3796 "gcc_disp_gpll0_clk",
3797 "dsi0_phy_pll_out_byteclk",
3798 "dsi0_phy_pll_out_dsiclk",
3799 "dp_phy_pll_link_clk",
3800 "dp_phy_pll_vco_div_clk",
3801 "edp_phy_pll_link_clk",
3802 "edp_phy_pll_vco_div_clk";
3805 #power-domain-cells = <1>;
3808 mdss: display-subsystem@ae00000 {
3809 compatible = "qcom,sc7280-mdss";
3810 reg = <0 0x0ae00000 0 0x1000>;
3813 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3815 clocks = <&gcc GCC_DISP_AHB_CLK>,
3816 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3817 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3818 clock-names = "iface",
3822 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3823 interrupt-controller;
3824 #interrupt-cells = <1>;
3826 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3827 interconnect-names = "mdp0-mem";
3829 iommus = <&apps_smmu 0x900 0x402>;
3831 #address-cells = <2>;
3835 status = "disabled";
3837 mdss_mdp: display-controller@ae01000 {
3838 compatible = "qcom,sc7280-dpu";
3839 reg = <0 0x0ae01000 0 0x8f030>,
3840 <0 0x0aeb0000 0 0x2008>;
3841 reg-names = "mdp", "vbif";
3843 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3844 <&gcc GCC_DISP_SF_AXI_CLK>,
3845 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3846 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3847 <&dispcc DISP_CC_MDSS_MDP_CLK>,
3848 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3849 clock-names = "bus",
3855 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3856 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3857 assigned-clock-rates = <19200000>,
3859 operating-points-v2 = <&mdp_opp_table>;
3860 power-domains = <&rpmhpd SC7280_CX>;
3862 interrupt-parent = <&mdss>;
3865 status = "disabled";
3868 #address-cells = <1>;
3873 dpu_intf1_out: endpoint {
3874 remote-endpoint = <&dsi0_in>;
3880 dpu_intf5_out: endpoint {
3881 remote-endpoint = <&edp_in>;
3887 dpu_intf0_out: endpoint {
3888 remote-endpoint = <&dp_in>;
3893 mdp_opp_table: opp-table {
3894 compatible = "operating-points-v2";
3897 opp-hz = /bits/ 64 <200000000>;
3898 required-opps = <&rpmhpd_opp_low_svs>;
3902 opp-hz = /bits/ 64 <300000000>;
3903 required-opps = <&rpmhpd_opp_svs>;
3907 opp-hz = /bits/ 64 <380000000>;
3908 required-opps = <&rpmhpd_opp_svs_l1>;
3912 opp-hz = /bits/ 64 <506666667>;
3913 required-opps = <&rpmhpd_opp_nom>;
3918 mdss_dsi: dsi@ae94000 {
3919 compatible = "qcom,mdss-dsi-ctrl";
3920 reg = <0 0x0ae94000 0 0x400>;
3921 reg-names = "dsi_ctrl";
3923 interrupt-parent = <&mdss>;
3926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3929 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3930 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3931 <&gcc GCC_DISP_HF_AXI_CLK>;
3932 clock-names = "byte",
3939 operating-points-v2 = <&dsi_opp_table>;
3940 power-domains = <&rpmhpd SC7280_CX>;
3942 phys = <&mdss_dsi_phy>;
3945 #address-cells = <1>;
3948 status = "disabled";
3951 #address-cells = <1>;
3957 remote-endpoint = <&dpu_intf1_out>;
3963 dsi0_out: endpoint {
3968 dsi_opp_table: opp-table {
3969 compatible = "operating-points-v2";
3972 opp-hz = /bits/ 64 <187500000>;
3973 required-opps = <&rpmhpd_opp_low_svs>;
3977 opp-hz = /bits/ 64 <300000000>;
3978 required-opps = <&rpmhpd_opp_svs>;
3982 opp-hz = /bits/ 64 <358000000>;
3983 required-opps = <&rpmhpd_opp_svs_l1>;
3988 mdss_dsi_phy: phy@ae94400 {
3989 compatible = "qcom,sc7280-dsi-phy-7nm";
3990 reg = <0 0x0ae94400 0 0x200>,
3991 <0 0x0ae94600 0 0x280>,
3992 <0 0x0ae94900 0 0x280>;
3993 reg-names = "dsi_phy",
4000 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4001 <&rpmhcc RPMH_CXO_CLK>;
4002 clock-names = "iface", "ref";
4004 status = "disabled";
4007 mdss_edp: edp@aea0000 {
4008 compatible = "qcom,sc7280-edp";
4009 pinctrl-names = "default";
4010 pinctrl-0 = <&edp_hot_plug_det>;
4012 reg = <0 0xaea0000 0 0x200>,
4013 <0 0xaea0200 0 0x200>,
4014 <0 0xaea0400 0 0xc00>,
4015 <0 0xaea1000 0 0x400>;
4017 interrupt-parent = <&mdss>;
4020 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4021 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
4022 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
4023 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
4024 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
4025 clock-names = "core_iface",
4030 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4031 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
4032 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4034 phys = <&mdss_edp_phy>;
4037 operating-points-v2 = <&edp_opp_table>;
4038 power-domains = <&rpmhpd SC7280_CX>;
4040 status = "disabled";
4043 #address-cells = <1>;
4049 remote-endpoint = <&dpu_intf5_out>;
4055 mdss_edp_out: endpoint { };
4059 edp_opp_table: opp-table {
4060 compatible = "operating-points-v2";
4063 opp-hz = /bits/ 64 <160000000>;
4064 required-opps = <&rpmhpd_opp_low_svs>;
4068 opp-hz = /bits/ 64 <270000000>;
4069 required-opps = <&rpmhpd_opp_svs>;
4073 opp-hz = /bits/ 64 <540000000>;
4074 required-opps = <&rpmhpd_opp_nom>;
4078 opp-hz = /bits/ 64 <810000000>;
4079 required-opps = <&rpmhpd_opp_nom>;
4084 mdss_edp_phy: phy@aec2a00 {
4085 compatible = "qcom,sc7280-edp-phy";
4087 reg = <0 0xaec2a00 0 0x19c>,
4088 <0 0xaec2200 0 0xa0>,
4089 <0 0xaec2600 0 0xa0>,
4090 <0 0xaec2000 0 0x1c0>;
4092 clocks = <&rpmhcc RPMH_CXO_CLK>,
4093 <&gcc GCC_EDP_CLKREF_EN>;
4094 clock-names = "aux",
4100 status = "disabled";
4103 mdss_dp: displayport-controller@ae90000 {
4104 compatible = "qcom,sc7280-dp";
4106 reg = <0 0xae90000 0 0x200>,
4107 <0 0xae90200 0 0x200>,
4108 <0 0xae90400 0 0xc00>,
4109 <0 0xae91000 0 0x400>,
4110 <0 0xae91400 0 0x400>;
4112 interrupt-parent = <&mdss>;
4115 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
4116 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
4117 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
4118 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
4119 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
4120 clock-names = "core_iface",
4125 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4126 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
4127 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
4131 operating-points-v2 = <&dp_opp_table>;
4132 power-domains = <&rpmhpd SC7280_CX>;
4134 #sound-dai-cells = <0>;
4136 status = "disabled";
4139 #address-cells = <1>;
4145 remote-endpoint = <&dpu_intf0_out>;
4151 dp_out: endpoint { };
4155 dp_opp_table: opp-table {
4156 compatible = "operating-points-v2";
4159 opp-hz = /bits/ 64 <160000000>;
4160 required-opps = <&rpmhpd_opp_low_svs>;
4164 opp-hz = /bits/ 64 <270000000>;
4165 required-opps = <&rpmhpd_opp_svs>;
4169 opp-hz = /bits/ 64 <540000000>;
4170 required-opps = <&rpmhpd_opp_svs_l1>;
4174 opp-hz = /bits/ 64 <810000000>;
4175 required-opps = <&rpmhpd_opp_nom>;
4181 pdc: interrupt-controller@b220000 {
4182 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4183 reg = <0 0x0b220000 0 0x30000>;
4184 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4185 <55 306 4>, <59 312 3>, <62 374 2>,
4186 <64 434 2>, <66 438 3>, <69 86 1>,
4187 <70 520 54>, <124 609 31>, <155 63 1>,
4189 #interrupt-cells = <2>;
4190 interrupt-parent = <&intc>;
4191 interrupt-controller;
4194 pdc_reset: reset-controller@b5e0000 {
4195 compatible = "qcom,sc7280-pdc-global";
4196 reg = <0 0x0b5e0000 0 0x20000>;
4200 tsens0: thermal-sensor@c263000 {
4201 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4202 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4203 <0 0x0c222000 0 0x1ff>; /* SROT */
4204 #qcom,sensors = <15>;
4205 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4206 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4207 interrupt-names = "uplow","critical";
4208 #thermal-sensor-cells = <1>;
4211 tsens1: thermal-sensor@c265000 {
4212 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4213 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4214 <0 0x0c223000 0 0x1ff>; /* SROT */
4215 #qcom,sensors = <12>;
4216 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4217 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4218 interrupt-names = "uplow","critical";
4219 #thermal-sensor-cells = <1>;
4222 aoss_reset: reset-controller@c2a0000 {
4223 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4224 reg = <0 0x0c2a0000 0 0x31000>;
4228 aoss_qmp: power-controller@c300000 {
4229 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4230 reg = <0 0x0c300000 0 0x400>;
4231 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4232 IPCC_MPROC_SIGNAL_GLINK_QMP
4233 IRQ_TYPE_EDGE_RISING>;
4234 mboxes = <&ipcc IPCC_CLIENT_AOP
4235 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4241 compatible = "qcom,rpmh-stats";
4242 reg = <0 0x0c3f0000 0 0x400>;
4245 spmi_bus: spmi@c440000 {
4246 compatible = "qcom,spmi-pmic-arb";
4247 reg = <0 0x0c440000 0 0x1100>,
4248 <0 0x0c600000 0 0x2000000>,
4249 <0 0x0e600000 0 0x100000>,
4250 <0 0x0e700000 0 0xa0000>,
4251 <0 0x0c40a000 0 0x26000>;
4252 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4253 interrupt-names = "periph_irq";
4254 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4257 #address-cells = <2>;
4259 interrupt-controller;
4260 #interrupt-cells = <4>;
4263 tlmm: pinctrl@f100000 {
4264 compatible = "qcom,sc7280-pinctrl";
4265 reg = <0 0x0f100000 0 0x300000>;
4266 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4269 interrupt-controller;
4270 #interrupt-cells = <2>;
4271 gpio-ranges = <&tlmm 0 0 175>;
4272 wakeup-parent = <&pdc>;
4274 dp_hot_plug_det: dp-hot-plug-det-pins {
4276 function = "dp_hot";
4279 edp_hot_plug_det: edp-hot-plug-det-pins {
4281 function = "edp_hot";
4284 mi2s0_data0: mi2s0-data0-pins {
4286 function = "mi2s0_data0";
4289 mi2s0_data1: mi2s0-data1-pins {
4291 function = "mi2s0_data1";
4294 mi2s0_mclk: mi2s0-mclk-pins {
4296 function = "pri_mi2s";
4299 mi2s0_sclk: mi2s0-sclk-pins {
4301 function = "mi2s0_sck";
4304 mi2s0_ws: mi2s0-ws-pins {
4306 function = "mi2s0_ws";
4309 mi2s1_data0: mi2s1-data0-pins {
4311 function = "mi2s1_data0";
4314 mi2s1_sclk: mi2s1-sclk-pins {
4316 function = "mi2s1_sck";
4319 mi2s1_ws: mi2s1-ws-pins {
4321 function = "mi2s1_ws";
4324 pcie1_clkreq_n: pcie1-clkreq-n-pins {
4326 function = "pcie1_clkreqn";
4329 qspi_clk: qspi-clk-pins {
4331 function = "qspi_clk";
4334 qspi_cs0: qspi-cs0-pins {
4336 function = "qspi_cs";
4339 qspi_cs1: qspi-cs1-pins {
4341 function = "qspi_cs";
4344 qspi_data01: qspi-data01-pins {
4345 pins = "gpio12", "gpio13";
4346 function = "qspi_data";
4349 qspi_data23: qspi-data23-pins {
4350 pins = "gpio16", "gpio17";
4351 function = "qspi_data";
4354 qup_i2c0_data_clk: qup-i2c0-data-clk-pins {
4355 pins = "gpio0", "gpio1";
4359 qup_i2c1_data_clk: qup-i2c1-data-clk-pins {
4360 pins = "gpio4", "gpio5";
4364 qup_i2c2_data_clk: qup-i2c2-data-clk-pins {
4365 pins = "gpio8", "gpio9";
4369 qup_i2c3_data_clk: qup-i2c3-data-clk-pins {
4370 pins = "gpio12", "gpio13";
4374 qup_i2c4_data_clk: qup-i2c4-data-clk-pins {
4375 pins = "gpio16", "gpio17";
4379 qup_i2c5_data_clk: qup-i2c5-data-clk-pins {
4380 pins = "gpio20", "gpio21";
4384 qup_i2c6_data_clk: qup-i2c6-data-clk-pins {
4385 pins = "gpio24", "gpio25";
4389 qup_i2c7_data_clk: qup-i2c7-data-clk-pins {
4390 pins = "gpio28", "gpio29";
4394 qup_i2c8_data_clk: qup-i2c8-data-clk-pins {
4395 pins = "gpio32", "gpio33";
4399 qup_i2c9_data_clk: qup-i2c9-data-clk-pins {
4400 pins = "gpio36", "gpio37";
4404 qup_i2c10_data_clk: qup-i2c10-data-clk-pins {
4405 pins = "gpio40", "gpio41";
4409 qup_i2c11_data_clk: qup-i2c11-data-clk-pins {
4410 pins = "gpio44", "gpio45";
4414 qup_i2c12_data_clk: qup-i2c12-data-clk-pins {
4415 pins = "gpio48", "gpio49";
4419 qup_i2c13_data_clk: qup-i2c13-data-clk-pins {
4420 pins = "gpio52", "gpio53";
4424 qup_i2c14_data_clk: qup-i2c14-data-clk-pins {
4425 pins = "gpio56", "gpio57";
4429 qup_i2c15_data_clk: qup-i2c15-data-clk-pins {
4430 pins = "gpio60", "gpio61";
4434 qup_spi0_data_clk: qup-spi0-data-clk-pins {
4435 pins = "gpio0", "gpio1", "gpio2";
4439 qup_spi0_cs: qup-spi0-cs-pins {
4444 qup_spi0_cs_gpio: qup-spi0-cs-gpio-pins {
4449 qup_spi1_data_clk: qup-spi1-data-clk-pins {
4450 pins = "gpio4", "gpio5", "gpio6";
4454 qup_spi1_cs: qup-spi1-cs-pins {
4459 qup_spi1_cs_gpio: qup-spi1-cs-gpio-pins {
4464 qup_spi2_data_clk: qup-spi2-data-clk-pins {
4465 pins = "gpio8", "gpio9", "gpio10";
4469 qup_spi2_cs: qup-spi2-cs-pins {
4474 qup_spi2_cs_gpio: qup-spi2-cs-gpio-pins {
4479 qup_spi3_data_clk: qup-spi3-data-clk-pins {
4480 pins = "gpio12", "gpio13", "gpio14";
4484 qup_spi3_cs: qup-spi3-cs-pins {
4489 qup_spi3_cs_gpio: qup-spi3-cs-gpio-pins {
4494 qup_spi4_data_clk: qup-spi4-data-clk-pins {
4495 pins = "gpio16", "gpio17", "gpio18";
4499 qup_spi4_cs: qup-spi4-cs-pins {
4504 qup_spi4_cs_gpio: qup-spi4-cs-gpio-pins {
4509 qup_spi5_data_clk: qup-spi5-data-clk-pins {
4510 pins = "gpio20", "gpio21", "gpio22";
4514 qup_spi5_cs: qup-spi5-cs-pins {
4519 qup_spi5_cs_gpio: qup-spi5-cs-gpio-pins {
4524 qup_spi6_data_clk: qup-spi6-data-clk-pins {
4525 pins = "gpio24", "gpio25", "gpio26";
4529 qup_spi6_cs: qup-spi6-cs-pins {
4534 qup_spi6_cs_gpio: qup-spi6-cs-gpio-pins {
4539 qup_spi7_data_clk: qup-spi7-data-clk-pins {
4540 pins = "gpio28", "gpio29", "gpio30";
4544 qup_spi7_cs: qup-spi7-cs-pins {
4549 qup_spi7_cs_gpio: qup-spi7-cs-gpio-pins {
4554 qup_spi8_data_clk: qup-spi8-data-clk-pins {
4555 pins = "gpio32", "gpio33", "gpio34";
4559 qup_spi8_cs: qup-spi8-cs-pins {
4564 qup_spi8_cs_gpio: qup-spi8-cs-gpio-pins {
4569 qup_spi9_data_clk: qup-spi9-data-clk-pins {
4570 pins = "gpio36", "gpio37", "gpio38";
4574 qup_spi9_cs: qup-spi9-cs-pins {
4579 qup_spi9_cs_gpio: qup-spi9-cs-gpio-pins {
4584 qup_spi10_data_clk: qup-spi10-data-clk-pins {
4585 pins = "gpio40", "gpio41", "gpio42";
4589 qup_spi10_cs: qup-spi10-cs-pins {
4594 qup_spi10_cs_gpio: qup-spi10-cs-gpio-pins {
4599 qup_spi11_data_clk: qup-spi11-data-clk-pins {
4600 pins = "gpio44", "gpio45", "gpio46";
4604 qup_spi11_cs: qup-spi11-cs-pins {
4609 qup_spi11_cs_gpio: qup-spi11-cs-gpio-pins {
4614 qup_spi12_data_clk: qup-spi12-data-clk-pins {
4615 pins = "gpio48", "gpio49", "gpio50";
4619 qup_spi12_cs: qup-spi12-cs-pins {
4624 qup_spi12_cs_gpio: qup-spi12-cs-gpio-pins {
4629 qup_spi13_data_clk: qup-spi13-data-clk-pins {
4630 pins = "gpio52", "gpio53", "gpio54";
4634 qup_spi13_cs: qup-spi13-cs-pins {
4639 qup_spi13_cs_gpio: qup-spi13-cs-gpio-pins {
4644 qup_spi14_data_clk: qup-spi14-data-clk-pins {
4645 pins = "gpio56", "gpio57", "gpio58";
4649 qup_spi14_cs: qup-spi14-cs-pins {
4654 qup_spi14_cs_gpio: qup-spi14-cs-gpio-pins {
4659 qup_spi15_data_clk: qup-spi15-data-clk-pins {
4660 pins = "gpio60", "gpio61", "gpio62";
4664 qup_spi15_cs: qup-spi15-cs-pins {
4669 qup_spi15_cs_gpio: qup-spi15-cs-gpio-pins {
4674 qup_uart0_cts: qup-uart0-cts-pins {
4679 qup_uart0_rts: qup-uart0-rts-pins {
4684 qup_uart0_tx: qup-uart0-tx-pins {
4689 qup_uart0_rx: qup-uart0-rx-pins {
4694 qup_uart1_cts: qup-uart1-cts-pins {
4699 qup_uart1_rts: qup-uart1-rts-pins {
4704 qup_uart1_tx: qup-uart1-tx-pins {
4709 qup_uart1_rx: qup-uart1-rx-pins {
4714 qup_uart2_cts: qup-uart2-cts-pins {
4719 qup_uart2_rts: qup-uart2-rts-pins {
4724 qup_uart2_tx: qup-uart2-tx-pins {
4729 qup_uart2_rx: qup-uart2-rx-pins {
4734 qup_uart3_cts: qup-uart3-cts-pins {
4739 qup_uart3_rts: qup-uart3-rts-pins {
4744 qup_uart3_tx: qup-uart3-tx-pins {
4749 qup_uart3_rx: qup-uart3-rx-pins {
4754 qup_uart4_cts: qup-uart4-cts-pins {
4759 qup_uart4_rts: qup-uart4-rts-pins {
4764 qup_uart4_tx: qup-uart4-tx-pins {
4769 qup_uart4_rx: qup-uart4-rx-pins {
4774 qup_uart5_cts: qup-uart5-cts-pins {
4779 qup_uart5_rts: qup-uart5-rts-pins {
4784 qup_uart5_tx: qup-uart5-tx-pins {
4789 qup_uart5_rx: qup-uart5-rx-pins {
4794 qup_uart6_cts: qup-uart6-cts-pins {
4799 qup_uart6_rts: qup-uart6-rts-pins {
4804 qup_uart6_tx: qup-uart6-tx-pins {
4809 qup_uart6_rx: qup-uart6-rx-pins {
4814 qup_uart7_cts: qup-uart7-cts-pins {
4819 qup_uart7_rts: qup-uart7-rts-pins {
4824 qup_uart7_tx: qup-uart7-tx-pins {
4829 qup_uart7_rx: qup-uart7-rx-pins {
4834 qup_uart8_cts: qup-uart8-cts-pins {
4839 qup_uart8_rts: qup-uart8-rts-pins {
4844 qup_uart8_tx: qup-uart8-tx-pins {
4849 qup_uart8_rx: qup-uart8-rx-pins {
4854 qup_uart9_cts: qup-uart9-cts-pins {
4859 qup_uart9_rts: qup-uart9-rts-pins {
4864 qup_uart9_tx: qup-uart9-tx-pins {
4869 qup_uart9_rx: qup-uart9-rx-pins {
4874 qup_uart10_cts: qup-uart10-cts-pins {
4879 qup_uart10_rts: qup-uart10-rts-pins {
4884 qup_uart10_tx: qup-uart10-tx-pins {
4889 qup_uart10_rx: qup-uart10-rx-pins {
4894 qup_uart11_cts: qup-uart11-cts-pins {
4899 qup_uart11_rts: qup-uart11-rts-pins {
4904 qup_uart11_tx: qup-uart11-tx-pins {
4909 qup_uart11_rx: qup-uart11-rx-pins {
4914 qup_uart12_cts: qup-uart12-cts-pins {
4919 qup_uart12_rts: qup-uart12-rts-pins {
4924 qup_uart12_tx: qup-uart12-tx-pins {
4929 qup_uart12_rx: qup-uart12-rx-pins {
4934 qup_uart13_cts: qup-uart13-cts-pins {
4939 qup_uart13_rts: qup-uart13-rts-pins {
4944 qup_uart13_tx: qup-uart13-tx-pins {
4949 qup_uart13_rx: qup-uart13-rx-pins {
4954 qup_uart14_cts: qup-uart14-cts-pins {
4959 qup_uart14_rts: qup-uart14-rts-pins {
4964 qup_uart14_tx: qup-uart14-tx-pins {
4969 qup_uart14_rx: qup-uart14-rx-pins {
4974 qup_uart15_cts: qup-uart15-cts-pins {
4979 qup_uart15_rts: qup-uart15-rts-pins {
4984 qup_uart15_tx: qup-uart15-tx-pins {
4989 qup_uart15_rx: qup-uart15-rx-pins {
4994 sdc1_clk: sdc1-clk-pins {
4998 sdc1_cmd: sdc1-cmd-pins {
5002 sdc1_data: sdc1-data-pins {
5006 sdc1_rclk: sdc1-rclk-pins {
5010 sdc1_clk_sleep: sdc1-clk-sleep-pins {
5012 drive-strength = <2>;
5016 sdc1_cmd_sleep: sdc1-cmd-sleep-pins {
5018 drive-strength = <2>;
5022 sdc1_data_sleep: sdc1-data-sleep-pins {
5024 drive-strength = <2>;
5028 sdc1_rclk_sleep: sdc1-rclk-sleep-pins {
5030 drive-strength = <2>;
5034 sdc2_clk: sdc2-clk-pins {
5038 sdc2_cmd: sdc2-cmd-pins {
5042 sdc2_data: sdc2-data-pins {
5046 sdc2_clk_sleep: sdc2-clk-sleep-pins {
5048 drive-strength = <2>;
5052 sdc2_cmd_sleep: sdc2-cmd-sleep-pins {
5054 drive-strength = <2>;
5058 sdc2_data_sleep: sdc2-data-sleep-pins {
5060 drive-strength = <2>;
5066 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5067 reg = <0 0x146a5000 0 0x6000>;
5069 #address-cells = <1>;
5072 ranges = <0 0 0x146a5000 0x6000>;
5075 compatible = "qcom,pil-reloc-info";
5076 reg = <0x594c 0xc8>;
5080 apps_smmu: iommu@15000000 {
5081 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5082 reg = <0 0x15000000 0 0x100000>;
5084 #global-interrupts = <1>;
5086 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
5087 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
5088 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
5089 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
5090 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
5091 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
5092 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
5093 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
5094 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
5095 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
5096 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
5097 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
5098 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
5099 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
5100 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
5101 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
5102 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
5103 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
5104 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
5105 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
5106 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
5107 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
5108 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
5109 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
5110 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
5111 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
5112 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
5113 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
5114 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
5115 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
5116 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
5117 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
5118 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
5119 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
5120 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
5121 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
5122 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
5123 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
5124 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
5125 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
5126 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
5127 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
5128 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
5129 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
5130 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
5131 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
5132 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
5133 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
5134 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
5135 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
5136 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
5137 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
5138 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
5139 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
5140 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
5141 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
5142 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
5143 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
5144 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
5145 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
5146 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
5147 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
5148 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
5149 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
5150 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
5151 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
5152 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
5153 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
5154 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
5155 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
5156 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
5157 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
5158 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
5159 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
5160 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
5161 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
5162 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
5163 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
5164 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
5165 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
5166 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
5169 intc: interrupt-controller@17a00000 {
5170 compatible = "arm,gic-v3";
5171 #address-cells = <2>;
5174 #interrupt-cells = <3>;
5175 interrupt-controller;
5176 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5177 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5178 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
5181 compatible = "arm,gic-v3-its";
5184 reg = <0 0x17a40000 0 0x20000>;
5185 status = "disabled";
5190 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5191 reg = <0 0x17c10000 0 0x1000>;
5192 clocks = <&sleep_clk>;
5193 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
5197 #address-cells = <1>;
5199 ranges = <0 0 0 0x20000000>;
5200 compatible = "arm,armv7-timer-mem";
5201 reg = <0 0x17c20000 0 0x1000>;
5205 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
5206 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
5207 reg = <0x17c21000 0x1000>,
5208 <0x17c22000 0x1000>;
5213 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
5214 reg = <0x17c23000 0x1000>;
5215 status = "disabled";
5220 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
5221 reg = <0x17c25000 0x1000>;
5222 status = "disabled";
5227 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
5228 reg = <0x17c27000 0x1000>;
5229 status = "disabled";
5234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
5235 reg = <0x17c29000 0x1000>;
5236 status = "disabled";
5241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
5242 reg = <0x17c2b000 0x1000>;
5243 status = "disabled";
5248 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
5249 reg = <0x17c2d000 0x1000>;
5250 status = "disabled";
5254 apps_rsc: rsc@18200000 {
5255 compatible = "qcom,rpmh-rsc";
5256 reg = <0 0x18200000 0 0x10000>,
5257 <0 0x18210000 0 0x10000>,
5258 <0 0x18220000 0 0x10000>;
5259 reg-names = "drv-0", "drv-1", "drv-2";
5260 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
5261 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
5262 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
5263 qcom,tcs-offset = <0xd00>;
5265 qcom,tcs-config = <ACTIVE_TCS 2>,
5270 apps_bcm_voter: bcm-voter {
5271 compatible = "qcom,bcm-voter";
5274 rpmhpd: power-controller {
5275 compatible = "qcom,sc7280-rpmhpd";
5276 #power-domain-cells = <1>;
5277 operating-points-v2 = <&rpmhpd_opp_table>;
5279 rpmhpd_opp_table: opp-table {
5280 compatible = "operating-points-v2";
5282 rpmhpd_opp_ret: opp1 {
5283 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5286 rpmhpd_opp_low_svs: opp2 {
5287 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5290 rpmhpd_opp_svs: opp3 {
5291 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5294 rpmhpd_opp_svs_l1: opp4 {
5295 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5298 rpmhpd_opp_svs_l2: opp5 {
5299 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5302 rpmhpd_opp_nom: opp6 {
5303 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5306 rpmhpd_opp_nom_l1: opp7 {
5307 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5310 rpmhpd_opp_turbo: opp8 {
5311 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5314 rpmhpd_opp_turbo_l1: opp9 {
5315 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5320 rpmhcc: clock-controller {
5321 compatible = "qcom,sc7280-rpmh-clk";
5322 clocks = <&xo_board>;
5328 epss_l3: interconnect@18590000 {
5329 compatible = "qcom,sc7280-epss-l3";
5330 reg = <0 0x18590000 0 0x1000>;
5331 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5332 clock-names = "xo", "alternate";
5333 #interconnect-cells = <1>;
5336 cpufreq_hw: cpufreq@18591000 {
5337 compatible = "qcom,cpufreq-epss";
5338 reg = <0 0x18591000 0 0x1000>,
5339 <0 0x18592000 0 0x1000>,
5340 <0 0x18593000 0 0x1000>;
5341 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5342 clock-names = "xo", "alternate";
5343 #freq-domain-cells = <1>;
5347 thermal_zones: thermal-zones {
5349 polling-delay-passive = <250>;
5350 polling-delay = <0>;
5352 thermal-sensors = <&tsens0 1>;
5355 cpu0_alert0: trip-point0 {
5356 temperature = <90000>;
5357 hysteresis = <2000>;
5361 cpu0_alert1: trip-point1 {
5362 temperature = <95000>;
5363 hysteresis = <2000>;
5367 cpu0_crit: cpu-crit {
5368 temperature = <110000>;
5376 trip = <&cpu0_alert0>;
5377 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5378 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5379 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5380 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5383 trip = <&cpu0_alert1>;
5384 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5385 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5386 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5387 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5393 polling-delay-passive = <250>;
5394 polling-delay = <0>;
5396 thermal-sensors = <&tsens0 2>;
5399 cpu1_alert0: trip-point0 {
5400 temperature = <90000>;
5401 hysteresis = <2000>;
5405 cpu1_alert1: trip-point1 {
5406 temperature = <95000>;
5407 hysteresis = <2000>;
5411 cpu1_crit: cpu-crit {
5412 temperature = <110000>;
5420 trip = <&cpu1_alert0>;
5421 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5422 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5423 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5424 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5427 trip = <&cpu1_alert1>;
5428 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5429 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5430 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5431 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5437 polling-delay-passive = <250>;
5438 polling-delay = <0>;
5440 thermal-sensors = <&tsens0 3>;
5443 cpu2_alert0: trip-point0 {
5444 temperature = <90000>;
5445 hysteresis = <2000>;
5449 cpu2_alert1: trip-point1 {
5450 temperature = <95000>;
5451 hysteresis = <2000>;
5455 cpu2_crit: cpu-crit {
5456 temperature = <110000>;
5464 trip = <&cpu2_alert0>;
5465 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5466 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5467 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5468 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5471 trip = <&cpu2_alert1>;
5472 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5473 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5474 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5475 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5481 polling-delay-passive = <250>;
5482 polling-delay = <0>;
5484 thermal-sensors = <&tsens0 4>;
5487 cpu3_alert0: trip-point0 {
5488 temperature = <90000>;
5489 hysteresis = <2000>;
5493 cpu3_alert1: trip-point1 {
5494 temperature = <95000>;
5495 hysteresis = <2000>;
5499 cpu3_crit: cpu-crit {
5500 temperature = <110000>;
5508 trip = <&cpu3_alert0>;
5509 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5510 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5511 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5512 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5515 trip = <&cpu3_alert1>;
5516 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5517 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5518 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5519 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5525 polling-delay-passive = <250>;
5526 polling-delay = <0>;
5528 thermal-sensors = <&tsens0 7>;
5531 cpu4_alert0: trip-point0 {
5532 temperature = <90000>;
5533 hysteresis = <2000>;
5537 cpu4_alert1: trip-point1 {
5538 temperature = <95000>;
5539 hysteresis = <2000>;
5543 cpu4_crit: cpu-crit {
5544 temperature = <110000>;
5552 trip = <&cpu4_alert0>;
5553 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5554 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5555 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5556 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5559 trip = <&cpu4_alert1>;
5560 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5561 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5562 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5563 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5569 polling-delay-passive = <250>;
5570 polling-delay = <0>;
5572 thermal-sensors = <&tsens0 8>;
5575 cpu5_alert0: trip-point0 {
5576 temperature = <90000>;
5577 hysteresis = <2000>;
5581 cpu5_alert1: trip-point1 {
5582 temperature = <95000>;
5583 hysteresis = <2000>;
5587 cpu5_crit: cpu-crit {
5588 temperature = <110000>;
5596 trip = <&cpu5_alert0>;
5597 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5598 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5599 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5600 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5603 trip = <&cpu5_alert1>;
5604 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5605 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5606 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5607 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5613 polling-delay-passive = <250>;
5614 polling-delay = <0>;
5616 thermal-sensors = <&tsens0 9>;
5619 cpu6_alert0: trip-point0 {
5620 temperature = <90000>;
5621 hysteresis = <2000>;
5625 cpu6_alert1: trip-point1 {
5626 temperature = <95000>;
5627 hysteresis = <2000>;
5631 cpu6_crit: cpu-crit {
5632 temperature = <110000>;
5640 trip = <&cpu6_alert0>;
5641 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5642 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5643 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5644 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5647 trip = <&cpu6_alert1>;
5648 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5650 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5651 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5657 polling-delay-passive = <250>;
5658 polling-delay = <0>;
5660 thermal-sensors = <&tsens0 10>;
5663 cpu7_alert0: trip-point0 {
5664 temperature = <90000>;
5665 hysteresis = <2000>;
5669 cpu7_alert1: trip-point1 {
5670 temperature = <95000>;
5671 hysteresis = <2000>;
5675 cpu7_crit: cpu-crit {
5676 temperature = <110000>;
5684 trip = <&cpu7_alert0>;
5685 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5686 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5687 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5688 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5691 trip = <&cpu7_alert1>;
5692 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5693 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5694 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5695 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5701 polling-delay-passive = <250>;
5702 polling-delay = <0>;
5704 thermal-sensors = <&tsens0 11>;
5707 cpu8_alert0: trip-point0 {
5708 temperature = <90000>;
5709 hysteresis = <2000>;
5713 cpu8_alert1: trip-point1 {
5714 temperature = <95000>;
5715 hysteresis = <2000>;
5719 cpu8_crit: cpu-crit {
5720 temperature = <110000>;
5728 trip = <&cpu8_alert0>;
5729 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5730 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5731 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5732 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5735 trip = <&cpu8_alert1>;
5736 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5737 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5738 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5739 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5745 polling-delay-passive = <250>;
5746 polling-delay = <0>;
5748 thermal-sensors = <&tsens0 12>;
5751 cpu9_alert0: trip-point0 {
5752 temperature = <90000>;
5753 hysteresis = <2000>;
5757 cpu9_alert1: trip-point1 {
5758 temperature = <95000>;
5759 hysteresis = <2000>;
5763 cpu9_crit: cpu-crit {
5764 temperature = <110000>;
5772 trip = <&cpu9_alert0>;
5773 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5774 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5775 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5776 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5779 trip = <&cpu9_alert1>;
5780 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5782 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5783 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5789 polling-delay-passive = <250>;
5790 polling-delay = <0>;
5792 thermal-sensors = <&tsens0 13>;
5795 cpu10_alert0: trip-point0 {
5796 temperature = <90000>;
5797 hysteresis = <2000>;
5801 cpu10_alert1: trip-point1 {
5802 temperature = <95000>;
5803 hysteresis = <2000>;
5807 cpu10_crit: cpu-crit {
5808 temperature = <110000>;
5816 trip = <&cpu10_alert0>;
5817 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5818 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5819 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5820 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5823 trip = <&cpu10_alert1>;
5824 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5825 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5826 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5827 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5833 polling-delay-passive = <250>;
5834 polling-delay = <0>;
5836 thermal-sensors = <&tsens0 14>;
5839 cpu11_alert0: trip-point0 {
5840 temperature = <90000>;
5841 hysteresis = <2000>;
5845 cpu11_alert1: trip-point1 {
5846 temperature = <95000>;
5847 hysteresis = <2000>;
5851 cpu11_crit: cpu-crit {
5852 temperature = <110000>;
5860 trip = <&cpu11_alert0>;
5861 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5862 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5863 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5864 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5867 trip = <&cpu11_alert1>;
5868 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5869 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5870 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5871 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5877 polling-delay-passive = <0>;
5878 polling-delay = <0>;
5880 thermal-sensors = <&tsens0 0>;
5883 aoss0_alert0: trip-point0 {
5884 temperature = <90000>;
5885 hysteresis = <2000>;
5889 aoss0_crit: aoss0-crit {
5890 temperature = <110000>;
5898 polling-delay-passive = <0>;
5899 polling-delay = <0>;
5901 thermal-sensors = <&tsens1 0>;
5904 aoss1_alert0: trip-point0 {
5905 temperature = <90000>;
5906 hysteresis = <2000>;
5910 aoss1_crit: aoss1-crit {
5911 temperature = <110000>;
5919 polling-delay-passive = <0>;
5920 polling-delay = <0>;
5922 thermal-sensors = <&tsens0 5>;
5925 cpuss0_alert0: trip-point0 {
5926 temperature = <90000>;
5927 hysteresis = <2000>;
5930 cpuss0_crit: cluster0-crit {
5931 temperature = <110000>;
5939 polling-delay-passive = <0>;
5940 polling-delay = <0>;
5942 thermal-sensors = <&tsens0 6>;
5945 cpuss1_alert0: trip-point0 {
5946 temperature = <90000>;
5947 hysteresis = <2000>;
5950 cpuss1_crit: cluster0-crit {
5951 temperature = <110000>;
5959 polling-delay-passive = <100>;
5960 polling-delay = <0>;
5962 thermal-sensors = <&tsens1 1>;
5965 gpuss0_alert0: trip-point0 {
5966 temperature = <95000>;
5967 hysteresis = <2000>;
5971 gpuss0_crit: gpuss0-crit {
5972 temperature = <110000>;
5980 trip = <&gpuss0_alert0>;
5981 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5987 polling-delay-passive = <100>;
5988 polling-delay = <0>;
5990 thermal-sensors = <&tsens1 2>;
5993 gpuss1_alert0: trip-point0 {
5994 temperature = <95000>;
5995 hysteresis = <2000>;
5999 gpuss1_crit: gpuss1-crit {
6000 temperature = <110000>;
6008 trip = <&gpuss1_alert0>;
6009 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6015 polling-delay-passive = <0>;
6016 polling-delay = <0>;
6018 thermal-sensors = <&tsens1 3>;
6021 nspss0_alert0: trip-point0 {
6022 temperature = <90000>;
6023 hysteresis = <2000>;
6027 nspss0_crit: nspss0-crit {
6028 temperature = <110000>;
6036 polling-delay-passive = <0>;
6037 polling-delay = <0>;
6039 thermal-sensors = <&tsens1 4>;
6042 nspss1_alert0: trip-point0 {
6043 temperature = <90000>;
6044 hysteresis = <2000>;
6048 nspss1_crit: nspss1-crit {
6049 temperature = <110000>;
6057 polling-delay-passive = <0>;
6058 polling-delay = <0>;
6060 thermal-sensors = <&tsens1 5>;
6063 video_alert0: trip-point0 {
6064 temperature = <90000>;
6065 hysteresis = <2000>;
6069 video_crit: video-crit {
6070 temperature = <110000>;
6078 polling-delay-passive = <0>;
6079 polling-delay = <0>;
6081 thermal-sensors = <&tsens1 6>;
6084 ddr_alert0: trip-point0 {
6085 temperature = <90000>;
6086 hysteresis = <2000>;
6090 ddr_crit: ddr-crit {
6091 temperature = <110000>;
6099 polling-delay-passive = <0>;
6100 polling-delay = <0>;
6102 thermal-sensors = <&tsens1 7>;
6105 mdmss0_alert0: trip-point0 {
6106 temperature = <90000>;
6107 hysteresis = <2000>;
6111 mdmss0_crit: mdmss0-crit {
6112 temperature = <110000>;
6120 polling-delay-passive = <0>;
6121 polling-delay = <0>;
6123 thermal-sensors = <&tsens1 8>;
6126 mdmss1_alert0: trip-point0 {
6127 temperature = <90000>;
6128 hysteresis = <2000>;
6132 mdmss1_crit: mdmss1-crit {
6133 temperature = <110000>;
6141 polling-delay-passive = <0>;
6142 polling-delay = <0>;
6144 thermal-sensors = <&tsens1 9>;
6147 mdmss2_alert0: trip-point0 {
6148 temperature = <90000>;
6149 hysteresis = <2000>;
6153 mdmss2_crit: mdmss2-crit {
6154 temperature = <110000>;
6162 polling-delay-passive = <0>;
6163 polling-delay = <0>;
6165 thermal-sensors = <&tsens1 10>;
6168 mdmss3_alert0: trip-point0 {
6169 temperature = <90000>;
6170 hysteresis = <2000>;
6174 mdmss3_crit: mdmss3-crit {
6175 temperature = <110000>;
6183 polling-delay-passive = <0>;
6184 polling-delay = <0>;
6186 thermal-sensors = <&tsens1 11>;
6189 camera0_alert0: trip-point0 {
6190 temperature = <90000>;
6191 hysteresis = <2000>;
6195 camera0_crit: camera0-crit {
6196 temperature = <110000>;
6205 compatible = "arm,armv8-timer";
6206 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
6207 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
6208 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
6209 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;