arch/arm64/boot/dts/qcom/sc7280.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * sc7280 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   6  */
   7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
   8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
  11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
  12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
  13 #include <dt-bindings/clock/qcom,rpmh.h>
  14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
  15 #include <dt-bindings/dma/qcom-gpi.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  18 #include <dt-bindings/interconnect/qcom,sc7280.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/mailbox/qcom-ipcc.h>
  21 #include <dt-bindings/power/qcom-rpmpd.h>
  22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  25 #include <dt-bindings/thermal/thermal.h>
  26
  27 / {
  28         interrupt-parent = <&intc>;
  29
  30         #address-cells = <2>;
  31         #size-cells = <2>;
  32
  33         chosen { };
  34
  35         aliases {
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 i2c12 = &i2c12;
  49                 i2c13 = &i2c13;
  50                 i2c14 = &i2c14;
  51                 i2c15 = &i2c15;
  52                 mmc1 = &sdhc_1;
  53                 mmc2 = &sdhc_2;
  54                 spi0 = &spi0;
  55                 spi1 = &spi1;
  56                 spi2 = &spi2;
  57                 spi3 = &spi3;
  58                 spi4 = &spi4;
  59                 spi5 = &spi5;
  60                 spi6 = &spi6;
  61                 spi7 = &spi7;
  62                 spi8 = &spi8;
  63                 spi9 = &spi9;
  64                 spi10 = &spi10;
  65                 spi11 = &spi11;
  66                 spi12 = &spi12;
  67                 spi13 = &spi13;
  68                 spi14 = &spi14;
  69                 spi15 = &spi15;
  70         };
  71
  72         clocks {
  73                 xo_board: xo-board {
  74                         compatible = "fixed-clock";
  75                         clock-frequency = <76800000>;
  76                         #clock-cells = <0>;
  77                 };
  78
  79                 sleep_clk: sleep-clk {
  80                         compatible = "fixed-clock";
  81                         clock-frequency = <32000>;
  82                         #clock-cells = <0>;
  83                 };
  84         };
  85
  86         reserved-memory {
  87                 #address-cells = <2>;
  88                 #size-cells = <2>;
  89                 ranges;
  90
  91                 wlan_ce_mem: memory@4cd000 {
  92                         no-map;
  93                         reg = <0x0 0x004cd000 0x0 0x1000>;
  94                 };
  95
  96                 hyp_mem: memory@80000000 {
  97                         reg = <0x0 0x80000000 0x0 0x600000>;
  98                         no-map;
  99                 };
 100
 101                 xbl_mem: memory@80600000 {
 102                         reg = <0x0 0x80600000 0x0 0x200000>;
 103                         no-map;
 104                 };
 105
 106                 aop_mem: memory@80800000 {
 107                         reg = <0x0 0x80800000 0x0 0x60000>;
 108                         no-map;
 109                 };
 110
 111                 aop_cmd_db_mem: memory@80860000 {
 112                         reg = <0x0 0x80860000 0x0 0x20000>;
 113                         compatible = "qcom,cmd-db";
 114                         no-map;
 115                 };
 116
 117                 reserved_xbl_uefi_log: memory@80880000 {
 118                         reg = <0x0 0x80884000 0x0 0x10000>;
 119                         no-map;
 120                 };
 121
 122                 sec_apps_mem: memory@808ff000 {
 123                         reg = <0x0 0x808ff000 0x0 0x1000>;
 124                         no-map;
 125                 };
 126
 127                 smem_mem: memory@80900000 {
 128                         reg = <0x0 0x80900000 0x0 0x200000>;
 129                         no-map;
 130                 };
 131
 132                 cpucp_mem: memory@80b00000 {
 133                         no-map;
 134                         reg = <0x0 0x80b00000 0x0 0x100000>;
 135                 };
 136
 137                 wlan_fw_mem: memory@80c00000 {
 138                         reg = <0x0 0x80c00000 0x0 0xc00000>;
 139                         no-map;
 140                 };
 141
 142                 video_mem: memory@8b200000 {
 143                         reg = <0x0 0x8b200000 0x0 0x500000>;
 144                         no-map;
 145                 };
 146
 147                 ipa_fw_mem: memory@8b700000 {
 148                         reg = <0 0x8b700000 0 0x10000>;
 149                         no-map;
 150                 };
 151
 152                 rmtfs_mem: memory@9c900000 {
 153                         compatible = "qcom,rmtfs-mem";
 154                         reg = <0x0 0x9c900000 0x0 0x280000>;
 155                         no-map;
 156
 157                         qcom,client-id = <1>;
 158                         qcom,vmid = <15>;
 159                 };
 160         };
 161
 162         cpus {
 163                 #address-cells = <2>;
 164                 #size-cells = <0>;
 165
 166                 CPU0: cpu@0 {
 167                         device_type = "cpu";
 168                         compatible = "arm,kryo";
 169                         reg = <0x0 0x0>;
 170                         enable-method = "psci";
 171                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 172                                            &LITTLE_CPU_SLEEP_1
 173                                            &CLUSTER_SLEEP_0>;
 174                         next-level-cache = <&L2_0>;
 175                         operating-points-v2 = <&cpu0_opp_table>;
 176                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 177                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 178                         qcom,freq-domain = <&cpufreq_hw 0>;
 179                         #cooling-cells = <2>;
 180                         L2_0: l2-cache {
 181                                 compatible = "cache";
 182                                 next-level-cache = <&L3_0>;
 183                                 L3_0: l3-cache {
 184                                         compatible = "cache";
 185                                 };
 186                         };
 187                 };
 188
 189                 CPU1: cpu@100 {
 190                         device_type = "cpu";
 191                         compatible = "arm,kryo";
 192                         reg = <0x0 0x100>;
 193                         enable-method = "psci";
 194                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 195                                            &LITTLE_CPU_SLEEP_1
 196                                            &CLUSTER_SLEEP_0>;
 197                         next-level-cache = <&L2_100>;
 198                         operating-points-v2 = <&cpu0_opp_table>;
 199                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 200                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 201                         qcom,freq-domain = <&cpufreq_hw 0>;
 202                         #cooling-cells = <2>;
 203                         L2_100: l2-cache {
 204                                 compatible = "cache";
 205                                 next-level-cache = <&L3_0>;
 206                         };
 207                 };
 208
 209                 CPU2: cpu@200 {
 210                         device_type = "cpu";
 211                         compatible = "arm,kryo";
 212                         reg = <0x0 0x200>;
 213                         enable-method = "psci";
 214                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 215                                            &LITTLE_CPU_SLEEP_1
 216                                            &CLUSTER_SLEEP_0>;
 217                         next-level-cache = <&L2_200>;
 218                         operating-points-v2 = <&cpu0_opp_table>;
 219                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 220                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 221                         qcom,freq-domain = <&cpufreq_hw 0>;
 222                         #cooling-cells = <2>;
 223                         L2_200: l2-cache {
 224                                 compatible = "cache";
 225                                 next-level-cache = <&L3_0>;
 226                         };
 227                 };
 228
 229                 CPU3: cpu@300 {
 230                         device_type = "cpu";
 231                         compatible = "arm,kryo";
 232                         reg = <0x0 0x300>;
 233                         enable-method = "psci";
 234                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 235                                            &LITTLE_CPU_SLEEP_1
 236                                            &CLUSTER_SLEEP_0>;
 237                         next-level-cache = <&L2_300>;
 238                         operating-points-v2 = <&cpu0_opp_table>;
 239                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 240                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 241                         qcom,freq-domain = <&cpufreq_hw 0>;
 242                         #cooling-cells = <2>;
 243                         L2_300: l2-cache {
 244                                 compatible = "cache";
 245                                 next-level-cache = <&L3_0>;
 246                         };
 247                 };
 248
 249                 CPU4: cpu@400 {
 250                         device_type = "cpu";
 251                         compatible = "arm,kryo";
 252                         reg = <0x0 0x400>;
 253                         enable-method = "psci";
 254                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 255                                            &BIG_CPU_SLEEP_1
 256                                            &CLUSTER_SLEEP_0>;
 257                         next-level-cache = <&L2_400>;
 258                         operating-points-v2 = <&cpu4_opp_table>;
 259                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 260                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 261                         qcom,freq-domain = <&cpufreq_hw 1>;
 262                         #cooling-cells = <2>;
 263                         L2_400: l2-cache {
 264                                 compatible = "cache";
 265                                 next-level-cache = <&L3_0>;
 266                         };
 267                 };
 268
 269                 CPU5: cpu@500 {
 270                         device_type = "cpu";
 271                         compatible = "arm,kryo";
 272                         reg = <0x0 0x500>;
 273                         enable-method = "psci";
 274                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 275                                            &BIG_CPU_SLEEP_1
 276                                            &CLUSTER_SLEEP_0>;
 277                         next-level-cache = <&L2_500>;
 278                         operating-points-v2 = <&cpu4_opp_table>;
 279                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 280                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 281                         qcom,freq-domain = <&cpufreq_hw 1>;
 282                         #cooling-cells = <2>;
 283                         L2_500: l2-cache {
 284                                 compatible = "cache";
 285                                 next-level-cache = <&L3_0>;
 286                         };
 287                 };
 288
 289                 CPU6: cpu@600 {
 290                         device_type = "cpu";
 291                         compatible = "arm,kryo";
 292                         reg = <0x0 0x600>;
 293                         enable-method = "psci";
 294                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 295                                            &BIG_CPU_SLEEP_1
 296                                            &CLUSTER_SLEEP_0>;
 297                         next-level-cache = <&L2_600>;
 298                         operating-points-v2 = <&cpu4_opp_table>;
 299                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 300                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 301                         qcom,freq-domain = <&cpufreq_hw 1>;
 302                         #cooling-cells = <2>;
 303                         L2_600: l2-cache {
 304                                 compatible = "cache";
 305                                 next-level-cache = <&L3_0>;
 306                         };
 307                 };
 308
 309                 CPU7: cpu@700 {
 310                         device_type = "cpu";
 311                         compatible = "arm,kryo";
 312                         reg = <0x0 0x700>;
 313                         enable-method = "psci";
 314                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 315                                            &BIG_CPU_SLEEP_1
 316                                            &CLUSTER_SLEEP_0>;
 317                         next-level-cache = <&L2_700>;
 318                         operating-points-v2 = <&cpu7_opp_table>;
 319                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 320                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 321                         qcom,freq-domain = <&cpufreq_hw 2>;
 322                         #cooling-cells = <2>;
 323                         L2_700: l2-cache {
 324                                 compatible = "cache";
 325                                 next-level-cache = <&L3_0>;
 326                         };
 327                 };
 328
 329                 cpu-map {
 330                         cluster0 {
 331                                 core0 {
 332                                         cpu = <&CPU0>;
 333                                 };
 334
 335                                 core1 {
 336                                         cpu = <&CPU1>;
 337                                 };
 338
 339                                 core2 {
 340                                         cpu = <&CPU2>;
 341                                 };
 342
 343                                 core3 {
 344                                         cpu = <&CPU3>;
 345                                 };
 346
 347                                 core4 {
 348                                         cpu = <&CPU4>;
 349                                 };
 350
 351                                 core5 {
 352                                         cpu = <&CPU5>;
 353                                 };
 354
 355                                 core6 {
 356                                         cpu = <&CPU6>;
 357                                 };
 358
 359                                 core7 {
 360                                         cpu = <&CPU7>;
 361                                 };
 362                         };
 363                 };
 364
 365                 idle-states {
 366                         entry-method = "psci";
 367
 368                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 369                                 compatible = "arm,idle-state";
 370                                 idle-state-name = "little-power-down";
 371                                 arm,psci-suspend-param = <0x40000003>;
 372                                 entry-latency-us = <549>;
 373                                 exit-latency-us = <901>;
 374                                 min-residency-us = <1774>;
 375                                 local-timer-stop;
 376                         };
 377
 378                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 379                                 compatible = "arm,idle-state";
 380                                 idle-state-name = "little-rail-power-down";
 381                                 arm,psci-suspend-param = <0x40000004>;
 382                                 entry-latency-us = <702>;
 383                                 exit-latency-us = <915>;
 384                                 min-residency-us = <4001>;
 385                                 local-timer-stop;
 386                         };
 387
 388                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 389                                 compatible = "arm,idle-state";
 390                                 idle-state-name = "big-power-down";
 391                                 arm,psci-suspend-param = <0x40000003>;
 392                                 entry-latency-us = <523>;
 393                                 exit-latency-us = <1244>;
 394                                 min-residency-us = <2207>;
 395                                 local-timer-stop;
 396                         };
 397
 398                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 399                                 compatible = "arm,idle-state";
 400                                 idle-state-name = "big-rail-power-down";
 401                                 arm,psci-suspend-param = <0x40000004>;
 402                                 entry-latency-us = <526>;
 403                                 exit-latency-us = <1854>;
 404                                 min-residency-us = <5555>;
 405                                 local-timer-stop;
 406                         };
 407
 408                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 409                                 compatible = "arm,idle-state";
 410                                 idle-state-name = "cluster-power-down";
 411                                 arm,psci-suspend-param = <0x40003444>;
 412                                 entry-latency-us = <3263>;
 413                                 exit-latency-us = <6562>;
 414                                 min-residency-us = <9926>;
 415                                 local-timer-stop;
 416                         };
 417                 };
 418         };
 419
 420         cpu0_opp_table: opp-table-cpu0 {
 421                 compatible = "operating-points-v2";
 422                 opp-shared;
 423
 424                 cpu0_opp_300mhz: opp-300000000 {
 425                         opp-hz = /bits/ 64 <300000000>;
 426                         opp-peak-kBps = <800000 9600000>;
 427                 };
 428
 429                 cpu0_opp_691mhz: opp-691200000 {
 430                         opp-hz = /bits/ 64 <691200000>;
 431                         opp-peak-kBps = <800000 17817600>;
 432                 };
 433
 434                 cpu0_opp_806mhz: opp-806400000 {
 435                         opp-hz = /bits/ 64 <806400000>;
 436                         opp-peak-kBps = <800000 20889600>;
 437                 };
 438
 439                 cpu0_opp_941mhz: opp-940800000 {
 440                         opp-hz = /bits/ 64 <940800000>;
 441                         opp-peak-kBps = <1804000 24576000>;
 442                 };
 443
 444                 cpu0_opp_1152mhz: opp-1152000000 {
 445                         opp-hz = /bits/ 64 <1152000000>;
 446                         opp-peak-kBps = <2188000 27033600>;
 447                 };
 448
 449                 cpu0_opp_1325mhz: opp-1324800000 {
 450                         opp-hz = /bits/ 64 <1324800000>;
 451                         opp-peak-kBps = <2188000 33792000>;
 452                 };
 453
 454                 cpu0_opp_1517mhz: opp-1516800000 {
 455                         opp-hz = /bits/ 64 <1516800000>;
 456                         opp-peak-kBps = <3072000 38092800>;
 457                 };
 458
 459                 cpu0_opp_1651mhz: opp-1651200000 {
 460                         opp-hz = /bits/ 64 <1651200000>;
 461                         opp-peak-kBps = <3072000 41779200>;
 462                 };
 463
 464                 cpu0_opp_1805mhz: opp-1804800000 {
 465                         opp-hz = /bits/ 64 <1804800000>;
 466                         opp-peak-kBps = <4068000 48537600>;
 467                 };
 468
 469                 cpu0_opp_1958mhz: opp-1958400000 {
 470                         opp-hz = /bits/ 64 <1958400000>;
 471                         opp-peak-kBps = <4068000 48537600>;
 472                 };
 473
 474                 cpu0_opp_2016mhz: opp-2016000000 {
 475                         opp-hz = /bits/ 64 <2016000000>;
 476                         opp-peak-kBps = <6220000 48537600>;
 477                 };
 478         };
 479
 480         cpu4_opp_table: opp-table-cpu4 {
 481                 compatible = "operating-points-v2";
 482                 opp-shared;
 483
 484                 cpu4_opp_691mhz: opp-691200000 {
 485                         opp-hz = /bits/ 64 <691200000>;
 486                         opp-peak-kBps = <1804000 9600000>;
 487                 };
 488
 489                 cpu4_opp_941mhz: opp-940800000 {
 490                         opp-hz = /bits/ 64 <940800000>;
 491                         opp-peak-kBps = <2188000 17817600>;
 492                 };
 493
 494                 cpu4_opp_1229mhz: opp-1228800000 {
 495                         opp-hz = /bits/ 64 <1228800000>;
 496                         opp-peak-kBps = <4068000 24576000>;
 497                 };
 498
 499                 cpu4_opp_1344mhz: opp-1344000000 {
 500                         opp-hz = /bits/ 64 <1344000000>;
 501                         opp-peak-kBps = <4068000 24576000>;
 502                 };
 503
 504                 cpu4_opp_1517mhz: opp-1516800000 {
 505                         opp-hz = /bits/ 64 <1516800000>;
 506                         opp-peak-kBps = <4068000 24576000>;
 507                 };
 508
 509                 cpu4_opp_1651mhz: opp-1651200000 {
 510                         opp-hz = /bits/ 64 <1651200000>;
 511                         opp-peak-kBps = <6220000 38092800>;
 512                 };
 513
 514                 cpu4_opp_1901mhz: opp-1900800000 {
 515                         opp-hz = /bits/ 64 <1900800000>;
 516                         opp-peak-kBps = <6220000 44851200>;
 517                 };
 518
 519                 cpu4_opp_2054mhz: opp-2054400000 {
 520                         opp-hz = /bits/ 64 <2054400000>;
 521                         opp-peak-kBps = <6220000 44851200>;
 522                 };
 523
 524                 cpu4_opp_2112mhz: opp-2112000000 {
 525                         opp-hz = /bits/ 64 <2112000000>;
 526                         opp-peak-kBps = <6220000 44851200>;
 527                 };
 528
 529                 cpu4_opp_2131mhz: opp-2131200000 {
 530                         opp-hz = /bits/ 64 <2131200000>;
 531                         opp-peak-kBps = <6220000 44851200>;
 532                 };
 533
 534                 cpu4_opp_2208mhz: opp-2208000000 {
 535                         opp-hz = /bits/ 64 <2208000000>;
 536                         opp-peak-kBps = <6220000 44851200>;
 537                 };
 538
 539                 cpu4_opp_2400mhz: opp-2400000000 {
 540                         opp-hz = /bits/ 64 <2400000000>;
 541                         opp-peak-kBps = <8532000 48537600>;
 542                 };
 543
 544                 cpu4_opp_2611mhz: opp-2611200000 {
 545                         opp-hz = /bits/ 64 <2611200000>;
 546                         opp-peak-kBps = <8532000 48537600>;
 547                 };
 548         };
 549
 550         cpu7_opp_table: opp-table-cpu7 {
 551                 compatible = "operating-points-v2";
 552                 opp-shared;
 553
 554                 cpu7_opp_806mhz: opp-806400000 {
 555                         opp-hz = /bits/ 64 <806400000>;
 556                         opp-peak-kBps = <1804000 9600000>;
 557                 };
 558
 559                 cpu7_opp_1056mhz: opp-1056000000 {
 560                         opp-hz = /bits/ 64 <1056000000>;
 561                         opp-peak-kBps = <2188000 17817600>;
 562                 };
 563
 564                 cpu7_opp_1325mhz: opp-1324800000 {
 565                         opp-hz = /bits/ 64 <1324800000>;
 566                         opp-peak-kBps = <4068000 24576000>;
 567                 };
 568
 569                 cpu7_opp_1517mhz: opp-1516800000 {
 570                         opp-hz = /bits/ 64 <1516800000>;
 571                         opp-peak-kBps = <4068000 24576000>;
 572                 };
 573
 574                 cpu7_opp_1766mhz: opp-1766400000 {
 575                         opp-hz = /bits/ 64 <1766400000>;
 576                         opp-peak-kBps = <6220000 38092800>;
 577                 };
 578
 579                 cpu7_opp_1862mhz: opp-1862400000 {
 580                         opp-hz = /bits/ 64 <1862400000>;
 581                         opp-peak-kBps = <6220000 38092800>;
 582                 };
 583
 584                 cpu7_opp_2035mhz: opp-2035200000 {
 585                         opp-hz = /bits/ 64 <2035200000>;
 586                         opp-peak-kBps = <6220000 38092800>;
 587                 };
 588
 589                 cpu7_opp_2112mhz: opp-2112000000 {
 590                         opp-hz = /bits/ 64 <2112000000>;
 591                         opp-peak-kBps = <6220000 44851200>;
 592                 };
 593
 594                 cpu7_opp_2208mhz: opp-2208000000 {
 595                         opp-hz = /bits/ 64 <2208000000>;
 596                         opp-peak-kBps = <6220000 44851200>;
 597                 };
 598
 599                 cpu7_opp_2381mhz: opp-2380800000 {
 600                         opp-hz = /bits/ 64 <2380800000>;
 601                         opp-peak-kBps = <6832000 44851200>;
 602                 };
 603
 604                 cpu7_opp_2400mhz: opp-2400000000 {
 605                         opp-hz = /bits/ 64 <2400000000>;
 606                         opp-peak-kBps = <8532000 48537600>;
 607                 };
 608
 609                 cpu7_opp_2515mhz: opp-2515200000 {
 610                         opp-hz = /bits/ 64 <2515200000>;
 611                         opp-peak-kBps = <8532000 48537600>;
 612                 };
 613
 614                 cpu7_opp_2707mhz: opp-2707200000 {
 615                         opp-hz = /bits/ 64 <2707200000>;
 616                         opp-peak-kBps = <8532000 48537600>;
 617                 };
 618
 619                 cpu7_opp_3014mhz: opp-3014400000 {
 620                         opp-hz = /bits/ 64 <3014400000>;
 621                         opp-peak-kBps = <8532000 48537600>;
 622                 };
 623         };
 624
 625         memory@80000000 {
 626                 device_type = "memory";
 627                 /* We expect the bootloader to fill in the size */
 628                 reg = <0 0x80000000 0 0>;
 629         };
 630
 631         firmware {
 632                 scm {
 633                         compatible = "qcom,scm-sc7280", "qcom,scm";
 634                 };
 635         };
 636
 637         clk_virt: interconnect {
 638                 compatible = "qcom,sc7280-clk-virt";
 639                 #interconnect-cells = <2>;
 640                 qcom,bcm-voters = <&apps_bcm_voter>;
 641         };
 642
 643         smem {
 644                 compatible = "qcom,smem";
 645                 memory-region = <&smem_mem>;
 646                 hwlocks = <&tcsr_mutex 3>;
 647         };
 648
 649         smp2p-adsp {
 650                 compatible = "qcom,smp2p";
 651                 qcom,smem = <443>, <429>;
 652                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 653                                              IPCC_MPROC_SIGNAL_SMP2P
 654                                              IRQ_TYPE_EDGE_RISING>;
 655                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 656                                 IPCC_MPROC_SIGNAL_SMP2P>;
 657
 658                 qcom,local-pid = <0>;
 659                 qcom,remote-pid = <2>;
 660
 661                 adsp_smp2p_out: master-kernel {
 662                         qcom,entry-name = "master-kernel";
 663                         #qcom,smem-state-cells = <1>;
 664                 };
 665
 666                 adsp_smp2p_in: slave-kernel {
 667                         qcom,entry-name = "slave-kernel";
 668                         interrupt-controller;
 669                         #interrupt-cells = <2>;
 670                 };
 671         };
 672
 673         smp2p-cdsp {
 674                 compatible = "qcom,smp2p";
 675                 qcom,smem = <94>, <432>;
 676                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 677                                              IPCC_MPROC_SIGNAL_SMP2P
 678                                              IRQ_TYPE_EDGE_RISING>;
 679                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 680                                 IPCC_MPROC_SIGNAL_SMP2P>;
 681
 682                 qcom,local-pid = <0>;
 683                 qcom,remote-pid = <5>;
 684
 685                 cdsp_smp2p_out: master-kernel {
 686                         qcom,entry-name = "master-kernel";
 687                         #qcom,smem-state-cells = <1>;
 688                 };
 689
 690                 cdsp_smp2p_in: slave-kernel {
 691                         qcom,entry-name = "slave-kernel";
 692                         interrupt-controller;
 693                         #interrupt-cells = <2>;
 694                 };
 695         };
 696
 697         smp2p-mpss {
 698                 compatible = "qcom,smp2p";
 699                 qcom,smem = <435>, <428>;
 700                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 701                                              IPCC_MPROC_SIGNAL_SMP2P
 702                                              IRQ_TYPE_EDGE_RISING>;
 703                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 704                                 IPCC_MPROC_SIGNAL_SMP2P>;
 705
 706                 qcom,local-pid = <0>;
 707                 qcom,remote-pid = <1>;
 708
 709                 modem_smp2p_out: master-kernel {
 710                         qcom,entry-name = "master-kernel";
 711                         #qcom,smem-state-cells = <1>;
 712                 };
 713
 714                 modem_smp2p_in: slave-kernel {
 715                         qcom,entry-name = "slave-kernel";
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                 };
 719
 720                 ipa_smp2p_out: ipa-ap-to-modem {
 721                         qcom,entry-name = "ipa";
 722                         #qcom,smem-state-cells = <1>;
 723                 };
 724
 725                 ipa_smp2p_in: ipa-modem-to-ap {
 726                         qcom,entry-name = "ipa";
 727                         interrupt-controller;
 728                         #interrupt-cells = <2>;
 729                 };
 730         };
 731
 732         smp2p-wpss {
 733                 compatible = "qcom,smp2p";
 734                 qcom,smem = <617>, <616>;
 735                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 736                                              IPCC_MPROC_SIGNAL_SMP2P
 737                                              IRQ_TYPE_EDGE_RISING>;
 738                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 739                                 IPCC_MPROC_SIGNAL_SMP2P>;
 740
 741                 qcom,local-pid = <0>;
 742                 qcom,remote-pid = <13>;
 743
 744                 wpss_smp2p_out: master-kernel {
 745                         qcom,entry-name = "master-kernel";
 746                         #qcom,smem-state-cells = <1>;
 747                 };
 748
 749                 wpss_smp2p_in: slave-kernel {
 750                         qcom,entry-name = "slave-kernel";
 751                         interrupt-controller;
 752                         #interrupt-cells = <2>;
 753                 };
 754         };
 755
 756         pmu {
 757                 compatible = "arm,armv8-pmuv3";
 758                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 759         };
 760
 761         psci {
 762                 compatible = "arm,psci-1.0";
 763                 method = "smc";
 764         };
 765
 766         qspi_opp_table: opp-table-qspi {
 767                 compatible = "operating-points-v2";
 768
 769                 opp-75000000 {
 770                         opp-hz = /bits/ 64 <75000000>;
 771                         required-opps = <&rpmhpd_opp_low_svs>;
 772                 };
 773
 774                 opp-150000000 {
 775                         opp-hz = /bits/ 64 <150000000>;
 776                         required-opps = <&rpmhpd_opp_svs>;
 777                 };
 778
 779                 opp-200000000 {
 780                         opp-hz = /bits/ 64 <200000000>;
 781                         required-opps = <&rpmhpd_opp_svs_l1>;
 782                 };
 783
 784                 opp-300000000 {
 785                         opp-hz = /bits/ 64 <300000000>;
 786                         required-opps = <&rpmhpd_opp_nom>;
 787                 };
 788         };
 789
 790         qup_opp_table: opp-table-qup {
 791                 compatible = "operating-points-v2";
 792
 793                 opp-75000000 {
 794                         opp-hz = /bits/ 64 <75000000>;
 795                         required-opps = <&rpmhpd_opp_low_svs>;
 796                 };
 797
 798                 opp-100000000 {
 799                         opp-hz = /bits/ 64 <100000000>;
 800                         required-opps = <&rpmhpd_opp_svs>;
 801                 };
 802
 803                 opp-128000000 {
 804                         opp-hz = /bits/ 64 <128000000>;
 805                         required-opps = <&rpmhpd_opp_nom>;
 806                 };
 807         };
 808
 809         soc: soc@0 {
 810                 #address-cells = <2>;
 811                 #size-cells = <2>;
 812                 ranges = <0 0 0 0 0x10 0>;
 813                 dma-ranges = <0 0 0 0 0x10 0>;
 814                 compatible = "simple-bus";
 815
 816                 gcc: clock-controller@100000 {
 817                         compatible = "qcom,gcc-sc7280";
 818                         reg = <0 0x00100000 0 0x1f0000>;
 819                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 820                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
 821                                  <0>, <&pcie1_lane>,
 822                                  <0>, <0>, <0>, <0>;
 823                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
 824                                       "pcie_0_pipe_clk", "pcie_1_pipe_clk",
 825                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
 826                                       "ufs_phy_tx_symbol_0_clk",
 827                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 828                         #clock-cells = <1>;
 829                         #reset-cells = <1>;
 830                         #power-domain-cells = <1>;
 831                 };
 832
 833                 ipcc: mailbox@408000 {
 834                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
 835                         reg = <0 0x00408000 0 0x1000>;
 836                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 837                         interrupt-controller;
 838                         #interrupt-cells = <3>;
 839                         #mbox-cells = <2>;
 840                 };
 841
 842                 qfprom: efuse@784000 {
 843                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
 844                         reg = <0 0x00784000 0 0xa20>,
 845                               <0 0x00780000 0 0xa20>,
 846                               <0 0x00782000 0 0x120>,
 847                               <0 0x00786000 0 0x1fff>;
 848                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 849                         clock-names = "core";
 850                         power-domains = <&rpmhpd SC7280_MX>;
 851                         #address-cells = <1>;
 852                         #size-cells = <1>;
 853
 854                         gpu_speed_bin: gpu_speed_bin@1e9 {
 855                                 reg = <0x1e9 0x2>;
 856                                 bits = <5 8>;
 857                         };
 858                 };
 859
 860                 sdhc_1: mmc@7c4000 {
 861                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 862                         pinctrl-names = "default", "sleep";
 863                         pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
 864                         pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
 865                         status = "disabled";
 866
 867                         reg = <0 0x007c4000 0 0x1000>,
 868                               <0 0x007c5000 0 0x1000>;
 869                         reg-names = "hc", "cqhci";
 870
 871                         iommus = <&apps_smmu 0xc0 0x0>;
 872                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
 873                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
 874                         interrupt-names = "hc_irq", "pwr_irq";
 875
 876                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 877                                  <&gcc GCC_SDCC1_APPS_CLK>,
 878                                  <&rpmhcc RPMH_CXO_CLK>;
 879                         clock-names = "iface", "core", "xo";
 880                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
 881                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
 882                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 883                         power-domains = <&rpmhpd SC7280_CX>;
 884                         operating-points-v2 = <&sdhc1_opp_table>;
 885
 886                         bus-width = <8>;
 887                         supports-cqe;
 888
 889                         qcom,dll-config = <0x0007642c>;
 890                         qcom,ddr-config = <0x80040868>;
 891
 892                         mmc-ddr-1_8v;
 893                         mmc-hs200-1_8v;
 894                         mmc-hs400-1_8v;
 895                         mmc-hs400-enhanced-strobe;
 896
 897                         resets = <&gcc GCC_SDCC1_BCR>;
 898
 899                         sdhc1_opp_table: opp-table {
 900                                 compatible = "operating-points-v2";
 901
 902                                 opp-100000000 {
 903                                         opp-hz = /bits/ 64 <100000000>;
 904                                         required-opps = <&rpmhpd_opp_low_svs>;
 905                                         opp-peak-kBps = <1800000 400000>;
 906                                         opp-avg-kBps = <100000 0>;
 907                                 };
 908
 909                                 opp-384000000 {
 910                                         opp-hz = /bits/ 64 <384000000>;
 911                                         required-opps = <&rpmhpd_opp_nom>;
 912                                         opp-peak-kBps = <5400000 1600000>;
 913                                         opp-avg-kBps = <390000 0>;
 914                                 };
 915                         };
 916
 917                 };
 918
 919                 gpi_dma0: dma-controller@900000 {
 920                         #dma-cells = <3>;
 921                         compatible = "qcom,sc7280-gpi-dma";
 922                         reg = <0 0x00900000 0 0x60000>;
 923                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 924                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 925                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 926                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 927                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 928                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 929                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 930                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 931                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 932                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 933                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 934                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
 935                         dma-channels = <12>;
 936                         dma-channel-mask = <0x7f>;
 937                         iommus = <&apps_smmu 0x0136 0x0>;
 938                         status = "disabled";
 939                 };
 940
 941                 qupv3_id_0: geniqup@9c0000 {
 942                         compatible = "qcom,geni-se-qup";
 943                         reg = <0 0x009c0000 0 0x2000>;
 944                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 945                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 946                         clock-names = "m-ahb", "s-ahb";
 947                         #address-cells = <2>;
 948                         #size-cells = <2>;
 949                         ranges;
 950                         iommus = <&apps_smmu 0x123 0x0>;
 951                         status = "disabled";
 952
 953                         i2c0: i2c@980000 {
 954                                 compatible = "qcom,geni-i2c";
 955                                 reg = <0 0x00980000 0 0x4000>;
 956                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 957                                 clock-names = "se";
 958                                 pinctrl-names = "default";
 959                                 pinctrl-0 = <&qup_i2c0_data_clk>;
 960                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 964                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 965                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 966                                 interconnect-names = "qup-core", "qup-config",
 967                                                         "qup-memory";
 968                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 969                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 970                                 dma-names = "tx", "rx";
 971                                 status = "disabled";
 972                         };
 973
 974                         spi0: spi@980000 {
 975                                 compatible = "qcom,geni-spi";
 976                                 reg = <0 0x00980000 0 0x4000>;
 977                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 978                                 clock-names = "se";
 979                                 pinctrl-names = "default";
 980                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
 981                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 982                                 #address-cells = <1>;
 983                                 #size-cells = <0>;
 984                                 power-domains = <&rpmhpd SC7280_CX>;
 985                                 operating-points-v2 = <&qup_opp_table>;
 986                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 987                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 988                                 interconnect-names = "qup-core", "qup-config";
 989                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 990                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 991                                 dma-names = "tx", "rx";
 992                                 status = "disabled";
 993                         };
 994
 995                         uart0: serial@980000 {
 996                                 compatible = "qcom,geni-uart";
 997                                 reg = <0 0x00980000 0 0x4000>;
 998                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 999                                 clock-names = "se";
1000                                 pinctrl-names = "default";
1001                                 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1002                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1003                                 power-domains = <&rpmhpd SC7280_CX>;
1004                                 operating-points-v2 = <&qup_opp_table>;
1005                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1006                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1007                                 interconnect-names = "qup-core", "qup-config";
1008                                 status = "disabled";
1009                         };
1010
1011                         i2c1: i2c@984000 {
1012                                 compatible = "qcom,geni-i2c";
1013                                 reg = <0 0x00984000 0 0x4000>;
1014                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1015                                 clock-names = "se";
1016                                 pinctrl-names = "default";
1017                                 pinctrl-0 = <&qup_i2c1_data_clk>;
1018                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1019                                 #address-cells = <1>;
1020                                 #size-cells = <0>;
1021                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1022                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1023                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1024                                 interconnect-names = "qup-core", "qup-config",
1025                                                         "qup-memory";
1026                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1027                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1028                                 dma-names = "tx", "rx";
1029                                 status = "disabled";
1030                         };
1031
1032                         spi1: spi@984000 {
1033                                 compatible = "qcom,geni-spi";
1034                                 reg = <0 0x00984000 0 0x4000>;
1035                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1036                                 clock-names = "se";
1037                                 pinctrl-names = "default";
1038                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1039                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042                                 power-domains = <&rpmhpd SC7280_CX>;
1043                                 operating-points-v2 = <&qup_opp_table>;
1044                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1045                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1046                                 interconnect-names = "qup-core", "qup-config";
1047                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1048                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1049                                 dma-names = "tx", "rx";
1050                                 status = "disabled";
1051                         };
1052
1053                         uart1: serial@984000 {
1054                                 compatible = "qcom,geni-uart";
1055                                 reg = <0 0x00984000 0 0x4000>;
1056                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1057                                 clock-names = "se";
1058                                 pinctrl-names = "default";
1059                                 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1060                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1061                                 power-domains = <&rpmhpd SC7280_CX>;
1062                                 operating-points-v2 = <&qup_opp_table>;
1063                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1064                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1065                                 interconnect-names = "qup-core", "qup-config";
1066                                 status = "disabled";
1067                         };
1068
1069                         i2c2: i2c@988000 {
1070                                 compatible = "qcom,geni-i2c";
1071                                 reg = <0 0x00988000 0 0x4000>;
1072                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1073                                 clock-names = "se";
1074                                 pinctrl-names = "default";
1075                                 pinctrl-0 = <&qup_i2c2_data_clk>;
1076                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1077                                 #address-cells = <1>;
1078                                 #size-cells = <0>;
1079                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1080                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1081                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1082                                 interconnect-names = "qup-core", "qup-config",
1083                                                         "qup-memory";
1084                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1085                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1086                                 dma-names = "tx", "rx";
1087                                 status = "disabled";
1088                         };
1089
1090                         spi2: spi@988000 {
1091                                 compatible = "qcom,geni-spi";
1092                                 reg = <0 0x00988000 0 0x4000>;
1093                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1094                                 clock-names = "se";
1095                                 pinctrl-names = "default";
1096                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1097                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1098                                 #address-cells = <1>;
1099                                 #size-cells = <0>;
1100                                 power-domains = <&rpmhpd SC7280_CX>;
1101                                 operating-points-v2 = <&qup_opp_table>;
1102                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1103                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1104                                 interconnect-names = "qup-core", "qup-config";
1105                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1106                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1107                                 dma-names = "tx", "rx";
1108                                 status = "disabled";
1109                         };
1110
1111                         uart2: serial@988000 {
1112                                 compatible = "qcom,geni-uart";
1113                                 reg = <0 0x00988000 0 0x4000>;
1114                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1115                                 clock-names = "se";
1116                                 pinctrl-names = "default";
1117                                 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1118                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1119                                 power-domains = <&rpmhpd SC7280_CX>;
1120                                 operating-points-v2 = <&qup_opp_table>;
1121                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1122                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1123                                 interconnect-names = "qup-core", "qup-config";
1124                                 status = "disabled";
1125                         };
1126
1127                         i2c3: i2c@98c000 {
1128                                 compatible = "qcom,geni-i2c";
1129                                 reg = <0 0x0098c000 0 0x4000>;
1130                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1131                                 clock-names = "se";
1132                                 pinctrl-names = "default";
1133                                 pinctrl-0 = <&qup_i2c3_data_clk>;
1134                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1135                                 #address-cells = <1>;
1136                                 #size-cells = <0>;
1137                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1138                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1139                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1140                                 interconnect-names = "qup-core", "qup-config",
1141                                                         "qup-memory";
1142                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1143                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1144                                 dma-names = "tx", "rx";
1145                                 status = "disabled";
1146                         };
1147
1148                         spi3: spi@98c000 {
1149                                 compatible = "qcom,geni-spi";
1150                                 reg = <0 0x0098c000 0 0x4000>;
1151                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1152                                 clock-names = "se";
1153                                 pinctrl-names = "default";
1154                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1155                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1156                                 #address-cells = <1>;
1157                                 #size-cells = <0>;
1158                                 power-domains = <&rpmhpd SC7280_CX>;
1159                                 operating-points-v2 = <&qup_opp_table>;
1160                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1161                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1162                                 interconnect-names = "qup-core", "qup-config";
1163                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1164                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1165                                 dma-names = "tx", "rx";
1166                                 status = "disabled";
1167                         };
1168
1169                         uart3: serial@98c000 {
1170                                 compatible = "qcom,geni-uart";
1171                                 reg = <0 0x0098c000 0 0x4000>;
1172                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1173                                 clock-names = "se";
1174                                 pinctrl-names = "default";
1175                                 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1176                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1177                                 power-domains = <&rpmhpd SC7280_CX>;
1178                                 operating-points-v2 = <&qup_opp_table>;
1179                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1180                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1181                                 interconnect-names = "qup-core", "qup-config";
1182                                 status = "disabled";
1183                         };
1184
1185                         i2c4: i2c@990000 {
1186                                 compatible = "qcom,geni-i2c";
1187                                 reg = <0 0x00990000 0 0x4000>;
1188                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1189                                 clock-names = "se";
1190                                 pinctrl-names = "default";
1191                                 pinctrl-0 = <&qup_i2c4_data_clk>;
1192                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1193                                 #address-cells = <1>;
1194                                 #size-cells = <0>;
1195                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1196                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1197                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1198                                 interconnect-names = "qup-core", "qup-config",
1199                                                         "qup-memory";
1200                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1201                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1202                                 dma-names = "tx", "rx";
1203                                 status = "disabled";
1204                         };
1205
1206                         spi4: spi@990000 {
1207                                 compatible = "qcom,geni-spi";
1208                                 reg = <0 0x00990000 0 0x4000>;
1209                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1210                                 clock-names = "se";
1211                                 pinctrl-names = "default";
1212                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1213                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1214                                 #address-cells = <1>;
1215                                 #size-cells = <0>;
1216                                 power-domains = <&rpmhpd SC7280_CX>;
1217                                 operating-points-v2 = <&qup_opp_table>;
1218                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1220                                 interconnect-names = "qup-core", "qup-config";
1221                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1222                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1223                                 dma-names = "tx", "rx";
1224                                 status = "disabled";
1225                         };
1226
1227                         uart4: serial@990000 {
1228                                 compatible = "qcom,geni-uart";
1229                                 reg = <0 0x00990000 0 0x4000>;
1230                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1231                                 clock-names = "se";
1232                                 pinctrl-names = "default";
1233                                 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1234                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1235                                 power-domains = <&rpmhpd SC7280_CX>;
1236                                 operating-points-v2 = <&qup_opp_table>;
1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1239                                 interconnect-names = "qup-core", "qup-config";
1240                                 status = "disabled";
1241                         };
1242
1243                         i2c5: i2c@994000 {
1244                                 compatible = "qcom,geni-i2c";
1245                                 reg = <0 0x00994000 0 0x4000>;
1246                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1247                                 clock-names = "se";
1248                                 pinctrl-names = "default";
1249                                 pinctrl-0 = <&qup_i2c5_data_clk>;
1250                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1251                                 #address-cells = <1>;
1252                                 #size-cells = <0>;
1253                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1254                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1255                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1256                                 interconnect-names = "qup-core", "qup-config",
1257                                                         "qup-memory";
1258                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1259                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1260                                 dma-names = "tx", "rx";
1261                                 status = "disabled";
1262                         };
1263
1264                         spi5: spi@994000 {
1265                                 compatible = "qcom,geni-spi";
1266                                 reg = <0 0x00994000 0 0x4000>;
1267                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1268                                 clock-names = "se";
1269                                 pinctrl-names = "default";
1270                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1271                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1272                                 #address-cells = <1>;
1273                                 #size-cells = <0>;
1274                                 power-domains = <&rpmhpd SC7280_CX>;
1275                                 operating-points-v2 = <&qup_opp_table>;
1276                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1277                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1278                                 interconnect-names = "qup-core", "qup-config";
1279                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1280                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1281                                 dma-names = "tx", "rx";
1282                                 status = "disabled";
1283                         };
1284
1285                         uart5: serial@994000 {
1286                                 compatible = "qcom,geni-uart";
1287                                 reg = <0 0x00994000 0 0x4000>;
1288                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1289                                 clock-names = "se";
1290                                 pinctrl-names = "default";
1291                                 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1292                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1293                                 power-domains = <&rpmhpd SC7280_CX>;
1294                                 operating-points-v2 = <&qup_opp_table>;
1295                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1296                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1297                                 interconnect-names = "qup-core", "qup-config";
1298                                 status = "disabled";
1299                         };
1300
1301                         i2c6: i2c@998000 {
1302                                 compatible = "qcom,geni-i2c";
1303                                 reg = <0 0x00998000 0 0x4000>;
1304                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1305                                 clock-names = "se";
1306                                 pinctrl-names = "default";
1307                                 pinctrl-0 = <&qup_i2c6_data_clk>;
1308                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1309                                 #address-cells = <1>;
1310                                 #size-cells = <0>;
1311                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1312                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1313                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1314                                 interconnect-names = "qup-core", "qup-config",
1315                                                         "qup-memory";
1316                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1317                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
1318                                 dma-names = "tx", "rx";
1319                                 status = "disabled";
1320                         };
1321
1322                         spi6: spi@998000 {
1323                                 compatible = "qcom,geni-spi";
1324                                 reg = <0 0x00998000 0 0x4000>;
1325                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1326                                 clock-names = "se";
1327                                 pinctrl-names = "default";
1328                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1329                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1330                                 #address-cells = <1>;
1331                                 #size-cells = <0>;
1332                                 power-domains = <&rpmhpd SC7280_CX>;
1333                                 operating-points-v2 = <&qup_opp_table>;
1334                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1335                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1336                                 interconnect-names = "qup-core", "qup-config";
1337                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1338                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
1339                                 dma-names = "tx", "rx";
1340                                 status = "disabled";
1341                         };
1342
1343                         uart6: serial@998000 {
1344                                 compatible = "qcom,geni-uart";
1345                                 reg = <0 0x00998000 0 0x4000>;
1346                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1347                                 clock-names = "se";
1348                                 pinctrl-names = "default";
1349                                 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1350                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1351                                 power-domains = <&rpmhpd SC7280_CX>;
1352                                 operating-points-v2 = <&qup_opp_table>;
1353                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1354                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1355                                 interconnect-names = "qup-core", "qup-config";
1356                                 status = "disabled";
1357                         };
1358
1359                         i2c7: i2c@99c000 {
1360                                 compatible = "qcom,geni-i2c";
1361                                 reg = <0 0x0099c000 0 0x4000>;
1362                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1363                                 clock-names = "se";
1364                                 pinctrl-names = "default";
1365                                 pinctrl-0 = <&qup_i2c7_data_clk>;
1366                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1367                                 #address-cells = <1>;
1368                                 #size-cells = <0>;
1369                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1370                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1371                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1372                                 interconnect-names = "qup-core", "qup-config",
1373                                                         "qup-memory";
1374                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1375                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
1376                                 dma-names = "tx", "rx";
1377                                 status = "disabled";
1378                         };
1379
1380                         spi7: spi@99c000 {
1381                                 compatible = "qcom,geni-spi";
1382                                 reg = <0 0x0099c000 0 0x4000>;
1383                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1384                                 clock-names = "se";
1385                                 pinctrl-names = "default";
1386                                 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1387                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1388                                 #address-cells = <1>;
1389                                 #size-cells = <0>;
1390                                 power-domains = <&rpmhpd SC7280_CX>;
1391                                 operating-points-v2 = <&qup_opp_table>;
1392                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1393                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1394                                 interconnect-names = "qup-core", "qup-config";
1395                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1396                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
1397                                 dma-names = "tx", "rx";
1398                                 status = "disabled";
1399                         };
1400
1401                         uart7: serial@99c000 {
1402                                 compatible = "qcom,geni-uart";
1403                                 reg = <0 0x0099c000 0 0x4000>;
1404                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1405                                 clock-names = "se";
1406                                 pinctrl-names = "default";
1407                                 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1408                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1409                                 power-domains = <&rpmhpd SC7280_CX>;
1410                                 operating-points-v2 = <&qup_opp_table>;
1411                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1412                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1413                                 interconnect-names = "qup-core", "qup-config";
1414                                 status = "disabled";
1415                         };
1416                 };
1417
1418                 gpi_dma1: dma-controller@a00000 {
1419                         #dma-cells = <3>;
1420                         compatible = "qcom,sc7280-gpi-dma";
1421                         reg = <0 0x00a00000 0 0x60000>;
1422                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
1423                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
1424                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
1425                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1426                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1427                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1428                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
1429                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
1430                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
1431                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
1432                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
1433                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1434                         dma-channels = <12>;
1435                         dma-channel-mask = <0x1e>;
1436                         iommus = <&apps_smmu 0x56 0x0>;
1437                         status = "disabled";
1438                 };
1439
1440                 qupv3_id_1: geniqup@ac0000 {
1441                         compatible = "qcom,geni-se-qup";
1442                         reg = <0 0x00ac0000 0 0x2000>;
1443                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1444                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1445                         clock-names = "m-ahb", "s-ahb";
1446                         #address-cells = <2>;
1447                         #size-cells = <2>;
1448                         ranges;
1449                         iommus = <&apps_smmu 0x43 0x0>;
1450                         status = "disabled";
1451
1452                         i2c8: i2c@a80000 {
1453                                 compatible = "qcom,geni-i2c";
1454                                 reg = <0 0x00a80000 0 0x4000>;
1455                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1456                                 clock-names = "se";
1457                                 pinctrl-names = "default";
1458                                 pinctrl-0 = <&qup_i2c8_data_clk>;
1459                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1460                                 #address-cells = <1>;
1461                                 #size-cells = <0>;
1462                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1463                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1464                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1465                                 interconnect-names = "qup-core", "qup-config",
1466                                                         "qup-memory";
1467                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1468                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1469                                 dma-names = "tx", "rx";
1470                                 status = "disabled";
1471                         };
1472
1473                         spi8: spi@a80000 {
1474                                 compatible = "qcom,geni-spi";
1475                                 reg = <0 0x00a80000 0 0x4000>;
1476                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1477                                 clock-names = "se";
1478                                 pinctrl-names = "default";
1479                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1480                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1481                                 #address-cells = <1>;
1482                                 #size-cells = <0>;
1483                                 power-domains = <&rpmhpd SC7280_CX>;
1484                                 operating-points-v2 = <&qup_opp_table>;
1485                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1486                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1487                                 interconnect-names = "qup-core", "qup-config";
1488                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1489                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1490                                 dma-names = "tx", "rx";
1491                                 status = "disabled";
1492                         };
1493
1494                         uart8: serial@a80000 {
1495                                 compatible = "qcom,geni-uart";
1496                                 reg = <0 0x00a80000 0 0x4000>;
1497                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1498                                 clock-names = "se";
1499                                 pinctrl-names = "default";
1500                                 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1501                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1502                                 power-domains = <&rpmhpd SC7280_CX>;
1503                                 operating-points-v2 = <&qup_opp_table>;
1504                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1505                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1506                                 interconnect-names = "qup-core", "qup-config";
1507                                 status = "disabled";
1508                         };
1509
1510                         i2c9: i2c@a84000 {
1511                                 compatible = "qcom,geni-i2c";
1512                                 reg = <0 0x00a84000 0 0x4000>;
1513                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1514                                 clock-names = "se";
1515                                 pinctrl-names = "default";
1516                                 pinctrl-0 = <&qup_i2c9_data_clk>;
1517                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1518                                 #address-cells = <1>;
1519                                 #size-cells = <0>;
1520                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1521                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1522                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1523                                 interconnect-names = "qup-core", "qup-config",
1524                                                         "qup-memory";
1525                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1526                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1527                                 dma-names = "tx", "rx";
1528                                 status = "disabled";
1529                         };
1530
1531                         spi9: spi@a84000 {
1532                                 compatible = "qcom,geni-spi";
1533                                 reg = <0 0x00a84000 0 0x4000>;
1534                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1535                                 clock-names = "se";
1536                                 pinctrl-names = "default";
1537                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1538                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1539                                 #address-cells = <1>;
1540                                 #size-cells = <0>;
1541                                 power-domains = <&rpmhpd SC7280_CX>;
1542                                 operating-points-v2 = <&qup_opp_table>;
1543                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1544                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1545                                 interconnect-names = "qup-core", "qup-config";
1546                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1547                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1548                                 dma-names = "tx", "rx";
1549                                 status = "disabled";
1550                         };
1551
1552                         uart9: serial@a84000 {
1553                                 compatible = "qcom,geni-uart";
1554                                 reg = <0 0x00a84000 0 0x4000>;
1555                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1556                                 clock-names = "se";
1557                                 pinctrl-names = "default";
1558                                 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1559                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1560                                 power-domains = <&rpmhpd SC7280_CX>;
1561                                 operating-points-v2 = <&qup_opp_table>;
1562                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1563                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1564                                 interconnect-names = "qup-core", "qup-config";
1565                                 status = "disabled";
1566                         };
1567
1568                         i2c10: i2c@a88000 {
1569                                 compatible = "qcom,geni-i2c";
1570                                 reg = <0 0x00a88000 0 0x4000>;
1571                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1572                                 clock-names = "se";
1573                                 pinctrl-names = "default";
1574                                 pinctrl-0 = <&qup_i2c10_data_clk>;
1575                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1576                                 #address-cells = <1>;
1577                                 #size-cells = <0>;
1578                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1579                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1580                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1581                                 interconnect-names = "qup-core", "qup-config",
1582                                                         "qup-memory";
1583                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1584                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1585                                 dma-names = "tx", "rx";
1586                                 status = "disabled";
1587                         };
1588
1589                         spi10: spi@a88000 {
1590                                 compatible = "qcom,geni-spi";
1591                                 reg = <0 0x00a88000 0 0x4000>;
1592                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1593                                 clock-names = "se";
1594                                 pinctrl-names = "default";
1595                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1596                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1597                                 #address-cells = <1>;
1598                                 #size-cells = <0>;
1599                                 power-domains = <&rpmhpd SC7280_CX>;
1600                                 operating-points-v2 = <&qup_opp_table>;
1601                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1602                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1603                                 interconnect-names = "qup-core", "qup-config";
1604                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1605                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1606                                 dma-names = "tx", "rx";
1607                                 status = "disabled";
1608                         };
1609
1610                         uart10: serial@a88000 {
1611                                 compatible = "qcom,geni-uart";
1612                                 reg = <0 0x00a88000 0 0x4000>;
1613                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1614                                 clock-names = "se";
1615                                 pinctrl-names = "default";
1616                                 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1617                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1618                                 power-domains = <&rpmhpd SC7280_CX>;
1619                                 operating-points-v2 = <&qup_opp_table>;
1620                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1621                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1622                                 interconnect-names = "qup-core", "qup-config";
1623                                 status = "disabled";
1624                         };
1625
1626                         i2c11: i2c@a8c000 {
1627                                 compatible = "qcom,geni-i2c";
1628                                 reg = <0 0x00a8c000 0 0x4000>;
1629                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1630                                 clock-names = "se";
1631                                 pinctrl-names = "default";
1632                                 pinctrl-0 = <&qup_i2c11_data_clk>;
1633                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1634                                 #address-cells = <1>;
1635                                 #size-cells = <0>;
1636                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1637                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1638                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1639                                 interconnect-names = "qup-core", "qup-config",
1640                                                         "qup-memory";
1641                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1642                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1643                                 dma-names = "tx", "rx";
1644                                 status = "disabled";
1645                         };
1646
1647                         spi11: spi@a8c000 {
1648                                 compatible = "qcom,geni-spi";
1649                                 reg = <0 0x00a8c000 0 0x4000>;
1650                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1651                                 clock-names = "se";
1652                                 pinctrl-names = "default";
1653                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1654                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1655                                 #address-cells = <1>;
1656                                 #size-cells = <0>;
1657                                 power-domains = <&rpmhpd SC7280_CX>;
1658                                 operating-points-v2 = <&qup_opp_table>;
1659                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1660                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1661                                 interconnect-names = "qup-core", "qup-config";
1662                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1663                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1664                                 dma-names = "tx", "rx";
1665                                 status = "disabled";
1666                         };
1667
1668                         uart11: serial@a8c000 {
1669                                 compatible = "qcom,geni-uart";
1670                                 reg = <0 0x00a8c000 0 0x4000>;
1671                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1672                                 clock-names = "se";
1673                                 pinctrl-names = "default";
1674                                 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1675                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1676                                 power-domains = <&rpmhpd SC7280_CX>;
1677                                 operating-points-v2 = <&qup_opp_table>;
1678                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1679                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1680                                 interconnect-names = "qup-core", "qup-config";
1681                                 status = "disabled";
1682                         };
1683
1684                         i2c12: i2c@a90000 {
1685                                 compatible = "qcom,geni-i2c";
1686                                 reg = <0 0x00a90000 0 0x4000>;
1687                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1688                                 clock-names = "se";
1689                                 pinctrl-names = "default";
1690                                 pinctrl-0 = <&qup_i2c12_data_clk>;
1691                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1695                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1696                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1697                                 interconnect-names = "qup-core", "qup-config",
1698                                                         "qup-memory";
1699                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1700                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1701                                 dma-names = "tx", "rx";
1702                                 status = "disabled";
1703                         };
1704
1705                         spi12: spi@a90000 {
1706                                 compatible = "qcom,geni-spi";
1707                                 reg = <0 0x00a90000 0 0x4000>;
1708                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1709                                 clock-names = "se";
1710                                 pinctrl-names = "default";
1711                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1712                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1713                                 #address-cells = <1>;
1714                                 #size-cells = <0>;
1715                                 power-domains = <&rpmhpd SC7280_CX>;
1716                                 operating-points-v2 = <&qup_opp_table>;
1717                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1718                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1719                                 interconnect-names = "qup-core", "qup-config";
1720                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1721                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1722                                 dma-names = "tx", "rx";
1723                                 status = "disabled";
1724                         };
1725
1726                         uart12: serial@a90000 {
1727                                 compatible = "qcom,geni-uart";
1728                                 reg = <0 0x00a90000 0 0x4000>;
1729                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1730                                 clock-names = "se";
1731                                 pinctrl-names = "default";
1732                                 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1733                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1734                                 power-domains = <&rpmhpd SC7280_CX>;
1735                                 operating-points-v2 = <&qup_opp_table>;
1736                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1737                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1738                                 interconnect-names = "qup-core", "qup-config";
1739                                 status = "disabled";
1740                         };
1741
1742                         i2c13: i2c@a94000 {
1743                                 compatible = "qcom,geni-i2c";
1744                                 reg = <0 0x00a94000 0 0x4000>;
1745                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1746                                 clock-names = "se";
1747                                 pinctrl-names = "default";
1748                                 pinctrl-0 = <&qup_i2c13_data_clk>;
1749                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1750                                 #address-cells = <1>;
1751                                 #size-cells = <0>;
1752                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1753                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1754                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1755                                 interconnect-names = "qup-core", "qup-config",
1756                                                         "qup-memory";
1757                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1758                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1759                                 dma-names = "tx", "rx";
1760                                 status = "disabled";
1761                         };
1762
1763                         spi13: spi@a94000 {
1764                                 compatible = "qcom,geni-spi";
1765                                 reg = <0 0x00a94000 0 0x4000>;
1766                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1767                                 clock-names = "se";
1768                                 pinctrl-names = "default";
1769                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1770                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1771                                 #address-cells = <1>;
1772                                 #size-cells = <0>;
1773                                 power-domains = <&rpmhpd SC7280_CX>;
1774                                 operating-points-v2 = <&qup_opp_table>;
1775                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1776                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1777                                 interconnect-names = "qup-core", "qup-config";
1778                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1779                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1780                                 dma-names = "tx", "rx";
1781                                 status = "disabled";
1782                         };
1783
1784                         uart13: serial@a94000 {
1785                                 compatible = "qcom,geni-uart";
1786                                 reg = <0 0x00a94000 0 0x4000>;
1787                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1788                                 clock-names = "se";
1789                                 pinctrl-names = "default";
1790                                 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1791                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1792                                 power-domains = <&rpmhpd SC7280_CX>;
1793                                 operating-points-v2 = <&qup_opp_table>;
1794                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1795                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1796                                 interconnect-names = "qup-core", "qup-config";
1797                                 status = "disabled";
1798                         };
1799
1800                         i2c14: i2c@a98000 {
1801                                 compatible = "qcom,geni-i2c";
1802                                 reg = <0 0x00a98000 0 0x4000>;
1803                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1804                                 clock-names = "se";
1805                                 pinctrl-names = "default";
1806                                 pinctrl-0 = <&qup_i2c14_data_clk>;
1807                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1808                                 #address-cells = <1>;
1809                                 #size-cells = <0>;
1810                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1811                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1812                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1813                                 interconnect-names = "qup-core", "qup-config",
1814                                                         "qup-memory";
1815                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1816                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
1817                                 dma-names = "tx", "rx";
1818                                 status = "disabled";
1819                         };
1820
1821                         spi14: spi@a98000 {
1822                                 compatible = "qcom,geni-spi";
1823                                 reg = <0 0x00a98000 0 0x4000>;
1824                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1825                                 clock-names = "se";
1826                                 pinctrl-names = "default";
1827                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1828                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1829                                 #address-cells = <1>;
1830                                 #size-cells = <0>;
1831                                 power-domains = <&rpmhpd SC7280_CX>;
1832                                 operating-points-v2 = <&qup_opp_table>;
1833                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1834                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1835                                 interconnect-names = "qup-core", "qup-config";
1836                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1837                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
1838                                 dma-names = "tx", "rx";
1839                                 status = "disabled";
1840                         };
1841
1842                         uart14: serial@a98000 {
1843                                 compatible = "qcom,geni-uart";
1844                                 reg = <0 0x00a98000 0 0x4000>;
1845                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1846                                 clock-names = "se";
1847                                 pinctrl-names = "default";
1848                                 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1849                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
1850                                 power-domains = <&rpmhpd SC7280_CX>;
1851                                 operating-points-v2 = <&qup_opp_table>;
1852                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1853                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1854                                 interconnect-names = "qup-core", "qup-config";
1855                                 status = "disabled";
1856                         };
1857
1858                         i2c15: i2c@a9c000 {
1859                                 compatible = "qcom,geni-i2c";
1860                                 reg = <0 0x00a9c000 0 0x4000>;
1861                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1862                                 clock-names = "se";
1863                                 pinctrl-names = "default";
1864                                 pinctrl-0 = <&qup_i2c15_data_clk>;
1865                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1866                                 #address-cells = <1>;
1867                                 #size-cells = <0>;
1868                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1869                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1870                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1871                                 interconnect-names = "qup-core", "qup-config",
1872                                                         "qup-memory";
1873                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1874                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
1875                                 dma-names = "tx", "rx";
1876                                 status = "disabled";
1877                         };
1878
1879                         spi15: spi@a9c000 {
1880                                 compatible = "qcom,geni-spi";
1881                                 reg = <0 0x00a9c000 0 0x4000>;
1882                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1883                                 clock-names = "se";
1884                                 pinctrl-names = "default";
1885                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1886                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1887                                 #address-cells = <1>;
1888                                 #size-cells = <0>;
1889                                 power-domains = <&rpmhpd SC7280_CX>;
1890                                 operating-points-v2 = <&qup_opp_table>;
1891                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1892                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1893                                 interconnect-names = "qup-core", "qup-config";
1894                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1895                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
1896                                 dma-names = "tx", "rx";
1897                                 status = "disabled";
1898                         };
1899
1900                         uart15: serial@a9c000 {
1901                                 compatible = "qcom,geni-uart";
1902                                 reg = <0 0x00a9c000 0 0x4000>;
1903                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1904                                 clock-names = "se";
1905                                 pinctrl-names = "default";
1906                                 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1907                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1908                                 power-domains = <&rpmhpd SC7280_CX>;
1909                                 operating-points-v2 = <&qup_opp_table>;
1910                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1911                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1912                                 interconnect-names = "qup-core", "qup-config";
1913                                 status = "disabled";
1914                         };
1915                 };
1916
1917                 cnoc2: interconnect@1500000 {
1918                         reg = <0 0x01500000 0 0x1000>;
1919                         compatible = "qcom,sc7280-cnoc2";
1920                         #interconnect-cells = <2>;
1921                         qcom,bcm-voters = <&apps_bcm_voter>;
1922                 };
1923
1924                 cnoc3: interconnect@1502000 {
1925                         reg = <0 0x01502000 0 0x1000>;
1926                         compatible = "qcom,sc7280-cnoc3";
1927                         #interconnect-cells = <2>;
1928                         qcom,bcm-voters = <&apps_bcm_voter>;
1929                 };
1930
1931                 mc_virt: interconnect@1580000 {
1932                         reg = <0 0x01580000 0 0x4>;
1933                         compatible = "qcom,sc7280-mc-virt";
1934                         #interconnect-cells = <2>;
1935                         qcom,bcm-voters = <&apps_bcm_voter>;
1936                 };
1937
1938                 system_noc: interconnect@1680000 {
1939                         reg = <0 0x01680000 0 0x15480>;
1940                         compatible = "qcom,sc7280-system-noc";
1941                         #interconnect-cells = <2>;
1942                         qcom,bcm-voters = <&apps_bcm_voter>;
1943                 };
1944
1945                 aggre1_noc: interconnect@16e0000 {
1946                         compatible = "qcom,sc7280-aggre1-noc";
1947                         reg = <0 0x016e0000 0 0x1c080>;
1948                         #interconnect-cells = <2>;
1949                         qcom,bcm-voters = <&apps_bcm_voter>;
1950                 };
1951
1952                 aggre2_noc: interconnect@1700000 {
1953                         reg = <0 0x01700000 0 0x2b080>;
1954                         compatible = "qcom,sc7280-aggre2-noc";
1955                         #interconnect-cells = <2>;
1956                         qcom,bcm-voters = <&apps_bcm_voter>;
1957                 };
1958
1959                 mmss_noc: interconnect@1740000 {
1960                         reg = <0 0x01740000 0 0x1e080>;
1961                         compatible = "qcom,sc7280-mmss-noc";
1962                         #interconnect-cells = <2>;
1963                         qcom,bcm-voters = <&apps_bcm_voter>;
1964                 };
1965
1966                 wifi: wifi@17a10040 {
1967                         compatible = "qcom,wcn6750-wifi";
1968                         reg = <0 0x17a10040 0 0x0>;
1969                         iommus = <&apps_smmu 0x1c00 0x1>;
1970                         interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
1971                                      <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
1972                                      <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
1973                                      <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
1974                                      <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
1975                                      <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
1976                                      <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
1977                                      <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
1978                                      <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
1979                                      <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
1980                                      <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
1981                                      <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
1982                                      <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
1983                                      <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
1984                                      <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
1985                                      <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
1986                                      <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
1987                                      <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
1988                                      <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
1989                                      <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
1990                                      <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
1991                                      <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
1992                                      <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
1993                                      <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
1994                                      <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
1995                                      <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
1996                                      <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
1997                                      <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
1998                                      <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
1999                                      <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
2000                                      <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
2001                                      <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
2002                         qcom,rproc = <&remoteproc_wpss>;
2003                         memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2004                         status = "disabled";
2005                 };
2006
2007                 pcie1: pci@1c08000 {
2008                         compatible = "qcom,pcie-sc7280";
2009                         reg = <0 0x01c08000 0 0x3000>,
2010                               <0 0x40000000 0 0xf1d>,
2011                               <0 0x40000f20 0 0xa8>,
2012                               <0 0x40001000 0 0x1000>,
2013                               <0 0x40100000 0 0x100000>;
2014
2015                         reg-names = "parf", "dbi", "elbi", "atu", "config";
2016                         device_type = "pci";
2017                         linux,pci-domain = <1>;
2018                         bus-range = <0x00 0xff>;
2019                         num-lanes = <2>;
2020
2021                         #address-cells = <3>;
2022                         #size-cells = <2>;
2023
2024                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
2025                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2026
2027                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
2028                         interrupt-names = "msi";
2029                         #interrupt-cells = <1>;
2030                         interrupt-map-mask = <0 0 0 0x7>;
2031                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2032                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2033                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2034                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2035
2036                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
2037                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
2038                                  <&pcie1_lane>,
2039                                  <&rpmhcc RPMH_CXO_CLK>,
2040                                  <&gcc GCC_PCIE_1_AUX_CLK>,
2041                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2042                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2043                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2044                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
2045                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
2046                                  <&gcc GCC_DDRSS_PCIE_SF_CLK>;
2047
2048                         clock-names = "pipe",
2049                                       "pipe_mux",
2050                                       "phy_pipe",
2051                                       "ref",
2052                                       "aux",
2053                                       "cfg",
2054                                       "bus_master",
2055                                       "bus_slave",
2056                                       "slave_q2a",
2057                                       "tbu",
2058                                       "ddrss_sf_tbu";
2059
2060                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2061                         assigned-clock-rates = <19200000>;
2062
2063                         resets = <&gcc GCC_PCIE_1_BCR>;
2064                         reset-names = "pci";
2065
2066                         power-domains = <&gcc GCC_PCIE_1_GDSC>;
2067
2068                         phys = <&pcie1_lane>;
2069                         phy-names = "pciephy";
2070
2071                         pinctrl-names = "default";
2072                         pinctrl-0 = <&pcie1_clkreq_n>;
2073
2074                         iommus = <&apps_smmu 0x1c80 0x1>;
2075
2076                         iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2077                                     <0x100 &apps_smmu 0x1c81 0x1>;
2078
2079                         status = "disabled";
2080                 };
2081
2082                 pcie1_phy: phy@1c0e000 {
2083                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2084                         reg = <0 0x01c0e000 0 0x1c0>;
2085                         #address-cells = <2>;
2086                         #size-cells = <2>;
2087                         ranges;
2088                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2089                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2090                                  <&gcc GCC_PCIE_CLKREF_EN>,
2091                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2092                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
2093
2094                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
2095                         reset-names = "phy";
2096
2097                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2098                         assigned-clock-rates = <100000000>;
2099
2100                         status = "disabled";
2101
2102                         pcie1_lane: phy@1c0e200 {
2103                                 reg = <0 0x01c0e200 0 0x170>,
2104                                       <0 0x01c0e400 0 0x200>,
2105                                       <0 0x01c0ea00 0 0x1f0>,
2106                                       <0 0x01c0e600 0 0x170>,
2107                                       <0 0x01c0e800 0 0x200>,
2108                                       <0 0x01c0ee00 0 0xf4>;
2109                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
2110                                 clock-names = "pipe0";
2111
2112                                 #phy-cells = <0>;
2113                                 #clock-cells = <0>;
2114                                 clock-output-names = "pcie_1_pipe_clk";
2115                         };
2116                 };
2117
2118                 ipa: ipa@1e40000 {
2119                         compatible = "qcom,sc7280-ipa";
2120
2121                         iommus = <&apps_smmu 0x480 0x0>,
2122                                  <&apps_smmu 0x482 0x0>;
2123                         reg = <0 0x1e40000 0 0x8000>,
2124                               <0 0x1e50000 0 0x4ad0>,
2125                               <0 0x1e04000 0 0x23000>;
2126                         reg-names = "ipa-reg",
2127                                     "ipa-shared",
2128                                     "gsi";
2129
2130                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2131                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
2132                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2133                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
2134                         interrupt-names = "ipa",
2135                                           "gsi",
2136                                           "ipa-clock-query",
2137                                           "ipa-setup-ready";
2138
2139                         clocks = <&rpmhcc RPMH_IPA_CLK>;
2140                         clock-names = "core";
2141
2142                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2143                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2144                         interconnect-names = "memory",
2145                                              "config";
2146
2147                         qcom,qmp = <&aoss_qmp>;
2148
2149                         qcom,smem-states = <&ipa_smp2p_out 0>,
2150                                            <&ipa_smp2p_out 1>;
2151                         qcom,smem-state-names = "ipa-clock-enabled-valid",
2152                                                 "ipa-clock-enabled";
2153
2154                         status = "disabled";
2155                 };
2156
2157                 tcsr_mutex: hwlock@1f40000 {
2158                         compatible = "qcom,tcsr-mutex", "syscon";
2159                         reg = <0 0x01f40000 0 0x40000>;
2160                         #hwlock-cells = <1>;
2161                 };
2162
2163                 tcsr: syscon@1fc0000 {
2164                         compatible = "qcom,sc7280-tcsr", "syscon";
2165                         reg = <0 0x01fc0000 0 0x30000>;
2166                 };
2167
2168                 lpasscc: lpasscc@3000000 {
2169                         compatible = "qcom,sc7280-lpasscc";
2170                         reg = <0 0x03000000 0 0x40>,
2171                               <0 0x03c04000 0 0x4>,
2172                               <0 0x03389000 0 0x24>;
2173                         reg-names = "qdsp6ss", "top_cc", "cc";
2174                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
2175                         clock-names = "iface";
2176                         #clock-cells = <1>;
2177                 };
2178
2179                 lpass_audiocc: clock-controller@3300000 {
2180                         compatible = "qcom,sc7280-lpassaudiocc";
2181                         reg = <0 0x03300000 0 0x30000>;
2182                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2183                                <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
2184                         clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2185                         power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2186                         #clock-cells = <1>;
2187                         #power-domain-cells = <1>;
2188                 };
2189
2190                 lpass_aon: clock-controller@3380000 {
2191                         compatible = "qcom,sc7280-lpassaoncc";
2192                         reg = <0 0x03380000 0 0x30000>;
2193                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2194                                <&rpmhcc RPMH_CXO_CLK_A>,
2195                                <&lpasscore LPASS_CORE_CC_CORE_CLK>;
2196                         clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2197                         #clock-cells = <1>;
2198                         #power-domain-cells = <1>;
2199                 };
2200
2201                 lpasscore: clock-controller@3900000 {
2202                         compatible = "qcom,sc7280-lpasscorecc";
2203                         reg = <0 0x03900000 0 0x50000>;
2204                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2205                         clock-names = "bi_tcxo";
2206                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2207                         #clock-cells = <1>;
2208                         #power-domain-cells = <1>;
2209                 };
2210
2211                 lpass_hm: clock-controller@3c00000 {
2212                         compatible = "qcom,sc7280-lpasshm";
2213                         reg = <0 0x3c00000 0 0x28>;
2214                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2215                         clock-names = "bi_tcxo";
2216                         #clock-cells = <1>;
2217                         #power-domain-cells = <1>;
2218                 };
2219
2220                 lpass_ag_noc: interconnect@3c40000 {
2221                         reg = <0 0x03c40000 0 0xf080>;
2222                         compatible = "qcom,sc7280-lpass-ag-noc";
2223                         #interconnect-cells = <2>;
2224                         qcom,bcm-voters = <&apps_bcm_voter>;
2225                 };
2226
2227                 lpass_tlmm: pinctrl@33c0000 {
2228                         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2229                         reg = <0 0x033c0000 0x0 0x20000>,
2230                                 <0 0x03550000 0x0 0x10000>;
2231                         qcom,adsp-bypass-mode;
2232                         gpio-controller;
2233                         #gpio-cells = <2>;
2234                         gpio-ranges = <&lpass_tlmm 0 0 15>;
2235
2236                         #clock-cells = <1>;
2237
2238                         lpass_dmic01_clk: dmic01-clk {
2239                                 pins = "gpio6";
2240                                 function = "dmic1_clk";
2241                         };
2242
2243                         lpass_dmic01_clk_sleep: dmic01-clk-sleep {
2244                                 pins = "gpio6";
2245                                 function = "dmic1_clk";
2246                         };
2247
2248                         lpass_dmic01_data: dmic01-data {
2249                                 pins = "gpio7";
2250                                 function = "dmic1_data";
2251                         };
2252
2253                         lpass_dmic01_data_sleep: dmic01-data-sleep {
2254                                 pins = "gpio7";
2255                                 function = "dmic1_data";
2256                         };
2257
2258                         lpass_dmic23_clk: dmic23-clk {
2259                                 pins = "gpio8";
2260                                 function = "dmic2_clk";
2261                         };
2262
2263                         lpass_dmic23_clk_sleep: dmic23-clk-sleep {
2264                                 pins = "gpio8";
2265                                 function = "dmic2_clk";
2266                         };
2267
2268                         lpass_dmic23_data: dmic23-data {
2269                                 pins = "gpio9";
2270                                 function = "dmic2_data";
2271                         };
2272
2273                         lpass_dmic23_data_sleep: dmic23-data-sleep {
2274                                 pins = "gpio9";
2275                                 function = "dmic2_data";
2276                         };
2277
2278                         lpass_rx_swr_clk: rx-swr-clk {
2279                                 pins = "gpio3";
2280                                 function = "swr_rx_clk";
2281                         };
2282
2283                         lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
2284                                 pins = "gpio3";
2285                                 function = "swr_rx_clk";
2286                         };
2287
2288                         lpass_rx_swr_data: rx-swr-data {
2289                                 pins = "gpio4", "gpio5";
2290                                 function = "swr_rx_data";
2291                         };
2292
2293                         lpass_rx_swr_data_sleep: rx-swr-data-sleep {
2294                                 pins = "gpio4", "gpio5";
2295                                 function = "swr_rx_data";
2296                         };
2297
2298                         lpass_tx_swr_clk: tx-swr-clk {
2299                                 pins = "gpio0";
2300                                 function = "swr_tx_clk";
2301                         };
2302
2303                         lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
2304                                 pins = "gpio0";
2305                                 function = "swr_tx_clk";
2306                         };
2307
2308                         lpass_tx_swr_data: tx-swr-data {
2309                                 pins = "gpio1", "gpio2", "gpio14";
2310                                 function = "swr_tx_data";
2311                         };
2312
2313                         lpass_tx_swr_data_sleep: tx-swr-data-sleep {
2314                                 pins = "gpio1", "gpio2", "gpio14";
2315                                 function = "swr_tx_data";
2316                         };
2317                 };
2318
2319                 gpu: gpu@3d00000 {
2320                         compatible = "qcom,adreno-635.0", "qcom,adreno";
2321                         reg = <0 0x03d00000 0 0x40000>,
2322                               <0 0x03d9e000 0 0x1000>,
2323                               <0 0x03d61000 0 0x800>;
2324                         reg-names = "kgsl_3d0_reg_memory",
2325                                     "cx_mem",
2326                                     "cx_dbgc";
2327                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2328                         iommus = <&adreno_smmu 0 0x401>;
2329                         operating-points-v2 = <&gpu_opp_table>;
2330                         qcom,gmu = <&gmu>;
2331                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2332                         interconnect-names = "gfx-mem";
2333                         #cooling-cells = <2>;
2334
2335                         nvmem-cells = <&gpu_speed_bin>;
2336                         nvmem-cell-names = "speed_bin";
2337
2338                         gpu_opp_table: opp-table {
2339                                 compatible = "operating-points-v2";
2340
2341                                 opp-315000000 {
2342                                         opp-hz = /bits/ 64 <315000000>;
2343                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2344                                         opp-peak-kBps = <1804000>;
2345                                         opp-supported-hw = <0x03>;
2346                                 };
2347
2348                                 opp-450000000 {
2349                                         opp-hz = /bits/ 64 <450000000>;
2350                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2351                                         opp-peak-kBps = <4068000>;
2352                                         opp-supported-hw = <0x03>;
2353                                 };
2354
2355                                 opp-550000000 {
2356                                         opp-hz = /bits/ 64 <550000000>;
2357                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2358                                         opp-peak-kBps = <6832000>;
2359                                         opp-supported-hw = <0x03>;
2360                                 };
2361
2362                                 opp-608000000 {
2363                                         opp-hz = /bits/ 64 <608000000>;
2364                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2365                                         opp-peak-kBps = <8368000>;
2366                                         opp-supported-hw = <0x02>;
2367                                 };
2368
2369                                 opp-700000000 {
2370                                         opp-hz = /bits/ 64 <700000000>;
2371                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2372                                         opp-peak-kBps = <8532000>;
2373                                         opp-supported-hw = <0x02>;
2374                                 };
2375
2376                                 opp-812000000 {
2377                                         opp-hz = /bits/ 64 <812000000>;
2378                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2379                                         opp-peak-kBps = <8532000>;
2380                                         opp-supported-hw = <0x02>;
2381                                 };
2382
2383                                 opp-840000000 {
2384                                         opp-hz = /bits/ 64 <840000000>;
2385                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2386                                         opp-peak-kBps = <8532000>;
2387                                         opp-supported-hw = <0x02>;
2388                                 };
2389
2390                                 opp-900000000 {
2391                                         opp-hz = /bits/ 64 <900000000>;
2392                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2393                                         opp-peak-kBps = <8532000>;
2394                                         opp-supported-hw = <0x02>;
2395                                 };
2396                         };
2397                 };
2398
2399                 gmu: gmu@3d6a000 {
2400                         compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2401                         reg = <0 0x03d6a000 0 0x34000>,
2402                                 <0 0x3de0000 0 0x10000>,
2403                                 <0 0x0b290000 0 0x10000>;
2404                         reg-names = "gmu", "rscc", "gmu_pdc";
2405                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2406                                         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2407                         interrupt-names = "hfi", "gmu";
2408                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2409                                  <&gpucc GPU_CC_CXO_CLK>,
2410                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2411                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2412                                  <&gpucc GPU_CC_AHB_CLK>,
2413                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2414                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2415                         clock-names = "gmu",
2416                                       "cxo",
2417                                       "axi",
2418                                       "memnoc",
2419                                       "ahb",
2420                                       "hub",
2421                                       "smmu_vote";
2422                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2423                                         <&gpucc GPU_CC_GX_GDSC>;
2424                         power-domain-names = "cx",
2425                                              "gx";
2426                         iommus = <&adreno_smmu 5 0x400>;
2427                         operating-points-v2 = <&gmu_opp_table>;
2428
2429                         gmu_opp_table: opp-table {
2430                                 compatible = "operating-points-v2";
2431
2432                                 opp-200000000 {
2433                                         opp-hz = /bits/ 64 <200000000>;
2434                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2435                                 };
2436                         };
2437                 };
2438
2439                 gpucc: clock-controller@3d90000 {
2440                         compatible = "qcom,sc7280-gpucc";
2441                         reg = <0 0x03d90000 0 0x9000>;
2442                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2443                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2444                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2445                         clock-names = "bi_tcxo",
2446                                       "gcc_gpu_gpll0_clk_src",
2447                                       "gcc_gpu_gpll0_div_clk_src";
2448                         #clock-cells = <1>;
2449                         #reset-cells = <1>;
2450                         #power-domain-cells = <1>;
2451                 };
2452
2453                 adreno_smmu: iommu@3da0000 {
2454                         compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
2455                         reg = <0 0x03da0000 0 0x20000>;
2456                         #iommu-cells = <2>;
2457                         #global-interrupts = <2>;
2458                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2459                                         <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
2460                                         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2461                                         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2462                                         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2463                                         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2464                                         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2465                                         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2466                                         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2467                                         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2468                                         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2469                                         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
2470
2471                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2472                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2473                                  <&gpucc GPU_CC_AHB_CLK>,
2474                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2475                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2476                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2477                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2478                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2479                                         "gcc_gpu_snoc_dvm_gfx_clk",
2480                                         "gpu_cc_ahb_clk",
2481                                         "gpu_cc_hlos1_vote_gpu_smmu_clk",
2482                                         "gpu_cc_cx_gmu_clk",
2483                                         "gpu_cc_hub_cx_int_clk",
2484                                         "gpu_cc_hub_aon_clk";
2485
2486                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2487                 };
2488
2489                 remoteproc_mpss: remoteproc@4080000 {
2490                         compatible = "qcom,sc7280-mpss-pas";
2491                         reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2492                         reg-names = "qdsp6", "rmb";
2493
2494                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2495                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2496                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2497                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2498                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2499                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2500                         interrupt-names = "wdog", "fatal", "ready", "handover",
2501                                           "stop-ack", "shutdown-ack";
2502
2503                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2504                                  <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
2505                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2506                                  <&rpmhcc RPMH_PKA_CLK>,
2507                                  <&rpmhcc RPMH_CXO_CLK>;
2508                         clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
2509
2510                         power-domains = <&rpmhpd SC7280_CX>,
2511                                         <&rpmhpd SC7280_MSS>;
2512                         power-domain-names = "cx", "mss";
2513
2514                         memory-region = <&mpss_mem>;
2515
2516                         qcom,qmp = <&aoss_qmp>;
2517
2518                         qcom,smem-states = <&modem_smp2p_out 0>;
2519                         qcom,smem-state-names = "stop";
2520
2521                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2522                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2523                         reset-names = "mss_restart", "pdc_reset";
2524
2525                         qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
2526                         qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
2527                         qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
2528
2529                         status = "disabled";
2530
2531                         glink-edge {
2532                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2533                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2534                                                              IRQ_TYPE_EDGE_RISING>;
2535                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
2536                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2537                                 label = "modem";
2538                                 qcom,remote-pid = <1>;
2539                         };
2540                 };
2541
2542                 stm@6002000 {
2543                         compatible = "arm,coresight-stm", "arm,primecell";
2544                         reg = <0 0x06002000 0 0x1000>,
2545                               <0 0x16280000 0 0x180000>;
2546                         reg-names = "stm-base", "stm-stimulus-base";
2547
2548                         clocks = <&aoss_qmp>;
2549                         clock-names = "apb_pclk";
2550
2551                         out-ports {
2552                                 port {
2553                                         stm_out: endpoint {
2554                                                 remote-endpoint = <&funnel0_in7>;
2555                                         };
2556                                 };
2557                         };
2558                 };
2559
2560                 funnel@6041000 {
2561                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2562                         reg = <0 0x06041000 0 0x1000>;
2563
2564                         clocks = <&aoss_qmp>;
2565                         clock-names = "apb_pclk";
2566
2567                         out-ports {
2568                                 port {
2569                                         funnel0_out: endpoint {
2570                                                 remote-endpoint = <&merge_funnel_in0>;
2571                                         };
2572                                 };
2573                         };
2574
2575                         in-ports {
2576                                 #address-cells = <1>;
2577                                 #size-cells = <0>;
2578
2579                                 port@7 {
2580                                         reg = <7>;
2581                                         funnel0_in7: endpoint {
2582                                                 remote-endpoint = <&stm_out>;
2583                                         };
2584                                 };
2585                         };
2586                 };
2587
2588                 funnel@6042000 {
2589                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2590                         reg = <0 0x06042000 0 0x1000>;
2591
2592                         clocks = <&aoss_qmp>;
2593                         clock-names = "apb_pclk";
2594
2595                         out-ports {
2596                                 port {
2597                                         funnel1_out: endpoint {
2598                                                 remote-endpoint = <&merge_funnel_in1>;
2599                                         };
2600                                 };
2601                         };
2602
2603                         in-ports {
2604                                 #address-cells = <1>;
2605                                 #size-cells = <0>;
2606
2607                                 port@4 {
2608                                         reg = <4>;
2609                                         funnel1_in4: endpoint {
2610                                                 remote-endpoint = <&apss_merge_funnel_out>;
2611                                         };
2612                                 };
2613                         };
2614                 };
2615
2616                 funnel@6045000 {
2617                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2618                         reg = <0 0x06045000 0 0x1000>;
2619
2620                         clocks = <&aoss_qmp>;
2621                         clock-names = "apb_pclk";
2622
2623                         out-ports {
2624                                 port {
2625                                         merge_funnel_out: endpoint {
2626                                                 remote-endpoint = <&swao_funnel_in>;
2627                                         };
2628                                 };
2629                         };
2630
2631                         in-ports {
2632                                 #address-cells = <1>;
2633                                 #size-cells = <0>;
2634
2635                                 port@0 {
2636                                         reg = <0>;
2637                                         merge_funnel_in0: endpoint {
2638                                                 remote-endpoint = <&funnel0_out>;
2639                                         };
2640                                 };
2641
2642                                 port@1 {
2643                                         reg = <1>;
2644                                         merge_funnel_in1: endpoint {
2645                                                 remote-endpoint = <&funnel1_out>;
2646                                         };
2647                                 };
2648                         };
2649                 };
2650
2651                 replicator@6046000 {
2652                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2653                         reg = <0 0x06046000 0 0x1000>;
2654
2655                         clocks = <&aoss_qmp>;
2656                         clock-names = "apb_pclk";
2657
2658                         out-ports {
2659                                 port {
2660                                         replicator_out: endpoint {
2661                                                 remote-endpoint = <&etr_in>;
2662                                         };
2663                                 };
2664                         };
2665
2666                         in-ports {
2667                                 port {
2668                                         replicator_in: endpoint {
2669                                                 remote-endpoint = <&swao_replicator_out>;
2670                                         };
2671                                 };
2672                         };
2673                 };
2674
2675                 etr@6048000 {
2676                         compatible = "arm,coresight-tmc", "arm,primecell";
2677                         reg = <0 0x06048000 0 0x1000>;
2678                         iommus = <&apps_smmu 0x04c0 0>;
2679
2680                         clocks = <&aoss_qmp>;
2681                         clock-names = "apb_pclk";
2682                         arm,scatter-gather;
2683
2684                         in-ports {
2685                                 port {
2686                                         etr_in: endpoint {
2687                                                 remote-endpoint = <&replicator_out>;
2688                                         };
2689                                 };
2690                         };
2691                 };
2692
2693                 funnel@6b04000 {
2694                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2695                         reg = <0 0x06b04000 0 0x1000>;
2696
2697                         clocks = <&aoss_qmp>;
2698                         clock-names = "apb_pclk";
2699
2700                         out-ports {
2701                                 port {
2702                                         swao_funnel_out: endpoint {
2703                                                 remote-endpoint = <&etf_in>;
2704                                         };
2705                                 };
2706                         };
2707
2708                         in-ports {
2709                                 #address-cells = <1>;
2710                                 #size-cells = <0>;
2711
2712                                 port@7 {
2713                                         reg = <7>;
2714                                         swao_funnel_in: endpoint {
2715                                                 remote-endpoint = <&merge_funnel_out>;
2716                                         };
2717                                 };
2718                         };
2719                 };
2720
2721                 etf@6b05000 {
2722                         compatible = "arm,coresight-tmc", "arm,primecell";
2723                         reg = <0 0x06b05000 0 0x1000>;
2724
2725                         clocks = <&aoss_qmp>;
2726                         clock-names = "apb_pclk";
2727
2728                         out-ports {
2729                                 port {
2730                                         etf_out: endpoint {
2731                                                 remote-endpoint = <&swao_replicator_in>;
2732                                         };
2733                                 };
2734                         };
2735
2736                         in-ports {
2737                                 port {
2738                                         etf_in: endpoint {
2739                                                 remote-endpoint = <&swao_funnel_out>;
2740                                         };
2741                                 };
2742                         };
2743                 };
2744
2745                 replicator@6b06000 {
2746                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2747                         reg = <0 0x06b06000 0 0x1000>;
2748
2749                         clocks = <&aoss_qmp>;
2750                         clock-names = "apb_pclk";
2751                         qcom,replicator-loses-context;
2752
2753                         out-ports {
2754                                 port {
2755                                         swao_replicator_out: endpoint {
2756                                                 remote-endpoint = <&replicator_in>;
2757                                         };
2758                                 };
2759                         };
2760
2761                         in-ports {
2762                                 port {
2763                                         swao_replicator_in: endpoint {
2764                                                 remote-endpoint = <&etf_out>;
2765                                         };
2766                                 };
2767                         };
2768                 };
2769
2770                 etm@7040000 {
2771                         compatible = "arm,coresight-etm4x", "arm,primecell";
2772                         reg = <0 0x07040000 0 0x1000>;
2773
2774                         cpu = <&CPU0>;
2775
2776                         clocks = <&aoss_qmp>;
2777                         clock-names = "apb_pclk";
2778                         arm,coresight-loses-context-with-cpu;
2779                         qcom,skip-power-up;
2780
2781                         out-ports {
2782                                 port {
2783                                         etm0_out: endpoint {
2784                                                 remote-endpoint = <&apss_funnel_in0>;
2785                                         };
2786                                 };
2787                         };
2788                 };
2789
2790                 etm@7140000 {
2791                         compatible = "arm,coresight-etm4x", "arm,primecell";
2792                         reg = <0 0x07140000 0 0x1000>;
2793
2794                         cpu = <&CPU1>;
2795
2796                         clocks = <&aoss_qmp>;
2797                         clock-names = "apb_pclk";
2798                         arm,coresight-loses-context-with-cpu;
2799                         qcom,skip-power-up;
2800
2801                         out-ports {
2802                                 port {
2803                                         etm1_out: endpoint {
2804                                                 remote-endpoint = <&apss_funnel_in1>;
2805                                         };
2806                                 };
2807                         };
2808                 };
2809
2810                 etm@7240000 {
2811                         compatible = "arm,coresight-etm4x", "arm,primecell";
2812                         reg = <0 0x07240000 0 0x1000>;
2813
2814                         cpu = <&CPU2>;
2815
2816                         clocks = <&aoss_qmp>;
2817                         clock-names = "apb_pclk";
2818                         arm,coresight-loses-context-with-cpu;
2819                         qcom,skip-power-up;
2820
2821                         out-ports {
2822                                 port {
2823                                         etm2_out: endpoint {
2824                                                 remote-endpoint = <&apss_funnel_in2>;
2825                                         };
2826                                 };
2827                         };
2828                 };
2829
2830                 etm@7340000 {
2831                         compatible = "arm,coresight-etm4x", "arm,primecell";
2832                         reg = <0 0x07340000 0 0x1000>;
2833
2834                         cpu = <&CPU3>;
2835
2836                         clocks = <&aoss_qmp>;
2837                         clock-names = "apb_pclk";
2838                         arm,coresight-loses-context-with-cpu;
2839                         qcom,skip-power-up;
2840
2841                         out-ports {
2842                                 port {
2843                                         etm3_out: endpoint {
2844                                                 remote-endpoint = <&apss_funnel_in3>;
2845                                         };
2846                                 };
2847                         };
2848                 };
2849
2850                 etm@7440000 {
2851                         compatible = "arm,coresight-etm4x", "arm,primecell";
2852                         reg = <0 0x07440000 0 0x1000>;
2853
2854                         cpu = <&CPU4>;
2855
2856                         clocks = <&aoss_qmp>;
2857                         clock-names = "apb_pclk";
2858                         arm,coresight-loses-context-with-cpu;
2859                         qcom,skip-power-up;
2860
2861                         out-ports {
2862                                 port {
2863                                         etm4_out: endpoint {
2864                                                 remote-endpoint = <&apss_funnel_in4>;
2865                                         };
2866                                 };
2867                         };
2868                 };
2869
2870                 etm@7540000 {
2871                         compatible = "arm,coresight-etm4x", "arm,primecell";
2872                         reg = <0 0x07540000 0 0x1000>;
2873
2874                         cpu = <&CPU5>;
2875
2876                         clocks = <&aoss_qmp>;
2877                         clock-names = "apb_pclk";
2878                         arm,coresight-loses-context-with-cpu;
2879                         qcom,skip-power-up;
2880
2881                         out-ports {
2882                                 port {
2883                                         etm5_out: endpoint {
2884                                                 remote-endpoint = <&apss_funnel_in5>;
2885                                         };
2886                                 };
2887                         };
2888                 };
2889
2890                 etm@7640000 {
2891                         compatible = "arm,coresight-etm4x", "arm,primecell";
2892                         reg = <0 0x07640000 0 0x1000>;
2893
2894                         cpu = <&CPU6>;
2895
2896                         clocks = <&aoss_qmp>;
2897                         clock-names = "apb_pclk";
2898                         arm,coresight-loses-context-with-cpu;
2899                         qcom,skip-power-up;
2900
2901                         out-ports {
2902                                 port {
2903                                         etm6_out: endpoint {
2904                                                 remote-endpoint = <&apss_funnel_in6>;
2905                                         };
2906                                 };
2907                         };
2908                 };
2909
2910                 etm@7740000 {
2911                         compatible = "arm,coresight-etm4x", "arm,primecell";
2912                         reg = <0 0x07740000 0 0x1000>;
2913
2914                         cpu = <&CPU7>;
2915
2916                         clocks = <&aoss_qmp>;
2917                         clock-names = "apb_pclk";
2918                         arm,coresight-loses-context-with-cpu;
2919                         qcom,skip-power-up;
2920
2921                         out-ports {
2922                                 port {
2923                                         etm7_out: endpoint {
2924                                                 remote-endpoint = <&apss_funnel_in7>;
2925                                         };
2926                                 };
2927                         };
2928                 };
2929
2930                 funnel@7800000 { /* APSS Funnel */
2931                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2932                         reg = <0 0x07800000 0 0x1000>;
2933
2934                         clocks = <&aoss_qmp>;
2935                         clock-names = "apb_pclk";
2936
2937                         out-ports {
2938                                 port {
2939                                         apss_funnel_out: endpoint {
2940                                                 remote-endpoint = <&apss_merge_funnel_in>;
2941                                         };
2942                                 };
2943                         };
2944
2945                         in-ports {
2946                                 #address-cells = <1>;
2947                                 #size-cells = <0>;
2948
2949                                 port@0 {
2950                                         reg = <0>;
2951                                         apss_funnel_in0: endpoint {
2952                                                 remote-endpoint = <&etm0_out>;
2953                                         };
2954                                 };
2955
2956                                 port@1 {
2957                                         reg = <1>;
2958                                         apss_funnel_in1: endpoint {
2959                                                 remote-endpoint = <&etm1_out>;
2960                                         };
2961                                 };
2962
2963                                 port@2 {
2964                                         reg = <2>;
2965                                         apss_funnel_in2: endpoint {
2966                                                 remote-endpoint = <&etm2_out>;
2967                                         };
2968                                 };
2969
2970                                 port@3 {
2971                                         reg = <3>;
2972                                         apss_funnel_in3: endpoint {
2973                                                 remote-endpoint = <&etm3_out>;
2974                                         };
2975                                 };
2976
2977                                 port@4 {
2978                                         reg = <4>;
2979                                         apss_funnel_in4: endpoint {
2980                                                 remote-endpoint = <&etm4_out>;
2981                                         };
2982                                 };
2983
2984                                 port@5 {
2985                                         reg = <5>;
2986                                         apss_funnel_in5: endpoint {
2987                                                 remote-endpoint = <&etm5_out>;
2988                                         };
2989                                 };
2990
2991                                 port@6 {
2992                                         reg = <6>;
2993                                         apss_funnel_in6: endpoint {
2994                                                 remote-endpoint = <&etm6_out>;
2995                                         };
2996                                 };
2997
2998                                 port@7 {
2999                                         reg = <7>;
3000                                         apss_funnel_in7: endpoint {
3001                                                 remote-endpoint = <&etm7_out>;
3002                                         };
3003                                 };
3004                         };
3005                 };
3006
3007                 funnel@7810000 {
3008                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3009                         reg = <0 0x07810000 0 0x1000>;
3010
3011                         clocks = <&aoss_qmp>;
3012                         clock-names = "apb_pclk";
3013
3014                         out-ports {
3015                                 port {
3016                                         apss_merge_funnel_out: endpoint {
3017                                                 remote-endpoint = <&funnel1_in4>;
3018                                         };
3019                                 };
3020                         };
3021
3022                         in-ports {
3023                                 port {
3024                                         apss_merge_funnel_in: endpoint {
3025                                                 remote-endpoint = <&apss_funnel_out>;
3026                                         };
3027                                 };
3028                         };
3029                 };
3030
3031                 sdhc_2: mmc@8804000 {
3032                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3033                         pinctrl-names = "default", "sleep";
3034                         pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3035                         pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3036                         status = "disabled";
3037
3038                         reg = <0 0x08804000 0 0x1000>;
3039
3040                         iommus = <&apps_smmu 0x100 0x0>;
3041                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3042                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3043                         interrupt-names = "hc_irq", "pwr_irq";
3044
3045                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3046                                  <&gcc GCC_SDCC2_APPS_CLK>,
3047                                  <&rpmhcc RPMH_CXO_CLK>;
3048                         clock-names = "iface", "core", "xo";
3049                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3050                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3051                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3052                         power-domains = <&rpmhpd SC7280_CX>;
3053                         operating-points-v2 = <&sdhc2_opp_table>;
3054
3055                         bus-width = <4>;
3056
3057                         qcom,dll-config = <0x0007642c>;
3058
3059                         resets = <&gcc GCC_SDCC2_BCR>;
3060
3061                         sdhc2_opp_table: opp-table {
3062                                 compatible = "operating-points-v2";
3063
3064                                 opp-100000000 {
3065                                         opp-hz = /bits/ 64 <100000000>;
3066                                         required-opps = <&rpmhpd_opp_low_svs>;
3067                                         opp-peak-kBps = <1800000 400000>;
3068                                         opp-avg-kBps = <100000 0>;
3069                                 };
3070
3071                                 opp-202000000 {
3072                                         opp-hz = /bits/ 64 <202000000>;
3073                                         required-opps = <&rpmhpd_opp_nom>;
3074                                         opp-peak-kBps = <5400000 1600000>;
3075                                         opp-avg-kBps = <200000 0>;
3076                                 };
3077                         };
3078
3079                 };
3080
3081                 usb_1_hsphy: phy@88e3000 {
3082                         compatible = "qcom,sc7280-usb-hs-phy",
3083                                      "qcom,usb-snps-hs-7nm-phy";
3084                         reg = <0 0x088e3000 0 0x400>;
3085                         status = "disabled";
3086                         #phy-cells = <0>;
3087
3088                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3089                         clock-names = "ref";
3090
3091                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
3092                 };
3093
3094                 usb_2_hsphy: phy@88e4000 {
3095                         compatible = "qcom,sc7280-usb-hs-phy",
3096                                      "qcom,usb-snps-hs-7nm-phy";
3097                         reg = <0 0x088e4000 0 0x400>;
3098                         status = "disabled";
3099                         #phy-cells = <0>;
3100
3101                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3102                         clock-names = "ref";
3103
3104                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3105                 };
3106
3107                 usb_1_qmpphy: phy-wrapper@88e9000 {
3108                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3109                                      "qcom,sm8250-qmp-usb3-dp-phy";
3110                         reg = <0 0x088e9000 0 0x200>,
3111                               <0 0x088e8000 0 0x40>,
3112                               <0 0x088ea000 0 0x200>;
3113                         status = "disabled";
3114                         #address-cells = <2>;
3115                         #size-cells = <2>;
3116                         ranges;
3117
3118                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3119                                  <&rpmhcc RPMH_CXO_CLK>,
3120                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
3121                         clock-names = "aux", "ref_clk_src", "com_aux";
3122
3123                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
3124                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
3125                         reset-names = "phy", "common";
3126
3127                         usb_1_ssphy: usb3-phy@88e9200 {
3128                                 reg = <0 0x088e9200 0 0x200>,
3129                                       <0 0x088e9400 0 0x200>,
3130                                       <0 0x088e9c00 0 0x400>,
3131                                       <0 0x088e9600 0 0x200>,
3132                                       <0 0x088e9800 0 0x200>,
3133                                       <0 0x088e9a00 0 0x100>;
3134                                 #clock-cells = <0>;
3135                                 #phy-cells = <0>;
3136                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3137                                 clock-names = "pipe0";
3138                                 clock-output-names = "usb3_phy_pipe_clk_src";
3139                         };
3140
3141                         dp_phy: dp-phy@88ea200 {
3142                                 reg = <0 0x088ea200 0 0x200>,
3143                                       <0 0x088ea400 0 0x200>,
3144                                       <0 0x088eaa00 0 0x200>,
3145                                       <0 0x088ea600 0 0x200>,
3146                                       <0 0x088ea800 0 0x200>;
3147                                 #phy-cells = <0>;
3148                                 #clock-cells = <1>;
3149                         };
3150                 };
3151
3152                 usb_2: usb@8cf8800 {
3153                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3154                         reg = <0 0x08cf8800 0 0x400>;
3155                         status = "disabled";
3156                         #address-cells = <2>;
3157                         #size-cells = <2>;
3158                         ranges;
3159                         dma-ranges;
3160
3161                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3162                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3163                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3164                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3165                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
3166                         clock-names = "cfg_noc",
3167                                       "core",
3168                                       "iface",
3169                                       "sleep",
3170                                       "mock_utmi";
3171
3172                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3173                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3174                         assigned-clock-rates = <19200000>, <200000000>;
3175
3176                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3177                                               <&pdc 12 IRQ_TYPE_EDGE_RISING>,
3178                                               <&pdc 13 IRQ_TYPE_EDGE_RISING>;
3179                         interrupt-names = "hs_phy_irq",
3180                                           "dp_hs_phy_irq",
3181                                           "dm_hs_phy_irq";
3182
3183                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3184
3185                         resets = <&gcc GCC_USB30_SEC_BCR>;
3186
3187                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3188                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3189                         interconnect-names = "usb-ddr", "apps-usb";
3190
3191                         usb_2_dwc3: usb@8c00000 {
3192                                 compatible = "snps,dwc3";
3193                                 reg = <0 0x08c00000 0 0xe000>;
3194                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
3195                                 iommus = <&apps_smmu 0xa0 0x0>;
3196                                 snps,dis_u2_susphy_quirk;
3197                                 snps,dis_enblslpm_quirk;
3198                                 phys = <&usb_2_hsphy>;
3199                                 phy-names = "usb2-phy";
3200                                 maximum-speed = "high-speed";
3201                                 usb-role-switch;
3202                                 port {
3203                                         usb2_role_switch: endpoint {
3204                                                 remote-endpoint = <&eud_ep>;
3205                                         };
3206                                 };
3207                         };
3208                 };
3209
3210                 qspi: spi@88dc000 {
3211                         compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3212                         reg = <0 0x088dc000 0 0x1000>;
3213                         #address-cells = <1>;
3214                         #size-cells = <0>;
3215                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3216                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
3217                                  <&gcc GCC_QSPI_CORE_CLK>;
3218                         clock-names = "iface", "core";
3219                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
3220                                         &cnoc2 SLAVE_QSPI_0 0>;
3221                         interconnect-names = "qspi-config";
3222                         power-domains = <&rpmhpd SC7280_CX>;
3223                         operating-points-v2 = <&qspi_opp_table>;
3224                         status = "disabled";
3225                 };
3226
3227                 remoteproc_wpss: remoteproc@8a00000 {
3228                         compatible = "qcom,sc7280-wpss-pil";
3229                         reg = <0 0x08a00000 0 0x10000>;
3230
3231                         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3232                                               <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3233                                               <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3234                                               <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3235                                               <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
3236                                               <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
3237                         interrupt-names = "wdog", "fatal", "ready", "handover",
3238                                           "stop-ack", "shutdown-ack";
3239
3240                         clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
3241                                  <&gcc GCC_WPSS_AHB_CLK>,
3242                                  <&gcc GCC_WPSS_RSCP_CLK>,
3243                                  <&rpmhcc RPMH_CXO_CLK>;
3244                         clock-names = "ahb_bdg", "ahb",
3245                                       "rscp", "xo";
3246
3247                         power-domains = <&rpmhpd SC7280_CX>,
3248                                         <&rpmhpd SC7280_MX>;
3249                         power-domain-names = "cx", "mx";
3250
3251                         memory-region = <&wpss_mem>;
3252
3253                         qcom,qmp = <&aoss_qmp>;
3254
3255                         qcom,smem-states = <&wpss_smp2p_out 0>;
3256                         qcom,smem-state-names = "stop";
3257
3258                         resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
3259                                  <&pdc_reset PDC_WPSS_SYNC_RESET>;
3260                         reset-names = "restart", "pdc_sync";
3261
3262                         qcom,halt-regs = <&tcsr_mutex 0x37000>;
3263
3264                         status = "disabled";
3265
3266                         glink-edge {
3267                                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3268                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
3269                                                              IRQ_TYPE_EDGE_RISING>;
3270                                 mboxes = <&ipcc IPCC_CLIENT_WPSS
3271                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3272
3273                                 label = "wpss";
3274                                 qcom,remote-pid = <13>;
3275                         };
3276                 };
3277
3278                 dc_noc: interconnect@90e0000 {
3279                         reg = <0 0x090e0000 0 0x5080>;
3280                         compatible = "qcom,sc7280-dc-noc";
3281                         #interconnect-cells = <2>;
3282                         qcom,bcm-voters = <&apps_bcm_voter>;
3283                 };
3284
3285                 gem_noc: interconnect@9100000 {
3286                         reg = <0 0x9100000 0 0xe2200>;
3287                         compatible = "qcom,sc7280-gem-noc";
3288                         #interconnect-cells = <2>;
3289                         qcom,bcm-voters = <&apps_bcm_voter>;
3290                 };
3291
3292                 system-cache-controller@9200000 {
3293                         compatible = "qcom,sc7280-llcc";
3294                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
3295                         reg-names = "llcc_base", "llcc_broadcast_base";
3296                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3297                 };
3298
3299                 eud: eud@88e0000 {
3300                         compatible = "qcom,sc7280-eud","qcom,eud";
3301                         reg = <0 0x88e0000 0 0x2000>,
3302                               <0 0x88e2000 0 0x1000>;
3303                         interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3304                         ports {
3305                                 port@0 {
3306                                         eud_ep: endpoint {
3307                                                 remote-endpoint = <&usb2_role_switch>;
3308                                         };
3309                                 };
3310                                 port@1 {
3311                                         eud_con: endpoint {
3312                                                 remote-endpoint = <&con_eud>;
3313                                         };
3314                                 };
3315                         };
3316                 };
3317
3318                 eud_typec: connector {
3319                         compatible = "usb-c-connector";
3320                         ports {
3321                                 port@0 {
3322                                         con_eud: endpoint {
3323                                                 remote-endpoint = <&eud_con>;
3324                                         };
3325                                 };
3326                         };
3327                 };
3328
3329                 nsp_noc: interconnect@a0c0000 {
3330                         reg = <0 0x0a0c0000 0 0x10000>;
3331                         compatible = "qcom,sc7280-nsp-noc";
3332                         #interconnect-cells = <2>;
3333                         qcom,bcm-voters = <&apps_bcm_voter>;
3334                 };
3335
3336                 usb_1: usb@a6f8800 {
3337                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3338                         reg = <0 0x0a6f8800 0 0x400>;
3339                         status = "disabled";
3340                         #address-cells = <2>;
3341                         #size-cells = <2>;
3342                         ranges;
3343                         dma-ranges;
3344
3345                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3346                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3347                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3348                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3349                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
3350                         clock-names = "cfg_noc",
3351                                       "core",
3352                                       "iface",
3353                                       "sleep",
3354                                       "mock_utmi";
3355
3356                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3357                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3358                         assigned-clock-rates = <19200000>, <200000000>;
3359
3360                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3361                                               <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
3362                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3363                                               <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
3364                         interrupt-names = "hs_phy_irq",
3365                                           "dp_hs_phy_irq",
3366                                           "dm_hs_phy_irq",
3367                                           "ss_phy_irq";
3368
3369                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3370
3371                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3372
3373                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3374                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3375                         interconnect-names = "usb-ddr", "apps-usb";
3376
3377                         usb_1_dwc3: usb@a600000 {
3378                                 compatible = "snps,dwc3";
3379                                 reg = <0 0x0a600000 0 0xe000>;
3380                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
3381                                 iommus = <&apps_smmu 0xe0 0x0>;
3382                                 snps,dis_u2_susphy_quirk;
3383                                 snps,dis_enblslpm_quirk;
3384                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
3385                                 phy-names = "usb2-phy", "usb3-phy";
3386                                 maximum-speed = "super-speed";
3387                                 wakeup-source;
3388                         };
3389                 };
3390
3391                 venus: video-codec@aa00000 {
3392                         compatible = "qcom,sc7280-venus";
3393                         reg = <0 0x0aa00000 0 0xd0600>;
3394                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
3395
3396                         clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
3397                                  <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
3398                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
3399                                  <&videocc VIDEO_CC_MVS0_CORE_CLK>,
3400                                  <&videocc VIDEO_CC_MVS0_AXI_CLK>;
3401                         clock-names = "core", "bus", "iface",
3402                                       "vcodec_core", "vcodec_bus";
3403
3404                         power-domains = <&videocc MVSC_GDSC>,
3405                                         <&videocc MVS0_GDSC>,
3406                                         <&rpmhpd SC7280_CX>;
3407                         power-domain-names = "venus", "vcodec0", "cx";
3408                         operating-points-v2 = <&venus_opp_table>;
3409
3410                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3411                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3412                         interconnect-names = "cpu-cfg", "video-mem";
3413
3414                         iommus = <&apps_smmu 0x2180 0x20>,
3415                                  <&apps_smmu 0x2184 0x20>;
3416                         memory-region = <&video_mem>;
3417
3418                         video-decoder {
3419                                 compatible = "venus-decoder";
3420                         };
3421
3422                         video-encoder {
3423                                 compatible = "venus-encoder";
3424                         };
3425
3426                         video-firmware {
3427                                 iommus = <&apps_smmu 0x21a2 0x0>;
3428                         };
3429
3430                         venus_opp_table: opp-table {
3431                                 compatible = "operating-points-v2";
3432
3433                                 opp-133330000 {
3434                                         opp-hz = /bits/ 64 <133330000>;
3435                                         required-opps = <&rpmhpd_opp_low_svs>;
3436                                 };
3437
3438                                 opp-240000000 {
3439                                         opp-hz = /bits/ 64 <240000000>;
3440                                         required-opps = <&rpmhpd_opp_svs>;
3441                                 };
3442
3443                                 opp-335000000 {
3444                                         opp-hz = /bits/ 64 <335000000>;
3445                                         required-opps = <&rpmhpd_opp_svs_l1>;
3446                                 };
3447
3448                                 opp-424000000 {
3449                                         opp-hz = /bits/ 64 <424000000>;
3450                                         required-opps = <&rpmhpd_opp_nom>;
3451                                 };
3452
3453                                 opp-460000048 {
3454                                         opp-hz = /bits/ 64 <460000048>;
3455                                         required-opps = <&rpmhpd_opp_turbo>;
3456                                 };
3457                         };
3458
3459                 };
3460
3461                 videocc: clock-controller@aaf0000 {
3462                         compatible = "qcom,sc7280-videocc";
3463                         reg = <0 0xaaf0000 0 0x10000>;
3464                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3465                                 <&rpmhcc RPMH_CXO_CLK_A>;
3466                         clock-names = "bi_tcxo", "bi_tcxo_ao";
3467                         #clock-cells = <1>;
3468                         #reset-cells = <1>;
3469                         #power-domain-cells = <1>;
3470                 };
3471
3472                 camcc: clock-controller@ad00000 {
3473                         compatible = "qcom,sc7280-camcc";
3474                         reg = <0 0x0ad00000 0 0x10000>;
3475                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3476                                 <&rpmhcc RPMH_CXO_CLK_A>,
3477                                 <&sleep_clk>;
3478                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3479                         #clock-cells = <1>;
3480                         #reset-cells = <1>;
3481                         #power-domain-cells = <1>;
3482                 };
3483
3484                 dispcc: clock-controller@af00000 {
3485                         compatible = "qcom,sc7280-dispcc";
3486                         reg = <0 0xaf00000 0 0x20000>;
3487                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3488                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3489                                  <&mdss_dsi_phy 0>,
3490                                  <&mdss_dsi_phy 1>,
3491                                  <&dp_phy 0>,
3492                                  <&dp_phy 1>,
3493                                  <&mdss_edp_phy 0>,
3494                                  <&mdss_edp_phy 1>;
3495                         clock-names = "bi_tcxo",
3496                                       "gcc_disp_gpll0_clk",
3497                                       "dsi0_phy_pll_out_byteclk",
3498                                       "dsi0_phy_pll_out_dsiclk",
3499                                       "dp_phy_pll_link_clk",
3500                                       "dp_phy_pll_vco_div_clk",
3501                                       "edp_phy_pll_link_clk",
3502                                       "edp_phy_pll_vco_div_clk";
3503                         #clock-cells = <1>;
3504                         #reset-cells = <1>;
3505                         #power-domain-cells = <1>;
3506                 };
3507
3508                 mdss: display-subsystem@ae00000 {
3509                         compatible = "qcom,sc7280-mdss";
3510                         reg = <0 0x0ae00000 0 0x1000>;
3511                         reg-names = "mdss";
3512
3513                         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3514
3515                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3516                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
3517                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
3518                         clock-names = "iface",
3519                                       "ahb",
3520                                       "core";
3521
3522                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3523                         interrupt-controller;
3524                         #interrupt-cells = <1>;
3525
3526                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3527                         interconnect-names = "mdp0-mem";
3528
3529                         iommus = <&apps_smmu 0x900 0x402>;
3530
3531                         #address-cells = <2>;
3532                         #size-cells = <2>;
3533                         ranges;
3534
3535                         status = "disabled";
3536
3537                         mdss_mdp: display-controller@ae01000 {
3538                                 compatible = "qcom,sc7280-dpu";
3539                                 reg = <0 0x0ae01000 0 0x8f030>,
3540                                         <0 0x0aeb0000 0 0x2008>;
3541                                 reg-names = "mdp", "vbif";
3542
3543                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3544                                         <&gcc GCC_DISP_SF_AXI_CLK>,
3545                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
3546                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3547                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
3548                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3549                                 clock-names = "bus",
3550                                               "nrt_bus",
3551                                               "iface",
3552                                               "lut",
3553                                               "core",
3554                                               "vsync";
3555                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3556                                                 <&dispcc DISP_CC_MDSS_AHB_CLK>;
3557                                 assigned-clock-rates = <19200000>,
3558                                                         <19200000>;
3559                                 operating-points-v2 = <&mdp_opp_table>;
3560                                 power-domains = <&rpmhpd SC7280_CX>;
3561
3562                                 interrupt-parent = <&mdss>;
3563                                 interrupts = <0>;
3564
3565                                 status = "disabled";
3566
3567                                 ports {
3568                                         #address-cells = <1>;
3569                                         #size-cells = <0>;
3570
3571                                         port@0 {
3572                                                 reg = <0>;
3573                                                 dpu_intf1_out: endpoint {
3574                                                         remote-endpoint = <&dsi0_in>;
3575                                                 };
3576                                         };
3577
3578                                         port@1 {
3579                                                 reg = <1>;
3580                                                 dpu_intf5_out: endpoint {
3581                                                         remote-endpoint = <&edp_in>;
3582                                                 };
3583                                         };
3584
3585                                         port@2 {
3586                                                 reg = <2>;
3587                                                 dpu_intf0_out: endpoint {
3588                                                         remote-endpoint = <&dp_in>;
3589                                                 };
3590                                         };
3591                                 };
3592
3593                                 mdp_opp_table: opp-table {
3594                                         compatible = "operating-points-v2";
3595
3596                                         opp-200000000 {
3597                                                 opp-hz = /bits/ 64 <200000000>;
3598                                                 required-opps = <&rpmhpd_opp_low_svs>;
3599                                         };
3600
3601                                         opp-300000000 {
3602                                                 opp-hz = /bits/ 64 <300000000>;
3603                                                 required-opps = <&rpmhpd_opp_svs>;
3604                                         };
3605
3606                                         opp-380000000 {
3607                                                 opp-hz = /bits/ 64 <380000000>;
3608                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3609                                         };
3610
3611                                         opp-506666667 {
3612                                                 opp-hz = /bits/ 64 <506666667>;
3613                                                 required-opps = <&rpmhpd_opp_nom>;
3614                                         };
3615                                 };
3616                         };
3617
3618                         mdss_dsi: dsi@ae94000 {
3619                                 compatible = "qcom,mdss-dsi-ctrl";
3620                                 reg = <0 0x0ae94000 0 0x400>;
3621                                 reg-names = "dsi_ctrl";
3622
3623                                 interrupt-parent = <&mdss>;
3624                                 interrupts = <4>;
3625
3626                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3627                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3628                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3629                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3630                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3631                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3632                                 clock-names = "byte",
3633                                               "byte_intf",
3634                                               "pixel",
3635                                               "core",
3636                                               "iface",
3637                                               "bus";
3638
3639                                 operating-points-v2 = <&dsi_opp_table>;
3640                                 power-domains = <&rpmhpd SC7280_CX>;
3641
3642                                 phys = <&mdss_dsi_phy>;
3643                                 phy-names = "dsi";
3644
3645                                 #address-cells = <1>;
3646                                 #size-cells = <0>;
3647
3648                                 status = "disabled";
3649
3650                                 ports {
3651                                         #address-cells = <1>;
3652                                         #size-cells = <0>;
3653
3654                                         port@0 {
3655                                                 reg = <0>;
3656                                                 dsi0_in: endpoint {
3657                                                         remote-endpoint = <&dpu_intf1_out>;
3658                                                 };
3659                                         };
3660
3661                                         port@1 {
3662                                                 reg = <1>;
3663                                                 dsi0_out: endpoint {
3664                                                 };
3665                                         };
3666                                 };
3667
3668                                 dsi_opp_table: opp-table {
3669                                         compatible = "operating-points-v2";
3670
3671                                         opp-187500000 {
3672                                                 opp-hz = /bits/ 64 <187500000>;
3673                                                 required-opps = <&rpmhpd_opp_low_svs>;
3674                                         };
3675
3676                                         opp-300000000 {
3677                                                 opp-hz = /bits/ 64 <300000000>;
3678                                                 required-opps = <&rpmhpd_opp_svs>;
3679                                         };
3680
3681                                         opp-358000000 {
3682                                                 opp-hz = /bits/ 64 <358000000>;
3683                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3684                                         };
3685                                 };
3686                         };
3687
3688                         mdss_dsi_phy: phy@ae94400 {
3689                                 compatible = "qcom,sc7280-dsi-phy-7nm";
3690                                 reg = <0 0x0ae94400 0 0x200>,
3691                                       <0 0x0ae94600 0 0x280>,
3692                                       <0 0x0ae94900 0 0x280>;
3693                                 reg-names = "dsi_phy",
3694                                             "dsi_phy_lane",
3695                                             "dsi_pll";
3696
3697                                 #clock-cells = <1>;
3698                                 #phy-cells = <0>;
3699
3700                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3701                                          <&rpmhcc RPMH_CXO_CLK>;
3702                                 clock-names = "iface", "ref";
3703
3704                                 status = "disabled";
3705                         };
3706
3707                         mdss_edp: edp@aea0000 {
3708                                 compatible = "qcom,sc7280-edp";
3709                                 pinctrl-names = "default";
3710                                 pinctrl-0 = <&edp_hot_plug_det>;
3711
3712                                 reg = <0 0xaea0000 0 0x200>,
3713                                       <0 0xaea0200 0 0x200>,
3714                                       <0 0xaea0400 0 0xc00>,
3715                                       <0 0xaea1000 0 0x400>;
3716
3717                                 interrupt-parent = <&mdss>;
3718                                 interrupts = <14>;
3719
3720                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3721                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
3722                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
3723                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
3724                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
3725                                 clock-names = "core_iface",
3726                                               "core_aux",
3727                                               "ctrl_link",
3728                                               "ctrl_link_iface",
3729                                               "stream_pixel";
3730                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3731                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
3732                                 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
3733
3734                                 phys = <&mdss_edp_phy>;
3735                                 phy-names = "dp";
3736
3737                                 operating-points-v2 = <&edp_opp_table>;
3738                                 power-domains = <&rpmhpd SC7280_CX>;
3739
3740                                 status = "disabled";
3741
3742                                 ports {
3743                                         #address-cells = <1>;
3744                                         #size-cells = <0>;
3745
3746                                         port@0 {
3747                                                 reg = <0>;
3748                                                 edp_in: endpoint {
3749                                                         remote-endpoint = <&dpu_intf5_out>;
3750                                                 };
3751                                         };
3752
3753                                         port@1 {
3754                                                 reg = <1>;
3755                                                 mdss_edp_out: endpoint { };
3756                                         };
3757                                 };
3758
3759                                 edp_opp_table: opp-table {
3760                                         compatible = "operating-points-v2";
3761
3762                                         opp-160000000 {
3763                                                 opp-hz = /bits/ 64 <160000000>;
3764                                                 required-opps = <&rpmhpd_opp_low_svs>;
3765                                         };
3766
3767                                         opp-270000000 {
3768                                                 opp-hz = /bits/ 64 <270000000>;
3769                                                 required-opps = <&rpmhpd_opp_svs>;
3770                                         };
3771
3772                                         opp-540000000 {
3773                                                 opp-hz = /bits/ 64 <540000000>;
3774                                                 required-opps = <&rpmhpd_opp_nom>;
3775                                         };
3776
3777                                         opp-810000000 {
3778                                                 opp-hz = /bits/ 64 <810000000>;
3779                                                 required-opps = <&rpmhpd_opp_nom>;
3780                                         };
3781                                 };
3782                         };
3783
3784                         mdss_edp_phy: phy@aec2a00 {
3785                                 compatible = "qcom,sc7280-edp-phy";
3786
3787                                 reg = <0 0xaec2a00 0 0x19c>,
3788                                       <0 0xaec2200 0 0xa0>,
3789                                       <0 0xaec2600 0 0xa0>,
3790                                       <0 0xaec2000 0 0x1c0>;
3791
3792                                 clocks = <&rpmhcc RPMH_CXO_CLK>,
3793                                          <&gcc GCC_EDP_CLKREF_EN>;
3794                                 clock-names = "aux",
3795                                               "cfg_ahb";
3796
3797                                 #clock-cells = <1>;
3798                                 #phy-cells = <0>;
3799
3800                                 status = "disabled";
3801                         };
3802
3803                         mdss_dp: displayport-controller@ae90000 {
3804                                 compatible = "qcom,sc7280-dp";
3805
3806                                 reg = <0 0xae90000 0 0x200>,
3807                                       <0 0xae90200 0 0x200>,
3808                                       <0 0xae90400 0 0xc00>,
3809                                       <0 0xae91000 0 0x400>,
3810                                       <0 0xae91400 0 0x400>;
3811
3812                                 interrupt-parent = <&mdss>;
3813                                 interrupts = <12>;
3814
3815                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3816                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3817                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3818                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3819                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3820                                 clock-names = "core_iface",
3821                                                 "core_aux",
3822                                                 "ctrl_link",
3823                                                 "ctrl_link_iface",
3824                                                 "stream_pixel";
3825                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3826                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3827                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3828                                 phys = <&dp_phy>;
3829                                 phy-names = "dp";
3830
3831                                 operating-points-v2 = <&dp_opp_table>;
3832                                 power-domains = <&rpmhpd SC7280_CX>;
3833
3834                                 #sound-dai-cells = <0>;
3835
3836                                 status = "disabled";
3837
3838                                 ports {
3839                                         #address-cells = <1>;
3840                                         #size-cells = <0>;
3841
3842                                         port@0 {
3843                                                 reg = <0>;
3844                                                 dp_in: endpoint {
3845                                                         remote-endpoint = <&dpu_intf0_out>;
3846                                                 };
3847                                         };
3848
3849                                         port@1 {
3850                                                 reg = <1>;
3851                                                 dp_out: endpoint { };
3852                                         };
3853                                 };
3854
3855                                 dp_opp_table: opp-table {
3856                                         compatible = "operating-points-v2";
3857
3858                                         opp-160000000 {
3859                                                 opp-hz = /bits/ 64 <160000000>;
3860                                                 required-opps = <&rpmhpd_opp_low_svs>;
3861                                         };
3862
3863                                         opp-270000000 {
3864                                                 opp-hz = /bits/ 64 <270000000>;
3865                                                 required-opps = <&rpmhpd_opp_svs>;
3866                                         };
3867
3868                                         opp-540000000 {
3869                                                 opp-hz = /bits/ 64 <540000000>;
3870                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3871                                         };
3872
3873                                         opp-810000000 {
3874                                                 opp-hz = /bits/ 64 <810000000>;
3875                                                 required-opps = <&rpmhpd_opp_nom>;
3876                                         };
3877                                 };
3878                         };
3879                 };
3880
3881                 pdc: interrupt-controller@b220000 {
3882                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
3883                         reg = <0 0x0b220000 0 0x30000>;
3884                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
3885                                           <55 306 4>, <59 312 3>, <62 374 2>,
3886                                           <64 434 2>, <66 438 3>, <69 86 1>,
3887                                           <70 520 54>, <124 609 31>, <155 63 1>,
3888                                           <156 716 12>;
3889                         #interrupt-cells = <2>;
3890                         interrupt-parent = <&intc>;
3891                         interrupt-controller;
3892                 };
3893
3894                 pdc_reset: reset-controller@b5e0000 {
3895                         compatible = "qcom,sc7280-pdc-global";
3896                         reg = <0 0x0b5e0000 0 0x20000>;
3897                         #reset-cells = <1>;
3898                 };
3899
3900                 tsens0: thermal-sensor@c263000 {
3901                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
3902                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3903                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3904                         #qcom,sensors = <15>;
3905                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3906                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3907                         interrupt-names = "uplow","critical";
3908                         #thermal-sensor-cells = <1>;
3909                 };
3910
3911                 tsens1: thermal-sensor@c265000 {
3912                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
3913                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3914                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3915                         #qcom,sensors = <12>;
3916                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3917                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3918                         interrupt-names = "uplow","critical";
3919                         #thermal-sensor-cells = <1>;
3920                 };
3921
3922                 aoss_reset: reset-controller@c2a0000 {
3923                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
3924                         reg = <0 0x0c2a0000 0 0x31000>;
3925                         #reset-cells = <1>;
3926                 };
3927
3928                 aoss_qmp: power-controller@c300000 {
3929                         compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
3930                         reg = <0 0x0c300000 0 0x400>;
3931                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
3932                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
3933                                                      IRQ_TYPE_EDGE_RISING>;
3934                         mboxes = <&ipcc IPCC_CLIENT_AOP
3935                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
3936
3937                         #clock-cells = <0>;
3938                 };
3939
3940                 sram@c3f0000 {
3941                         compatible = "qcom,rpmh-stats";
3942                         reg = <0 0x0c3f0000 0 0x400>;
3943                 };
3944
3945                 spmi_bus: spmi@c440000 {
3946                         compatible = "qcom,spmi-pmic-arb";
3947                         reg = <0 0x0c440000 0 0x1100>,
3948                               <0 0x0c600000 0 0x2000000>,
3949                               <0 0x0e600000 0 0x100000>,
3950                               <0 0x0e700000 0 0xa0000>,
3951                               <0 0x0c40a000 0 0x26000>;
3952                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3953                         interrupt-names = "periph_irq";
3954                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3955                         qcom,ee = <0>;
3956                         qcom,channel = <0>;
3957                         #address-cells = <1>;
3958                         #size-cells = <1>;
3959                         interrupt-controller;
3960                         #interrupt-cells = <4>;
3961                 };
3962
3963                 tlmm: pinctrl@f100000 {
3964                         compatible = "qcom,sc7280-pinctrl";
3965                         reg = <0 0x0f100000 0 0x300000>;
3966                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
3967                         gpio-controller;
3968                         #gpio-cells = <2>;
3969                         interrupt-controller;
3970                         #interrupt-cells = <2>;
3971                         gpio-ranges = <&tlmm 0 0 175>;
3972                         wakeup-parent = <&pdc>;
3973
3974                         dp_hot_plug_det: dp-hot-plug-det {
3975                                 pins = "gpio47";
3976                                 function = "dp_hot";
3977                         };
3978
3979                         edp_hot_plug_det: edp-hot-plug-det {
3980                                 pins = "gpio60";
3981                                 function = "edp_hot";
3982                         };
3983
3984                         mi2s0_data0: mi2s0-data0 {
3985                                 pins = "gpio98";
3986                                 function = "mi2s0_data0";
3987                         };
3988
3989                         mi2s0_data1: mi2s0-data1 {
3990                                 pins = "gpio99";
3991                                 function = "mi2s0_data1";
3992                         };
3993
3994                         mi2s0_mclk: mi2s0-mclk {
3995                                 pins = "gpio96";
3996                                 function = "pri_mi2s";
3997                         };
3998
3999                         mi2s0_sclk: mi2s0-sclk {
4000                                 pins = "gpio97";
4001                                 function = "mi2s0_sck";
4002                         };
4003
4004                         mi2s0_ws: mi2s0-ws {
4005                                 pins = "gpio100";
4006                                 function = "mi2s0_ws";
4007                         };
4008
4009                         mi2s1_data0: mi2s1-data0 {
4010                                 pins = "gpio107";
4011                                 function = "mi2s1_data0";
4012                         };
4013
4014                         mi2s1_sclk: mi2s1-sclk {
4015                                 pins = "gpio106";
4016                                 function = "mi2s1_sck";
4017                         };
4018
4019                         mi2s1_ws: mi2s1-ws {
4020                                 pins = "gpio108";
4021                                 function = "mi2s1_ws";
4022                         };
4023
4024                         pcie1_clkreq_n: pcie1-clkreq-n {
4025                                 pins = "gpio79";
4026                                 function = "pcie1_clkreqn";
4027                         };
4028
4029                         qspi_clk: qspi-clk {
4030                                 pins = "gpio14";
4031                                 function = "qspi_clk";
4032                         };
4033
4034                         qspi_cs0: qspi-cs0 {
4035                                 pins = "gpio15";
4036                                 function = "qspi_cs";
4037                         };
4038
4039                         qspi_cs1: qspi-cs1 {
4040                                 pins = "gpio19";
4041                                 function = "qspi_cs";
4042                         };
4043
4044                         qspi_data01: qspi-data01 {
4045                                 pins = "gpio12", "gpio13";
4046                                 function = "qspi_data";
4047                         };
4048
4049                         qspi_data12: qspi-data12 {
4050                                 pins = "gpio16", "gpio17";
4051                                 function = "qspi_data";
4052                         };
4053
4054                         qup_i2c0_data_clk: qup-i2c0-data-clk {
4055                                 pins = "gpio0", "gpio1";
4056                                 function = "qup00";
4057                         };
4058
4059                         qup_i2c1_data_clk: qup-i2c1-data-clk {
4060                                 pins = "gpio4", "gpio5";
4061                                 function = "qup01";
4062                         };
4063
4064                         qup_i2c2_data_clk: qup-i2c2-data-clk {
4065                                 pins = "gpio8", "gpio9";
4066                                 function = "qup02";
4067                         };
4068
4069                         qup_i2c3_data_clk: qup-i2c3-data-clk {
4070                                 pins = "gpio12", "gpio13";
4071                                 function = "qup03";
4072                         };
4073
4074                         qup_i2c4_data_clk: qup-i2c4-data-clk {
4075                                 pins = "gpio16", "gpio17";
4076                                 function = "qup04";
4077                         };
4078
4079                         qup_i2c5_data_clk: qup-i2c5-data-clk {
4080                                 pins = "gpio20", "gpio21";
4081                                 function = "qup05";
4082                         };
4083
4084                         qup_i2c6_data_clk: qup-i2c6-data-clk {
4085                                 pins = "gpio24", "gpio25";
4086                                 function = "qup06";
4087                         };
4088
4089                         qup_i2c7_data_clk: qup-i2c7-data-clk {
4090                                 pins = "gpio28", "gpio29";
4091                                 function = "qup07";
4092                         };
4093
4094                         qup_i2c8_data_clk: qup-i2c8-data-clk {
4095                                 pins = "gpio32", "gpio33";
4096                                 function = "qup10";
4097                         };
4098
4099                         qup_i2c9_data_clk: qup-i2c9-data-clk {
4100                                 pins = "gpio36", "gpio37";
4101                                 function = "qup11";
4102                         };
4103
4104                         qup_i2c10_data_clk: qup-i2c10-data-clk {
4105                                 pins = "gpio40", "gpio41";
4106                                 function = "qup12";
4107                         };
4108
4109                         qup_i2c11_data_clk: qup-i2c11-data-clk {
4110                                 pins = "gpio44", "gpio45";
4111                                 function = "qup13";
4112                         };
4113
4114                         qup_i2c12_data_clk: qup-i2c12-data-clk {
4115                                 pins = "gpio48", "gpio49";
4116                                 function = "qup14";
4117                         };
4118
4119                         qup_i2c13_data_clk: qup-i2c13-data-clk {
4120                                 pins = "gpio52", "gpio53";
4121                                 function = "qup15";
4122                         };
4123
4124                         qup_i2c14_data_clk: qup-i2c14-data-clk {
4125                                 pins = "gpio56", "gpio57";
4126                                 function = "qup16";
4127                         };
4128
4129                         qup_i2c15_data_clk: qup-i2c15-data-clk {
4130                                 pins = "gpio60", "gpio61";
4131                                 function = "qup17";
4132                         };
4133
4134                         qup_spi0_data_clk: qup-spi0-data-clk {
4135                                 pins = "gpio0", "gpio1", "gpio2";
4136                                 function = "qup00";
4137                         };
4138
4139                         qup_spi0_cs: qup-spi0-cs {
4140                                 pins = "gpio3";
4141                                 function = "qup00";
4142                         };
4143
4144                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
4145                                 pins = "gpio3";
4146                                 function = "gpio";
4147                         };
4148
4149                         qup_spi1_data_clk: qup-spi1-data-clk {
4150                                 pins = "gpio4", "gpio5", "gpio6";
4151                                 function = "qup01";
4152                         };
4153
4154                         qup_spi1_cs: qup-spi1-cs {
4155                                 pins = "gpio7";
4156                                 function = "qup01";
4157                         };
4158
4159                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
4160                                 pins = "gpio7";
4161                                 function = "gpio";
4162                         };
4163
4164                         qup_spi2_data_clk: qup-spi2-data-clk {
4165                                 pins = "gpio8", "gpio9", "gpio10";
4166                                 function = "qup02";
4167                         };
4168
4169                         qup_spi2_cs: qup-spi2-cs {
4170                                 pins = "gpio11";
4171                                 function = "qup02";
4172                         };
4173
4174                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
4175                                 pins = "gpio11";
4176                                 function = "gpio";
4177                         };
4178
4179                         qup_spi3_data_clk: qup-spi3-data-clk {
4180                                 pins = "gpio12", "gpio13", "gpio14";
4181                                 function = "qup03";
4182                         };
4183
4184                         qup_spi3_cs: qup-spi3-cs {
4185                                 pins = "gpio15";
4186                                 function = "qup03";
4187                         };
4188
4189                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
4190                                 pins = "gpio15";
4191                                 function = "gpio";
4192                         };
4193
4194                         qup_spi4_data_clk: qup-spi4-data-clk {
4195                                 pins = "gpio16", "gpio17", "gpio18";
4196                                 function = "qup04";
4197                         };
4198
4199                         qup_spi4_cs: qup-spi4-cs {
4200                                 pins = "gpio19";
4201                                 function = "qup04";
4202                         };
4203
4204                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
4205                                 pins = "gpio19";
4206                                 function = "gpio";
4207                         };
4208
4209                         qup_spi5_data_clk: qup-spi5-data-clk {
4210                                 pins = "gpio20", "gpio21", "gpio22";
4211                                 function = "qup05";
4212                         };
4213
4214                         qup_spi5_cs: qup-spi5-cs {
4215                                 pins = "gpio23";
4216                                 function = "qup05";
4217                         };
4218
4219                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
4220                                 pins = "gpio23";
4221                                 function = "gpio";
4222                         };
4223
4224                         qup_spi6_data_clk: qup-spi6-data-clk {
4225                                 pins = "gpio24", "gpio25", "gpio26";
4226                                 function = "qup06";
4227                         };
4228
4229                         qup_spi6_cs: qup-spi6-cs {
4230                                 pins = "gpio27";
4231                                 function = "qup06";
4232                         };
4233
4234                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
4235                                 pins = "gpio27";
4236                                 function = "gpio";
4237                         };
4238
4239                         qup_spi7_data_clk: qup-spi7-data-clk {
4240                                 pins = "gpio28", "gpio29", "gpio30";
4241                                 function = "qup07";
4242                         };
4243
4244                         qup_spi7_cs: qup-spi7-cs {
4245                                 pins = "gpio31";
4246                                 function = "qup07";
4247                         };
4248
4249                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
4250                                 pins = "gpio31";
4251                                 function = "gpio";
4252                         };
4253
4254                         qup_spi8_data_clk: qup-spi8-data-clk {
4255                                 pins = "gpio32", "gpio33", "gpio34";
4256                                 function = "qup10";
4257                         };
4258
4259                         qup_spi8_cs: qup-spi8-cs {
4260                                 pins = "gpio35";
4261                                 function = "qup10";
4262                         };
4263
4264                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
4265                                 pins = "gpio35";
4266                                 function = "gpio";
4267                         };
4268
4269                         qup_spi9_data_clk: qup-spi9-data-clk {
4270                                 pins = "gpio36", "gpio37", "gpio38";
4271                                 function = "qup11";
4272                         };
4273
4274                         qup_spi9_cs: qup-spi9-cs {
4275                                 pins = "gpio39";
4276                                 function = "qup11";
4277                         };
4278
4279                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
4280                                 pins = "gpio39";
4281                                 function = "gpio";
4282                         };
4283
4284                         qup_spi10_data_clk: qup-spi10-data-clk {
4285                                 pins = "gpio40", "gpio41", "gpio42";
4286                                 function = "qup12";
4287                         };
4288
4289                         qup_spi10_cs: qup-spi10-cs {
4290                                 pins = "gpio43";
4291                                 function = "qup12";
4292                         };
4293
4294                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
4295                                 pins = "gpio43";
4296                                 function = "gpio";
4297                         };
4298
4299                         qup_spi11_data_clk: qup-spi11-data-clk {
4300                                 pins = "gpio44", "gpio45", "gpio46";
4301                                 function = "qup13";
4302                         };
4303
4304                         qup_spi11_cs: qup-spi11-cs {
4305                                 pins = "gpio47";
4306                                 function = "qup13";
4307                         };
4308
4309                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
4310                                 pins = "gpio47";
4311                                 function = "gpio";
4312                         };
4313
4314                         qup_spi12_data_clk: qup-spi12-data-clk {
4315                                 pins = "gpio48", "gpio49", "gpio50";
4316                                 function = "qup14";
4317                         };
4318
4319                         qup_spi12_cs: qup-spi12-cs {
4320                                 pins = "gpio51";
4321                                 function = "qup14";
4322                         };
4323
4324                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
4325                                 pins = "gpio51";
4326                                 function = "gpio";
4327                         };
4328
4329                         qup_spi13_data_clk: qup-spi13-data-clk {
4330                                 pins = "gpio52", "gpio53", "gpio54";
4331                                 function = "qup15";
4332                         };
4333
4334                         qup_spi13_cs: qup-spi13-cs {
4335                                 pins = "gpio55";
4336                                 function = "qup15";
4337                         };
4338
4339                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
4340                                 pins = "gpio55";
4341                                 function = "gpio";
4342                         };
4343
4344                         qup_spi14_data_clk: qup-spi14-data-clk {
4345                                 pins = "gpio56", "gpio57", "gpio58";
4346                                 function = "qup16";
4347                         };
4348
4349                         qup_spi14_cs: qup-spi14-cs {
4350                                 pins = "gpio59";
4351                                 function = "qup16";
4352                         };
4353
4354                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
4355                                 pins = "gpio59";
4356                                 function = "gpio";
4357                         };
4358
4359                         qup_spi15_data_clk: qup-spi15-data-clk {
4360                                 pins = "gpio60", "gpio61", "gpio62";
4361                                 function = "qup17";
4362                         };
4363
4364                         qup_spi15_cs: qup-spi15-cs {
4365                                 pins = "gpio63";
4366                                 function = "qup17";
4367                         };
4368
4369                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
4370                                 pins = "gpio63";
4371                                 function = "gpio";
4372                         };
4373
4374                         qup_uart0_cts: qup-uart0-cts {
4375                                 pins = "gpio0";
4376                                 function = "qup00";
4377                         };
4378
4379                         qup_uart0_rts: qup-uart0-rts {
4380                                 pins = "gpio1";
4381                                 function = "qup00";
4382                         };
4383
4384                         qup_uart0_tx: qup-uart0-tx {
4385                                 pins = "gpio2";
4386                                 function = "qup00";
4387                         };
4388
4389                         qup_uart0_rx: qup-uart0-rx {
4390                                 pins = "gpio3";
4391                                 function = "qup00";
4392                         };
4393
4394                         qup_uart1_cts: qup-uart1-cts {
4395                                 pins = "gpio4";
4396                                 function = "qup01";
4397                         };
4398
4399                         qup_uart1_rts: qup-uart1-rts {
4400                                 pins = "gpio5";
4401                                 function = "qup01";
4402                         };
4403
4404                         qup_uart1_tx: qup-uart1-tx {
4405                                 pins = "gpio6";
4406                                 function = "qup01";
4407                         };
4408
4409                         qup_uart1_rx: qup-uart1-rx {
4410                                 pins = "gpio7";
4411                                 function = "qup01";
4412                         };
4413
4414                         qup_uart2_cts: qup-uart2-cts {
4415                                 pins = "gpio8";
4416                                 function = "qup02";
4417                         };
4418
4419                         qup_uart2_rts: qup-uart2-rts {
4420                                 pins = "gpio9";
4421                                 function = "qup02";
4422                         };
4423
4424                         qup_uart2_tx: qup-uart2-tx {
4425                                 pins = "gpio10";
4426                                 function = "qup02";
4427                         };
4428
4429                         qup_uart2_rx: qup-uart2-rx {
4430                                 pins = "gpio11";
4431                                 function = "qup02";
4432                         };
4433
4434                         qup_uart3_cts: qup-uart3-cts {
4435                                 pins = "gpio12";
4436                                 function = "qup03";
4437                         };
4438
4439                         qup_uart3_rts: qup-uart3-rts {
4440                                 pins = "gpio13";
4441                                 function = "qup03";
4442                         };
4443
4444                         qup_uart3_tx: qup-uart3-tx {
4445                                 pins = "gpio14";
4446                                 function = "qup03";
4447                         };
4448
4449                         qup_uart3_rx: qup-uart3-rx {
4450                                 pins = "gpio15";
4451                                 function = "qup03";
4452                         };
4453
4454                         qup_uart4_cts: qup-uart4-cts {
4455                                 pins = "gpio16";
4456                                 function = "qup04";
4457                         };
4458
4459                         qup_uart4_rts: qup-uart4-rts {
4460                                 pins = "gpio17";
4461                                 function = "qup04";
4462                         };
4463
4464                         qup_uart4_tx: qup-uart4-tx {
4465                                 pins = "gpio18";
4466                                 function = "qup04";
4467                         };
4468
4469                         qup_uart4_rx: qup-uart4-rx {
4470                                 pins = "gpio19";
4471                                 function = "qup04";
4472                         };
4473
4474                         qup_uart5_cts: qup-uart5-cts {
4475                                 pins = "gpio20";
4476                                 function = "qup05";
4477                         };
4478
4479                         qup_uart5_rts: qup-uart5-rts {
4480                                 pins = "gpio21";
4481                                 function = "qup05";
4482                         };
4483
4484                         qup_uart5_tx: qup-uart5-tx {
4485                                 pins = "gpio22";
4486                                 function = "qup05";
4487                         };
4488
4489                         qup_uart5_rx: qup-uart5-rx {
4490                                 pins = "gpio23";
4491                                 function = "qup05";
4492                         };
4493
4494                         qup_uart6_cts: qup-uart6-cts {
4495                                 pins = "gpio24";
4496                                 function = "qup06";
4497                         };
4498
4499                         qup_uart6_rts: qup-uart6-rts {
4500                                 pins = "gpio25";
4501                                 function = "qup06";
4502                         };
4503
4504                         qup_uart6_tx: qup-uart6-tx {
4505                                 pins = "gpio26";
4506                                 function = "qup06";
4507                         };
4508
4509                         qup_uart6_rx: qup-uart6-rx {
4510                                 pins = "gpio27";
4511                                 function = "qup06";
4512                         };
4513
4514                         qup_uart7_cts: qup-uart7-cts {
4515                                 pins = "gpio28";
4516                                 function = "qup07";
4517                         };
4518
4519                         qup_uart7_rts: qup-uart7-rts {
4520                                 pins = "gpio29";
4521                                 function = "qup07";
4522                         };
4523
4524                         qup_uart7_tx: qup-uart7-tx {
4525                                 pins = "gpio30";
4526                                 function = "qup07";
4527                         };
4528
4529                         qup_uart7_rx: qup-uart7-rx {
4530                                 pins = "gpio31";
4531                                 function = "qup07";
4532                         };
4533
4534                         qup_uart8_cts: qup-uart8-cts {
4535                                 pins = "gpio32";
4536                                 function = "qup10";
4537                         };
4538
4539                         qup_uart8_rts: qup-uart8-rts {
4540                                 pins = "gpio33";
4541                                 function = "qup10";
4542                         };
4543
4544                         qup_uart8_tx: qup-uart8-tx {
4545                                 pins = "gpio34";
4546                                 function = "qup10";
4547                         };
4548
4549                         qup_uart8_rx: qup-uart8-rx {
4550                                 pins = "gpio35";
4551                                 function = "qup10";
4552                         };
4553
4554                         qup_uart9_cts: qup-uart9-cts {
4555                                 pins = "gpio36";
4556                                 function = "qup11";
4557                         };
4558
4559                         qup_uart9_rts: qup-uart9-rts {
4560                                 pins = "gpio37";
4561                                 function = "qup11";
4562                         };
4563
4564                         qup_uart9_tx: qup-uart9-tx {
4565                                 pins = "gpio38";
4566                                 function = "qup11";
4567                         };
4568
4569                         qup_uart9_rx: qup-uart9-rx {
4570                                 pins = "gpio39";
4571                                 function = "qup11";
4572                         };
4573
4574                         qup_uart10_cts: qup-uart10-cts {
4575                                 pins = "gpio40";
4576                                 function = "qup12";
4577                         };
4578
4579                         qup_uart10_rts: qup-uart10-rts {
4580                                 pins = "gpio41";
4581                                 function = "qup12";
4582                         };
4583
4584                         qup_uart10_tx: qup-uart10-tx {
4585                                 pins = "gpio42";
4586                                 function = "qup12";
4587                         };
4588
4589                         qup_uart10_rx: qup-uart10-rx {
4590                                 pins = "gpio43";
4591                                 function = "qup12";
4592                         };
4593
4594                         qup_uart11_cts: qup-uart11-cts {
4595                                 pins = "gpio44";
4596                                 function = "qup13";
4597                         };
4598
4599                         qup_uart11_rts: qup-uart11-rts {
4600                                 pins = "gpio45";
4601                                 function = "qup13";
4602                         };
4603
4604                         qup_uart11_tx: qup-uart11-tx {
4605                                 pins = "gpio46";
4606                                 function = "qup13";
4607                         };
4608
4609                         qup_uart11_rx: qup-uart11-rx {
4610                                 pins = "gpio47";
4611                                 function = "qup13";
4612                         };
4613
4614                         qup_uart12_cts: qup-uart12-cts {
4615                                 pins = "gpio48";
4616                                 function = "qup14";
4617                         };
4618
4619                         qup_uart12_rts: qup-uart12-rts {
4620                                 pins = "gpio49";
4621                                 function = "qup14";
4622                         };
4623
4624                         qup_uart12_tx: qup-uart12-tx {
4625                                 pins = "gpio50";
4626                                 function = "qup14";
4627                         };
4628
4629                         qup_uart12_rx: qup-uart12-rx {
4630                                 pins = "gpio51";
4631                                 function = "qup14";
4632                         };
4633
4634                         qup_uart13_cts: qup-uart13-cts {
4635                                 pins = "gpio52";
4636                                 function = "qup15";
4637                         };
4638
4639                         qup_uart13_rts: qup-uart13-rts {
4640                                 pins = "gpio53";
4641                                 function = "qup15";
4642                         };
4643
4644                         qup_uart13_tx: qup-uart13-tx {
4645                                 pins = "gpio54";
4646                                 function = "qup15";
4647                         };
4648
4649                         qup_uart13_rx: qup-uart13-rx {
4650                                 pins = "gpio55";
4651                                 function = "qup15";
4652                         };
4653
4654                         qup_uart14_cts: qup-uart14-cts {
4655                                 pins = "gpio56";
4656                                 function = "qup16";
4657                         };
4658
4659                         qup_uart14_rts: qup-uart14-rts {
4660                                 pins = "gpio57";
4661                                 function = "qup16";
4662                         };
4663
4664                         qup_uart14_tx: qup-uart14-tx {
4665                                 pins = "gpio58";
4666                                 function = "qup16";
4667                         };
4668
4669                         qup_uart14_rx: qup-uart14-rx {
4670                                 pins = "gpio59";
4671                                 function = "qup16";
4672                         };
4673
4674                         qup_uart15_cts: qup-uart15-cts {
4675                                 pins = "gpio60";
4676                                 function = "qup17";
4677                         };
4678
4679                         qup_uart15_rts: qup-uart15-rts {
4680                                 pins = "gpio61";
4681                                 function = "qup17";
4682                         };
4683
4684                         qup_uart15_tx: qup-uart15-tx {
4685                                 pins = "gpio62";
4686                                 function = "qup17";
4687                         };
4688
4689                         qup_uart15_rx: qup-uart15-rx {
4690                                 pins = "gpio63";
4691                                 function = "qup17";
4692                         };
4693
4694                         sdc1_clk: sdc1-clk {
4695                                 pins = "sdc1_clk";
4696                         };
4697
4698                         sdc1_cmd: sdc1-cmd {
4699                                 pins = "sdc1_cmd";
4700                         };
4701
4702                         sdc1_data: sdc1-data {
4703                                 pins = "sdc1_data";
4704                         };
4705
4706                         sdc1_rclk: sdc1-rclk {
4707                                 pins = "sdc1_rclk";
4708                         };
4709
4710                         sdc1_clk_sleep: sdc1-clk-sleep {
4711                                 pins = "sdc1_clk";
4712                                 drive-strength = <2>;
4713                                 bias-bus-hold;
4714                         };
4715
4716                         sdc1_cmd_sleep: sdc1-cmd-sleep {
4717                                 pins = "sdc1_cmd";
4718                                 drive-strength = <2>;
4719                                 bias-bus-hold;
4720                         };
4721
4722                         sdc1_data_sleep: sdc1-data-sleep {
4723                                 pins = "sdc1_data";
4724                                 drive-strength = <2>;
4725                                 bias-bus-hold;
4726                         };
4727
4728                         sdc1_rclk_sleep: sdc1-rclk-sleep {
4729                                 pins = "sdc1_rclk";
4730                                 drive-strength = <2>;
4731                                 bias-bus-hold;
4732                         };
4733
4734                         sdc2_clk: sdc2-clk {
4735                                 pins = "sdc2_clk";
4736                         };
4737
4738                         sdc2_cmd: sdc2-cmd {
4739                                 pins = "sdc2_cmd";
4740                         };
4741
4742                         sdc2_data: sdc2-data {
4743                                 pins = "sdc2_data";
4744                         };
4745
4746                         sdc2_clk_sleep: sdc2-clk-sleep {
4747                                 pins = "sdc2_clk";
4748                                 drive-strength = <2>;
4749                                 bias-bus-hold;
4750                         };
4751
4752                         sdc2_cmd_sleep: sdc2-cmd-sleep {
4753                                 pins = "sdc2_cmd";
4754                                 drive-strength = <2>;
4755                                 bias-bus-hold;
4756                         };
4757
4758                         sdc2_data_sleep: sdc2-data-sleep {
4759                                 pins = "sdc2_data";
4760                                 drive-strength = <2>;
4761                                 bias-bus-hold;
4762                         };
4763                 };
4764
4765                 sram@146a5000 {
4766                         compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
4767                         reg = <0 0x146a5000 0 0x6000>;
4768
4769                         #address-cells = <1>;
4770                         #size-cells = <1>;
4771
4772                         ranges = <0 0 0x146a5000 0x6000>;
4773
4774                         pil-reloc@594c {
4775                                 compatible = "qcom,pil-reloc-info";
4776                                 reg = <0x594c 0xc8>;
4777                         };
4778                 };
4779
4780                 apps_smmu: iommu@15000000 {
4781                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
4782                         reg = <0 0x15000000 0 0x100000>;
4783                         #iommu-cells = <2>;
4784                         #global-interrupts = <1>;
4785                         dma-coherent;
4786                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4787                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
4788                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
4789                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
4790                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
4791                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
4792                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
4793                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
4794                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4795                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4796                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4797                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4798                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4799                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4800                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4801                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4802                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4803                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4804                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4805                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4806                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4807                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4808                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4809                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4810                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4811                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4812                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4813                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4814                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4815                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4816                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4817                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4818                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4819                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4820                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4821                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4822                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4823                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4824                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4825                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4826                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4827                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4828                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4829                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4830                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4831                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4832                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4833                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4834                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4835                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4836                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4837                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4838                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4839                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4840                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4841                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4842                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4843                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4844                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4845                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4846                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4847                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4848                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4849                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4850                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4851                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4852                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4853                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4854                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4855                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4856                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4857                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4858                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4859                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4860                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4861                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4862                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4863                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4864                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4865                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4866                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
4867                 };
4868
4869                 intc: interrupt-controller@17a00000 {
4870                         compatible = "arm,gic-v3";
4871                         #address-cells = <2>;
4872                         #size-cells = <2>;
4873                         ranges;
4874                         #interrupt-cells = <3>;
4875                         interrupt-controller;
4876                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
4877                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
4878                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
4879
4880                         gic-its@17a40000 {
4881                                 compatible = "arm,gic-v3-its";
4882                                 msi-controller;
4883                                 #msi-cells = <1>;
4884                                 reg = <0 0x17a40000 0 0x20000>;
4885                                 status = "disabled";
4886                         };
4887                 };
4888
4889                 watchdog@17c10000 {
4890                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
4891                         reg = <0 0x17c10000 0 0x1000>;
4892                         clocks = <&sleep_clk>;
4893                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
4894                 };
4895
4896                 timer@17c20000 {
4897                         #address-cells = <1>;
4898                         #size-cells = <1>;
4899                         ranges = <0 0 0 0x20000000>;
4900                         compatible = "arm,armv7-timer-mem";
4901                         reg = <0 0x17c20000 0 0x1000>;
4902
4903                         frame@17c21000 {
4904                                 frame-number = <0>;
4905                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4906                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4907                                 reg = <0x17c21000 0x1000>,
4908                                       <0x17c22000 0x1000>;
4909                         };
4910
4911                         frame@17c23000 {
4912                                 frame-number = <1>;
4913                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4914                                 reg = <0x17c23000 0x1000>;
4915                                 status = "disabled";
4916                         };
4917
4918                         frame@17c25000 {
4919                                 frame-number = <2>;
4920                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4921                                 reg = <0x17c25000 0x1000>;
4922                                 status = "disabled";
4923                         };
4924
4925                         frame@17c27000 {
4926                                 frame-number = <3>;
4927                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4928                                 reg = <0x17c27000 0x1000>;
4929                                 status = "disabled";
4930                         };
4931
4932                         frame@17c29000 {
4933                                 frame-number = <4>;
4934                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4935                                 reg = <0x17c29000 0x1000>;
4936                                 status = "disabled";
4937                         };
4938
4939                         frame@17c2b000 {
4940                                 frame-number = <5>;
4941                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4942                                 reg = <0x17c2b000 0x1000>;
4943                                 status = "disabled";
4944                         };
4945
4946                         frame@17c2d000 {
4947                                 frame-number = <6>;
4948                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4949                                 reg = <0x17c2d000 0x1000>;
4950                                 status = "disabled";
4951                         };
4952                 };
4953
4954                 apps_rsc: rsc@18200000 {
4955                         compatible = "qcom,rpmh-rsc";
4956                         reg = <0 0x18200000 0 0x10000>,
4957                               <0 0x18210000 0 0x10000>,
4958                               <0 0x18220000 0 0x10000>;
4959                         reg-names = "drv-0", "drv-1", "drv-2";
4960                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4961                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4962                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4963                         qcom,tcs-offset = <0xd00>;
4964                         qcom,drv-id = <2>;
4965                         qcom,tcs-config = <ACTIVE_TCS  2>,
4966                                           <SLEEP_TCS   3>,
4967                                           <WAKE_TCS    3>,
4968                                           <CONTROL_TCS 1>;
4969
4970                         apps_bcm_voter: bcm-voter {
4971                                 compatible = "qcom,bcm-voter";
4972                         };
4973
4974                         rpmhpd: power-controller {
4975                                 compatible = "qcom,sc7280-rpmhpd";
4976                                 #power-domain-cells = <1>;
4977                                 operating-points-v2 = <&rpmhpd_opp_table>;
4978
4979                                 rpmhpd_opp_table: opp-table {
4980                                         compatible = "operating-points-v2";
4981
4982                                         rpmhpd_opp_ret: opp1 {
4983                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4984                                         };
4985
4986                                         rpmhpd_opp_low_svs: opp2 {
4987                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4988                                         };
4989
4990                                         rpmhpd_opp_svs: opp3 {
4991                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4992                                         };
4993
4994                                         rpmhpd_opp_svs_l1: opp4 {
4995                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4996                                         };
4997
4998                                         rpmhpd_opp_svs_l2: opp5 {
4999                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5000                                         };
5001
5002                                         rpmhpd_opp_nom: opp6 {
5003                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5004                                         };
5005
5006                                         rpmhpd_opp_nom_l1: opp7 {
5007                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5008                                         };
5009
5010                                         rpmhpd_opp_turbo: opp8 {
5011                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5012                                         };
5013
5014                                         rpmhpd_opp_turbo_l1: opp9 {
5015                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5016                                         };
5017                                 };
5018                         };
5019
5020                         rpmhcc: clock-controller {
5021                                 compatible = "qcom,sc7280-rpmh-clk";
5022                                 clocks = <&xo_board>;
5023                                 clock-names = "xo";
5024                                 #clock-cells = <1>;
5025                         };
5026                 };
5027
5028                 epss_l3: interconnect@18590000 {
5029                         compatible = "qcom,sc7280-epss-l3";
5030                         reg = <0 0x18590000 0 0x1000>;
5031                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5032                         clock-names = "xo", "alternate";
5033                         #interconnect-cells = <1>;
5034                 };
5035
5036                 cpufreq_hw: cpufreq@18591000 {
5037                         compatible = "qcom,cpufreq-epss";
5038                         reg = <0 0x18591000 0 0x1000>,
5039                               <0 0x18592000 0 0x1000>,
5040                               <0 0x18593000 0 0x1000>;
5041                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
5042                         clock-names = "xo", "alternate";
5043                         #freq-domain-cells = <1>;
5044                 };
5045         };
5046
5047         thermal_zones: thermal-zones {
5048                 cpu0-thermal {
5049                         polling-delay-passive = <250>;
5050                         polling-delay = <0>;
5051
5052                         thermal-sensors = <&tsens0 1>;
5053
5054                         trips {
5055                                 cpu0_alert0: trip-point0 {
5056                                         temperature = <90000>;
5057                                         hysteresis = <2000>;
5058                                         type = "passive";
5059                                 };
5060
5061                                 cpu0_alert1: trip-point1 {
5062                                         temperature = <95000>;
5063                                         hysteresis = <2000>;
5064                                         type = "passive";
5065                                 };
5066
5067                                 cpu0_crit: cpu-crit {
5068                                         temperature = <110000>;
5069                                         hysteresis = <0>;
5070                                         type = "critical";
5071                                 };
5072                         };
5073
5074                         cooling-maps {
5075                                 map0 {
5076                                         trip = <&cpu0_alert0>;
5077                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5078                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5079                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5080                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5081                                 };
5082                                 map1 {
5083                                         trip = <&cpu0_alert1>;
5084                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5085                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5086                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5087                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5088                                 };
5089                         };
5090                 };
5091
5092                 cpu1-thermal {
5093                         polling-delay-passive = <250>;
5094                         polling-delay = <0>;
5095
5096                         thermal-sensors = <&tsens0 2>;
5097
5098                         trips {
5099                                 cpu1_alert0: trip-point0 {
5100                                         temperature = <90000>;
5101                                         hysteresis = <2000>;
5102                                         type = "passive";
5103                                 };
5104
5105                                 cpu1_alert1: trip-point1 {
5106                                         temperature = <95000>;
5107                                         hysteresis = <2000>;
5108                                         type = "passive";
5109                                 };
5110
5111                                 cpu1_crit: cpu-crit {
5112                                         temperature = <110000>;
5113                                         hysteresis = <0>;
5114                                         type = "critical";
5115                                 };
5116                         };
5117
5118                         cooling-maps {
5119                                 map0 {
5120                                         trip = <&cpu1_alert0>;
5121                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5122                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5123                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5124                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5125                                 };
5126                                 map1 {
5127                                         trip = <&cpu1_alert1>;
5128                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5129                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5130                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5131                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5132                                 };
5133                         };
5134                 };
5135
5136                 cpu2-thermal {
5137                         polling-delay-passive = <250>;
5138                         polling-delay = <0>;
5139
5140                         thermal-sensors = <&tsens0 3>;
5141
5142                         trips {
5143                                 cpu2_alert0: trip-point0 {
5144                                         temperature = <90000>;
5145                                         hysteresis = <2000>;
5146                                         type = "passive";
5147                                 };
5148
5149                                 cpu2_alert1: trip-point1 {
5150                                         temperature = <95000>;
5151                                         hysteresis = <2000>;
5152                                         type = "passive";
5153                                 };
5154
5155                                 cpu2_crit: cpu-crit {
5156                                         temperature = <110000>;
5157                                         hysteresis = <0>;
5158                                         type = "critical";
5159                                 };
5160                         };
5161
5162                         cooling-maps {
5163                                 map0 {
5164                                         trip = <&cpu2_alert0>;
5165                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5166                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5167                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5168                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5169                                 };
5170                                 map1 {
5171                                         trip = <&cpu2_alert1>;
5172                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5173                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5174                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5175                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5176                                 };
5177                         };
5178                 };
5179
5180                 cpu3-thermal {
5181                         polling-delay-passive = <250>;
5182                         polling-delay = <0>;
5183
5184                         thermal-sensors = <&tsens0 4>;
5185
5186                         trips {
5187                                 cpu3_alert0: trip-point0 {
5188                                         temperature = <90000>;
5189                                         hysteresis = <2000>;
5190                                         type = "passive";
5191                                 };
5192
5193                                 cpu3_alert1: trip-point1 {
5194                                         temperature = <95000>;
5195                                         hysteresis = <2000>;
5196                                         type = "passive";
5197                                 };
5198
5199                                 cpu3_crit: cpu-crit {
5200                                         temperature = <110000>;
5201                                         hysteresis = <0>;
5202                                         type = "critical";
5203                                 };
5204                         };
5205
5206                         cooling-maps {
5207                                 map0 {
5208                                         trip = <&cpu3_alert0>;
5209                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5210                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5211                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5212                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5213                                 };
5214                                 map1 {
5215                                         trip = <&cpu3_alert1>;
5216                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5217                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5218                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5219                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5220                                 };
5221                         };
5222                 };
5223
5224                 cpu4-thermal {
5225                         polling-delay-passive = <250>;
5226                         polling-delay = <0>;
5227
5228                         thermal-sensors = <&tsens0 7>;
5229
5230                         trips {
5231                                 cpu4_alert0: trip-point0 {
5232                                         temperature = <90000>;
5233                                         hysteresis = <2000>;
5234                                         type = "passive";
5235                                 };
5236
5237                                 cpu4_alert1: trip-point1 {
5238                                         temperature = <95000>;
5239                                         hysteresis = <2000>;
5240                                         type = "passive";
5241                                 };
5242
5243                                 cpu4_crit: cpu-crit {
5244                                         temperature = <110000>;
5245                                         hysteresis = <0>;
5246                                         type = "critical";
5247                                 };
5248                         };
5249
5250                         cooling-maps {
5251                                 map0 {
5252                                         trip = <&cpu4_alert0>;
5253                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5254                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5255                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5256                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5257                                 };
5258                                 map1 {
5259                                         trip = <&cpu4_alert1>;
5260                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5261                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5262                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5263                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5264                                 };
5265                         };
5266                 };
5267
5268                 cpu5-thermal {
5269                         polling-delay-passive = <250>;
5270                         polling-delay = <0>;
5271
5272                         thermal-sensors = <&tsens0 8>;
5273
5274                         trips {
5275                                 cpu5_alert0: trip-point0 {
5276                                         temperature = <90000>;
5277                                         hysteresis = <2000>;
5278                                         type = "passive";
5279                                 };
5280
5281                                 cpu5_alert1: trip-point1 {
5282                                         temperature = <95000>;
5283                                         hysteresis = <2000>;
5284                                         type = "passive";
5285                                 };
5286
5287                                 cpu5_crit: cpu-crit {
5288                                         temperature = <110000>;
5289                                         hysteresis = <0>;
5290                                         type = "critical";
5291                                 };
5292                         };
5293
5294                         cooling-maps {
5295                                 map0 {
5296                                         trip = <&cpu5_alert0>;
5297                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5298                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5299                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5300                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5301                                 };
5302                                 map1 {
5303                                         trip = <&cpu5_alert1>;
5304                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5305                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5306                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5307                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5308                                 };
5309                         };
5310                 };
5311
5312                 cpu6-thermal {
5313                         polling-delay-passive = <250>;
5314                         polling-delay = <0>;
5315
5316                         thermal-sensors = <&tsens0 9>;
5317
5318                         trips {
5319                                 cpu6_alert0: trip-point0 {
5320                                         temperature = <90000>;
5321                                         hysteresis = <2000>;
5322                                         type = "passive";
5323                                 };
5324
5325                                 cpu6_alert1: trip-point1 {
5326                                         temperature = <95000>;
5327                                         hysteresis = <2000>;
5328                                         type = "passive";
5329                                 };
5330
5331                                 cpu6_crit: cpu-crit {
5332                                         temperature = <110000>;
5333                                         hysteresis = <0>;
5334                                         type = "critical";
5335                                 };
5336                         };
5337
5338                         cooling-maps {
5339                                 map0 {
5340                                         trip = <&cpu6_alert0>;
5341                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5342                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5343                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5344                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5345                                 };
5346                                 map1 {
5347                                         trip = <&cpu6_alert1>;
5348                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5349                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5350                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5351                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5352                                 };
5353                         };
5354                 };
5355
5356                 cpu7-thermal {
5357                         polling-delay-passive = <250>;
5358                         polling-delay = <0>;
5359
5360                         thermal-sensors = <&tsens0 10>;
5361
5362                         trips {
5363                                 cpu7_alert0: trip-point0 {
5364                                         temperature = <90000>;
5365                                         hysteresis = <2000>;
5366                                         type = "passive";
5367                                 };
5368
5369                                 cpu7_alert1: trip-point1 {
5370                                         temperature = <95000>;
5371                                         hysteresis = <2000>;
5372                                         type = "passive";
5373                                 };
5374
5375                                 cpu7_crit: cpu-crit {
5376                                         temperature = <110000>;
5377                                         hysteresis = <0>;
5378                                         type = "critical";
5379                                 };
5380                         };
5381
5382                         cooling-maps {
5383                                 map0 {
5384                                         trip = <&cpu7_alert0>;
5385                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5386                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5387                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5388                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5389                                 };
5390                                 map1 {
5391                                         trip = <&cpu7_alert1>;
5392                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5393                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5394                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5395                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5396                                 };
5397                         };
5398                 };
5399
5400                 cpu8-thermal {
5401                         polling-delay-passive = <250>;
5402                         polling-delay = <0>;
5403
5404                         thermal-sensors = <&tsens0 11>;
5405
5406                         trips {
5407                                 cpu8_alert0: trip-point0 {
5408                                         temperature = <90000>;
5409                                         hysteresis = <2000>;
5410                                         type = "passive";
5411                                 };
5412
5413                                 cpu8_alert1: trip-point1 {
5414                                         temperature = <95000>;
5415                                         hysteresis = <2000>;
5416                                         type = "passive";
5417                                 };
5418
5419                                 cpu8_crit: cpu-crit {
5420                                         temperature = <110000>;
5421                                         hysteresis = <0>;
5422                                         type = "critical";
5423                                 };
5424                         };
5425
5426                         cooling-maps {
5427                                 map0 {
5428                                         trip = <&cpu8_alert0>;
5429                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5430                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5431                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5432                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5433                                 };
5434                                 map1 {
5435                                         trip = <&cpu8_alert1>;
5436                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5437                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5438                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5439                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5440                                 };
5441                         };
5442                 };
5443
5444                 cpu9-thermal {
5445                         polling-delay-passive = <250>;
5446                         polling-delay = <0>;
5447
5448                         thermal-sensors = <&tsens0 12>;
5449
5450                         trips {
5451                                 cpu9_alert0: trip-point0 {
5452                                         temperature = <90000>;
5453                                         hysteresis = <2000>;
5454                                         type = "passive";
5455                                 };
5456
5457                                 cpu9_alert1: trip-point1 {
5458                                         temperature = <95000>;
5459                                         hysteresis = <2000>;
5460                                         type = "passive";
5461                                 };
5462
5463                                 cpu9_crit: cpu-crit {
5464                                         temperature = <110000>;
5465                                         hysteresis = <0>;
5466                                         type = "critical";
5467                                 };
5468                         };
5469
5470                         cooling-maps {
5471                                 map0 {
5472                                         trip = <&cpu9_alert0>;
5473                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5474                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5475                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5476                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5477                                 };
5478                                 map1 {
5479                                         trip = <&cpu9_alert1>;
5480                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5481                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5482                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5483                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5484                                 };
5485                         };
5486                 };
5487
5488                 cpu10-thermal {
5489                         polling-delay-passive = <250>;
5490                         polling-delay = <0>;
5491
5492                         thermal-sensors = <&tsens0 13>;
5493
5494                         trips {
5495                                 cpu10_alert0: trip-point0 {
5496                                         temperature = <90000>;
5497                                         hysteresis = <2000>;
5498                                         type = "passive";
5499                                 };
5500
5501                                 cpu10_alert1: trip-point1 {
5502                                         temperature = <95000>;
5503                                         hysteresis = <2000>;
5504                                         type = "passive";
5505                                 };
5506
5507                                 cpu10_crit: cpu-crit {
5508                                         temperature = <110000>;
5509                                         hysteresis = <0>;
5510                                         type = "critical";
5511                                 };
5512                         };
5513
5514                         cooling-maps {
5515                                 map0 {
5516                                         trip = <&cpu10_alert0>;
5517                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5518                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5519                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5520                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5521                                 };
5522                                 map1 {
5523                                         trip = <&cpu10_alert1>;
5524                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5525                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5526                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5527                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5528                                 };
5529                         };
5530                 };
5531
5532                 cpu11-thermal {
5533                         polling-delay-passive = <250>;
5534                         polling-delay = <0>;
5535
5536                         thermal-sensors = <&tsens0 14>;
5537
5538                         trips {
5539                                 cpu11_alert0: trip-point0 {
5540                                         temperature = <90000>;
5541                                         hysteresis = <2000>;
5542                                         type = "passive";
5543                                 };
5544
5545                                 cpu11_alert1: trip-point1 {
5546                                         temperature = <95000>;
5547                                         hysteresis = <2000>;
5548                                         type = "passive";
5549                                 };
5550
5551                                 cpu11_crit: cpu-crit {
5552                                         temperature = <110000>;
5553                                         hysteresis = <0>;
5554                                         type = "critical";
5555                                 };
5556                         };
5557
5558                         cooling-maps {
5559                                 map0 {
5560                                         trip = <&cpu11_alert0>;
5561                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5562                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5563                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5564                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5565                                 };
5566                                 map1 {
5567                                         trip = <&cpu11_alert1>;
5568                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5569                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5570                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5571                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5572                                 };
5573                         };
5574                 };
5575
5576                 aoss0-thermal {
5577                         polling-delay-passive = <0>;
5578                         polling-delay = <0>;
5579
5580                         thermal-sensors = <&tsens0 0>;
5581
5582                         trips {
5583                                 aoss0_alert0: trip-point0 {
5584                                         temperature = <90000>;
5585                                         hysteresis = <2000>;
5586                                         type = "hot";
5587                                 };
5588
5589                                 aoss0_crit: aoss0-crit {
5590                                         temperature = <110000>;
5591                                         hysteresis = <0>;
5592                                         type = "critical";
5593                                 };
5594                         };
5595                 };
5596
5597                 aoss1-thermal {
5598                         polling-delay-passive = <0>;
5599                         polling-delay = <0>;
5600
5601                         thermal-sensors = <&tsens1 0>;
5602
5603                         trips {
5604                                 aoss1_alert0: trip-point0 {
5605                                         temperature = <90000>;
5606                                         hysteresis = <2000>;
5607                                         type = "hot";
5608                                 };
5609
5610                                 aoss1_crit: aoss1-crit {
5611                                         temperature = <110000>;
5612                                         hysteresis = <0>;
5613                                         type = "critical";
5614                                 };
5615                         };
5616                 };
5617
5618                 cpuss0-thermal {
5619                         polling-delay-passive = <0>;
5620                         polling-delay = <0>;
5621
5622                         thermal-sensors = <&tsens0 5>;
5623
5624                         trips {
5625                                 cpuss0_alert0: trip-point0 {
5626                                         temperature = <90000>;
5627                                         hysteresis = <2000>;
5628                                         type = "hot";
5629                                 };
5630                                 cpuss0_crit: cluster0-crit {
5631                                         temperature = <110000>;
5632                                         hysteresis = <0>;
5633                                         type = "critical";
5634                                 };
5635                         };
5636                 };
5637
5638                 cpuss1-thermal {
5639                         polling-delay-passive = <0>;
5640                         polling-delay = <0>;
5641
5642                         thermal-sensors = <&tsens0 6>;
5643
5644                         trips {
5645                                 cpuss1_alert0: trip-point0 {
5646                                         temperature = <90000>;
5647                                         hysteresis = <2000>;
5648                                         type = "hot";
5649                                 };
5650                                 cpuss1_crit: cluster0-crit {
5651                                         temperature = <110000>;
5652                                         hysteresis = <0>;
5653                                         type = "critical";
5654                                 };
5655                         };
5656                 };
5657
5658                 gpuss0-thermal {
5659                         polling-delay-passive = <100>;
5660                         polling-delay = <0>;
5661
5662                         thermal-sensors = <&tsens1 1>;
5663
5664                         trips {
5665                                 gpuss0_alert0: trip-point0 {
5666                                         temperature = <95000>;
5667                                         hysteresis = <2000>;
5668                                         type = "passive";
5669                                 };
5670
5671                                 gpuss0_crit: gpuss0-crit {
5672                                         temperature = <110000>;
5673                                         hysteresis = <0>;
5674                                         type = "critical";
5675                                 };
5676                         };
5677
5678                         cooling-maps {
5679                                 map0 {
5680                                         trip = <&gpuss0_alert0>;
5681                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5682                                 };
5683                         };
5684                 };
5685
5686                 gpuss1-thermal {
5687                         polling-delay-passive = <100>;
5688                         polling-delay = <0>;
5689
5690                         thermal-sensors = <&tsens1 2>;
5691
5692                         trips {
5693                                 gpuss1_alert0: trip-point0 {
5694                                         temperature = <95000>;
5695                                         hysteresis = <2000>;
5696                                         type = "passive";
5697                                 };
5698
5699                                 gpuss1_crit: gpuss1-crit {
5700                                         temperature = <110000>;
5701                                         hysteresis = <0>;
5702                                         type = "critical";
5703                                 };
5704                         };
5705
5706                         cooling-maps {
5707                                 map0 {
5708                                         trip = <&gpuss1_alert0>;
5709                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
5710                                 };
5711                         };
5712                 };
5713
5714                 nspss0-thermal {
5715                         polling-delay-passive = <0>;
5716                         polling-delay = <0>;
5717
5718                         thermal-sensors = <&tsens1 3>;
5719
5720                         trips {
5721                                 nspss0_alert0: trip-point0 {
5722                                         temperature = <90000>;
5723                                         hysteresis = <2000>;
5724                                         type = "hot";
5725                                 };
5726
5727                                 nspss0_crit: nspss0-crit {
5728                                         temperature = <110000>;
5729                                         hysteresis = <0>;
5730                                         type = "critical";
5731                                 };
5732                         };
5733                 };
5734
5735                 nspss1-thermal {
5736                         polling-delay-passive = <0>;
5737                         polling-delay = <0>;
5738
5739                         thermal-sensors = <&tsens1 4>;
5740
5741                         trips {
5742                                 nspss1_alert0: trip-point0 {
5743                                         temperature = <90000>;
5744                                         hysteresis = <2000>;
5745                                         type = "hot";
5746                                 };
5747
5748                                 nspss1_crit: nspss1-crit {
5749                                         temperature = <110000>;
5750                                         hysteresis = <0>;
5751                                         type = "critical";
5752                                 };
5753                         };
5754                 };
5755
5756                 video-thermal {
5757                         polling-delay-passive = <0>;
5758                         polling-delay = <0>;
5759
5760                         thermal-sensors = <&tsens1 5>;
5761
5762                         trips {
5763                                 video_alert0: trip-point0 {
5764                                         temperature = <90000>;
5765                                         hysteresis = <2000>;
5766                                         type = "hot";
5767                                 };
5768
5769                                 video_crit: video-crit {
5770                                         temperature = <110000>;
5771                                         hysteresis = <0>;
5772                                         type = "critical";
5773                                 };
5774                         };
5775                 };
5776
5777                 ddr-thermal {
5778                         polling-delay-passive = <0>;
5779                         polling-delay = <0>;
5780
5781                         thermal-sensors = <&tsens1 6>;
5782
5783                         trips {
5784                                 ddr_alert0: trip-point0 {
5785                                         temperature = <90000>;
5786                                         hysteresis = <2000>;
5787                                         type = "hot";
5788                                 };
5789
5790                                 ddr_crit: ddr-crit {
5791                                         temperature = <110000>;
5792                                         hysteresis = <0>;
5793                                         type = "critical";
5794                                 };
5795                         };
5796                 };
5797
5798                 mdmss0-thermal {
5799                         polling-delay-passive = <0>;
5800                         polling-delay = <0>;
5801
5802                         thermal-sensors = <&tsens1 7>;
5803
5804                         trips {
5805                                 mdmss0_alert0: trip-point0 {
5806                                         temperature = <90000>;
5807                                         hysteresis = <2000>;
5808                                         type = "hot";
5809                                 };
5810
5811                                 mdmss0_crit: mdmss0-crit {
5812                                         temperature = <110000>;
5813                                         hysteresis = <0>;
5814                                         type = "critical";
5815                                 };
5816                         };
5817                 };
5818
5819                 mdmss1-thermal {
5820                         polling-delay-passive = <0>;
5821                         polling-delay = <0>;
5822
5823                         thermal-sensors = <&tsens1 8>;
5824
5825                         trips {
5826                                 mdmss1_alert0: trip-point0 {
5827                                         temperature = <90000>;
5828                                         hysteresis = <2000>;
5829                                         type = "hot";
5830                                 };
5831
5832                                 mdmss1_crit: mdmss1-crit {
5833                                         temperature = <110000>;
5834                                         hysteresis = <0>;
5835                                         type = "critical";
5836                                 };
5837                         };
5838                 };
5839
5840                 mdmss2-thermal {
5841                         polling-delay-passive = <0>;
5842                         polling-delay = <0>;
5843
5844                         thermal-sensors = <&tsens1 9>;
5845
5846                         trips {
5847                                 mdmss2_alert0: trip-point0 {
5848                                         temperature = <90000>;
5849                                         hysteresis = <2000>;
5850                                         type = "hot";
5851                                 };
5852
5853                                 mdmss2_crit: mdmss2-crit {
5854                                         temperature = <110000>;
5855                                         hysteresis = <0>;
5856                                         type = "critical";
5857                                 };
5858                         };
5859                 };
5860
5861                 mdmss3-thermal {
5862                         polling-delay-passive = <0>;
5863                         polling-delay = <0>;
5864
5865                         thermal-sensors = <&tsens1 10>;
5866
5867                         trips {
5868                                 mdmss3_alert0: trip-point0 {
5869                                         temperature = <90000>;
5870                                         hysteresis = <2000>;
5871                                         type = "hot";
5872                                 };
5873
5874                                 mdmss3_crit: mdmss3-crit {
5875                                         temperature = <110000>;
5876                                         hysteresis = <0>;
5877                                         type = "critical";
5878                                 };
5879                         };
5880                 };
5881
5882                 camera0-thermal {
5883                         polling-delay-passive = <0>;
5884                         polling-delay = <0>;
5885
5886                         thermal-sensors = <&tsens1 11>;
5887
5888                         trips {
5889                                 camera0_alert0: trip-point0 {
5890                                         temperature = <90000>;
5891                                         hysteresis = <2000>;
5892                                         type = "hot";
5893                                 };
5894
5895                                 camera0_crit: camera0-crit {
5896                                         temperature = <110000>;
5897                                         hysteresis = <0>;
5898                                         type = "critical";
5899                                 };
5900                         };
5901                 };
5902         };
5903
5904         timer {
5905                 compatible = "arm,armv8-timer";
5906                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
5907                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
5908                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
5909                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
5910         };
5911 };