1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-rpmpd.h>
19 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
20 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/thermal/thermal.h>
25 interrupt-parent = <&intc>;
59 compatible = "fixed-clock";
60 clock-frequency = <38400000>;
64 sleep_clk: sleep-clk {
65 compatible = "fixed-clock";
66 clock-frequency = <32764>;
77 compatible = "qcom,kryo468";
79 clocks = <&cpufreq_hw 0>;
80 enable-method = "psci";
81 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
84 capacity-dmips-mhz = <415>;
85 dynamic-power-coefficient = <137>;
86 operating-points-v2 = <&cpu0_opp_table>;
87 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
88 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
89 next-level-cache = <&L2_0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
96 next-level-cache = <&L3_0>;
107 compatible = "qcom,kryo468";
109 clocks = <&cpufreq_hw 0>;
110 enable-method = "psci";
111 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
114 capacity-dmips-mhz = <415>;
115 dynamic-power-coefficient = <137>;
116 next-level-cache = <&L2_100>;
117 operating-points-v2 = <&cpu0_opp_table>;
118 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
120 #cooling-cells = <2>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
123 compatible = "cache";
126 next-level-cache = <&L3_0>;
132 compatible = "qcom,kryo468";
134 clocks = <&cpufreq_hw 0>;
135 enable-method = "psci";
136 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
139 capacity-dmips-mhz = <415>;
140 dynamic-power-coefficient = <137>;
141 next-level-cache = <&L2_200>;
142 operating-points-v2 = <&cpu0_opp_table>;
143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
145 #cooling-cells = <2>;
146 qcom,freq-domain = <&cpufreq_hw 0>;
148 compatible = "cache";
151 next-level-cache = <&L3_0>;
157 compatible = "qcom,kryo468";
159 clocks = <&cpufreq_hw 0>;
160 enable-method = "psci";
161 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
164 capacity-dmips-mhz = <415>;
165 dynamic-power-coefficient = <137>;
166 next-level-cache = <&L2_300>;
167 operating-points-v2 = <&cpu0_opp_table>;
168 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
170 #cooling-cells = <2>;
171 qcom,freq-domain = <&cpufreq_hw 0>;
173 compatible = "cache";
176 next-level-cache = <&L3_0>;
182 compatible = "qcom,kryo468";
184 clocks = <&cpufreq_hw 0>;
185 enable-method = "psci";
186 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
189 capacity-dmips-mhz = <415>;
190 dynamic-power-coefficient = <137>;
191 next-level-cache = <&L2_400>;
192 operating-points-v2 = <&cpu0_opp_table>;
193 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
195 #cooling-cells = <2>;
196 qcom,freq-domain = <&cpufreq_hw 0>;
198 compatible = "cache";
201 next-level-cache = <&L3_0>;
207 compatible = "qcom,kryo468";
209 clocks = <&cpufreq_hw 0>;
210 enable-method = "psci";
211 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
214 capacity-dmips-mhz = <415>;
215 dynamic-power-coefficient = <137>;
216 next-level-cache = <&L2_500>;
217 operating-points-v2 = <&cpu0_opp_table>;
218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
220 #cooling-cells = <2>;
221 qcom,freq-domain = <&cpufreq_hw 0>;
223 compatible = "cache";
226 next-level-cache = <&L3_0>;
232 compatible = "qcom,kryo468";
234 clocks = <&cpufreq_hw 1>;
235 enable-method = "psci";
236 cpu-idle-states = <&BIG_CPU_SLEEP_0
239 capacity-dmips-mhz = <1024>;
240 dynamic-power-coefficient = <480>;
241 next-level-cache = <&L2_600>;
242 operating-points-v2 = <&cpu6_opp_table>;
243 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
245 #cooling-cells = <2>;
246 qcom,freq-domain = <&cpufreq_hw 1>;
248 compatible = "cache";
251 next-level-cache = <&L3_0>;
257 compatible = "qcom,kryo468";
259 clocks = <&cpufreq_hw 1>;
260 enable-method = "psci";
261 cpu-idle-states = <&BIG_CPU_SLEEP_0
264 capacity-dmips-mhz = <1024>;
265 dynamic-power-coefficient = <480>;
266 next-level-cache = <&L2_700>;
267 operating-points-v2 = <&cpu6_opp_table>;
268 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
269 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
270 #cooling-cells = <2>;
271 qcom,freq-domain = <&cpufreq_hw 1>;
273 compatible = "cache";
276 next-level-cache = <&L3_0>;
317 entry-method = "psci";
319 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
320 compatible = "arm,idle-state";
321 idle-state-name = "little-power-down";
322 arm,psci-suspend-param = <0x40000003>;
323 entry-latency-us = <549>;
324 exit-latency-us = <901>;
325 min-residency-us = <1774>;
329 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
330 compatible = "arm,idle-state";
331 idle-state-name = "little-rail-power-down";
332 arm,psci-suspend-param = <0x40000004>;
333 entry-latency-us = <702>;
334 exit-latency-us = <915>;
335 min-residency-us = <4001>;
339 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
340 compatible = "arm,idle-state";
341 idle-state-name = "big-power-down";
342 arm,psci-suspend-param = <0x40000003>;
343 entry-latency-us = <523>;
344 exit-latency-us = <1244>;
345 min-residency-us = <2207>;
349 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
350 compatible = "arm,idle-state";
351 idle-state-name = "big-rail-power-down";
352 arm,psci-suspend-param = <0x40000004>;
353 entry-latency-us = <526>;
354 exit-latency-us = <1854>;
355 min-residency-us = <5555>;
359 CLUSTER_SLEEP_0: cluster-sleep-0 {
360 compatible = "arm,idle-state";
361 idle-state-name = "cluster-power-down";
362 arm,psci-suspend-param = <0x40003444>;
363 entry-latency-us = <3263>;
364 exit-latency-us = <6562>;
365 min-residency-us = <9926>;
373 compatible = "qcom,scm-sc7180", "qcom,scm";
378 device_type = "memory";
379 /* We expect the bootloader to fill in the size */
380 reg = <0 0x80000000 0 0>;
383 cpu0_opp_table: opp-table-cpu0 {
384 compatible = "operating-points-v2";
387 cpu0_opp1: opp-300000000 {
388 opp-hz = /bits/ 64 <300000000>;
389 opp-peak-kBps = <1200000 4800000>;
392 cpu0_opp2: opp-576000000 {
393 opp-hz = /bits/ 64 <576000000>;
394 opp-peak-kBps = <1200000 4800000>;
397 cpu0_opp3: opp-768000000 {
398 opp-hz = /bits/ 64 <768000000>;
399 opp-peak-kBps = <1200000 4800000>;
402 cpu0_opp4: opp-1017600000 {
403 opp-hz = /bits/ 64 <1017600000>;
404 opp-peak-kBps = <1804000 8908800>;
407 cpu0_opp5: opp-1248000000 {
408 opp-hz = /bits/ 64 <1248000000>;
409 opp-peak-kBps = <2188000 12902400>;
412 cpu0_opp6: opp-1324800000 {
413 opp-hz = /bits/ 64 <1324800000>;
414 opp-peak-kBps = <2188000 12902400>;
417 cpu0_opp7: opp-1516800000 {
418 opp-hz = /bits/ 64 <1516800000>;
419 opp-peak-kBps = <3072000 15052800>;
422 cpu0_opp8: opp-1612800000 {
423 opp-hz = /bits/ 64 <1612800000>;
424 opp-peak-kBps = <3072000 15052800>;
427 cpu0_opp9: opp-1708800000 {
428 opp-hz = /bits/ 64 <1708800000>;
429 opp-peak-kBps = <3072000 15052800>;
432 cpu0_opp10: opp-1804800000 {
433 opp-hz = /bits/ 64 <1804800000>;
434 opp-peak-kBps = <4068000 22425600>;
438 cpu6_opp_table: opp-table-cpu6 {
439 compatible = "operating-points-v2";
442 cpu6_opp1: opp-300000000 {
443 opp-hz = /bits/ 64 <300000000>;
444 opp-peak-kBps = <2188000 8908800>;
447 cpu6_opp2: opp-652800000 {
448 opp-hz = /bits/ 64 <652800000>;
449 opp-peak-kBps = <2188000 8908800>;
452 cpu6_opp3: opp-825600000 {
453 opp-hz = /bits/ 64 <825600000>;
454 opp-peak-kBps = <2188000 8908800>;
457 cpu6_opp4: opp-979200000 {
458 opp-hz = /bits/ 64 <979200000>;
459 opp-peak-kBps = <2188000 8908800>;
462 cpu6_opp5: opp-1113600000 {
463 opp-hz = /bits/ 64 <1113600000>;
464 opp-peak-kBps = <2188000 8908800>;
467 cpu6_opp6: opp-1267200000 {
468 opp-hz = /bits/ 64 <1267200000>;
469 opp-peak-kBps = <4068000 12902400>;
472 cpu6_opp7: opp-1555200000 {
473 opp-hz = /bits/ 64 <1555200000>;
474 opp-peak-kBps = <4068000 15052800>;
477 cpu6_opp8: opp-1708800000 {
478 opp-hz = /bits/ 64 <1708800000>;
479 opp-peak-kBps = <6220000 19353600>;
482 cpu6_opp9: opp-1843200000 {
483 opp-hz = /bits/ 64 <1843200000>;
484 opp-peak-kBps = <6220000 19353600>;
487 cpu6_opp10: opp-1900800000 {
488 opp-hz = /bits/ 64 <1900800000>;
489 opp-peak-kBps = <6220000 22425600>;
492 cpu6_opp11: opp-1996800000 {
493 opp-hz = /bits/ 64 <1996800000>;
494 opp-peak-kBps = <6220000 22425600>;
497 cpu6_opp12: opp-2112000000 {
498 opp-hz = /bits/ 64 <2112000000>;
499 opp-peak-kBps = <6220000 22425600>;
502 cpu6_opp13: opp-2208000000 {
503 opp-hz = /bits/ 64 <2208000000>;
504 opp-peak-kBps = <7216000 22425600>;
507 cpu6_opp14: opp-2323200000 {
508 opp-hz = /bits/ 64 <2323200000>;
509 opp-peak-kBps = <7216000 22425600>;
512 cpu6_opp15: opp-2400000000 {
513 opp-hz = /bits/ 64 <2400000000>;
514 opp-peak-kBps = <8532000 23347200>;
517 cpu6_opp16: opp-2553600000 {
518 opp-hz = /bits/ 64 <2553600000>;
519 opp-peak-kBps = <8532000 23347200>;
523 qspi_opp_table: opp-table-qspi {
524 compatible = "operating-points-v2";
527 opp-hz = /bits/ 64 <75000000>;
528 required-opps = <&rpmhpd_opp_low_svs>;
532 opp-hz = /bits/ 64 <150000000>;
533 required-opps = <&rpmhpd_opp_svs>;
537 opp-hz = /bits/ 64 <300000000>;
538 required-opps = <&rpmhpd_opp_nom>;
542 qup_opp_table: opp-table-qup {
543 compatible = "operating-points-v2";
546 opp-hz = /bits/ 64 <75000000>;
547 required-opps = <&rpmhpd_opp_low_svs>;
551 opp-hz = /bits/ 64 <100000000>;
552 required-opps = <&rpmhpd_opp_svs>;
556 opp-hz = /bits/ 64 <128000000>;
557 required-opps = <&rpmhpd_opp_nom>;
562 compatible = "arm,armv8-pmuv3";
563 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
567 compatible = "arm,psci-1.0";
571 reserved_memory: reserved-memory {
572 #address-cells = <2>;
576 hyp_mem: memory@80000000 {
577 reg = <0x0 0x80000000 0x0 0x600000>;
581 xbl_mem: memory@80600000 {
582 reg = <0x0 0x80600000 0x0 0x200000>;
586 aop_mem: memory@80800000 {
587 reg = <0x0 0x80800000 0x0 0x20000>;
591 aop_cmd_db_mem: memory@80820000 {
592 reg = <0x0 0x80820000 0x0 0x20000>;
593 compatible = "qcom,cmd-db";
597 sec_apps_mem: memory@808ff000 {
598 reg = <0x0 0x808ff000 0x0 0x1000>;
602 smem_mem: memory@80900000 {
603 reg = <0x0 0x80900000 0x0 0x200000>;
607 tz_mem: memory@80b00000 {
608 reg = <0x0 0x80b00000 0x0 0x3900000>;
612 ipa_fw_mem: memory@8b700000 {
613 reg = <0 0x8b700000 0 0x10000>;
617 rmtfs_mem: memory@94600000 {
618 compatible = "qcom,rmtfs-mem";
619 reg = <0x0 0x94600000 0x0 0x200000>;
622 qcom,client-id = <1>;
628 compatible = "qcom,smem";
629 memory-region = <&smem_mem>;
630 hwlocks = <&tcsr_mutex 3>;
634 compatible = "qcom,smp2p";
635 qcom,smem = <94>, <432>;
637 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
639 mboxes = <&apss_shared 6>;
641 qcom,local-pid = <0>;
642 qcom,remote-pid = <5>;
644 cdsp_smp2p_out: master-kernel {
645 qcom,entry-name = "master-kernel";
646 #qcom,smem-state-cells = <1>;
649 cdsp_smp2p_in: slave-kernel {
650 qcom,entry-name = "slave-kernel";
652 interrupt-controller;
653 #interrupt-cells = <2>;
658 compatible = "qcom,smp2p";
659 qcom,smem = <443>, <429>;
661 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
663 mboxes = <&apss_shared 10>;
665 qcom,local-pid = <0>;
666 qcom,remote-pid = <2>;
668 adsp_smp2p_out: master-kernel {
669 qcom,entry-name = "master-kernel";
670 #qcom,smem-state-cells = <1>;
673 adsp_smp2p_in: slave-kernel {
674 qcom,entry-name = "slave-kernel";
676 interrupt-controller;
677 #interrupt-cells = <2>;
682 compatible = "qcom,smp2p";
683 qcom,smem = <435>, <428>;
684 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
685 mboxes = <&apss_shared 14>;
686 qcom,local-pid = <0>;
687 qcom,remote-pid = <1>;
689 modem_smp2p_out: master-kernel {
690 qcom,entry-name = "master-kernel";
691 #qcom,smem-state-cells = <1>;
694 modem_smp2p_in: slave-kernel {
695 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
700 ipa_smp2p_out: ipa-ap-to-modem {
701 qcom,entry-name = "ipa";
702 #qcom,smem-state-cells = <1>;
705 ipa_smp2p_in: ipa-modem-to-ap {
706 qcom,entry-name = "ipa";
707 interrupt-controller;
708 #interrupt-cells = <2>;
713 #address-cells = <2>;
715 ranges = <0 0 0 0 0x10 0>;
716 dma-ranges = <0 0 0 0 0x10 0>;
717 compatible = "simple-bus";
719 gcc: clock-controller@100000 {
720 compatible = "qcom,gcc-sc7180";
721 reg = <0 0x00100000 0 0x1f0000>;
722 clocks = <&rpmhcc RPMH_CXO_CLK>,
723 <&rpmhcc RPMH_CXO_CLK_A>,
725 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
728 #power-domain-cells = <1>;
729 power-domains = <&rpmhpd SC7180_CX>;
732 qfprom: efuse@784000 {
733 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
734 reg = <0 0x00784000 0 0x7a0>,
735 <0 0x00780000 0 0x7a0>,
736 <0 0x00782000 0 0x100>,
737 <0 0x00786000 0 0x1fff>;
739 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
740 clock-names = "core";
741 #address-cells = <1>;
744 qusb2p_hstx_trim: hstx-trim-primary@25b {
749 gpu_speed_bin: gpu_speed_bin@1d2 {
756 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
757 reg = <0 0x007c4000 0 0x1000>,
758 <0 0x007c5000 0 0x1000>;
759 reg-names = "hc", "cqhci";
761 iommus = <&apps_smmu 0x60 0x0>;
762 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
764 interrupt-names = "hc_irq", "pwr_irq";
766 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
767 <&gcc GCC_SDCC1_APPS_CLK>,
768 <&rpmhcc RPMH_CXO_CLK>;
769 clock-names = "iface", "core", "xo";
770 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
771 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
772 interconnect-names = "sdhc-ddr","cpu-sdhc";
773 power-domains = <&rpmhpd SC7180_CX>;
774 operating-points-v2 = <&sdhc1_opp_table>;
783 mmc-hs400-enhanced-strobe;
787 sdhc1_opp_table: opp-table {
788 compatible = "operating-points-v2";
791 opp-hz = /bits/ 64 <100000000>;
792 required-opps = <&rpmhpd_opp_low_svs>;
793 opp-peak-kBps = <1800000 600000>;
794 opp-avg-kBps = <100000 0>;
798 opp-hz = /bits/ 64 <384000000>;
799 required-opps = <&rpmhpd_opp_nom>;
800 opp-peak-kBps = <5400000 1600000>;
801 opp-avg-kBps = <390000 0>;
806 qupv3_id_0: geniqup@8c0000 {
807 compatible = "qcom,geni-se-qup";
808 reg = <0 0x008c0000 0 0x6000>;
809 clock-names = "m-ahb", "s-ahb";
810 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
811 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
812 #address-cells = <2>;
815 iommus = <&apps_smmu 0x43 0x0>;
819 compatible = "qcom,geni-i2c";
820 reg = <0 0x00880000 0 0x4000>;
822 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
823 pinctrl-names = "default";
824 pinctrl-0 = <&qup_i2c0_default>;
825 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
826 #address-cells = <1>;
828 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
829 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
830 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
831 interconnect-names = "qup-core", "qup-config",
833 power-domains = <&rpmhpd SC7180_CX>;
834 required-opps = <&rpmhpd_opp_low_svs>;
839 compatible = "qcom,geni-spi";
840 reg = <0 0x00880000 0 0x4000>;
842 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
843 pinctrl-names = "default";
844 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
845 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
846 #address-cells = <1>;
848 power-domains = <&rpmhpd SC7180_CX>;
849 operating-points-v2 = <&qup_opp_table>;
850 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
851 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
852 interconnect-names = "qup-core", "qup-config";
856 uart0: serial@880000 {
857 compatible = "qcom,geni-uart";
858 reg = <0 0x00880000 0 0x4000>;
860 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
861 pinctrl-names = "default";
862 pinctrl-0 = <&qup_uart0_default>;
863 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
864 power-domains = <&rpmhpd SC7180_CX>;
865 operating-points-v2 = <&qup_opp_table>;
866 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
867 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
868 interconnect-names = "qup-core", "qup-config";
873 compatible = "qcom,geni-i2c";
874 reg = <0 0x00884000 0 0x4000>;
876 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
877 pinctrl-names = "default";
878 pinctrl-0 = <&qup_i2c1_default>;
879 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
880 #address-cells = <1>;
882 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
883 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
884 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
885 interconnect-names = "qup-core", "qup-config",
887 power-domains = <&rpmhpd SC7180_CX>;
888 required-opps = <&rpmhpd_opp_low_svs>;
893 compatible = "qcom,geni-spi";
894 reg = <0 0x00884000 0 0x4000>;
896 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
897 pinctrl-names = "default";
898 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
899 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
900 #address-cells = <1>;
902 power-domains = <&rpmhpd SC7180_CX>;
903 operating-points-v2 = <&qup_opp_table>;
904 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
906 interconnect-names = "qup-core", "qup-config";
910 uart1: serial@884000 {
911 compatible = "qcom,geni-uart";
912 reg = <0 0x00884000 0 0x4000>;
914 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
915 pinctrl-names = "default";
916 pinctrl-0 = <&qup_uart1_default>;
917 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
918 power-domains = <&rpmhpd SC7180_CX>;
919 operating-points-v2 = <&qup_opp_table>;
920 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
922 interconnect-names = "qup-core", "qup-config";
927 compatible = "qcom,geni-i2c";
928 reg = <0 0x00888000 0 0x4000>;
930 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
931 pinctrl-names = "default";
932 pinctrl-0 = <&qup_i2c2_default>;
933 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
934 #address-cells = <1>;
936 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
938 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
939 interconnect-names = "qup-core", "qup-config",
941 power-domains = <&rpmhpd SC7180_CX>;
942 required-opps = <&rpmhpd_opp_low_svs>;
946 uart2: serial@888000 {
947 compatible = "qcom,geni-uart";
948 reg = <0 0x00888000 0 0x4000>;
950 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
951 pinctrl-names = "default";
952 pinctrl-0 = <&qup_uart2_default>;
953 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
954 power-domains = <&rpmhpd SC7180_CX>;
955 operating-points-v2 = <&qup_opp_table>;
956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
957 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
958 interconnect-names = "qup-core", "qup-config";
963 compatible = "qcom,geni-i2c";
964 reg = <0 0x0088c000 0 0x4000>;
966 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
967 pinctrl-names = "default";
968 pinctrl-0 = <&qup_i2c3_default>;
969 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
970 #address-cells = <1>;
972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
974 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
975 interconnect-names = "qup-core", "qup-config",
977 power-domains = <&rpmhpd SC7180_CX>;
978 required-opps = <&rpmhpd_opp_low_svs>;
983 compatible = "qcom,geni-spi";
984 reg = <0 0x0088c000 0 0x4000>;
986 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
987 pinctrl-names = "default";
988 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
989 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
990 #address-cells = <1>;
992 power-domains = <&rpmhpd SC7180_CX>;
993 operating-points-v2 = <&qup_opp_table>;
994 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
995 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
996 interconnect-names = "qup-core", "qup-config";
1000 uart3: serial@88c000 {
1001 compatible = "qcom,geni-uart";
1002 reg = <0 0x0088c000 0 0x4000>;
1004 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_uart3_default>;
1007 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1008 power-domains = <&rpmhpd SC7180_CX>;
1009 operating-points-v2 = <&qup_opp_table>;
1010 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1011 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1012 interconnect-names = "qup-core", "qup-config";
1013 status = "disabled";
1017 compatible = "qcom,geni-i2c";
1018 reg = <0 0x00890000 0 0x4000>;
1020 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1021 pinctrl-names = "default";
1022 pinctrl-0 = <&qup_i2c4_default>;
1023 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1024 #address-cells = <1>;
1026 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1027 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1028 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1029 interconnect-names = "qup-core", "qup-config",
1031 power-domains = <&rpmhpd SC7180_CX>;
1032 required-opps = <&rpmhpd_opp_low_svs>;
1033 status = "disabled";
1036 uart4: serial@890000 {
1037 compatible = "qcom,geni-uart";
1038 reg = <0 0x00890000 0 0x4000>;
1040 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1041 pinctrl-names = "default";
1042 pinctrl-0 = <&qup_uart4_default>;
1043 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1044 power-domains = <&rpmhpd SC7180_CX>;
1045 operating-points-v2 = <&qup_opp_table>;
1046 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1048 interconnect-names = "qup-core", "qup-config";
1049 status = "disabled";
1053 compatible = "qcom,geni-i2c";
1054 reg = <0 0x00894000 0 0x4000>;
1056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1057 pinctrl-names = "default";
1058 pinctrl-0 = <&qup_i2c5_default>;
1059 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1060 #address-cells = <1>;
1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1064 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1065 interconnect-names = "qup-core", "qup-config",
1067 power-domains = <&rpmhpd SC7180_CX>;
1068 required-opps = <&rpmhpd_opp_low_svs>;
1069 status = "disabled";
1073 compatible = "qcom,geni-spi";
1074 reg = <0 0x00894000 0 0x4000>;
1076 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1077 pinctrl-names = "default";
1078 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1079 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1080 #address-cells = <1>;
1082 power-domains = <&rpmhpd SC7180_CX>;
1083 operating-points-v2 = <&qup_opp_table>;
1084 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1086 interconnect-names = "qup-core", "qup-config";
1087 status = "disabled";
1090 uart5: serial@894000 {
1091 compatible = "qcom,geni-uart";
1092 reg = <0 0x00894000 0 0x4000>;
1094 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1095 pinctrl-names = "default";
1096 pinctrl-0 = <&qup_uart5_default>;
1097 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1098 power-domains = <&rpmhpd SC7180_CX>;
1099 operating-points-v2 = <&qup_opp_table>;
1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1101 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1102 interconnect-names = "qup-core", "qup-config";
1103 status = "disabled";
1107 qupv3_id_1: geniqup@ac0000 {
1108 compatible = "qcom,geni-se-qup";
1109 reg = <0 0x00ac0000 0 0x6000>;
1110 clock-names = "m-ahb", "s-ahb";
1111 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1112 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1113 #address-cells = <2>;
1116 iommus = <&apps_smmu 0x4c3 0x0>;
1117 status = "disabled";
1120 compatible = "qcom,geni-i2c";
1121 reg = <0 0x00a80000 0 0x4000>;
1123 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&qup_i2c6_default>;
1126 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1127 #address-cells = <1>;
1129 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1131 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1132 interconnect-names = "qup-core", "qup-config",
1134 power-domains = <&rpmhpd SC7180_CX>;
1135 required-opps = <&rpmhpd_opp_low_svs>;
1136 status = "disabled";
1140 compatible = "qcom,geni-spi";
1141 reg = <0 0x00a80000 0 0x4000>;
1143 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1144 pinctrl-names = "default";
1145 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1146 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1147 #address-cells = <1>;
1149 power-domains = <&rpmhpd SC7180_CX>;
1150 operating-points-v2 = <&qup_opp_table>;
1151 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1153 interconnect-names = "qup-core", "qup-config";
1154 status = "disabled";
1157 uart6: serial@a80000 {
1158 compatible = "qcom,geni-uart";
1159 reg = <0 0x00a80000 0 0x4000>;
1161 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1162 pinctrl-names = "default";
1163 pinctrl-0 = <&qup_uart6_default>;
1164 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1165 power-domains = <&rpmhpd SC7180_CX>;
1166 operating-points-v2 = <&qup_opp_table>;
1167 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1169 interconnect-names = "qup-core", "qup-config";
1170 status = "disabled";
1174 compatible = "qcom,geni-i2c";
1175 reg = <0 0x00a84000 0 0x4000>;
1177 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1178 pinctrl-names = "default";
1179 pinctrl-0 = <&qup_i2c7_default>;
1180 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1181 #address-cells = <1>;
1183 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1184 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1185 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1186 interconnect-names = "qup-core", "qup-config",
1188 power-domains = <&rpmhpd SC7180_CX>;
1189 required-opps = <&rpmhpd_opp_low_svs>;
1190 status = "disabled";
1193 uart7: serial@a84000 {
1194 compatible = "qcom,geni-uart";
1195 reg = <0 0x00a84000 0 0x4000>;
1197 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1198 pinctrl-names = "default";
1199 pinctrl-0 = <&qup_uart7_default>;
1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1201 power-domains = <&rpmhpd SC7180_CX>;
1202 operating-points-v2 = <&qup_opp_table>;
1203 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1204 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1205 interconnect-names = "qup-core", "qup-config";
1206 status = "disabled";
1210 compatible = "qcom,geni-i2c";
1211 reg = <0 0x00a88000 0 0x4000>;
1213 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1214 pinctrl-names = "default";
1215 pinctrl-0 = <&qup_i2c8_default>;
1216 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1217 #address-cells = <1>;
1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1221 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1222 interconnect-names = "qup-core", "qup-config",
1224 power-domains = <&rpmhpd SC7180_CX>;
1225 required-opps = <&rpmhpd_opp_low_svs>;
1226 status = "disabled";
1230 compatible = "qcom,geni-spi";
1231 reg = <0 0x00a88000 0 0x4000>;
1233 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1236 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1237 #address-cells = <1>;
1239 power-domains = <&rpmhpd SC7180_CX>;
1240 operating-points-v2 = <&qup_opp_table>;
1241 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1242 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1243 interconnect-names = "qup-core", "qup-config";
1244 status = "disabled";
1247 uart8: serial@a88000 {
1248 compatible = "qcom,geni-debug-uart";
1249 reg = <0 0x00a88000 0 0x4000>;
1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&qup_uart8_default>;
1254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1255 power-domains = <&rpmhpd SC7180_CX>;
1256 operating-points-v2 = <&qup_opp_table>;
1257 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1259 interconnect-names = "qup-core", "qup-config";
1260 status = "disabled";
1264 compatible = "qcom,geni-i2c";
1265 reg = <0 0x00a8c000 0 0x4000>;
1267 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1268 pinctrl-names = "default";
1269 pinctrl-0 = <&qup_i2c9_default>;
1270 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1271 #address-cells = <1>;
1273 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1274 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1275 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1276 interconnect-names = "qup-core", "qup-config",
1278 power-domains = <&rpmhpd SC7180_CX>;
1279 required-opps = <&rpmhpd_opp_low_svs>;
1280 status = "disabled";
1283 uart9: serial@a8c000 {
1284 compatible = "qcom,geni-uart";
1285 reg = <0 0x00a8c000 0 0x4000>;
1287 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1288 pinctrl-names = "default";
1289 pinctrl-0 = <&qup_uart9_default>;
1290 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1291 power-domains = <&rpmhpd SC7180_CX>;
1292 operating-points-v2 = <&qup_opp_table>;
1293 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1294 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1295 interconnect-names = "qup-core", "qup-config";
1296 status = "disabled";
1300 compatible = "qcom,geni-i2c";
1301 reg = <0 0x00a90000 0 0x4000>;
1303 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1304 pinctrl-names = "default";
1305 pinctrl-0 = <&qup_i2c10_default>;
1306 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1307 #address-cells = <1>;
1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1312 interconnect-names = "qup-core", "qup-config",
1314 power-domains = <&rpmhpd SC7180_CX>;
1315 required-opps = <&rpmhpd_opp_low_svs>;
1316 status = "disabled";
1320 compatible = "qcom,geni-spi";
1321 reg = <0 0x00a90000 0 0x4000>;
1323 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1324 pinctrl-names = "default";
1325 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1326 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1327 #address-cells = <1>;
1329 power-domains = <&rpmhpd SC7180_CX>;
1330 operating-points-v2 = <&qup_opp_table>;
1331 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333 interconnect-names = "qup-core", "qup-config";
1334 status = "disabled";
1337 uart10: serial@a90000 {
1338 compatible = "qcom,geni-uart";
1339 reg = <0 0x00a90000 0 0x4000>;
1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1342 pinctrl-names = "default";
1343 pinctrl-0 = <&qup_uart10_default>;
1344 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1345 power-domains = <&rpmhpd SC7180_CX>;
1346 operating-points-v2 = <&qup_opp_table>;
1347 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1349 interconnect-names = "qup-core", "qup-config";
1350 status = "disabled";
1354 compatible = "qcom,geni-i2c";
1355 reg = <0 0x00a94000 0 0x4000>;
1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1358 pinctrl-names = "default";
1359 pinctrl-0 = <&qup_i2c11_default>;
1360 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1361 #address-cells = <1>;
1363 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1365 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1366 interconnect-names = "qup-core", "qup-config",
1368 power-domains = <&rpmhpd SC7180_CX>;
1369 required-opps = <&rpmhpd_opp_low_svs>;
1370 status = "disabled";
1374 compatible = "qcom,geni-spi";
1375 reg = <0 0x00a94000 0 0x4000>;
1377 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1378 pinctrl-names = "default";
1379 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1380 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1381 #address-cells = <1>;
1383 power-domains = <&rpmhpd SC7180_CX>;
1384 operating-points-v2 = <&qup_opp_table>;
1385 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1386 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1387 interconnect-names = "qup-core", "qup-config";
1388 status = "disabled";
1391 uart11: serial@a94000 {
1392 compatible = "qcom,geni-uart";
1393 reg = <0 0x00a94000 0 0x4000>;
1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1396 pinctrl-names = "default";
1397 pinctrl-0 = <&qup_uart11_default>;
1398 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1399 power-domains = <&rpmhpd SC7180_CX>;
1400 operating-points-v2 = <&qup_opp_table>;
1401 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1402 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1403 interconnect-names = "qup-core", "qup-config";
1404 status = "disabled";
1408 config_noc: interconnect@1500000 {
1409 compatible = "qcom,sc7180-config-noc";
1410 reg = <0 0x01500000 0 0x28000>;
1411 #interconnect-cells = <2>;
1412 qcom,bcm-voters = <&apps_bcm_voter>;
1415 system_noc: interconnect@1620000 {
1416 compatible = "qcom,sc7180-system-noc";
1417 reg = <0 0x01620000 0 0x17080>;
1418 #interconnect-cells = <2>;
1419 qcom,bcm-voters = <&apps_bcm_voter>;
1422 mc_virt: interconnect@1638000 {
1423 compatible = "qcom,sc7180-mc-virt";
1424 reg = <0 0x01638000 0 0x1000>;
1425 #interconnect-cells = <2>;
1426 qcom,bcm-voters = <&apps_bcm_voter>;
1429 qup_virt: interconnect@1650000 {
1430 compatible = "qcom,sc7180-qup-virt";
1431 reg = <0 0x01650000 0 0x1000>;
1432 #interconnect-cells = <2>;
1433 qcom,bcm-voters = <&apps_bcm_voter>;
1436 aggre1_noc: interconnect@16e0000 {
1437 compatible = "qcom,sc7180-aggre1-noc";
1438 reg = <0 0x016e0000 0 0x15080>;
1439 #interconnect-cells = <2>;
1440 qcom,bcm-voters = <&apps_bcm_voter>;
1443 aggre2_noc: interconnect@1705000 {
1444 compatible = "qcom,sc7180-aggre2-noc";
1445 reg = <0 0x01705000 0 0x9000>;
1446 #interconnect-cells = <2>;
1447 qcom,bcm-voters = <&apps_bcm_voter>;
1450 compute_noc: interconnect@170e000 {
1451 compatible = "qcom,sc7180-compute-noc";
1452 reg = <0 0x0170e000 0 0x6000>;
1453 #interconnect-cells = <2>;
1454 qcom,bcm-voters = <&apps_bcm_voter>;
1457 mmss_noc: interconnect@1740000 {
1458 compatible = "qcom,sc7180-mmss-noc";
1459 reg = <0 0x01740000 0 0x1c100>;
1460 #interconnect-cells = <2>;
1461 qcom,bcm-voters = <&apps_bcm_voter>;
1465 compatible = "qcom,sc7180-ipa";
1467 iommus = <&apps_smmu 0x440 0x0>,
1468 <&apps_smmu 0x442 0x0>;
1469 reg = <0 0x01e40000 0 0x7000>,
1470 <0 0x01e47000 0 0x2000>,
1471 <0 0x01e04000 0 0x2c000>;
1472 reg-names = "ipa-reg",
1476 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1477 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1478 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1479 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1480 interrupt-names = "ipa",
1485 clocks = <&rpmhcc RPMH_IPA_CLK>;
1486 clock-names = "core";
1488 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1489 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1491 interconnect-names = "memory",
1495 qcom,qmp = <&aoss_qmp>;
1497 qcom,smem-states = <&ipa_smp2p_out 0>,
1499 qcom,smem-state-names = "ipa-clock-enabled-valid",
1500 "ipa-clock-enabled";
1502 status = "disabled";
1505 tcsr_mutex: hwlock@1f40000 {
1506 compatible = "qcom,tcsr-mutex";
1507 reg = <0 0x01f40000 0 0x20000>;
1508 #hwlock-cells = <1>;
1511 tcsr_regs_1: syscon@1f60000 {
1512 compatible = "qcom,sc7180-tcsr", "syscon";
1513 reg = <0 0x01f60000 0 0x20000>;
1516 tcsr_regs_2: syscon@1fc0000 {
1517 compatible = "qcom,sc7180-tcsr", "syscon";
1518 reg = <0 0x01fc0000 0 0x40000>;
1521 tlmm: pinctrl@3500000 {
1522 compatible = "qcom,sc7180-pinctrl";
1523 reg = <0 0x03500000 0 0x300000>,
1524 <0 0x03900000 0 0x300000>,
1525 <0 0x03d00000 0 0x300000>;
1526 reg-names = "west", "north", "south";
1527 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1530 interrupt-controller;
1531 #interrupt-cells = <2>;
1532 gpio-ranges = <&tlmm 0 0 120>;
1533 wakeup-parent = <&pdc>;
1535 dp_hot_plug_det: dp-hot-plug-det-state {
1537 function = "dp_hot";
1540 qspi_clk: qspi-clk-state {
1542 function = "qspi_clk";
1545 qspi_cs0: qspi-cs0-state {
1547 function = "qspi_cs";
1550 qspi_cs1: qspi-cs1-state {
1552 function = "qspi_cs";
1555 qspi_data0: qspi-data0-state {
1557 function = "qspi_data";
1560 qspi_data1: qspi-data1-state {
1562 function = "qspi_data";
1565 qspi_data23: qspi-data23-state {
1566 pins = "gpio66", "gpio67";
1567 function = "qspi_data";
1570 qup_i2c0_default: qup-i2c0-default-state {
1571 pins = "gpio34", "gpio35";
1575 qup_i2c1_default: qup-i2c1-default-state {
1576 pins = "gpio0", "gpio1";
1580 qup_i2c2_default: qup-i2c2-default-state {
1581 pins = "gpio15", "gpio16";
1582 function = "qup02_i2c";
1585 qup_i2c3_default: qup-i2c3-default-state {
1586 pins = "gpio38", "gpio39";
1590 qup_i2c4_default: qup-i2c4-default-state {
1591 pins = "gpio115", "gpio116";
1592 function = "qup04_i2c";
1595 qup_i2c5_default: qup-i2c5-default-state {
1596 pins = "gpio25", "gpio26";
1600 qup_i2c6_default: qup-i2c6-default-state {
1601 pins = "gpio59", "gpio60";
1605 qup_i2c7_default: qup-i2c7-default-state {
1606 pins = "gpio6", "gpio7";
1607 function = "qup11_i2c";
1610 qup_i2c8_default: qup-i2c8-default-state {
1611 pins = "gpio42", "gpio43";
1615 qup_i2c9_default: qup-i2c9-default-state {
1616 pins = "gpio46", "gpio47";
1617 function = "qup13_i2c";
1620 qup_i2c10_default: qup-i2c10-default-state {
1621 pins = "gpio86", "gpio87";
1625 qup_i2c11_default: qup-i2c11-default-state {
1626 pins = "gpio53", "gpio54";
1630 qup_spi0_spi: qup-spi0-spi-state {
1631 pins = "gpio34", "gpio35", "gpio36";
1635 qup_spi0_cs: qup-spi0-cs-state {
1640 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
1645 qup_spi1_spi: qup-spi1-spi-state {
1646 pins = "gpio0", "gpio1", "gpio2";
1650 qup_spi1_cs: qup-spi1-cs-state {
1655 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
1660 qup_spi3_spi: qup-spi3-spi-state {
1661 pins = "gpio38", "gpio39", "gpio40";
1665 qup_spi3_cs: qup-spi3-cs-state {
1670 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
1675 qup_spi5_spi: qup-spi5-spi-state {
1676 pins = "gpio25", "gpio26", "gpio27";
1680 qup_spi5_cs: qup-spi5-cs-state {
1685 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
1690 qup_spi6_spi: qup-spi6-spi-state {
1691 pins = "gpio59", "gpio60", "gpio61";
1695 qup_spi6_cs: qup-spi6-cs-state {
1700 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
1705 qup_spi8_spi: qup-spi8-spi-state {
1706 pins = "gpio42", "gpio43", "gpio44";
1710 qup_spi8_cs: qup-spi8-cs-state {
1715 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
1720 qup_spi10_spi: qup-spi10-spi-state {
1721 pins = "gpio86", "gpio87", "gpio88";
1725 qup_spi10_cs: qup-spi10-cs-state {
1730 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
1735 qup_spi11_spi: qup-spi11-spi-state {
1736 pins = "gpio53", "gpio54", "gpio55";
1740 qup_spi11_cs: qup-spi11-cs-state {
1745 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
1750 qup_uart0_default: qup-uart0-default-state {
1751 qup_uart0_cts: cts-pins {
1756 qup_uart0_rts: rts-pins {
1761 qup_uart0_tx: tx-pins {
1766 qup_uart0_rx: rx-pins {
1772 qup_uart1_default: qup-uart1-default-state {
1773 qup_uart1_cts: cts-pins {
1778 qup_uart1_rts: rts-pins {
1783 qup_uart1_tx: tx-pins {
1788 qup_uart1_rx: rx-pins {
1794 qup_uart2_default: qup-uart2-default-state {
1795 qup_uart2_tx: tx-pins {
1797 function = "qup02_uart";
1800 qup_uart2_rx: rx-pins {
1802 function = "qup02_uart";
1806 qup_uart3_default: qup-uart3-default-state {
1807 qup_uart3_cts: cts-pins {
1812 qup_uart3_rts: rts-pins {
1817 qup_uart3_tx: tx-pins {
1822 qup_uart3_rx: rx-pins {
1828 qup_uart4_default: qup-uart4-default-state {
1829 qup_uart4_tx: tx-pins {
1831 function = "qup04_uart";
1834 qup_uart4_rx: rx-pins {
1836 function = "qup04_uart";
1840 qup_uart5_default: qup-uart5-default-state {
1841 qup_uart5_cts: cts-pins {
1846 qup_uart5_rts: rts-pins {
1851 qup_uart5_tx: tx-pins {
1856 qup_uart5_rx: rx-pins {
1862 qup_uart6_default: qup-uart6-default-state {
1863 qup_uart6_cts: cts-pins {
1868 qup_uart6_rts: rts-pins {
1873 qup_uart6_tx: tx-pins {
1878 qup_uart6_rx: rx-pins {
1884 qup_uart7_default: qup-uart7-default-state {
1885 qup_uart7_tx: tx-pins {
1887 function = "qup11_uart";
1890 qup_uart7_rx: rx-pins {
1892 function = "qup11_uart";
1896 qup_uart8_default: qup-uart8-default-state {
1897 qup_uart8_tx: tx-pins {
1902 qup_uart8_rx: rx-pins {
1908 qup_uart9_default: qup-uart9-default-state {
1909 qup_uart9_tx: tx-pins {
1911 function = "qup13_uart";
1914 qup_uart9_rx: rx-pins {
1916 function = "qup13_uart";
1920 qup_uart10_default: qup-uart10-default-state {
1921 qup_uart10_cts: cts-pins {
1926 qup_uart10_rts: rts-pins {
1931 qup_uart10_tx: tx-pins {
1936 qup_uart10_rx: rx-pins {
1942 qup_uart11_default: qup-uart11-default-state {
1943 qup_uart11_cts: cts-pins {
1948 qup_uart11_rts: rts-pins {
1953 qup_uart11_tx: tx-pins {
1958 qup_uart11_rx: rx-pins {
1964 sec_mi2s_active: sec-mi2s-active-state {
1965 pins = "gpio49", "gpio50", "gpio51";
1966 function = "mi2s_1";
1969 pri_mi2s_active: pri-mi2s-active-state {
1970 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1971 function = "mi2s_0";
1974 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
1976 function = "lpass_ext";
1980 remoteproc_mpss: remoteproc@4080000 {
1981 compatible = "qcom,sc7180-mpss-pas";
1982 reg = <0 0x04080000 0 0x4040>;
1984 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1985 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1986 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1987 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1988 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1989 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1990 interrupt-names = "wdog", "fatal", "ready", "handover",
1991 "stop-ack", "shutdown-ack";
1993 clocks = <&rpmhcc RPMH_CXO_CLK>;
1996 power-domains = <&rpmhpd SC7180_CX>,
1997 <&rpmhpd SC7180_MX>,
1998 <&rpmhpd SC7180_MSS>;
1999 power-domain-names = "cx", "mx", "mss";
2001 memory-region = <&mpss_mem>;
2003 qcom,qmp = <&aoss_qmp>;
2005 qcom,smem-states = <&modem_smp2p_out 0>;
2006 qcom,smem-state-names = "stop";
2008 status = "disabled";
2011 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2013 qcom,remote-pid = <1>;
2014 mboxes = <&apss_shared 12>;
2019 compatible = "qcom,adreno-618.0", "qcom,adreno";
2020 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2021 <0 0x05061000 0 0x800>;
2022 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2023 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2024 iommus = <&adreno_smmu 0>;
2025 operating-points-v2 = <&gpu_opp_table>;
2028 #cooling-cells = <2>;
2030 nvmem-cells = <&gpu_speed_bin>;
2031 nvmem-cell-names = "speed_bin";
2033 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2034 interconnect-names = "gfx-mem";
2036 gpu_opp_table: opp-table {
2037 compatible = "operating-points-v2";
2040 opp-hz = /bits/ 64 <825000000>;
2041 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2042 opp-peak-kBps = <8532000>;
2043 opp-supported-hw = <0x04>;
2047 opp-hz = /bits/ 64 <800000000>;
2048 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2049 opp-peak-kBps = <8532000>;
2050 opp-supported-hw = <0x07>;
2054 opp-hz = /bits/ 64 <650000000>;
2055 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2056 opp-peak-kBps = <7216000>;
2057 opp-supported-hw = <0x07>;
2061 opp-hz = /bits/ 64 <565000000>;
2062 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2063 opp-peak-kBps = <5412000>;
2064 opp-supported-hw = <0x07>;
2068 opp-hz = /bits/ 64 <430000000>;
2069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2070 opp-peak-kBps = <5412000>;
2071 opp-supported-hw = <0x07>;
2075 opp-hz = /bits/ 64 <355000000>;
2076 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2077 opp-peak-kBps = <3072000>;
2078 opp-supported-hw = <0x07>;
2082 opp-hz = /bits/ 64 <267000000>;
2083 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2084 opp-peak-kBps = <3072000>;
2085 opp-supported-hw = <0x07>;
2089 opp-hz = /bits/ 64 <180000000>;
2090 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2091 opp-peak-kBps = <1804000>;
2092 opp-supported-hw = <0x07>;
2097 adreno_smmu: iommu@5040000 {
2098 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2099 reg = <0 0x05040000 0 0x10000>;
2101 #global-interrupts = <2>;
2102 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2105 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2106 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2107 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2108 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2109 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2110 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2111 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2113 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2114 <&gcc GCC_GPU_CFG_AHB_CLK>;
2115 clock-names = "bus", "iface";
2117 power-domains = <&gpucc CX_GDSC>;
2121 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2122 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2123 <0 0x0b490000 0 0x10000>;
2124 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2125 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2127 interrupt-names = "hfi", "gmu";
2128 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2129 <&gpucc GPU_CC_CXO_CLK>,
2130 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2131 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2132 clock-names = "gmu", "cxo", "axi", "memnoc";
2133 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2134 power-domain-names = "cx", "gx";
2135 iommus = <&adreno_smmu 5>;
2136 operating-points-v2 = <&gmu_opp_table>;
2138 gmu_opp_table: opp-table {
2139 compatible = "operating-points-v2";
2142 opp-hz = /bits/ 64 <200000000>;
2143 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2148 gpucc: clock-controller@5090000 {
2149 compatible = "qcom,sc7180-gpucc";
2150 reg = <0 0x05090000 0 0x9000>;
2151 clocks = <&rpmhcc RPMH_CXO_CLK>,
2152 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2153 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2154 clock-names = "bi_tcxo",
2155 "gcc_gpu_gpll0_clk_src",
2156 "gcc_gpu_gpll0_div_clk_src";
2159 #power-domain-cells = <1>;
2163 compatible = "qcom,sc7180-dcc", "qcom,dcc";
2164 reg = <0x0 0x010a2000 0x0 0x1000>,
2165 <0x0 0x010ae000 0x0 0x2000>;
2169 compatible = "arm,coresight-stm", "arm,primecell";
2170 reg = <0 0x06002000 0 0x1000>,
2171 <0 0x16280000 0 0x180000>;
2172 reg-names = "stm-base", "stm-stimulus-base";
2174 clocks = <&aoss_qmp>;
2175 clock-names = "apb_pclk";
2180 remote-endpoint = <&funnel0_in7>;
2187 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2188 reg = <0 0x06041000 0 0x1000>;
2190 clocks = <&aoss_qmp>;
2191 clock-names = "apb_pclk";
2195 funnel0_out: endpoint {
2196 remote-endpoint = <&merge_funnel_in0>;
2202 #address-cells = <1>;
2207 funnel0_in7: endpoint {
2208 remote-endpoint = <&stm_out>;
2215 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2216 reg = <0 0x06042000 0 0x1000>;
2218 clocks = <&aoss_qmp>;
2219 clock-names = "apb_pclk";
2223 funnel1_out: endpoint {
2224 remote-endpoint = <&merge_funnel_in1>;
2230 #address-cells = <1>;
2235 funnel1_in4: endpoint {
2236 remote-endpoint = <&apss_merge_funnel_out>;
2243 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2244 reg = <0 0x06045000 0 0x1000>;
2246 clocks = <&aoss_qmp>;
2247 clock-names = "apb_pclk";
2251 merge_funnel_out: endpoint {
2252 remote-endpoint = <&swao_funnel_in>;
2258 #address-cells = <1>;
2263 merge_funnel_in0: endpoint {
2264 remote-endpoint = <&funnel0_out>;
2270 merge_funnel_in1: endpoint {
2271 remote-endpoint = <&funnel1_out>;
2277 replicator@6046000 {
2278 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2279 reg = <0 0x06046000 0 0x1000>;
2281 clocks = <&aoss_qmp>;
2282 clock-names = "apb_pclk";
2286 replicator_out: endpoint {
2287 remote-endpoint = <&etr_in>;
2294 replicator_in: endpoint {
2295 remote-endpoint = <&swao_replicator_out>;
2302 compatible = "arm,coresight-tmc", "arm,primecell";
2303 reg = <0 0x06048000 0 0x1000>;
2304 iommus = <&apps_smmu 0x04a0 0x20>;
2306 clocks = <&aoss_qmp>;
2307 clock-names = "apb_pclk";
2313 remote-endpoint = <&replicator_out>;
2320 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2321 reg = <0 0x06b04000 0 0x1000>;
2323 clocks = <&aoss_qmp>;
2324 clock-names = "apb_pclk";
2328 swao_funnel_out: endpoint {
2329 remote-endpoint = <&etf_in>;
2335 #address-cells = <1>;
2340 swao_funnel_in: endpoint {
2341 remote-endpoint = <&merge_funnel_out>;
2348 compatible = "arm,coresight-tmc", "arm,primecell";
2349 reg = <0 0x06b05000 0 0x1000>;
2351 clocks = <&aoss_qmp>;
2352 clock-names = "apb_pclk";
2357 remote-endpoint = <&swao_replicator_in>;
2365 remote-endpoint = <&swao_funnel_out>;
2371 replicator@6b06000 {
2372 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2373 reg = <0 0x06b06000 0 0x1000>;
2375 clocks = <&aoss_qmp>;
2376 clock-names = "apb_pclk";
2377 qcom,replicator-loses-context;
2381 swao_replicator_out: endpoint {
2382 remote-endpoint = <&replicator_in>;
2389 swao_replicator_in: endpoint {
2390 remote-endpoint = <&etf_out>;
2397 compatible = "arm,coresight-etm4x", "arm,primecell";
2398 reg = <0 0x07040000 0 0x1000>;
2402 clocks = <&aoss_qmp>;
2403 clock-names = "apb_pclk";
2404 arm,coresight-loses-context-with-cpu;
2409 etm0_out: endpoint {
2410 remote-endpoint = <&apss_funnel_in0>;
2417 compatible = "arm,coresight-etm4x", "arm,primecell";
2418 reg = <0 0x07140000 0 0x1000>;
2422 clocks = <&aoss_qmp>;
2423 clock-names = "apb_pclk";
2424 arm,coresight-loses-context-with-cpu;
2429 etm1_out: endpoint {
2430 remote-endpoint = <&apss_funnel_in1>;
2437 compatible = "arm,coresight-etm4x", "arm,primecell";
2438 reg = <0 0x07240000 0 0x1000>;
2442 clocks = <&aoss_qmp>;
2443 clock-names = "apb_pclk";
2444 arm,coresight-loses-context-with-cpu;
2449 etm2_out: endpoint {
2450 remote-endpoint = <&apss_funnel_in2>;
2457 compatible = "arm,coresight-etm4x", "arm,primecell";
2458 reg = <0 0x07340000 0 0x1000>;
2462 clocks = <&aoss_qmp>;
2463 clock-names = "apb_pclk";
2464 arm,coresight-loses-context-with-cpu;
2469 etm3_out: endpoint {
2470 remote-endpoint = <&apss_funnel_in3>;
2477 compatible = "arm,coresight-etm4x", "arm,primecell";
2478 reg = <0 0x07440000 0 0x1000>;
2482 clocks = <&aoss_qmp>;
2483 clock-names = "apb_pclk";
2484 arm,coresight-loses-context-with-cpu;
2489 etm4_out: endpoint {
2490 remote-endpoint = <&apss_funnel_in4>;
2497 compatible = "arm,coresight-etm4x", "arm,primecell";
2498 reg = <0 0x07540000 0 0x1000>;
2502 clocks = <&aoss_qmp>;
2503 clock-names = "apb_pclk";
2504 arm,coresight-loses-context-with-cpu;
2509 etm5_out: endpoint {
2510 remote-endpoint = <&apss_funnel_in5>;
2517 compatible = "arm,coresight-etm4x", "arm,primecell";
2518 reg = <0 0x07640000 0 0x1000>;
2522 clocks = <&aoss_qmp>;
2523 clock-names = "apb_pclk";
2524 arm,coresight-loses-context-with-cpu;
2529 etm6_out: endpoint {
2530 remote-endpoint = <&apss_funnel_in6>;
2537 compatible = "arm,coresight-etm4x", "arm,primecell";
2538 reg = <0 0x07740000 0 0x1000>;
2542 clocks = <&aoss_qmp>;
2543 clock-names = "apb_pclk";
2544 arm,coresight-loses-context-with-cpu;
2549 etm7_out: endpoint {
2550 remote-endpoint = <&apss_funnel_in7>;
2556 funnel@7800000 { /* APSS Funnel */
2557 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2558 reg = <0 0x07800000 0 0x1000>;
2560 clocks = <&aoss_qmp>;
2561 clock-names = "apb_pclk";
2565 apss_funnel_out: endpoint {
2566 remote-endpoint = <&apss_merge_funnel_in>;
2572 #address-cells = <1>;
2577 apss_funnel_in0: endpoint {
2578 remote-endpoint = <&etm0_out>;
2584 apss_funnel_in1: endpoint {
2585 remote-endpoint = <&etm1_out>;
2591 apss_funnel_in2: endpoint {
2592 remote-endpoint = <&etm2_out>;
2598 apss_funnel_in3: endpoint {
2599 remote-endpoint = <&etm3_out>;
2605 apss_funnel_in4: endpoint {
2606 remote-endpoint = <&etm4_out>;
2612 apss_funnel_in5: endpoint {
2613 remote-endpoint = <&etm5_out>;
2619 apss_funnel_in6: endpoint {
2620 remote-endpoint = <&etm6_out>;
2626 apss_funnel_in7: endpoint {
2627 remote-endpoint = <&etm7_out>;
2634 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2635 reg = <0 0x07810000 0 0x1000>;
2637 clocks = <&aoss_qmp>;
2638 clock-names = "apb_pclk";
2642 apss_merge_funnel_out: endpoint {
2643 remote-endpoint = <&funnel1_in4>;
2650 apss_merge_funnel_in: endpoint {
2651 remote-endpoint = <&apss_funnel_out>;
2657 sdhc_2: mmc@8804000 {
2658 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2659 reg = <0 0x08804000 0 0x1000>;
2661 iommus = <&apps_smmu 0x80 0>;
2662 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2663 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2664 interrupt-names = "hc_irq", "pwr_irq";
2666 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2667 <&gcc GCC_SDCC2_APPS_CLK>,
2668 <&rpmhcc RPMH_CXO_CLK>;
2669 clock-names = "iface", "core", "xo";
2671 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2673 interconnect-names = "sdhc-ddr","cpu-sdhc";
2674 power-domains = <&rpmhpd SC7180_CX>;
2675 operating-points-v2 = <&sdhc2_opp_table>;
2679 status = "disabled";
2681 sdhc2_opp_table: opp-table {
2682 compatible = "operating-points-v2";
2685 opp-hz = /bits/ 64 <100000000>;
2686 required-opps = <&rpmhpd_opp_low_svs>;
2687 opp-peak-kBps = <1800000 600000>;
2688 opp-avg-kBps = <100000 0>;
2692 opp-hz = /bits/ 64 <202000000>;
2693 required-opps = <&rpmhpd_opp_nom>;
2694 opp-peak-kBps = <5400000 1600000>;
2695 opp-avg-kBps = <200000 0>;
2701 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1";
2702 reg = <0 0x088dc000 0 0x600>;
2703 iommus = <&apps_smmu 0x20 0x0>;
2704 #address-cells = <1>;
2706 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2707 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2708 <&gcc GCC_QSPI_CORE_CLK>;
2709 clock-names = "iface", "core";
2710 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2711 &config_noc SLAVE_QSPI_0 0>;
2712 interconnect-names = "qspi-config";
2713 power-domains = <&rpmhpd SC7180_CX>;
2714 operating-points-v2 = <&qspi_opp_table>;
2715 status = "disabled";
2718 usb_1_hsphy: phy@88e3000 {
2719 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2720 reg = <0 0x088e3000 0 0x400>;
2721 status = "disabled";
2723 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2724 <&rpmhcc RPMH_CXO_CLK>;
2725 clock-names = "cfg_ahb", "ref";
2726 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2728 nvmem-cells = <&qusb2p_hstx_trim>;
2731 usb_1_qmpphy: phy-wrapper@88e9000 {
2732 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2733 reg = <0 0x088e9000 0 0x18c>,
2734 <0 0x088e8000 0 0x3c>,
2735 <0 0x088ea000 0 0x18c>;
2736 status = "disabled";
2737 #address-cells = <2>;
2741 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2742 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2743 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2744 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2745 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2747 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2748 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2749 reset-names = "phy", "common";
2751 usb_1_ssphy: usb3-phy@88e9200 {
2752 reg = <0 0x088e9200 0 0x128>,
2753 <0 0x088e9400 0 0x200>,
2754 <0 0x088e9c00 0 0x218>,
2755 <0 0x088e9600 0 0x128>,
2756 <0 0x088e9800 0 0x200>,
2757 <0 0x088e9a00 0 0x18>;
2760 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2761 clock-names = "pipe0";
2762 clock-output-names = "usb3_phy_pipe_clk_src";
2765 dp_phy: dp-phy@88ea200 {
2766 reg = <0 0x088ea200 0 0x200>,
2767 <0 0x088ea400 0 0x200>,
2768 <0 0x088eaa00 0 0x200>,
2769 <0 0x088ea600 0 0x200>,
2770 <0 0x088ea800 0 0x200>;
2776 dc_noc: interconnect@9160000 {
2777 compatible = "qcom,sc7180-dc-noc";
2778 reg = <0 0x09160000 0 0x03200>;
2779 #interconnect-cells = <2>;
2780 qcom,bcm-voters = <&apps_bcm_voter>;
2783 system-cache-controller@9200000 {
2784 compatible = "qcom,sc7180-llcc";
2785 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2786 reg-names = "llcc0_base", "llcc_broadcast_base";
2787 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2790 gem_noc: interconnect@9680000 {
2791 compatible = "qcom,sc7180-gem-noc";
2792 reg = <0 0x09680000 0 0x3e200>;
2793 #interconnect-cells = <2>;
2794 qcom,bcm-voters = <&apps_bcm_voter>;
2797 npu_noc: interconnect@9990000 {
2798 compatible = "qcom,sc7180-npu-noc";
2799 reg = <0 0x09990000 0 0x1600>;
2800 #interconnect-cells = <2>;
2801 qcom,bcm-voters = <&apps_bcm_voter>;
2804 usb_1: usb@a6f8800 {
2805 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2806 reg = <0 0x0a6f8800 0 0x400>;
2807 status = "disabled";
2808 #address-cells = <2>;
2813 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2814 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2815 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2816 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
2817 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
2818 clock-names = "cfg_noc",
2824 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2825 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2826 assigned-clock-rates = <19200000>, <150000000>;
2828 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2829 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2830 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2831 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2832 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2833 "dm_hs_phy_irq", "dp_hs_phy_irq";
2835 power-domains = <&gcc USB30_PRIM_GDSC>;
2836 required-opps = <&rpmhpd_opp_nom>;
2838 resets = <&gcc GCC_USB30_PRIM_BCR>;
2840 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2842 interconnect-names = "usb-ddr", "apps-usb";
2846 usb_1_dwc3: usb@a600000 {
2847 compatible = "snps,dwc3";
2848 reg = <0 0x0a600000 0 0xe000>;
2849 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2850 iommus = <&apps_smmu 0x540 0>;
2851 snps,dis_u2_susphy_quirk;
2852 snps,dis_enblslpm_quirk;
2853 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2854 phy-names = "usb2-phy", "usb3-phy";
2855 maximum-speed = "super-speed";
2859 venus: video-codec@aa00000 {
2860 compatible = "qcom,sc7180-venus";
2861 reg = <0 0x0aa00000 0 0xff000>;
2862 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2863 power-domains = <&videocc VENUS_GDSC>,
2864 <&videocc VCODEC0_GDSC>,
2865 <&rpmhpd SC7180_CX>;
2866 power-domain-names = "venus", "vcodec0", "cx";
2867 operating-points-v2 = <&venus_opp_table>;
2868 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2869 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2870 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2871 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2872 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2873 clock-names = "core", "iface", "bus",
2874 "vcodec0_core", "vcodec0_bus";
2875 iommus = <&apps_smmu 0x0c00 0x60>;
2876 memory-region = <&venus_mem>;
2877 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2878 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2879 interconnect-names = "video-mem", "cpu-cfg";
2882 compatible = "venus-decoder";
2886 compatible = "venus-encoder";
2889 venus_opp_table: opp-table {
2890 compatible = "operating-points-v2";
2893 opp-hz = /bits/ 64 <150000000>;
2894 required-opps = <&rpmhpd_opp_low_svs>;
2898 opp-hz = /bits/ 64 <270000000>;
2899 required-opps = <&rpmhpd_opp_svs>;
2903 opp-hz = /bits/ 64 <340000000>;
2904 required-opps = <&rpmhpd_opp_svs_l1>;
2908 opp-hz = /bits/ 64 <434000000>;
2909 required-opps = <&rpmhpd_opp_nom>;
2913 opp-hz = /bits/ 64 <500000097>;
2914 required-opps = <&rpmhpd_opp_turbo>;
2919 videocc: clock-controller@ab00000 {
2920 compatible = "qcom,sc7180-videocc";
2921 reg = <0 0x0ab00000 0 0x10000>;
2922 clocks = <&rpmhcc RPMH_CXO_CLK>;
2923 clock-names = "bi_tcxo";
2926 #power-domain-cells = <1>;
2929 camnoc_virt: interconnect@ac00000 {
2930 compatible = "qcom,sc7180-camnoc-virt";
2931 reg = <0 0x0ac00000 0 0x1000>;
2932 #interconnect-cells = <2>;
2933 qcom,bcm-voters = <&apps_bcm_voter>;
2936 camcc: clock-controller@ad00000 {
2937 compatible = "qcom,sc7180-camcc";
2938 reg = <0 0x0ad00000 0 0x10000>;
2939 clocks = <&rpmhcc RPMH_CXO_CLK>,
2940 <&gcc GCC_CAMERA_AHB_CLK>,
2941 <&gcc GCC_CAMERA_XO_CLK>;
2942 clock-names = "bi_tcxo", "iface", "xo";
2945 #power-domain-cells = <1>;
2948 mdss: display-subsystem@ae00000 {
2949 compatible = "qcom,sc7180-mdss";
2950 reg = <0 0x0ae00000 0 0x1000>;
2953 power-domains = <&dispcc MDSS_GDSC>;
2955 clocks = <&gcc GCC_DISP_AHB_CLK>,
2956 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2957 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2958 clock-names = "iface", "ahb", "core";
2960 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2961 interrupt-controller;
2962 #interrupt-cells = <1>;
2964 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2965 interconnect-names = "mdp0-mem";
2967 iommus = <&apps_smmu 0x800 0x2>;
2969 #address-cells = <2>;
2973 status = "disabled";
2975 mdp: display-controller@ae01000 {
2976 compatible = "qcom,sc7180-dpu";
2977 reg = <0 0x0ae01000 0 0x8f000>,
2978 <0 0x0aeb0000 0 0x2008>;
2979 reg-names = "mdp", "vbif";
2981 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2982 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2983 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2984 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2985 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2986 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2987 clock-names = "bus", "iface", "rot", "lut", "core",
2989 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2990 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2991 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2992 assigned-clock-rates = <19200000>,
2995 operating-points-v2 = <&mdp_opp_table>;
2996 power-domains = <&rpmhpd SC7180_CX>;
2998 interrupt-parent = <&mdss>;
3002 #address-cells = <1>;
3007 dpu_intf1_out: endpoint {
3008 remote-endpoint = <&mdss_dsi0_in>;
3014 dpu_intf0_out: endpoint {
3015 remote-endpoint = <&dp_in>;
3020 mdp_opp_table: opp-table {
3021 compatible = "operating-points-v2";
3024 opp-hz = /bits/ 64 <200000000>;
3025 required-opps = <&rpmhpd_opp_low_svs>;
3029 opp-hz = /bits/ 64 <300000000>;
3030 required-opps = <&rpmhpd_opp_svs>;
3034 opp-hz = /bits/ 64 <345000000>;
3035 required-opps = <&rpmhpd_opp_svs_l1>;
3039 opp-hz = /bits/ 64 <460000000>;
3040 required-opps = <&rpmhpd_opp_nom>;
3045 mdss_dsi0: dsi@ae94000 {
3046 compatible = "qcom,sc7180-dsi-ctrl",
3047 "qcom,mdss-dsi-ctrl";
3048 reg = <0 0x0ae94000 0 0x400>;
3049 reg-names = "dsi_ctrl";
3051 interrupt-parent = <&mdss>;
3054 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3055 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3056 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3057 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3058 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3059 <&gcc GCC_DISP_HF_AXI_CLK>;
3060 clock-names = "byte",
3067 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3068 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3070 operating-points-v2 = <&dsi_opp_table>;
3071 power-domains = <&rpmhpd SC7180_CX>;
3073 phys = <&mdss_dsi0_phy>;
3075 #address-cells = <1>;
3078 status = "disabled";
3081 #address-cells = <1>;
3086 mdss_dsi0_in: endpoint {
3087 remote-endpoint = <&dpu_intf1_out>;
3093 mdss_dsi0_out: endpoint {
3098 dsi_opp_table: opp-table {
3099 compatible = "operating-points-v2";
3102 opp-hz = /bits/ 64 <187500000>;
3103 required-opps = <&rpmhpd_opp_low_svs>;
3107 opp-hz = /bits/ 64 <300000000>;
3108 required-opps = <&rpmhpd_opp_svs>;
3112 opp-hz = /bits/ 64 <358000000>;
3113 required-opps = <&rpmhpd_opp_svs_l1>;
3118 mdss_dsi0_phy: phy@ae94400 {
3119 compatible = "qcom,dsi-phy-10nm";
3120 reg = <0 0x0ae94400 0 0x200>,
3121 <0 0x0ae94600 0 0x280>,
3122 <0 0x0ae94a00 0 0x1e0>;
3123 reg-names = "dsi_phy",
3130 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3131 <&rpmhcc RPMH_CXO_CLK>;
3132 clock-names = "iface", "ref";
3134 status = "disabled";
3137 mdss_dp: displayport-controller@ae90000 {
3138 compatible = "qcom,sc7180-dp";
3139 status = "disabled";
3141 reg = <0 0x0ae90000 0 0x200>,
3142 <0 0x0ae90200 0 0x200>,
3143 <0 0x0ae90400 0 0xc00>,
3144 <0 0x0ae91000 0 0x400>,
3145 <0 0x0ae91400 0 0x400>;
3147 interrupt-parent = <&mdss>;
3150 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3151 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3152 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3153 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3154 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3155 clock-names = "core_iface", "core_aux", "ctrl_link",
3156 "ctrl_link_iface", "stream_pixel";
3157 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3158 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3159 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3163 operating-points-v2 = <&dp_opp_table>;
3164 power-domains = <&rpmhpd SC7180_CX>;
3166 #sound-dai-cells = <0>;
3169 #address-cells = <1>;
3174 remote-endpoint = <&dpu_intf0_out>;
3180 mdss_dp_out: endpoint { };
3184 dp_opp_table: opp-table {
3185 compatible = "operating-points-v2";
3188 opp-hz = /bits/ 64 <160000000>;
3189 required-opps = <&rpmhpd_opp_low_svs>;
3193 opp-hz = /bits/ 64 <270000000>;
3194 required-opps = <&rpmhpd_opp_svs>;
3198 opp-hz = /bits/ 64 <540000000>;
3199 required-opps = <&rpmhpd_opp_svs_l1>;
3203 opp-hz = /bits/ 64 <810000000>;
3204 required-opps = <&rpmhpd_opp_nom>;
3210 dispcc: clock-controller@af00000 {
3211 compatible = "qcom,sc7180-dispcc";
3212 reg = <0 0x0af00000 0 0x200000>;
3213 clocks = <&rpmhcc RPMH_CXO_CLK>,
3214 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3219 clock-names = "bi_tcxo",
3220 "gcc_disp_gpll0_clk_src",
3221 "dsi0_phy_pll_out_byteclk",
3222 "dsi0_phy_pll_out_dsiclk",
3223 "dp_phy_pll_link_clk",
3224 "dp_phy_pll_vco_div_clk";
3227 #power-domain-cells = <1>;
3230 pdc: interrupt-controller@b220000 {
3231 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3232 reg = <0 0x0b220000 0 0x30000>;
3233 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3234 #interrupt-cells = <2>;
3235 interrupt-parent = <&intc>;
3236 interrupt-controller;
3239 pdc_reset: reset-controller@b2e0000 {
3240 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3241 reg = <0 0x0b2e0000 0 0x20000>;
3245 tsens0: thermal-sensor@c263000 {
3246 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3247 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3248 <0 0x0c222000 0 0x1ff>; /* SROT */
3249 #qcom,sensors = <15>;
3250 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3251 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3252 interrupt-names = "uplow","critical";
3253 #thermal-sensor-cells = <1>;
3256 tsens1: thermal-sensor@c265000 {
3257 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3258 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3259 <0 0x0c223000 0 0x1ff>; /* SROT */
3260 #qcom,sensors = <10>;
3261 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3262 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3263 interrupt-names = "uplow","critical";
3264 #thermal-sensor-cells = <1>;
3267 aoss_reset: reset-controller@c2a0000 {
3268 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3269 reg = <0 0x0c2a0000 0 0x31000>;
3273 aoss_qmp: power-management@c300000 {
3274 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp";
3275 reg = <0 0x0c300000 0 0x400>;
3276 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3277 mboxes = <&apss_shared 0>;
3283 compatible = "qcom,rpmh-stats";
3284 reg = <0 0x0c3f0000 0 0x400>;
3287 spmi_bus: spmi@c440000 {
3288 compatible = "qcom,spmi-pmic-arb";
3289 reg = <0 0x0c440000 0 0x1100>,
3290 <0 0x0c600000 0 0x2000000>,
3291 <0 0x0e600000 0 0x100000>,
3292 <0 0x0e700000 0 0xa0000>,
3293 <0 0x0c40a000 0 0x26000>;
3294 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3295 interrupt-names = "periph_irq";
3296 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3299 #address-cells = <2>;
3301 interrupt-controller;
3302 #interrupt-cells = <4>;
3306 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd";
3307 reg = <0 0x146aa000 0 0x2000>;
3309 #address-cells = <1>;
3312 ranges = <0 0 0x146aa000 0x2000>;
3315 compatible = "qcom,pil-reloc-info";
3320 apps_smmu: iommu@15000000 {
3321 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3322 reg = <0 0x15000000 0 0x100000>;
3324 #global-interrupts = <1>;
3325 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3326 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3327 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3328 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3329 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3330 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3332 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3333 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3334 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3335 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3336 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3337 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3338 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3339 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3340 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3341 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3342 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3343 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3344 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3345 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3346 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3347 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3348 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3349 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3350 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3351 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3352 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3353 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3354 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3355 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3356 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3357 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3358 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3359 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3360 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3361 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3362 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3363 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3364 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3365 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3366 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3367 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3368 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3369 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3370 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3371 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3372 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3373 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3374 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3375 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3376 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3377 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3378 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3379 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3380 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3381 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3382 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3383 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3384 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3385 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3386 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3387 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3388 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3389 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3390 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3391 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3392 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3393 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3403 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3404 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3405 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3408 intc: interrupt-controller@17a00000 {
3409 compatible = "arm,gic-v3";
3410 #address-cells = <2>;
3413 #interrupt-cells = <3>;
3414 interrupt-controller;
3415 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3416 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3417 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3419 msi-controller@17a40000 {
3420 compatible = "arm,gic-v3-its";
3423 reg = <0 0x17a40000 0 0x20000>;
3424 status = "disabled";
3428 apss_shared: mailbox@17c00000 {
3429 compatible = "qcom,sc7180-apss-shared",
3430 "qcom,sdm845-apss-shared";
3431 reg = <0 0x17c00000 0 0x10000>;
3436 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3437 reg = <0 0x17c10000 0 0x1000>;
3438 clocks = <&sleep_clk>;
3439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3443 #address-cells = <1>;
3445 ranges = <0 0 0 0x20000000>;
3446 compatible = "arm,armv7-timer-mem";
3447 reg = <0 0x17c20000 0 0x1000>;
3451 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3452 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3453 reg = <0x17c21000 0x1000>,
3454 <0x17c22000 0x1000>;
3459 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3460 reg = <0x17c23000 0x1000>;
3461 status = "disabled";
3466 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3467 reg = <0x17c25000 0x1000>;
3468 status = "disabled";
3473 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3474 reg = <0x17c27000 0x1000>;
3475 status = "disabled";
3480 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3481 reg = <0x17c29000 0x1000>;
3482 status = "disabled";
3487 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3488 reg = <0x17c2b000 0x1000>;
3489 status = "disabled";
3494 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3495 reg = <0x17c2d000 0x1000>;
3496 status = "disabled";
3500 apps_rsc: rsc@18200000 {
3501 compatible = "qcom,rpmh-rsc";
3502 reg = <0 0x18200000 0 0x10000>,
3503 <0 0x18210000 0 0x10000>,
3504 <0 0x18220000 0 0x10000>;
3505 reg-names = "drv-0", "drv-1", "drv-2";
3506 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3507 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3508 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3509 qcom,tcs-offset = <0xd00>;
3511 qcom,tcs-config = <ACTIVE_TCS 2>,
3516 rpmhcc: clock-controller {
3517 compatible = "qcom,sc7180-rpmh-clk";
3518 clocks = <&xo_board>;
3523 rpmhpd: power-controller {
3524 compatible = "qcom,sc7180-rpmhpd";
3525 #power-domain-cells = <1>;
3526 operating-points-v2 = <&rpmhpd_opp_table>;
3528 rpmhpd_opp_table: opp-table {
3529 compatible = "operating-points-v2";
3531 rpmhpd_opp_ret: opp1 {
3532 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3535 rpmhpd_opp_min_svs: opp2 {
3536 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3539 rpmhpd_opp_low_svs: opp3 {
3540 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3543 rpmhpd_opp_svs: opp4 {
3544 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3547 rpmhpd_opp_svs_l1: opp5 {
3548 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3551 rpmhpd_opp_svs_l2: opp6 {
3555 rpmhpd_opp_nom: opp7 {
3556 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3559 rpmhpd_opp_nom_l1: opp8 {
3560 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3563 rpmhpd_opp_nom_l2: opp9 {
3564 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3567 rpmhpd_opp_turbo: opp10 {
3568 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3571 rpmhpd_opp_turbo_l1: opp11 {
3572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3577 apps_bcm_voter: bcm-voter {
3578 compatible = "qcom,bcm-voter";
3582 osm_l3: interconnect@18321000 {
3583 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3";
3584 reg = <0 0x18321000 0 0x1400>;
3586 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3587 clock-names = "xo", "alternate";
3589 #interconnect-cells = <1>;
3592 cpufreq_hw: cpufreq@18323000 {
3593 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
3594 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3595 reg-names = "freq-domain0", "freq-domain1";
3597 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3598 clock-names = "xo", "alternate";
3600 #freq-domain-cells = <1>;
3604 wifi: wifi@18800000 {
3605 compatible = "qcom,wcn3990-wifi";
3606 reg = <0 0x18800000 0 0x800000>;
3607 reg-names = "membase";
3608 iommus = <&apps_smmu 0xc0 0x1>;
3610 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3611 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3612 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3613 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3614 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3615 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3616 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3617 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3618 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3619 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3620 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3621 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3622 memory-region = <&wlan_mem>;
3623 qcom,msa-fixed-perm;
3624 status = "disabled";
3627 lpasscc: clock-controller@62d00000 {
3628 compatible = "qcom,sc7180-lpasscorecc";
3629 reg = <0 0x62d00000 0 0x50000>,
3630 <0 0x62780000 0 0x30000>;
3631 reg-names = "lpass_core_cc", "lpass_audio_cc";
3632 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3633 <&rpmhcc RPMH_CXO_CLK>;
3634 clock-names = "iface", "bi_tcxo";
3635 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3637 #power-domain-cells = <1>;
3639 status = "reserved"; /* Controlled by ADSP */
3642 lpass_cpu: lpass@62d87000 {
3643 compatible = "qcom,sc7180-lpass-cpu";
3645 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3646 reg-names = "lpass-hdmiif", "lpass-lpaif";
3648 iommus = <&apps_smmu 0x1020 0>,
3649 <&apps_smmu 0x1021 0>,
3650 <&apps_smmu 0x1032 0>;
3652 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3653 required-opps = <&rpmhpd_opp_nom>;
3655 status = "disabled";
3657 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3658 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3659 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3660 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3661 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3662 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3664 clock-names = "pcnoc-sway-clk", "audio-core",
3665 "mclk0", "pcnoc-mport-clk",
3666 "mi2s-bit-clk0", "mi2s-bit-clk1";
3669 #sound-dai-cells = <1>;
3670 #address-cells = <1>;
3673 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3675 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3678 lpass_hm: clock-controller@63000000 {
3679 compatible = "qcom,sc7180-lpasshm";
3680 reg = <0 0x63000000 0 0x28>;
3681 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3682 <&rpmhcc RPMH_CXO_CLK>;
3683 clock-names = "iface", "bi_tcxo";
3684 power-domains = <&rpmhpd SC7180_CX>;
3687 #power-domain-cells = <1>;
3689 status = "reserved"; /* Controlled by ADSP */
3694 cpu0_thermal: cpu0-thermal {
3695 polling-delay-passive = <250>;
3696 polling-delay = <0>;
3698 thermal-sensors = <&tsens0 1>;
3699 sustainable-power = <1052>;
3702 cpu0_alert0: trip-point0 {
3703 temperature = <90000>;
3704 hysteresis = <2000>;
3708 cpu0_alert1: trip-point1 {
3709 temperature = <95000>;
3710 hysteresis = <2000>;
3714 cpu0_crit: cpu-crit {
3715 temperature = <110000>;
3716 hysteresis = <1000>;
3723 trip = <&cpu0_alert0>;
3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3725 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3726 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3727 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3728 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3732 trip = <&cpu0_alert1>;
3733 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3734 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3735 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3736 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3737 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3738 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3743 cpu1_thermal: cpu1-thermal {
3744 polling-delay-passive = <250>;
3745 polling-delay = <0>;
3747 thermal-sensors = <&tsens0 2>;
3748 sustainable-power = <1052>;
3751 cpu1_alert0: trip-point0 {
3752 temperature = <90000>;
3753 hysteresis = <2000>;
3757 cpu1_alert1: trip-point1 {
3758 temperature = <95000>;
3759 hysteresis = <2000>;
3763 cpu1_crit: cpu-crit {
3764 temperature = <110000>;
3765 hysteresis = <1000>;
3772 trip = <&cpu1_alert0>;
3773 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3774 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3776 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3781 trip = <&cpu1_alert1>;
3782 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3783 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3784 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3785 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3786 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3787 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3792 cpu2_thermal: cpu2-thermal {
3793 polling-delay-passive = <250>;
3794 polling-delay = <0>;
3796 thermal-sensors = <&tsens0 3>;
3797 sustainable-power = <1052>;
3800 cpu2_alert0: trip-point0 {
3801 temperature = <90000>;
3802 hysteresis = <2000>;
3806 cpu2_alert1: trip-point1 {
3807 temperature = <95000>;
3808 hysteresis = <2000>;
3812 cpu2_crit: cpu-crit {
3813 temperature = <110000>;
3814 hysteresis = <1000>;
3821 trip = <&cpu2_alert0>;
3822 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3823 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3824 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3825 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3826 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3830 trip = <&cpu2_alert1>;
3831 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3832 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3834 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3835 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3836 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3841 cpu3_thermal: cpu3-thermal {
3842 polling-delay-passive = <250>;
3843 polling-delay = <0>;
3845 thermal-sensors = <&tsens0 4>;
3846 sustainable-power = <1052>;
3849 cpu3_alert0: trip-point0 {
3850 temperature = <90000>;
3851 hysteresis = <2000>;
3855 cpu3_alert1: trip-point1 {
3856 temperature = <95000>;
3857 hysteresis = <2000>;
3861 cpu3_crit: cpu-crit {
3862 temperature = <110000>;
3863 hysteresis = <1000>;
3870 trip = <&cpu3_alert0>;
3871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3875 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3876 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3879 trip = <&cpu3_alert1>;
3880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3884 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3890 cpu4_thermal: cpu4-thermal {
3891 polling-delay-passive = <250>;
3892 polling-delay = <0>;
3894 thermal-sensors = <&tsens0 5>;
3895 sustainable-power = <1052>;
3898 cpu4_alert0: trip-point0 {
3899 temperature = <90000>;
3900 hysteresis = <2000>;
3904 cpu4_alert1: trip-point1 {
3905 temperature = <95000>;
3906 hysteresis = <2000>;
3910 cpu4_crit: cpu-crit {
3911 temperature = <110000>;
3912 hysteresis = <1000>;
3919 trip = <&cpu4_alert0>;
3920 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3921 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3922 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3923 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3924 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3928 trip = <&cpu4_alert1>;
3929 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3930 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3931 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3932 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3933 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3934 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3939 cpu5_thermal: cpu5-thermal {
3940 polling-delay-passive = <250>;
3941 polling-delay = <0>;
3943 thermal-sensors = <&tsens0 6>;
3944 sustainable-power = <1052>;
3947 cpu5_alert0: trip-point0 {
3948 temperature = <90000>;
3949 hysteresis = <2000>;
3953 cpu5_alert1: trip-point1 {
3954 temperature = <95000>;
3955 hysteresis = <2000>;
3959 cpu5_crit: cpu-crit {
3960 temperature = <110000>;
3961 hysteresis = <1000>;
3968 trip = <&cpu5_alert0>;
3969 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3970 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3971 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3972 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3973 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3974 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3977 trip = <&cpu5_alert1>;
3978 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3979 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3980 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3981 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3982 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3983 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3988 cpu6_thermal: cpu6-thermal {
3989 polling-delay-passive = <250>;
3990 polling-delay = <0>;
3992 thermal-sensors = <&tsens0 9>;
3993 sustainable-power = <1425>;
3996 cpu6_alert0: trip-point0 {
3997 temperature = <90000>;
3998 hysteresis = <2000>;
4002 cpu6_alert1: trip-point1 {
4003 temperature = <95000>;
4004 hysteresis = <2000>;
4008 cpu6_crit: cpu-crit {
4009 temperature = <110000>;
4010 hysteresis = <1000>;
4017 trip = <&cpu6_alert0>;
4018 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4022 trip = <&cpu6_alert1>;
4023 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4024 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4029 cpu7_thermal: cpu7-thermal {
4030 polling-delay-passive = <250>;
4031 polling-delay = <0>;
4033 thermal-sensors = <&tsens0 10>;
4034 sustainable-power = <1425>;
4037 cpu7_alert0: trip-point0 {
4038 temperature = <90000>;
4039 hysteresis = <2000>;
4043 cpu7_alert1: trip-point1 {
4044 temperature = <95000>;
4045 hysteresis = <2000>;
4049 cpu7_crit: cpu-crit {
4050 temperature = <110000>;
4051 hysteresis = <1000>;
4058 trip = <&cpu7_alert0>;
4059 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4060 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4063 trip = <&cpu7_alert1>;
4064 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4065 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4070 cpu8_thermal: cpu8-thermal {
4071 polling-delay-passive = <250>;
4072 polling-delay = <0>;
4074 thermal-sensors = <&tsens0 11>;
4075 sustainable-power = <1425>;
4078 cpu8_alert0: trip-point0 {
4079 temperature = <90000>;
4080 hysteresis = <2000>;
4084 cpu8_alert1: trip-point1 {
4085 temperature = <95000>;
4086 hysteresis = <2000>;
4090 cpu8_crit: cpu-crit {
4091 temperature = <110000>;
4092 hysteresis = <1000>;
4099 trip = <&cpu8_alert0>;
4100 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4104 trip = <&cpu8_alert1>;
4105 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4106 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4111 cpu9_thermal: cpu9-thermal {
4112 polling-delay-passive = <250>;
4113 polling-delay = <0>;
4115 thermal-sensors = <&tsens0 12>;
4116 sustainable-power = <1425>;
4119 cpu9_alert0: trip-point0 {
4120 temperature = <90000>;
4121 hysteresis = <2000>;
4125 cpu9_alert1: trip-point1 {
4126 temperature = <95000>;
4127 hysteresis = <2000>;
4131 cpu9_crit: cpu-crit {
4132 temperature = <110000>;
4133 hysteresis = <1000>;
4140 trip = <&cpu9_alert0>;
4141 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4142 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4145 trip = <&cpu9_alert1>;
4146 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4153 polling-delay-passive = <250>;
4154 polling-delay = <0>;
4156 thermal-sensors = <&tsens0 0>;
4159 aoss0_alert0: trip-point0 {
4160 temperature = <90000>;
4161 hysteresis = <2000>;
4165 aoss0_crit: aoss0-crit {
4166 temperature = <110000>;
4167 hysteresis = <2000>;
4174 polling-delay-passive = <250>;
4175 polling-delay = <0>;
4177 thermal-sensors = <&tsens0 7>;
4180 cpuss0_alert0: trip-point0 {
4181 temperature = <90000>;
4182 hysteresis = <2000>;
4185 cpuss0_crit: cluster0-crit {
4186 temperature = <110000>;
4187 hysteresis = <2000>;
4194 polling-delay-passive = <250>;
4195 polling-delay = <0>;
4197 thermal-sensors = <&tsens0 8>;
4200 cpuss1_alert0: trip-point0 {
4201 temperature = <90000>;
4202 hysteresis = <2000>;
4205 cpuss1_crit: cluster0-crit {
4206 temperature = <110000>;
4207 hysteresis = <2000>;
4214 polling-delay-passive = <250>;
4215 polling-delay = <0>;
4217 thermal-sensors = <&tsens0 13>;
4220 gpuss0_alert0: trip-point0 {
4221 temperature = <95000>;
4222 hysteresis = <2000>;
4226 gpuss0_crit: gpuss0-crit {
4227 temperature = <110000>;
4228 hysteresis = <2000>;
4235 trip = <&gpuss0_alert0>;
4236 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4242 polling-delay-passive = <250>;
4243 polling-delay = <0>;
4245 thermal-sensors = <&tsens0 14>;
4248 gpuss1_alert0: trip-point0 {
4249 temperature = <95000>;
4250 hysteresis = <2000>;
4254 gpuss1_crit: gpuss1-crit {
4255 temperature = <110000>;
4256 hysteresis = <2000>;
4263 trip = <&gpuss1_alert0>;
4264 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4270 polling-delay-passive = <250>;
4271 polling-delay = <0>;
4273 thermal-sensors = <&tsens1 0>;
4276 aoss1_alert0: trip-point0 {
4277 temperature = <90000>;
4278 hysteresis = <2000>;
4282 aoss1_crit: aoss1-crit {
4283 temperature = <110000>;
4284 hysteresis = <2000>;
4291 polling-delay-passive = <250>;
4292 polling-delay = <0>;
4294 thermal-sensors = <&tsens1 1>;
4297 cwlan_alert0: trip-point0 {
4298 temperature = <90000>;
4299 hysteresis = <2000>;
4303 cwlan_crit: cwlan-crit {
4304 temperature = <110000>;
4305 hysteresis = <2000>;
4312 polling-delay-passive = <250>;
4313 polling-delay = <0>;
4315 thermal-sensors = <&tsens1 2>;
4318 audio_alert0: trip-point0 {
4319 temperature = <90000>;
4320 hysteresis = <2000>;
4324 audio_crit: audio-crit {
4325 temperature = <110000>;
4326 hysteresis = <2000>;
4333 polling-delay-passive = <250>;
4334 polling-delay = <0>;
4336 thermal-sensors = <&tsens1 3>;
4339 ddr_alert0: trip-point0 {
4340 temperature = <90000>;
4341 hysteresis = <2000>;
4345 ddr_crit: ddr-crit {
4346 temperature = <110000>;
4347 hysteresis = <2000>;
4354 polling-delay-passive = <250>;
4355 polling-delay = <0>;
4357 thermal-sensors = <&tsens1 4>;
4360 q6_hvx_alert0: trip-point0 {
4361 temperature = <90000>;
4362 hysteresis = <2000>;
4366 q6_hvx_crit: q6-hvx-crit {
4367 temperature = <110000>;
4368 hysteresis = <2000>;
4375 polling-delay-passive = <250>;
4376 polling-delay = <0>;
4378 thermal-sensors = <&tsens1 5>;
4381 camera_alert0: trip-point0 {
4382 temperature = <90000>;
4383 hysteresis = <2000>;
4387 camera_crit: camera-crit {
4388 temperature = <110000>;
4389 hysteresis = <2000>;
4396 polling-delay-passive = <250>;
4397 polling-delay = <0>;
4399 thermal-sensors = <&tsens1 6>;
4402 mdm_alert0: trip-point0 {
4403 temperature = <90000>;
4404 hysteresis = <2000>;
4408 mdm_crit: mdm-crit {
4409 temperature = <110000>;
4410 hysteresis = <2000>;
4417 polling-delay-passive = <250>;
4418 polling-delay = <0>;
4420 thermal-sensors = <&tsens1 7>;
4423 mdm_dsp_alert0: trip-point0 {
4424 temperature = <90000>;
4425 hysteresis = <2000>;
4429 mdm_dsp_crit: mdm-dsp-crit {
4430 temperature = <110000>;
4431 hysteresis = <2000>;
4438 polling-delay-passive = <250>;
4439 polling-delay = <0>;
4441 thermal-sensors = <&tsens1 8>;
4444 npu_alert0: trip-point0 {
4445 temperature = <90000>;
4446 hysteresis = <2000>;
4450 npu_crit: npu-crit {
4451 temperature = <110000>;
4452 hysteresis = <2000>;
4459 polling-delay-passive = <250>;
4460 polling-delay = <0>;
4462 thermal-sensors = <&tsens1 9>;
4465 video_alert0: trip-point0 {
4466 temperature = <90000>;
4467 hysteresis = <2000>;
4471 video_crit: video-crit {
4472 temperature = <110000>;
4473 hysteresis = <2000>;
4481 compatible = "arm,armv8-timer";
4482 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4483 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4484 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4485 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;