1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2023, Linaro Limited
6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 interrupt-parent = <&intc>;
23 xo_board_clk: xo-board-clk {
24 compatible = "fixed-clock";
28 sleep_clk: sleep-clk {
29 compatible = "fixed-clock";
40 compatible = "qcom,kryo";
42 enable-method = "psci";
43 qcom,freq-domain = <&cpufreq_hw 0>;
44 next-level-cache = <&L2_0>;
49 next-level-cache = <&L3_0>;
60 compatible = "qcom,kryo";
62 enable-method = "psci";
63 qcom,freq-domain = <&cpufreq_hw 0>;
64 next-level-cache = <&L2_1>;
69 next-level-cache = <&L3_0>;
75 compatible = "qcom,kryo";
77 enable-method = "psci";
78 qcom,freq-domain = <&cpufreq_hw 0>;
79 next-level-cache = <&L2_2>;
84 next-level-cache = <&L3_0>;
90 compatible = "qcom,kryo";
92 enable-method = "psci";
93 qcom,freq-domain = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_3>;
99 next-level-cache = <&L3_0>;
105 compatible = "qcom,kryo";
107 enable-method = "psci";
108 qcom,freq-domain = <&cpufreq_hw 1>;
109 next-level-cache = <&L2_4>;
111 compatible = "cache";
114 next-level-cache = <&L3_1>;
116 compatible = "cache";
126 compatible = "qcom,kryo";
128 enable-method = "psci";
129 qcom,freq-domain = <&cpufreq_hw 1>;
130 next-level-cache = <&L2_5>;
132 compatible = "cache";
135 next-level-cache = <&L3_1>;
141 compatible = "qcom,kryo";
143 enable-method = "psci";
144 qcom,freq-domain = <&cpufreq_hw 1>;
145 next-level-cache = <&L2_6>;
147 compatible = "cache";
150 next-level-cache = <&L3_1>;
156 compatible = "qcom,kryo";
158 enable-method = "psci";
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 next-level-cache = <&L2_7>;
162 compatible = "cache";
165 next-level-cache = <&L3_1>;
210 compatible = "qcom,scm-sa8775p", "qcom,scm";
214 aggre1_noc: interconnect-aggre1-noc {
215 compatible = "qcom,sa8775p-aggre1-noc";
216 #interconnect-cells = <2>;
217 qcom,bcm-voters = <&apps_bcm_voter>;
220 aggre2_noc: interconnect-aggre2-noc {
221 compatible = "qcom,sa8775p-aggre2-noc";
222 #interconnect-cells = <2>;
223 qcom,bcm-voters = <&apps_bcm_voter>;
226 clk_virt: interconnect-clk-virt {
227 compatible = "qcom,sa8775p-clk-virt";
228 #interconnect-cells = <2>;
229 qcom,bcm-voters = <&apps_bcm_voter>;
232 config_noc: interconnect-config-noc {
233 compatible = "qcom,sa8775p-config-noc";
234 #interconnect-cells = <2>;
235 qcom,bcm-voters = <&apps_bcm_voter>;
238 dc_noc: interconnect-dc-noc {
239 compatible = "qcom,sa8775p-dc-noc";
240 #interconnect-cells = <2>;
241 qcom,bcm-voters = <&apps_bcm_voter>;
244 gem_noc: interconnect-gem-noc {
245 compatible = "qcom,sa8775p-gem-noc";
246 #interconnect-cells = <2>;
247 qcom,bcm-voters = <&apps_bcm_voter>;
250 gpdsp_anoc: interconnect-gpdsp-anoc {
251 compatible = "qcom,sa8775p-gpdsp-anoc";
252 #interconnect-cells = <2>;
253 qcom,bcm-voters = <&apps_bcm_voter>;
256 lpass_ag_noc: interconnect-lpass-ag-noc {
257 compatible = "qcom,sa8775p-lpass-ag-noc";
258 #interconnect-cells = <2>;
259 qcom,bcm-voters = <&apps_bcm_voter>;
262 mc_virt: interconnect-mc-virt {
263 compatible = "qcom,sa8775p-mc-virt";
264 #interconnect-cells = <2>;
265 qcom,bcm-voters = <&apps_bcm_voter>;
268 mmss_noc: interconnect-mmss-noc {
269 compatible = "qcom,sa8775p-mmss-noc";
270 #interconnect-cells = <2>;
271 qcom,bcm-voters = <&apps_bcm_voter>;
274 nspa_noc: interconnect-nspa-noc {
275 compatible = "qcom,sa8775p-nspa-noc";
276 #interconnect-cells = <2>;
277 qcom,bcm-voters = <&apps_bcm_voter>;
280 nspb_noc: interconnect-nspb-noc {
281 compatible = "qcom,sa8775p-nspb-noc";
282 #interconnect-cells = <2>;
283 qcom,bcm-voters = <&apps_bcm_voter>;
286 pcie_anoc: interconnect-pcie-anoc {
287 compatible = "qcom,sa8775p-pcie-anoc";
288 #interconnect-cells = <2>;
289 qcom,bcm-voters = <&apps_bcm_voter>;
292 system_noc: interconnect-system-noc {
293 compatible = "qcom,sa8775p-system-noc";
294 #interconnect-cells = <2>;
295 qcom,bcm-voters = <&apps_bcm_voter>;
298 /* Will be updated by the bootloader. */
300 device_type = "memory";
301 reg = <0x0 0x80000000 0x0 0x0>;
304 qup_opp_table_100mhz: opp-table-qup100mhz {
305 compatible = "operating-points-v2";
308 opp-hz = /bits/ 64 <100000000>;
309 required-opps = <&rpmhpd_opp_svs_l1>;
314 compatible = "arm,armv8-pmuv3";
315 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
319 compatible = "arm,psci-1.0";
324 #address-cells = <2>;
328 sail_ss_mem: sail-ss@80000000 {
329 reg = <0x0 0x80000000 0x0 0x10000000>;
333 hyp_mem: hyp@90000000 {
334 reg = <0x0 0x90000000 0x0 0x600000>;
338 xbl_boot_mem: xbl-boot@90600000 {
339 reg = <0x0 0x90600000 0x0 0x200000>;
343 aop_image_mem: aop-image@90800000 {
344 reg = <0x0 0x90800000 0x0 0x60000>;
348 aop_cmd_db_mem: aop-cmd-db@90860000 {
349 compatible = "qcom,cmd-db";
350 reg = <0x0 0x90860000 0x0 0x20000>;
354 uefi_log: uefi-log@908b0000 {
355 reg = <0x0 0x908b0000 0x0 0x10000>;
359 reserved_mem: reserved@908f0000 {
360 reg = <0x0 0x908f0000 0x0 0xf000>;
364 secdata_apss_mem: secdata-apss@908ff000 {
365 reg = <0x0 0x908ff000 0x0 0x1000>;
369 smem_mem: smem@90900000 {
370 compatible = "qcom,smem";
371 reg = <0x0 0x90900000 0x0 0x200000>;
373 hwlocks = <&tcsr_mutex 3>;
376 cpucp_fw_mem: cpucp-fw@90b00000 {
377 reg = <0x0 0x90b00000 0x0 0x100000>;
381 lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
382 reg = <0x0 0x93b00000 0x0 0xf00000>;
386 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
387 reg = <0x0 0x94a00000 0x0 0x800000>;
391 pil_camera_mem: pil-camera@95200000 {
392 reg = <0x0 0x95200000 0x0 0x500000>;
396 pil_adsp_mem: pil-adsp@95c00000 {
397 reg = <0x0 0x95c00000 0x0 0x1e00000>;
401 pil_gdsp0_mem: pil-gdsp0@97b00000 {
402 reg = <0x0 0x97b00000 0x0 0x1e00000>;
406 pil_gdsp1_mem: pil-gdsp1@99900000 {
407 reg = <0x0 0x99900000 0x0 0x1e00000>;
411 pil_cdsp0_mem: pil-cdsp0@9b800000 {
412 reg = <0x0 0x9b800000 0x0 0x1e00000>;
416 pil_gpu_mem: pil-gpu@9d600000 {
417 reg = <0x0 0x9d600000 0x0 0x2000>;
421 pil_cdsp1_mem: pil-cdsp1@9d700000 {
422 reg = <0x0 0x9d700000 0x0 0x1e00000>;
426 pil_cvp_mem: pil-cvp@9f500000 {
427 reg = <0x0 0x9f500000 0x0 0x700000>;
431 pil_video_mem: pil-video@9fc00000 {
432 reg = <0x0 0x9fc00000 0x0 0x700000>;
436 hyptz_reserved_mem: hyptz-reserved@beb00000 {
437 reg = <0x0 0xbeb00000 0x0 0x11500000>;
441 tz_stat_mem: tz-stat@d0000000 {
442 reg = <0x0 0xd0000000 0x0 0x100000>;
446 tags_mem: tags@d0100000 {
447 reg = <0x0 0xd0100000 0x0 0x1200000>;
451 qtee_mem: qtee@d1300000 {
452 reg = <0x0 0xd1300000 0x0 0x500000>;
456 trusted_apps_mem: trusted-apps@d1800000 {
457 reg = <0x0 0xd1800000 0x0 0x3900000>;
463 compatible = "simple-bus";
464 #address-cells = <2>;
466 ranges = <0 0 0 0 0x10 0>;
468 gcc: clock-controller@100000 {
469 compatible = "qcom,sa8775p-gcc";
470 reg = <0x0 0x00100000 0x0 0xc7018>;
473 #power-domain-cells = <1>;
474 clocks = <&rpmhcc RPMH_CXO_CLK>,
489 power-domains = <&rpmhpd SA8775P_CX>;
492 ipcc: mailbox@408000 {
493 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
494 reg = <0x0 0x00408000 0x0 0x1000>;
495 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-controller;
497 #interrupt-cells = <3>;
501 qupv3_id_2: geniqup@8c0000 {
502 compatible = "qcom,geni-se-qup";
503 reg = <0x0 0x008c0000 0x0 0x6000>;
505 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
506 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
507 clock-names = "m-ahb", "s-ahb";
508 iommus = <&apps_smmu 0x5a3 0x0>;
509 #address-cells = <2>;
514 compatible = "qcom,geni-i2c";
515 reg = <0x0 0x880000 0x0 0x4000>;
516 #address-cells = <1>;
518 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
521 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
522 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
523 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
524 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
525 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
527 interconnect-names = "qup-core",
530 power-domains = <&rpmhpd SA8775P_CX>;
535 compatible = "qcom,geni-spi";
536 reg = <0x0 0x880000 0x0 0x4000>;
537 #address-cells = <1>;
539 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
542 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
543 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
544 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
545 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
546 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
547 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
548 interconnect-names = "qup-core",
551 power-domains = <&rpmhpd SA8775P_CX>;
556 compatible = "qcom,geni-i2c";
557 reg = <0x0 0x884000 0x0 0x4000>;
558 #address-cells = <1>;
560 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
563 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
564 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
565 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
566 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
567 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
568 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
569 interconnect-names = "qup-core",
572 power-domains = <&rpmhpd SA8775P_CX>;
577 compatible = "qcom,geni-spi";
578 reg = <0x0 0x884000 0x0 0x4000>;
579 #address-cells = <1>;
581 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
584 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
585 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
587 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
588 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
590 interconnect-names = "qup-core",
593 power-domains = <&rpmhpd SA8775P_CX>;
598 compatible = "qcom,geni-i2c";
599 reg = <0x0 0x888000 0x0 0x4000>;
600 #address-cells = <1>;
602 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
605 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
606 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
607 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
608 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
609 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
610 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
611 interconnect-names = "qup-core",
614 power-domains = <&rpmhpd SA8775P_CX>;
619 compatible = "qcom,geni-spi";
620 reg = <0x0 0x00888000 0x0 0x4000>;
621 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
624 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
625 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
626 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
627 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
628 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
630 interconnect-names = "qup-core",
633 power-domains = <&rpmhpd SA8775P_CX>;
634 #address-cells = <1>;
640 compatible = "qcom,geni-i2c";
641 reg = <0x0 0x88c000 0x0 0x4000>;
642 #address-cells = <1>;
644 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
651 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
653 interconnect-names = "qup-core",
656 power-domains = <&rpmhpd SA8775P_CX>;
661 compatible = "qcom,geni-spi";
662 reg = <0x0 0x88c000 0x0 0x4000>;
663 #address-cells = <1>;
665 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
668 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
669 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
671 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
672 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
674 interconnect-names = "qup-core",
677 power-domains = <&rpmhpd SA8775P_CX>;
681 uart17: serial@88c000 {
682 compatible = "qcom,geni-uart";
683 reg = <0x0 0x0088c000 0x0 0x4000>;
684 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
687 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
688 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
689 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
690 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
691 interconnect-names = "qup-core", "qup-config";
692 power-domains = <&rpmhpd SA8775P_CX>;
697 compatible = "qcom,geni-i2c";
698 reg = <0x0 0x00890000 0x0 0x4000>;
699 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
702 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
703 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
704 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
705 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
706 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
707 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
708 interconnect-names = "qup-core",
711 power-domains = <&rpmhpd SA8775P_CX>;
712 #address-cells = <1>;
718 compatible = "qcom,geni-spi";
719 reg = <0x0 0x890000 0x0 0x4000>;
720 #address-cells = <1>;
722 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
725 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
726 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
728 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
729 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
731 interconnect-names = "qup-core",
734 power-domains = <&rpmhpd SA8775P_CX>;
739 compatible = "qcom,geni-i2c";
740 reg = <0x0 0x894000 0x0 0x4000>;
741 #address-cells = <1>;
743 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
746 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
747 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
748 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
749 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
750 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
752 interconnect-names = "qup-core",
755 power-domains = <&rpmhpd SA8775P_CX>;
760 compatible = "qcom,geni-spi";
761 reg = <0x0 0x894000 0x0 0x4000>;
762 #address-cells = <1>;
764 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
767 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
768 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
769 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
770 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
771 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
772 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
773 interconnect-names = "qup-core",
776 power-domains = <&rpmhpd SA8775P_CX>;
781 compatible = "qcom,geni-i2c";
782 reg = <0x0 0x898000 0x0 0x4000>;
783 #address-cells = <1>;
785 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
788 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
789 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
790 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
791 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
792 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
793 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
794 interconnect-names = "qup-core",
797 power-domains = <&rpmhpd SA8775P_CX>;
802 compatible = "qcom,geni-spi";
803 reg = <0x0 0x898000 0x0 0x4000>;
804 #address-cells = <1>;
806 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
809 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
810 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
811 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
812 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
813 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
814 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
815 interconnect-names = "qup-core",
818 power-domains = <&rpmhpd SA8775P_CX>;
823 qupv3_id_0: geniqup@9c0000 {
824 compatible = "qcom,geni-se-qup";
825 reg = <0x0 0x9c0000 0x0 0x6000>;
826 #address-cells = <2>;
829 clock-names = "m-ahb", "s-ahb";
830 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
831 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
832 iommus = <&apps_smmu 0x403 0x0>;
836 compatible = "qcom,geni-i2c";
837 reg = <0x0 0x980000 0x0 0x4000>;
838 #address-cells = <1>;
840 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
843 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
844 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
845 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
846 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
847 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
849 interconnect-names = "qup-core",
852 power-domains = <&rpmhpd SA8775P_CX>;
857 compatible = "qcom,geni-spi";
858 reg = <0x0 0x980000 0x0 0x4000>;
859 #address-cells = <1>;
861 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
864 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
865 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
867 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
868 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
870 interconnect-names = "qup-core",
873 power-domains = <&rpmhpd SA8775P_CX>;
878 compatible = "qcom,geni-i2c";
879 reg = <0x0 0x984000 0x0 0x4000>;
880 #address-cells = <1>;
882 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
885 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
886 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
888 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
889 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
890 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
891 interconnect-names = "qup-core",
894 power-domains = <&rpmhpd SA8775P_CX>;
899 compatible = "qcom,geni-spi";
900 reg = <0x0 0x984000 0x0 0x4000>;
901 #address-cells = <1>;
903 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
906 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
907 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
909 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
910 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
912 interconnect-names = "qup-core",
915 power-domains = <&rpmhpd SA8775P_CX>;
920 compatible = "qcom,geni-i2c";
921 reg = <0x0 0x988000 0x0 0x4000>;
922 #address-cells = <1>;
924 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
927 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
928 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
930 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
931 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
932 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
933 interconnect-names = "qup-core",
936 power-domains = <&rpmhpd SA8775P_CX>;
941 compatible = "qcom,geni-spi";
942 reg = <0x0 0x988000 0x0 0x4000>;
943 #address-cells = <1>;
945 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
954 interconnect-names = "qup-core",
957 power-domains = <&rpmhpd SA8775P_CX>;
962 compatible = "qcom,geni-i2c";
963 reg = <0x0 0x98c000 0x0 0x4000>;
964 #address-cells = <1>;
966 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
973 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
975 interconnect-names = "qup-core",
978 power-domains = <&rpmhpd SA8775P_CX>;
983 compatible = "qcom,geni-spi";
984 reg = <0x0 0x98c000 0x0 0x4000>;
985 #address-cells = <1>;
987 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
996 interconnect-names = "qup-core",
999 power-domains = <&rpmhpd SA8775P_CX>;
1000 status = "disabled";
1004 compatible = "qcom,geni-i2c";
1005 reg = <0x0 0x990000 0x0 0x4000>;
1006 #address-cells = <1>;
1008 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1012 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1014 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1015 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1017 interconnect-names = "qup-core",
1020 power-domains = <&rpmhpd SA8775P_CX>;
1021 status = "disabled";
1025 compatible = "qcom,geni-spi";
1026 reg = <0x0 0x990000 0x0 0x4000>;
1027 #address-cells = <1>;
1029 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1033 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1035 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1036 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1038 interconnect-names = "qup-core",
1041 power-domains = <&rpmhpd SA8775P_CX>;
1042 status = "disabled";
1046 compatible = "qcom,geni-i2c";
1047 reg = <0x0 0x994000 0x0 0x4000>;
1048 #address-cells = <1>;
1050 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1054 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1056 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1057 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1059 interconnect-names = "qup-core",
1062 power-domains = <&rpmhpd SA8775P_CX>;
1063 status = "disabled";
1067 compatible = "qcom,geni-spi";
1068 reg = <0x0 0x994000 0x0 0x4000>;
1069 #address-cells = <1>;
1071 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1074 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1075 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1077 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
1078 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
1079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1080 interconnect-names = "qup-core",
1083 power-domains = <&rpmhpd SA8775P_CX>;
1084 status = "disabled";
1087 uart5: serial@994000 {
1088 compatible = "qcom,geni-uart";
1089 reg = <0x0 0x994000 0x0 0x4000>;
1090 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1093 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
1094 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
1095 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1096 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
1097 interconnect-names = "qup-core", "qup-config";
1098 power-domains = <&rpmhpd SA8775P_CX>;
1099 status = "disabled";
1103 qupv3_id_1: geniqup@ac0000 {
1104 compatible = "qcom,geni-se-qup";
1105 reg = <0x0 0x00ac0000 0x0 0x6000>;
1106 #address-cells = <2>;
1109 clock-names = "m-ahb", "s-ahb";
1110 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1111 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1112 iommus = <&apps_smmu 0x443 0x0>;
1113 status = "disabled";
1116 compatible = "qcom,geni-i2c";
1117 reg = <0x0 0xa80000 0x0 0x4000>;
1118 #address-cells = <1>;
1120 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1123 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1124 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1125 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1126 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1127 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1129 interconnect-names = "qup-core",
1132 power-domains = <&rpmhpd SA8775P_CX>;
1133 status = "disabled";
1137 compatible = "qcom,geni-spi";
1138 reg = <0x0 0xa80000 0x0 0x4000>;
1139 #address-cells = <1>;
1141 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1148 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1150 interconnect-names = "qup-core",
1153 power-domains = <&rpmhpd SA8775P_CX>;
1154 status = "disabled";
1158 compatible = "qcom,geni-i2c";
1159 reg = <0x0 0xa84000 0x0 0x4000>;
1160 #address-cells = <1>;
1162 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1163 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1165 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1166 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1168 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1169 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1171 interconnect-names = "qup-core",
1174 power-domains = <&rpmhpd SA8775P_CX>;
1175 status = "disabled";
1179 compatible = "qcom,geni-spi";
1180 reg = <0x0 0xa84000 0x0 0x4000>;
1181 #address-cells = <1>;
1183 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1186 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1187 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1189 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1190 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1192 interconnect-names = "qup-core",
1195 power-domains = <&rpmhpd SA8775P_CX>;
1196 status = "disabled";
1200 compatible = "qcom,geni-i2c";
1201 reg = <0x0 0xa88000 0x0 0x4000>;
1202 #address-cells = <1>;
1204 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1207 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1208 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1209 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1210 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1211 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1213 interconnect-names = "qup-core",
1216 power-domains = <&rpmhpd SA8775P_CX>;
1217 status = "disabled";
1221 compatible = "qcom,geni-spi";
1222 reg = <0x0 0xa88000 0x0 0x4000>;
1223 #address-cells = <1>;
1225 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1228 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1229 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1231 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1232 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1233 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1234 interconnect-names = "qup-core",
1237 power-domains = <&rpmhpd SA8775P_CX>;
1238 status = "disabled";
1241 uart9: serial@a88000 {
1242 compatible = "qcom,geni-uart";
1243 reg = <0x0 0xa88000 0x0 0x4000>;
1244 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1247 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1248 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1250 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1251 interconnect-names = "qup-core", "qup-config";
1252 power-domains = <&rpmhpd SA8775P_CX>;
1253 status = "disabled";
1257 compatible = "qcom,geni-i2c";
1258 reg = <0x0 0xa8c000 0x0 0x4000>;
1259 #address-cells = <1>;
1261 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1264 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1265 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1267 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1268 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1269 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1270 interconnect-names = "qup-core",
1273 power-domains = <&rpmhpd SA8775P_CX>;
1274 status = "disabled";
1278 compatible = "qcom,geni-spi";
1279 reg = <0x0 0xa8c000 0x0 0x4000>;
1280 #address-cells = <1>;
1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1285 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1286 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1287 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1288 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1289 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1290 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1291 interconnect-names = "qup-core",
1294 power-domains = <&rpmhpd SA8775P_CX>;
1295 status = "disabled";
1298 uart10: serial@a8c000 {
1299 compatible = "qcom,geni-uart";
1300 reg = <0x0 0x00a8c000 0x0 0x4000>;
1301 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1303 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1304 interconnect-names = "qup-core", "qup-config";
1305 interconnects = <&clk_virt MASTER_QUP_CORE_1 0
1306 &clk_virt SLAVE_QUP_CORE_1 0>,
1307 <&gem_noc MASTER_APPSS_PROC 0
1308 &config_noc SLAVE_QUP_1 0>;
1309 power-domains = <&rpmhpd SA8775P_CX>;
1310 operating-points-v2 = <&qup_opp_table_100mhz>;
1311 status = "disabled";
1315 compatible = "qcom,geni-i2c";
1316 reg = <0x0 0xa90000 0x0 0x4000>;
1317 #address-cells = <1>;
1319 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1320 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1322 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1323 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1324 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1325 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1326 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1328 interconnect-names = "qup-core",
1331 power-domains = <&rpmhpd SA8775P_CX>;
1332 status = "disabled";
1336 compatible = "qcom,geni-spi";
1337 reg = <0x0 0xa90000 0x0 0x4000>;
1338 #address-cells = <1>;
1340 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1343 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1344 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1345 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1346 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1347 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1348 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1349 interconnect-names = "qup-core",
1352 power-domains = <&rpmhpd SA8775P_CX>;
1353 status = "disabled";
1357 compatible = "qcom,geni-i2c";
1358 reg = <0x0 0xa94000 0x0 0x4000>;
1359 #address-cells = <1>;
1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1364 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1365 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1366 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1367 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1368 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1369 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1370 interconnect-names = "qup-core",
1373 power-domains = <&rpmhpd SA8775P_CX>;
1374 status = "disabled";
1378 compatible = "qcom,geni-spi";
1379 reg = <0x0 0xa94000 0x0 0x4000>;
1380 #address-cells = <1>;
1382 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1385 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1386 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1388 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1389 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1391 interconnect-names = "qup-core",
1394 power-domains = <&rpmhpd SA8775P_CX>;
1395 status = "disabled";
1398 uart12: serial@a94000 {
1399 compatible = "qcom,geni-uart";
1400 reg = <0x0 0x00a94000 0x0 0x4000>;
1401 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1404 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1405 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1407 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
1408 interconnect-names = "qup-core", "qup-config";
1409 power-domains = <&rpmhpd SA8775P_CX>;
1410 status = "disabled";
1414 compatible = "qcom,geni-i2c";
1415 reg = <0x0 0xa98000 0x0 0x4000>;
1416 #address-cells = <1>;
1418 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1421 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1422 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1423 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1424 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
1425 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1426 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1427 interconnect-names = "qup-core",
1430 power-domains = <&rpmhpd SA8775P_CX>;
1431 status = "disabled";
1435 qupv3_id_3: geniqup@bc0000 {
1436 compatible = "qcom,geni-se-qup";
1437 reg = <0x0 0xbc0000 0x0 0x6000>;
1438 #address-cells = <2>;
1441 clock-names = "m-ahb", "s-ahb";
1442 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1443 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1444 iommus = <&apps_smmu 0x43 0x0>;
1445 status = "disabled";
1448 compatible = "qcom,geni-i2c";
1449 reg = <0x0 0xb80000 0x0 0x4000>;
1450 #address-cells = <1>;
1452 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1455 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1456 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1458 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1459 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1461 interconnect-names = "qup-core",
1464 power-domains = <&rpmhpd SA8775P_CX>;
1465 status = "disabled";
1469 compatible = "qcom,geni-spi";
1470 reg = <0x0 0xb80000 0x0 0x4000>;
1471 #address-cells = <1>;
1473 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1476 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
1477 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1479 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
1480 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1482 interconnect-names = "qup-core",
1485 power-domains = <&rpmhpd SA8775P_CX>;
1486 status = "disabled";
1490 ufs_mem_hc: ufs@1d84000 {
1491 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1492 reg = <0x0 0x01d84000 0x0 0x3000>;
1493 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1494 phys = <&ufs_mem_phy>;
1495 phy-names = "ufsphy";
1496 lanes-per-direction = <2>;
1498 resets = <&gcc GCC_UFS_PHY_BCR>;
1499 reset-names = "rst";
1500 power-domains = <&gcc UFS_PHY_GDSC>;
1501 required-opps = <&rpmhpd_opp_nom>;
1502 iommus = <&apps_smmu 0x100 0x0>;
1504 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1505 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1506 <&gcc GCC_UFS_PHY_AHB_CLK>,
1507 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1508 <&rpmhcc RPMH_CXO_CLK>,
1509 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1510 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1511 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1512 clock-names = "core_clk",
1517 "tx_lane0_sync_clk",
1518 "rx_lane0_sync_clk",
1519 "rx_lane1_sync_clk";
1520 freq-table-hz = <75000000 300000000>,
1523 <75000000 300000000>,
1528 status = "disabled";
1531 ufs_mem_phy: phy@1d87000 {
1532 compatible = "qcom,sa8775p-qmp-ufs-phy";
1533 reg = <0x0 0x01d87000 0x0 0xe10>;
1535 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
1536 * enables the CXO clock to eDP *and* UFS PHY.
1538 clocks = <&rpmhcc RPMH_CXO_CLK>,
1539 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1540 <&gcc GCC_EDP_REF_CLKREF_EN>;
1541 clock-names = "ref", "ref_aux", "qref";
1542 power-domains = <&gcc UFS_PHY_GDSC>;
1543 resets = <&ufs_mem_hc 0>;
1544 reset-names = "ufsphy";
1546 status = "disabled";
1549 usb_0_hsphy: phy@88e4000 {
1550 compatible = "qcom,sa8775p-usb-hs-phy",
1551 "qcom,usb-snps-hs-5nm-phy";
1552 reg = <0 0x088e4000 0 0x120>;
1553 clocks = <&rpmhcc RPMH_CXO_CLK>;
1554 clock-names = "ref";
1555 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
1559 status = "disabled";
1562 usb_0_qmpphy: phy@88e8000 {
1563 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1564 reg = <0 0x088e8000 0 0x2000>;
1566 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1567 <&gcc GCC_USB_CLKREF_EN>,
1568 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1569 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1570 clock-names = "aux", "ref", "com_aux", "pipe";
1572 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1573 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
1574 reset-names = "phy", "phy_phy";
1576 power-domains = <&gcc USB30_PRIM_GDSC>;
1579 clock-output-names = "usb3_prim_phy_pipe_clk_src";
1583 status = "disabled";
1586 usb_0: usb@a6f8800 {
1587 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1588 reg = <0 0x0a6f8800 0 0x400>;
1589 #address-cells = <2>;
1593 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1594 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1595 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1596 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1597 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1598 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1600 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1601 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1602 assigned-clock-rates = <19200000>, <200000000>;
1604 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
1605 <&pdc 14 IRQ_TYPE_EDGE_RISING>,
1606 <&pdc 15 IRQ_TYPE_EDGE_RISING>,
1607 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
1608 interrupt-names = "pwr_event",
1613 power-domains = <&gcc USB30_PRIM_GDSC>;
1614 required-opps = <&rpmhpd_opp_nom>;
1616 resets = <&gcc GCC_USB30_PRIM_BCR>;
1618 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
1619 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
1620 interconnect-names = "usb-ddr", "apps-usb";
1624 status = "disabled";
1626 usb_0_dwc3: usb@a600000 {
1627 compatible = "snps,dwc3";
1628 reg = <0 0x0a600000 0 0xe000>;
1629 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1630 iommus = <&apps_smmu 0x080 0x0>;
1631 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
1632 phy-names = "usb2-phy", "usb3-phy";
1636 usb_1_hsphy: phy@88e6000 {
1637 compatible = "qcom,sa8775p-usb-hs-phy",
1638 "qcom,usb-snps-hs-5nm-phy";
1639 reg = <0 0x088e6000 0 0x120>;
1640 clocks = <&gcc GCC_USB_CLKREF_EN>;
1641 clock-names = "ref";
1642 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
1646 status = "disabled";
1649 usb_1_qmpphy: phy@88ea000 {
1650 compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
1651 reg = <0 0x088ea000 0 0x2000>;
1653 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1654 <&gcc GCC_USB_CLKREF_EN>,
1655 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1656 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1657 clock-names = "aux", "ref", "com_aux", "pipe";
1659 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1660 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
1661 reset-names = "phy", "phy_phy";
1663 power-domains = <&gcc USB30_SEC_GDSC>;
1666 clock-output-names = "usb3_sec_phy_pipe_clk_src";
1670 status = "disabled";
1673 usb_1: usb@a8f8800 {
1674 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1675 reg = <0 0x0a8f8800 0 0x400>;
1676 #address-cells = <2>;
1680 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1681 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1682 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1683 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1684 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
1685 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1687 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1688 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1689 assigned-clock-rates = <19200000>, <200000000>;
1691 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
1692 <&pdc 8 IRQ_TYPE_EDGE_RISING>,
1693 <&pdc 7 IRQ_TYPE_EDGE_RISING>,
1694 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
1695 interrupt-names = "pwr_event",
1700 power-domains = <&gcc USB30_SEC_GDSC>;
1701 required-opps = <&rpmhpd_opp_nom>;
1703 resets = <&gcc GCC_USB30_SEC_BCR>;
1705 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
1706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
1707 interconnect-names = "usb-ddr", "apps-usb";
1711 status = "disabled";
1713 usb_1_dwc3: usb@a800000 {
1714 compatible = "snps,dwc3";
1715 reg = <0 0x0a800000 0 0xe000>;
1716 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
1717 iommus = <&apps_smmu 0x0a0 0x0>;
1718 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
1719 phy-names = "usb2-phy", "usb3-phy";
1723 usb_2_hsphy: phy@88e7000 {
1724 compatible = "qcom,sa8775p-usb-hs-phy",
1725 "qcom,usb-snps-hs-5nm-phy";
1726 reg = <0 0x088e7000 0 0x120>;
1727 clocks = <&gcc GCC_USB_CLKREF_EN>;
1728 clock-names = "ref";
1729 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
1733 status = "disabled";
1736 usb_2: usb@a4f8800 {
1737 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
1738 reg = <0 0x0a4f8800 0 0x400>;
1739 #address-cells = <2>;
1743 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
1744 <&gcc GCC_USB20_MASTER_CLK>,
1745 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
1746 <&gcc GCC_USB20_SLEEP_CLK>,
1747 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1748 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
1750 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1751 <&gcc GCC_USB20_MASTER_CLK>;
1752 assigned-clock-rates = <19200000>, <200000000>;
1754 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
1755 <&pdc 10 IRQ_TYPE_EDGE_RISING>,
1756 <&pdc 9 IRQ_TYPE_EDGE_RISING>;
1757 interrupt-names = "pwr_event",
1761 power-domains = <&gcc USB20_PRIM_GDSC>;
1762 required-opps = <&rpmhpd_opp_nom>;
1764 resets = <&gcc GCC_USB20_PRIM_BCR>;
1766 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
1767 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
1768 interconnect-names = "usb-ddr", "apps-usb";
1772 status = "disabled";
1774 usb_2_dwc3: usb@a400000 {
1775 compatible = "snps,dwc3";
1776 reg = <0 0x0a400000 0 0xe000>;
1777 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
1778 iommus = <&apps_smmu 0x020 0x0>;
1779 phys = <&usb_2_hsphy>;
1780 phy-names = "usb2-phy";
1784 tcsr_mutex: hwlock@1f40000 {
1785 compatible = "qcom,tcsr-mutex";
1786 reg = <0x0 0x01f40000 0x0 0x20000>;
1787 #hwlock-cells = <1>;
1790 gpucc: clock-controller@3d90000 {
1791 compatible = "qcom,sa8775p-gpucc";
1792 reg = <0x0 0x03d90000 0x0 0xa000>;
1793 clocks = <&rpmhcc RPMH_CXO_CLK>,
1794 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1795 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1796 clock-names = "bi_tcxo",
1797 "gcc_gpu_gpll0_clk_src",
1798 "gcc_gpu_gpll0_div_clk_src";
1801 #power-domain-cells = <1>;
1804 adreno_smmu: iommu@3da0000 {
1805 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
1806 "qcom,smmu-500", "arm,mmu-500";
1807 reg = <0x0 0x03da0000 0x0 0x20000>;
1809 #global-interrupts = <2>;
1811 power-domains = <&gpucc GPU_CC_CX_GDSC>;
1812 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1813 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1814 <&gpucc GPU_CC_AHB_CLK>,
1815 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1816 <&gpucc GPU_CC_CX_GMU_CLK>,
1817 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
1818 <&gpucc GPU_CC_HUB_AON_CLK>;
1819 clock-names = "gcc_gpu_memnoc_gfx_clk",
1820 "gcc_gpu_snoc_dvm_gfx_clk",
1822 "gpu_cc_hlos1_vote_gpu_smmu_clk",
1823 "gpu_cc_cx_gmu_clk",
1824 "gpu_cc_hub_cx_int_clk",
1825 "gpu_cc_hub_aon_clk";
1826 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
1840 pdc: interrupt-controller@b220000 {
1841 compatible = "qcom,sa8775p-pdc", "qcom,pdc";
1842 reg = <0x0 0x0b220000 0x0 0x30000>,
1843 <0x0 0x17c000f0 0x0 0x64>;
1844 qcom,pdc-ranges = <0 480 40>,
1882 #interrupt-cells = <2>;
1883 interrupt-parent = <&intc>;
1884 interrupt-controller;
1887 aoss_qmp: power-management@c300000 {
1888 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
1889 reg = <0x0 0x0c300000 0x0 0x400>;
1890 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
1891 IPCC_MPROC_SIGNAL_GLINK_QMP
1892 IRQ_TYPE_EDGE_RISING>;
1893 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1897 spmi_bus: spmi@c440000 {
1898 compatible = "qcom,spmi-pmic-arb";
1899 reg = <0x0 0x0c440000 0x0 0x1100>,
1900 <0x0 0x0c600000 0x0 0x2000000>,
1901 <0x0 0x0e600000 0x0 0x100000>,
1902 <0x0 0x0e700000 0x0 0xa0000>,
1903 <0x0 0x0c40a000 0x0 0x26000>;
1911 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1912 interrupt-names = "periph_irq";
1913 interrupt-controller;
1914 #interrupt-cells = <4>;
1915 #address-cells = <2>;
1919 tlmm: pinctrl@f000000 {
1920 compatible = "qcom,sa8775p-tlmm";
1921 reg = <0x0 0x0f000000 0x0 0x1000000>;
1922 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1925 interrupt-controller;
1926 #interrupt-cells = <2>;
1927 gpio-ranges = <&tlmm 0 0 149>;
1930 apps_smmu: iommu@15000000 {
1931 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1932 reg = <0x0 0x15000000 0x0 0x100000>;
1934 #global-interrupts = <2>;
1936 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1973 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1974 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1975 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1977 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1978 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1979 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1980 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1981 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1985 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1986 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1987 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1988 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1989 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1990 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1995 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1998 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1999 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
2006 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
2008 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
2022 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
2023 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
2024 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
2025 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
2026 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
2028 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
2029 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
2031 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
2035 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
2052 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
2053 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
2054 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
2055 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
2056 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
2057 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
2058 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
2059 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
2060 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
2061 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
2064 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
2065 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
2068 pcie_smmu: iommu@15200000 {
2069 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2070 reg = <0x0 0x15200000 0x0 0x80000>;
2072 #global-interrupts = <2>;
2074 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
2075 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
2076 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
2081 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
2099 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2100 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
2101 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
2105 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
2106 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
2107 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
2108 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
2119 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
2127 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
2128 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
2129 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
2130 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
2134 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
2135 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
2136 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
2137 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
2138 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
2139 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
2142 intc: interrupt-controller@17a00000 {
2143 compatible = "arm,gic-v3";
2144 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
2145 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
2146 interrupt-controller;
2147 #interrupt-cells = <3>;
2148 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2149 #redistributor-regions = <1>;
2150 redistributor-stride = <0x0 0x20000>;
2154 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
2155 reg = <0x0 0x17c10000 0x0 0x1000>;
2156 clocks = <&sleep_clk>;
2157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2160 memtimer: timer@17c20000 {
2161 compatible = "arm,armv7-timer-mem";
2162 reg = <0x0 0x17c20000 0x0 0x1000>;
2163 ranges = <0x0 0x0 0x0 0x20000000>;
2164 #address-cells = <1>;
2168 reg = <0x17c21000 0x1000>,
2169 <0x17c22000 0x1000>;
2170 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2171 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2176 reg = <0x17c23000 0x1000>;
2177 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2179 status = "disabled";
2183 reg = <0x17c25000 0x1000>;
2184 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2186 status = "disabled";
2190 reg = <0x17c27000 0x1000>;
2191 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2193 status = "disabled";
2197 reg = <0x17c29000 0x1000>;
2198 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2200 status = "disabled";
2204 reg = <0x17c2b000 0x1000>;
2205 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2207 status = "disabled";
2211 reg = <0x17c2d000 0x1000>;
2212 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2214 status = "disabled";
2218 apps_rsc: rsc@18200000 {
2219 compatible = "qcom,rpmh-rsc";
2220 reg = <0x0 0x18200000 0x0 0x10000>,
2221 <0x0 0x18210000 0x0 0x10000>,
2222 <0x0 0x18220000 0x0 0x10000>;
2223 reg-names = "drv-0", "drv-1", "drv-2";
2224 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2225 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2226 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
2227 qcom,tcs-offset = <0xd00>;
2229 qcom,tcs-config = <ACTIVE_TCS 2>,
2235 apps_bcm_voter: bcm-voter {
2236 compatible = "qcom,bcm-voter";
2239 rpmhcc: clock-controller {
2240 compatible = "qcom,sa8775p-rpmh-clk";
2243 clocks = <&xo_board_clk>;
2246 rpmhpd: power-controller {
2247 compatible = "qcom,sa8775p-rpmhpd";
2248 #power-domain-cells = <1>;
2249 operating-points-v2 = <&rpmhpd_opp_table>;
2251 rpmhpd_opp_table: opp-table {
2252 compatible = "operating-points-v2";
2254 rpmhpd_opp_ret: opp-0 {
2255 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2258 rpmhpd_opp_min_svs: opp-1 {
2259 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2262 rpmhpd_opp_low_svs: opp2 {
2263 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2266 rpmhpd_opp_svs: opp3 {
2267 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2270 rpmhpd_opp_svs_l1: opp-4 {
2271 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2274 rpmhpd_opp_nom: opp-5 {
2275 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2278 rpmhpd_opp_nom_l1: opp-6 {
2279 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2282 rpmhpd_opp_nom_l2: opp-7 {
2283 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2286 rpmhpd_opp_turbo: opp-8 {
2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2290 rpmhpd_opp_turbo_l1: opp-9 {
2291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2297 cpufreq_hw: cpufreq@18591000 {
2298 compatible = "qcom,sa8775p-cpufreq-epss",
2299 "qcom,cpufreq-epss";
2300 reg = <0x0 0x18591000 0x0 0x1000>,
2301 <0x0 0x18593000 0x0 0x1000>;
2302 reg-names = "freq-domain0", "freq-domain1";
2304 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2305 clock-names = "xo", "alternate";
2307 #freq-domain-cells = <1>;
2312 compatible = "arm,armv8-timer";
2313 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2314 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2315 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
2316 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;