arch/arm64/boot/dts/qcom/qcm2290.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (c) 2023, Linaro Ltd
   4  *
   5  * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
   9 #include <dt-bindings/clock/qcom,rpmcc.h>
  10 #include <dt-bindings/dma/qcom-gpi.h>
  11 #include <dt-bindings/firmware/qcom,scm.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/qcom-rpmpd.h>
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         chosen { };
  23
  24         clocks {
  25                 xo_board: xo-board {
  26                         compatible = "fixed-clock";
  27                         #clock-cells = <0>;
  28                 };
  29
  30                 sleep_clk: sleep-clk {
  31                         compatible = "fixed-clock";
  32                         clock-frequency = <32764>;
  33                         #clock-cells = <0>;
  34                 };
  35         };
  36
  37         cpus {
  38                 #address-cells = <2>;
  39                 #size-cells = <0>;
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x0 0x0>;
  45                         clocks = <&cpufreq_hw 0>;
  46                         capacity-dmips-mhz = <1024>;
  47                         dynamic-power-coefficient = <100>;
  48                         enable-method = "psci";
  49                         next-level-cache = <&L2_0>;
  50                         qcom,freq-domain = <&cpufreq_hw 0>;
  51                         power-domains = <&CPU_PD0>;
  52                         power-domain-names = "psci";
  53                         L2_0: l2-cache {
  54                                 compatible = "cache";
  55                                 cache-level = <2>;
  56                                 cache-unified;
  57                         };
  58                 };
  59
  60                 CPU1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x0 0x1>;
  64                         clocks = <&cpufreq_hw 0>;
  65                         capacity-dmips-mhz = <1024>;
  66                         dynamic-power-coefficient = <100>;
  67                         enable-method = "psci";
  68                         next-level-cache = <&L2_0>;
  69                         qcom,freq-domain = <&cpufreq_hw 0>;
  70                         power-domains = <&CPU_PD1>;
  71                         power-domain-names = "psci";
  72                 };
  73
  74                 CPU2: cpu@2 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x0 0x2>;
  78                         clocks = <&cpufreq_hw 0>;
  79                         capacity-dmips-mhz = <1024>;
  80                         dynamic-power-coefficient = <100>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&L2_0>;
  83                         qcom,freq-domain = <&cpufreq_hw 0>;
  84                         power-domains = <&CPU_PD2>;
  85                         power-domain-names = "psci";
  86                 };
  87
  88                 CPU3: cpu@3 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a53";
  91                         reg = <0x0 0x3>;
  92                         clocks = <&cpufreq_hw 0>;
  93                         capacity-dmips-mhz = <1024>;
  94                         dynamic-power-coefficient = <100>;
  95                         enable-method = "psci";
  96                         next-level-cache = <&L2_0>;
  97                         qcom,freq-domain = <&cpufreq_hw 0>;
  98                         power-domains = <&CPU_PD3>;
  99                         power-domain-names = "psci";
 100                 };
 101
 102                 cpu-map {
 103                         cluster0 {
 104                                 core0 {
 105                                         cpu = <&CPU0>;
 106                                 };
 107
 108                                 core1 {
 109                                         cpu = <&CPU1>;
 110                                 };
 111
 112                                 core2 {
 113                                         cpu = <&CPU2>;
 114                                 };
 115
 116                                 core3 {
 117                                         cpu = <&CPU3>;
 118                                 };
 119                         };
 120                 };
 121
 122                 domain-idle-states {
 123                         CLUSTER_SLEEP: cluster-sleep-0 {
 124                                 compatible = "domain-idle-state";
 125                                 arm,psci-suspend-param = <0x41000043>;
 126                                 entry-latency-us = <800>;
 127                                 exit-latency-us = <2118>;
 128                                 min-residency-us = <7376>;
 129                         };
 130                 };
 131
 132                 idle-states {
 133                         entry-method = "psci";
 134
 135                         CPU_SLEEP: cpu-sleep-0 {
 136                                 compatible = "arm,idle-state";
 137                                 idle-state-name = "power-collapse";
 138                                 arm,psci-suspend-param = <0x40000003>;
 139                                 entry-latency-us = <290>;
 140                                 exit-latency-us = <376>;
 141                                 min-residency-us = <1182>;
 142                                 local-timer-stop;
 143                         };
 144                 };
 145         };
 146
 147         firmware {
 148                 scm: scm {
 149                         compatible = "qcom,scm-qcm2290", "qcom,scm";
 150                         clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 151                         clock-names = "core";
 152                         #reset-cells = <1>;
 153                 };
 154         };
 155
 156         memory@40000000 {
 157                 device_type = "memory";
 158                 /* We expect the bootloader to fill in the size */
 159                 reg = <0 0x40000000 0 0>;
 160         };
 161
 162         pmu {
 163                 compatible = "arm,armv8-pmuv3";
 164                 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 165         };
 166
 167         psci {
 168                 compatible = "arm,psci-1.0";
 169                 method = "smc";
 170
 171                 CPU_PD0: power-domain-cpu0 {
 172                         #power-domain-cells = <0>;
 173                         power-domains = <&CLUSTER_PD>;
 174                         domain-idle-states = <&CPU_SLEEP>;
 175                 };
 176
 177                 CPU_PD1: power-domain-cpu1 {
 178                         #power-domain-cells = <0>;
 179                         power-domains = <&CLUSTER_PD>;
 180                         domain-idle-states = <&CPU_SLEEP>;
 181                 };
 182
 183                 CPU_PD2: power-domain-cpu2 {
 184                         #power-domain-cells = <0>;
 185                         power-domains = <&CLUSTER_PD>;
 186                         domain-idle-states = <&CPU_SLEEP>;
 187                 };
 188
 189                 CPU_PD3: power-domain-cpu3 {
 190                         #power-domain-cells = <0>;
 191                         power-domains = <&CLUSTER_PD>;
 192                         domain-idle-states = <&CPU_SLEEP>;
 193                 };
 194
 195                 CLUSTER_PD: power-domain-cpu-cluster {
 196                         #power-domain-cells = <0>;
 197                         domain-idle-states = <&CLUSTER_SLEEP>;
 198                 };
 199         };
 200
 201         reserved_memory: reserved-memory {
 202                 #address-cells = <2>;
 203                 #size-cells = <2>;
 204                 ranges;
 205
 206                 hyp_mem: hyp@45700000 {
 207                         reg = <0x0 0x45700000 0x0 0x600000>;
 208                         no-map;
 209                 };
 210
 211                 xbl_aop_mem: xbl-aop@45e00000 {
 212                         reg = <0x0 0x45e00000 0x0 0x140000>;
 213                         no-map;
 214                 };
 215
 216                 sec_apps_mem: sec-apps@45fff000 {
 217                         reg = <0x0 0x45fff000 0x0 0x1000>;
 218                         no-map;
 219                 };
 220
 221                 smem_mem: smem@46000000 {
 222                         compatible = "qcom,smem";
 223                         reg = <0x0 0x46000000 0x0 0x200000>;
 224                         no-map;
 225
 226                         hwlocks = <&tcsr_mutex 3>;
 227                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
 228                 };
 229
 230                 pil_modem_mem: modem@4ab00000 {
 231                         reg = <0x0 0x4ab00000 0x0 0x6900000>;
 232                         no-map;
 233                 };
 234
 235                 pil_video_mem: video@51400000 {
 236                         reg = <0x0 0x51400000 0x0 0x500000>;
 237                         no-map;
 238                 };
 239
 240                 wlan_msa_mem: wlan-msa@51900000 {
 241                         reg = <0x0 0x51900000 0x0 0x100000>;
 242                         no-map;
 243                 };
 244
 245                 pil_adsp_mem: adsp@51a00000 {
 246                         reg = <0x0 0x51a00000 0x0 0x1c00000>;
 247                         no-map;
 248                 };
 249
 250                 pil_ipa_fw_mem: ipa-fw@53600000 {
 251                         reg = <0x0 0x53600000 0x0 0x10000>;
 252                         no-map;
 253                 };
 254
 255                 pil_ipa_gsi_mem: ipa-gsi@53610000 {
 256                         reg = <0x0 0x53610000 0x0 0x5000>;
 257                         no-map;
 258                 };
 259
 260                 pil_gpu_mem: zap@53615000 {
 261                         compatible = "shared-dma-pool";
 262                         reg = <0x0 0x53615000 0x0 0x2000>;
 263                         no-map;
 264                 };
 265
 266                 cont_splash_memory: framebuffer@5c000000 {
 267                         reg = <0x0 0x5c000000 0x0 0x00f00000>;
 268                         no-map;
 269                 };
 270
 271                 dfps_data_memory: dpfs-data@5cf00000 {
 272                         reg = <0x0 0x5cf00000 0x0 0x0100000>;
 273                         no-map;
 274                 };
 275
 276                 removed_mem: reserved@60000000 {
 277                         reg = <0x0 0x60000000 0x0 0x3900000>;
 278                         no-map;
 279                 };
 280
 281                 rmtfs_mem: memory@89b01000 {
 282                         compatible = "qcom,rmtfs-mem";
 283                         reg = <0x0 0x89b01000 0x0 0x200000>;
 284                         no-map;
 285
 286                         qcom,client-id = <1>;
 287                         qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
 288                 };
 289         };
 290
 291         rpm-glink {
 292                 compatible = "qcom,glink-rpm";
 293                 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
 294                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 295                 mboxes = <&apcs_glb 0>;
 296
 297                 rpm_requests: rpm-requests {
 298                         compatible = "qcom,rpm-qcm2290";
 299                         qcom,glink-channels = "rpm_requests";
 300
 301                         rpmcc: clock-controller {
 302                                 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
 303                                 clocks = <&xo_board>;
 304                                 clock-names = "xo";
 305                                 #clock-cells = <1>;
 306                         };
 307
 308                         rpmpd: power-controller {
 309                                 compatible = "qcom,qcm2290-rpmpd";
 310                                 #power-domain-cells = <1>;
 311                                 operating-points-v2 = <&rpmpd_opp_table>;
 312
 313                                 rpmpd_opp_table: opp-table {
 314                                         compatible = "operating-points-v2";
 315
 316                                         rpmpd_opp_min_svs: opp1 {
 317                                                 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 318                                         };
 319
 320                                         rpmpd_opp_low_svs: opp2 {
 321                                                 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 322                                         };
 323
 324                                         rpmpd_opp_svs: opp3 {
 325                                                 opp-level = <RPM_SMD_LEVEL_SVS>;
 326                                         };
 327
 328                                         rpmpd_opp_svs_plus: opp4 {
 329                                                 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 330                                         };
 331
 332                                         rpmpd_opp_nom: opp5 {
 333                                                 opp-level = <RPM_SMD_LEVEL_NOM>;
 334                                         };
 335
 336                                         rpmpd_opp_nom_plus: opp6 {
 337                                                 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 338                                         };
 339
 340                                         rpmpd_opp_turbo: opp7 {
 341                                                 opp-level = <RPM_SMD_LEVEL_TURBO>;
 342                                         };
 343
 344                                         rpmpd_opp_turbo_plus: opp8 {
 345                                                 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
 346                                         };
 347                                 };
 348                         };
 349                 };
 350         };
 351
 352         smp2p-adsp {
 353                 compatible = "qcom,smp2p";
 354                 qcom,smem = <443>, <429>;
 355
 356                 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
 357
 358                 mboxes = <&apcs_glb 10>;
 359
 360                 qcom,local-pid = <0>;
 361                 qcom,remote-pid = <2>;
 362
 363                 adsp_smp2p_out: master-kernel {
 364                         qcom,entry-name = "master-kernel";
 365                         #qcom,smem-state-cells = <1>;
 366                 };
 367
 368                 adsp_smp2p_in: slave-kernel {
 369                         qcom,entry-name = "slave-kernel";
 370                         interrupt-controller;
 371                         #interrupt-cells = <2>;
 372                 };
 373         };
 374
 375         smp2p-mpss {
 376                 compatible = "qcom,smp2p";
 377                 qcom,smem = <435>, <428>;
 378
 379                 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
 380
 381                 mboxes = <&apcs_glb 14>;
 382
 383                 qcom,local-pid = <0>;
 384                 qcom,remote-pid = <1>;
 385
 386                 modem_smp2p_out: master-kernel {
 387                         qcom,entry-name = "master-kernel";
 388                         #qcom,smem-state-cells = <1>;
 389                 };
 390
 391                 modem_smp2p_in: slave-kernel {
 392                         qcom,entry-name = "slave-kernel";
 393                         interrupt-controller;
 394                         #interrupt-cells = <2>;
 395                 };
 396
 397                 wlan_smp2p_in: wlan-wpss-to-ap {
 398                         qcom,entry-name = "wlan";
 399                         interrupt-controller;
 400                         #interrupt-cells = <2>;
 401                 };
 402         };
 403
 404         soc: soc@0 {
 405                 compatible = "simple-bus";
 406                 #address-cells = <2>;
 407                 #size-cells = <2>;
 408                 ranges = <0 0 0 0 0x10 0>;
 409                 dma-ranges = <0 0 0 0 0x10 0>;
 410
 411                 tcsr_mutex: hwlock@340000 {
 412                         compatible = "qcom,tcsr-mutex";
 413                         reg = <0x0 0x00340000 0x0 0x20000>;
 414                         #hwlock-cells = <1>;
 415                 };
 416
 417                 tlmm: pinctrl@500000 {
 418                         compatible = "qcom,qcm2290-tlmm";
 419                         reg = <0x0 0x00500000 0x0 0x300000>;
 420                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 421                         gpio-controller;
 422                         gpio-ranges = <&tlmm 0 0 127>;
 423                         #gpio-cells = <2>;
 424                         interrupt-controller;
 425                         #interrupt-cells = <2>;
 426
 427                         qup_i2c0_default: qup-i2c0-default-state {
 428                                 pins = "gpio0", "gpio1";
 429                                 function = "qup0";
 430                                 drive-strength = <2>;
 431                                 bias-pull-up;
 432                         };
 433
 434                         qup_i2c1_default: qup-i2c1-default-state {
 435                                 pins = "gpio4", "gpio5";
 436                                 function = "qup1";
 437                                 drive-strength = <2>;
 438                                 bias-pull-up;
 439                         };
 440
 441                         qup_i2c2_default: qup-i2c2-default-state {
 442                                 pins = "gpio6", "gpio7";
 443                                 function = "qup2";
 444                                 drive-strength = <2>;
 445                                 bias-pull-up;
 446                         };
 447
 448                         qup_i2c3_default: qup-i2c3-default-state {
 449                                 pins = "gpio8", "gpio9";
 450                                 function = "qup3";
 451                                 drive-strength = <2>;
 452                                 bias-pull-up;
 453                         };
 454
 455                         qup_i2c4_default: qup-i2c4-default-state {
 456                                 pins = "gpio12", "gpio13";
 457                                 function = "qup4";
 458                                 drive-strength = <2>;
 459                                 bias-pull-up;
 460                         };
 461
 462                         qup_i2c5_default: qup-i2c5-default-state {
 463                                 pins = "gpio14", "gpio15";
 464                                 function = "qup5";
 465                                 drive-strength = <2>;
 466                                 bias-pull-up;
 467                         };
 468
 469                         qup_spi0_default: qup-spi0-default-state {
 470                                 pins = "gpio0", "gpio1","gpio2", "gpio3";
 471                                 function = "qup0";
 472                                 drive-strength = <2>;
 473                                 bias-pull-up;
 474                         };
 475
 476                         qup_spi1_default: qup-spi1-default-state {
 477                                 pins = "gpio4", "gpio5", "gpio69", "gpio70";
 478                                 function = "qup1";
 479                                 drive-strength = <2>;
 480                                 bias-pull-up;
 481                         };
 482
 483                         qup_spi2_default: qup-spi2-default-state {
 484                                 pins = "gpio6", "gpio7", "gpio71", "gpio80";
 485                                 function = "qup2";
 486                                 drive-strength = <2>;
 487                                 bias-pull-up;
 488                         };
 489
 490                         qup_spi3_default: qup-spi3-default-state {
 491                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
 492                                 function = "qup3";
 493                                 drive-strength = <2>;
 494                                 bias-pull-up;
 495                         };
 496
 497                         qup_spi4_default: qup-spi4-default-state {
 498                                 pins = "gpio12", "gpio13", "gpio96", "gpio97";
 499                                 function = "qup4";
 500                                 drive-strength = <2>;
 501                                 bias-pull-up;
 502                         };
 503
 504                         qup_spi5_default: qup-spi5-default-state {
 505                                 pins = "gpio14", "gpio15", "gpio16", "gpio17";
 506                                 function = "qup5";
 507                                 drive-strength = <2>;
 508                                 bias-pull-up;
 509                         };
 510
 511                         qup_uart0_default: qup-uart0-default-state {
 512                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 513                                 function = "qup0";
 514                                 drive-strength = <2>;
 515                                 bias-disable;
 516                         };
 517
 518                         qup_uart4_default: qup-uart4-default-state {
 519                                 pins = "gpio12", "gpio13";
 520                                 function = "qup4";
 521                                 drive-strength = <2>;
 522                                 bias-disable;
 523                         };
 524
 525                         sdc1_state_on: sdc1-on-state {
 526                                 clk-pins {
 527                                         pins = "sdc1_clk";
 528                                         drive-strength = <16>;
 529                                         bias-disable;
 530                                 };
 531
 532                                 cmd-pins {
 533                                         pins = "sdc1_cmd";
 534                                         drive-strength = <10>;
 535                                         bias-pull-up;
 536                                 };
 537
 538                                 data-pins {
 539                                         pins = "sdc1_data";
 540                                         drive-strength = <10>;
 541                                         bias-pull-up;
 542                                 };
 543
 544                                 rclk-pins {
 545                                         pins = "sdc1_rclk";
 546                                         bias-pull-down;
 547                                 };
 548                         };
 549
 550                         sdc1_state_off: sdc1-off-state {
 551                                 clk-pins {
 552                                         pins = "sdc1_clk";
 553                                         drive-strength = <2>;
 554                                         bias-disable;
 555                                 };
 556
 557                                 cmd-pins {
 558                                         pins = "sdc1_cmd";
 559                                         drive-strength = <2>;
 560                                         bias-pull-up;
 561                                 };
 562
 563                                 data-pins {
 564                                         pins = "sdc1_data";
 565                                         drive-strength = <2>;
 566                                         bias-pull-up;
 567                                 };
 568
 569                                 rclk-pins {
 570                                         pins = "sdc1_rclk";
 571                                         bias-pull-down;
 572                                 };
 573                         };
 574
 575                         sdc2_state_on: sdc2-on-state {
 576                                 clk-pins {
 577                                         pins = "sdc2_clk";
 578                                         drive-strength = <16>;
 579                                         bias-disable;
 580                                 };
 581
 582                                 cmd-pins {
 583                                         pins = "sdc2_cmd";
 584                                         drive-strength = <10>;
 585                                         bias-pull-up;
 586                                 };
 587
 588                                 data-pins {
 589                                         pins = "sdc2_data";
 590                                         drive-strength = <10>;
 591                                         bias-pull-up;
 592                                 };
 593                         };
 594
 595                         sdc2_state_off: sdc2-off-state {
 596                                 clk-pins {
 597                                         pins = "sdc2_clk";
 598                                         drive-strength = <2>;
 599                                         bias-disable;
 600                                 };
 601
 602                                 cmd-pins {
 603                                         pins = "sdc2_cmd";
 604                                         drive-strength = <2>;
 605                                         bias-pull-up;
 606                                 };
 607
 608                                 data-pins {
 609                                         pins = "sdc2_data";
 610                                         drive-strength = <2>;
 611                                         bias-pull-up;
 612                                 };
 613                         };
 614                 };
 615
 616                 gcc: clock-controller@1400000 {
 617                         compatible = "qcom,gcc-qcm2290";
 618                         reg = <0x0 0x01400000 0x0 0x1f0000>;
 619                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 620                         clock-names = "bi_tcxo", "sleep_clk";
 621                         #clock-cells = <1>;
 622                         #reset-cells = <1>;
 623                         #power-domain-cells = <1>;
 624                 };
 625
 626                 usb_hsphy: phy@1613000 {
 627                         compatible = "qcom,qcm2290-qusb2-phy";
 628                         reg = <0x0 0x01613000 0x0 0x180>;
 629
 630                         clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
 631                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
 632                         clock-names = "cfg_ahb", "ref";
 633
 634                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 635                         nvmem-cells = <&qusb2_hstx_trim>;
 636                         #phy-cells = <0>;
 637
 638                         status = "disabled";
 639                 };
 640
 641                 qfprom@1b44000 {
 642                         compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
 643                         reg = <0x0 0x01b44000 0x0 0x3000>;
 644                         #address-cells = <1>;
 645                         #size-cells = <1>;
 646
 647                         qusb2_hstx_trim: hstx-trim@25b {
 648                                 reg = <0x25b 0x1>;
 649                                 bits = <1 4>;
 650                         };
 651                 };
 652
 653                 spmi_bus: spmi@1c40000 {
 654                         compatible = "qcom,spmi-pmic-arb";
 655                         reg = <0x0 0x01c40000 0x0 0x1100>,
 656                               <0x0 0x01e00000 0x0 0x2000000>,
 657                               <0x0 0x03e00000 0x0 0x100000>,
 658                               <0x0 0x03f00000 0x0 0xa0000>,
 659                               <0x0 0x01c0a000 0x0 0x26000>;
 660                         reg-names = "core",
 661                                     "chnls",
 662                                     "obsrvr",
 663                                     "intr",
 664                                     "cnfg";
 665                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 666                         interrupt-names = "periph_irq";
 667                         qcom,ee = <0>;
 668                         qcom,channel = <0>;
 669                         #address-cells = <2>;
 670                         #size-cells = <0>;
 671                         interrupt-controller;
 672                         #interrupt-cells = <4>;
 673                 };
 674
 675                 tsens0: thermal-sensor@4411000 {
 676                         compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
 677                         reg = <0x0 0x04411000 0x0 0x1ff>,
 678                               <0x0 0x04410000 0x0 0x8>;
 679                         #qcom,sensors = <10>;
 680                         interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 682                         interrupt-names = "uplow", "critical";
 683                         #thermal-sensor-cells = <1>;
 684                 };
 685
 686                 rng: rng@4453000 {
 687                         compatible = "qcom,prng-ee";
 688                         reg = <0x0 0x04453000 0x0 0x1000>;
 689                         clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
 690                         clock-names = "core";
 691                 };
 692
 693                 rpm_msg_ram: sram@45f0000 {
 694                         compatible = "qcom,rpm-msg-ram";
 695                         reg = <0x0 0x045f0000 0x0 0x7000>;
 696                 };
 697
 698                 sram@4690000 {
 699                         compatible = "qcom,rpm-stats";
 700                         reg = <0x0 0x04690000 0x0 0x10000>;
 701                 };
 702
 703                 sdhc_1: mmc@4744000 {
 704                         compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
 705                         reg = <0x0 0x04744000 0x0 0x1000>,
 706                               <0x0 0x04745000 0x0 0x1000>,
 707                               <0x0 0x04748000 0x0 0x8000>;
 708                         reg-names = "hc",
 709                                     "cqhci",
 710                                     "ice";
 711
 712                         interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
 714                         interrupt-names = "hc_irq", "pwr_irq";
 715
 716                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 717                                  <&gcc GCC_SDCC1_APPS_CLK>,
 718                                  <&rpmcc RPM_SMD_XO_CLK_SRC>,
 719                                  <&gcc GCC_SDCC1_ICE_CORE_CLK>;
 720                         clock-names = "iface",
 721                                       "core",
 722                                       "xo",
 723                                       "ice";
 724
 725                         resets = <&gcc GCC_SDCC1_BCR>;
 726
 727                         power-domains = <&rpmpd QCM2290_VDDCX>;
 728                         iommus = <&apps_smmu 0xc0 0x0>;
 729
 730                         qcom,dll-config = <0x000f642c>;
 731                         qcom,ddr-config = <0x80040868>;
 732                         bus-width = <8>;
 733
 734                         status = "disabled";
 735                 };
 736
 737                 sdhc_2: mmc@4784000 {
 738                         compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
 739                         reg = <0x0 0x04784000 0x0 0x1000>;
 740                         reg-names = "hc";
 741
 742                         interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 744                         interrupt-names = "hc_irq", "pwr_irq";
 745
 746                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 747                                  <&gcc GCC_SDCC2_APPS_CLK>,
 748                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
 749                         clock-names = "iface",
 750                                       "core",
 751                                       "xo";
 752
 753                         resets = <&gcc GCC_SDCC2_BCR>;
 754
 755                         power-domains = <&rpmpd QCM2290_VDDCX>;
 756                         operating-points-v2 = <&sdhc2_opp_table>;
 757                         iommus = <&apps_smmu 0xa0 0x0>;
 758
 759                         qcom,dll-config = <0x0007642c>;
 760                         qcom,ddr-config = <0x80040868>;
 761                         bus-width = <4>;
 762
 763                         status = "disabled";
 764
 765                         sdhc2_opp_table: opp-table {
 766                                 compatible = "operating-points-v2";
 767
 768                                 opp-100000000 {
 769                                         opp-hz = /bits/ 64 <100000000>;
 770                                         required-opps = <&rpmpd_opp_low_svs>;
 771                                 };
 772
 773                                 opp-202000000 {
 774                                         opp-hz = /bits/ 64 <202000000>;
 775                                         required-opps = <&rpmpd_opp_svs_plus>;
 776                                 };
 777                         };
 778                 };
 779
 780                 gpi_dma0: dma-controller@4a00000 {
 781                         compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
 782                         reg = <0x0 0x04a00000 0x0 0x60000>;
 783                         interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 784                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 785                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 791                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 792                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 793                         dma-channels =  <10>;
 794                         dma-channel-mask = <0x1f>;
 795                         iommus = <&apps_smmu 0xf6 0x0>;
 796                         #dma-cells = <3>;
 797                         status = "disabled";
 798                 };
 799
 800                 qupv3_id_0: geniqup@4ac0000 {
 801                         compatible = "qcom,geni-se-qup";
 802                         reg = <0x0 0x04ac0000 0x0 0x2000>;
 803                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 804                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 805                         clock-names = "m-ahb", "s-ahb";
 806                         iommus = <&apps_smmu 0xe3 0x0>;
 807                         #address-cells = <2>;
 808                         #size-cells = <2>;
 809                         ranges;
 810                         status = "disabled";
 811
 812                         i2c0: i2c@4a80000 {
 813                                 compatible = "qcom,geni-i2c";
 814                                 reg = <0x0 0x04a80000 0x0 0x4000>;
 815                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 816                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 817                                 clock-names = "se";
 818                                 pinctrl-0 = <&qup_i2c0_default>;
 819                                 pinctrl-names = "default";
 820                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 821                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 822                                 dma-names = "tx", "rx";
 823                                 #address-cells = <1>;
 824                                 #size-cells = <0>;
 825                                 status = "disabled";
 826                         };
 827
 828                         spi0: spi@4a80000 {
 829                                 compatible = "qcom,geni-spi";
 830                                 reg = <0x0 0x04a80000 0x0 0x4000>;
 831                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 833                                 clock-names = "se";
 834                                 pinctrl-0 = <&qup_spi0_default>;
 835                                 pinctrl-names = "default";
 836                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 837                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 838                                 dma-names = "tx", "rx";
 839                                 #address-cells = <1>;
 840                                 #size-cells = <0>;
 841                                 status = "disabled";
 842                         };
 843
 844                         uart0: serial@4a80000 {
 845                                 compatible = "qcom,geni-uart";
 846                                 reg = <0x0 0x04a80000 0x0 0x4000>;
 847                                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 848                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 849                                 clock-names = "se";
 850                                 pinctrl-0 = <&qup_uart0_default>;
 851                                 pinctrl-names = "default";
 852                                 status = "disabled";
 853                         };
 854
 855                         i2c1: i2c@4a84000 {
 856                                 compatible = "qcom,geni-i2c";
 857                                 reg = <0x0 0x04a84000 0x0 0x4000>;
 858                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
 859                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 860                                 clock-names = "se";
 861                                 pinctrl-0 = <&qup_i2c1_default>;
 862                                 pinctrl-names = "default";
 863                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 864                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 865                                 dma-names = "tx", "rx";
 866                                 #address-cells = <1>;
 867                                 #size-cells = <0>;
 868                                 status = "disabled";
 869                         };
 870
 871                         spi1: spi@4a84000 {
 872                                 compatible = "qcom,geni-spi";
 873                                 reg = <0x0 0x04a84000 0x0 0x4000>;
 874                                 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
 875                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 876                                 clock-names = "se";
 877                                 pinctrl-0 = <&qup_spi1_default>;
 878                                 pinctrl-names = "default";
 879                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 880                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 881                                 dma-names = "tx", "rx";
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 status = "disabled";
 885                         };
 886
 887                         i2c2: i2c@4a88000 {
 888                                 compatible = "qcom,geni-i2c";
 889                                 reg = <0x0 0x04a88000 0x0 0x4000>;
 890                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
 891                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 892                                 clock-names = "se";
 893                                 pinctrl-0 = <&qup_i2c2_default>;
 894                                 pinctrl-names = "default";
 895                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 896                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 897                                 dma-names = "tx", "rx";
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900                                 status = "disabled";
 901                         };
 902
 903                         spi2: spi@4a88000 {
 904                                 compatible = "qcom,geni-spi";
 905                                 reg = <0x0 0x04a88000 0x0 0x4000>;
 906                                 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
 907                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 908                                 clock-names = "se";
 909                                 pinctrl-0 = <&qup_spi2_default>;
 910                                 pinctrl-names = "default";
 911                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
 912                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
 913                                 dma-names = "tx", "rx";
 914                                 #address-cells = <1>;
 915                                 #size-cells = <0>;
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c3: i2c@4a8c000 {
 920                                 compatible = "qcom,geni-i2c";
 921                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
 922                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
 923                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 924                                 clock-names = "se";
 925                                 pinctrl-0 = <&qup_i2c3_default>;
 926                                 pinctrl-names = "default";
 927                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 928                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 929                                 dma-names = "tx", "rx";
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 status = "disabled";
 933                         };
 934
 935                         spi3: spi@4a8c000 {
 936                                 compatible = "qcom,geni-spi";
 937                                 reg = <0x0 0x04a8c000 0x0 0x4000>;
 938                                 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 940                                 clock-names = "se";
 941                                 pinctrl-0 = <&qup_spi3_default>;
 942                                 pinctrl-names = "default";
 943                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
 944                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
 945                                 dma-names = "tx", "rx";
 946                                 #address-cells = <1>;
 947                                 #size-cells = <0>;
 948                                 status = "disabled";
 949                         };
 950
 951                         i2c4: i2c@4a90000 {
 952                                 compatible = "qcom,geni-i2c";
 953                                 reg = <0x0 0x04a90000 0x0 0x4000>;
 954                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
 955                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 956                                 clock-names = "se";
 957                                 pinctrl-0 = <&qup_i2c4_default>;
 958                                 pinctrl-names = "default";
 959                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 960                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 961                                 dma-names = "tx", "rx";
 962                                 #address-cells = <1>;
 963                                 #size-cells = <0>;
 964                                 status = "disabled";
 965                         };
 966
 967                         spi4: spi@4a90000 {
 968                                 compatible = "qcom,geni-spi";
 969                                 reg = <0x0 0x04a90000 0x0 0x4000>;
 970                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
 971                                 clock-names = "se";
 972                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 973                                 pinctrl-names = "default";
 974                                 pinctrl-0 = <&qup_spi4_default>;
 975                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
 976                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
 977                                 dma-names = "tx", "rx";
 978                                 #address-cells = <1>;
 979                                 #size-cells = <0>;
 980                                 status = "disabled";
 981                         };
 982
 983                         uart4: serial@4a90000 {
 984                                 compatible = "qcom,geni-uart";
 985                                 reg = <0x0 0x04a90000 0x0 0x4000>;
 986                                 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
 987                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 988                                 clock-names = "se";
 989                                 pinctrl-0 = <&qup_uart4_default>;
 990                                 pinctrl-names = "default";
 991                                 status = "disabled";
 992                         };
 993
 994                         i2c5: i2c@4a94000 {
 995                                 compatible = "qcom,geni-i2c";
 996                                 reg = <0x0 0x04a94000 0x0 0x4000>;
 997                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
 998                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 999                                 clock-names = "se";
1000                                 pinctrl-0 = <&qup_i2c5_default>;
1001                                 pinctrl-names = "default";
1002                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1003                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1004                                 dma-names = "tx", "rx";
1005                                 #address-cells = <1>;
1006                                 #size-cells = <0>;
1007                                 status = "disabled";
1008                         };
1009
1010                         spi5: spi@4a94000 {
1011                                 compatible = "qcom,geni-spi";
1012                                 reg = <0x0 0x04a94000 0x0 0x4000>;
1013                                 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1014                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1015                                 clock-names = "se";
1016                                 pinctrl-0 = <&qup_spi5_default>;
1017                                 pinctrl-names = "default";
1018                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1019                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1020                                 dma-names = "tx", "rx";
1021                                 #address-cells = <1>;
1022                                 #size-cells = <0>;
1023                                 status = "disabled";
1024                         };
1025                 };
1026
1027                 usb: usb@4ef8800 {
1028                         compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1029                         reg = <0x0 0x04ef8800 0x0 0x400>;
1030                         interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1031                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1032                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
1033
1034                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1035                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1036                                  <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1037                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1038                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1039                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1040                         clock-names = "cfg_noc",
1041                                       "core",
1042                                       "iface",
1043                                       "sleep",
1044                                       "mock_utmi",
1045                                       "xo";
1046
1047                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1048                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1049                         assigned-clock-rates = <19200000>, <133333333>;
1050
1051                         resets = <&gcc GCC_USB30_PRIM_BCR>;
1052                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1053                         wakeup-source;
1054
1055                         #address-cells = <2>;
1056                         #size-cells = <2>;
1057                         ranges;
1058
1059                         status = "disabled";
1060
1061                         usb_dwc3: usb@4e00000 {
1062                                 compatible = "snps,dwc3";
1063                                 reg = <0x0 0x04e00000 0x0 0xcd00>;
1064                                 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1065                                 phys = <&usb_hsphy>;
1066                                 phy-names = "usb2-phy";
1067                                 iommus = <&apps_smmu 0x120 0x0>;
1068                                 snps,dis_u2_susphy_quirk;
1069                                 snps,dis_enblslpm_quirk;
1070                                 snps,has-lpm-erratum;
1071                                 snps,hird-threshold = /bits/ 8 <0x10>;
1072                                 snps,usb3_lpm_capable;
1073                                 maximum-speed = "super-speed";
1074                                 dr_mode = "otg";
1075                         };
1076                 };
1077
1078                 remoteproc_mpss: remoteproc@6080000 {
1079                         compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1080                         reg = <0x0 0x06080000 0x0 0x100>;
1081
1082                         interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1083                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1084                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1085                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1086                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1087                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1088                         interrupt-names = "wdog",
1089                                           "fatal",
1090                                           "ready",
1091                                           "handover",
1092                                           "stop-ack",
1093                                           "shutdown-ack";
1094
1095                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1096                         clock-names = "xo";
1097
1098                         power-domains = <&rpmpd QCM2290_VDDCX>;
1099
1100                         memory-region = <&pil_modem_mem>;
1101
1102                         qcom,smem-states = <&modem_smp2p_out 0>;
1103                         qcom,smem-state-names = "stop";
1104
1105                         status = "disabled";
1106
1107                         glink-edge {
1108                                 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1109                                 label = "mpss";
1110                                 qcom,remote-pid = <1>;
1111                                 mboxes = <&apcs_glb 12>;
1112                         };
1113                 };
1114
1115                 remoteproc_adsp: remoteproc@ab00000 {
1116                         compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1117                         reg = <0x0 0x0ab00000 0x0 0x100>;
1118
1119                         interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1120                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1121                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1122                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1123                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1124                         interrupt-names = "wdog",
1125                                           "fatal",
1126                                           "ready",
1127                                           "handover",
1128                                           "stop-ack";
1129
1130                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1131                         clock-names = "xo";
1132
1133                         power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1134                                         <&rpmpd QCM2290_VDD_LPI_MX>;
1135
1136                         memory-region = <&pil_adsp_mem>;
1137
1138                         qcom,smem-states = <&adsp_smp2p_out 0>;
1139                         qcom,smem-state-names = "stop";
1140
1141                         status = "disabled";
1142
1143                         glink-edge {
1144                                 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1145                                 label = "lpass";
1146                                 qcom,remote-pid = <2>;
1147                                 mboxes = <&apcs_glb 8>;
1148                         };
1149                 };
1150
1151                 apps_smmu: iommu@c600000 {
1152                         compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1153                         reg = <0x0 0x0c600000 0x0 0x80000>;
1154                         #iommu-cells = <2>;
1155                         #global-interrupts = <1>;
1156
1157                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1158                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1159                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1160                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1161                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1162                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1163                                      <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1164                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1165                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1167                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1168                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1170                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1171                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1172                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1173                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1174                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1175                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1176                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1177                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1178                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1179                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1180                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1181                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1182                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1183                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1184                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1185                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1186                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1187                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1188                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1189                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1190                                      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1191                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1192                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1193                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1194                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1195                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1196                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1197                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1198                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1199                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1200                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1201                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1202                                      <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1203                                      <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1204                                      <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1205                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1206                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1207                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1208                                      <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1209                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1210                                      <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1211                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1212                                      <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1213                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1214                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1215                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1216                                      <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1217                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1218                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1219                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1220                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1221                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1222                 };
1223
1224                 wifi: wifi@c800000 {
1225                         compatible = "qcom,wcn3990-wifi";
1226                         reg = <0x0 0x0c800000 0x0 0x800000>;
1227                         reg-names = "membase";
1228                         memory-region = <&wlan_msa_mem>;
1229                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1230                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1231                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1232                                      <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1233                                      <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1234                                      <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1235                                      <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1236                                      <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1237                                      <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1238                                      <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1239                                      <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1240                                      <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1241                         iommus = <&apps_smmu 0x1a0 0x1>;
1242                         qcom,msa-fixed-perm;
1243                         status = "disabled";
1244                 };
1245
1246                 watchdog@f017000 {
1247                         compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1248                         reg = <0x0 0x0f017000 0x0 0x1000>;
1249                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1250                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1251                         clocks = <&sleep_clk>;
1252                 };
1253
1254                 apcs_glb: mailbox@f111000 {
1255                         compatible = "qcom,qcm2290-apcs-hmss-global";
1256                         reg = <0x0 0x0f111000 0x0 0x1000>;
1257                         #mbox-cells = <1>;
1258                 };
1259
1260                 timer@f120000 {
1261                         compatible = "arm,armv7-timer-mem";
1262                         reg = <0x0 0x0f120000 0x0 0x1000>;
1263                         #address-cells = <1>;
1264                         #size-cells = <1>;
1265                         ranges = <0 0x0 0x0f121000 0x8000>;
1266
1267                         frame@0 {
1268                                 reg = <0x0 0x1000>,
1269                                       <0x1000 0x1000>;
1270                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1271                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1272                                 frame-number = <0>;
1273                         };
1274
1275                         frame@2000 {
1276                                 reg = <0x2000 0x1000>;
1277                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1278                                 frame-number = <1>;
1279                                 status = "disabled";
1280                         };
1281
1282                         frame@3000 {
1283                                 reg = <0x3000 0x1000>;
1284                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1285                                 frame-number = <2>;
1286                                 status = "disabled";
1287                         };
1288
1289                         frame@4000 {
1290                                 reg = <0x4000 0x1000>;
1291                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1292                                 frame-number = <3>;
1293                                 status = "disabled";
1294                         };
1295
1296                         frame@5000 {
1297                                 reg = <0x5000 0x1000>;
1298                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1299                                 frame-number = <4>;
1300                                 status = "disabled";
1301                         };
1302
1303                         frame@6000 {
1304                                 reg = <0x6000 0x1000>;
1305                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1306                                 frame-number = <5>;
1307                                 status = "disabled";
1308                         };
1309
1310                         frame@7000 {
1311                                 reg = <0x7000 0x1000>;
1312                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1313                                 frame-number = <6>;
1314                                 status = "disabled";
1315                         };
1316                 };
1317
1318                 intc: interrupt-controller@f200000 {
1319                         compatible = "arm,gic-v3";
1320                         reg = <0x0 0x0f200000 0x0 0x10000>,
1321                               <0x0 0x0f300000 0x0 0x100000>;
1322                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1323                         #interrupt-cells = <3>;
1324                         interrupt-controller;
1325                         interrupt-parent = <&intc>;
1326                         #redistributor-regions = <1>;
1327                         redistributor-stride = <0x0 0x20000>;
1328                 };
1329
1330                 cpufreq_hw: cpufreq@f521000 {
1331                         compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
1332                         reg = <0x0 0x0f521000 0x0 0x1000>;
1333                         reg-names = "freq-domain0";
1334                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1335                         interrupt-names = "dcvsh-irq-0";
1336                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1337                         clock-names = "xo", "alternate";
1338
1339                         #freq-domain-cells = <1>;
1340                         #clock-cells = <1>;
1341                 };
1342         };
1343
1344         thermal-zones {
1345                 mapss-thermal {
1346                         polling-delay-passive = <0>;
1347                         polling-delay = <0>;
1348
1349                         thermal-sensors = <&tsens0 0>;
1350
1351                         trips {
1352                                 mapss_alert0: trip-point0 {
1353                                         temperature = <90000>;
1354                                         hysteresis = <2000>;
1355                                         type = "passive";
1356                                 };
1357
1358                                 mapss_alert1: trip-point1 {
1359                                         temperature = <95000>;
1360                                         hysteresis = <2000>;
1361                                         type = "passive";
1362                                 };
1363
1364                                 mapss_crit: mapss-crit {
1365                                         temperature = <110000>;
1366                                         hysteresis = <1000>;
1367                                         type = "critical";
1368                                 };
1369                         };
1370                 };
1371
1372                 video-thermal {
1373                         polling-delay-passive = <0>;
1374                         polling-delay = <0>;
1375
1376                         thermal-sensors = <&tsens0 1>;
1377
1378                         trips {
1379                                 video_alert0: trip-point0 {
1380                                         temperature = <90000>;
1381                                         hysteresis = <2000>;
1382                                         type = "passive";
1383                                 };
1384
1385                                 video_alert1: trip-point1 {
1386                                         temperature = <95000>;
1387                                         hysteresis = <2000>;
1388                                         type = "passive";
1389                                 };
1390
1391                                 video_crit: video-crit {
1392                                         temperature = <110000>;
1393                                         hysteresis = <1000>;
1394                                         type = "critical";
1395                                 };
1396                         };
1397                 };
1398
1399                 wlan-thermal {
1400                         polling-delay-passive = <0>;
1401                         polling-delay = <0>;
1402
1403                         thermal-sensors = <&tsens0 2>;
1404
1405                         trips {
1406                                 wlan_alert0: trip-point0 {
1407                                         temperature = <90000>;
1408                                         hysteresis = <2000>;
1409                                         type = "passive";
1410                                 };
1411
1412                                 wlan_alert1: trip-point1 {
1413                                         temperature = <95000>;
1414                                         hysteresis = <2000>;
1415                                         type = "passive";
1416                                 };
1417
1418                                 wlan_crit: wlan-crit {
1419                                         temperature = <110000>;
1420                                         hysteresis = <1000>;
1421                                         type = "critical";
1422                                 };
1423                         };
1424                 };
1425
1426                 cpuss0-thermal {
1427                         polling-delay-passive = <0>;
1428                         polling-delay = <0>;
1429
1430                         thermal-sensors = <&tsens0 3>;
1431
1432                         trips {
1433                                 cpuss0_alert0: trip-point0 {
1434                                         temperature = <90000>;
1435                                         hysteresis = <2000>;
1436                                         type = "passive";
1437                                 };
1438
1439                                 cpuss0_alert1: trip-point1 {
1440                                         temperature = <95000>;
1441                                         hysteresis = <2000>;
1442                                         type = "passive";
1443                                 };
1444
1445                                 cpuss0_crit: cpuss0-crit {
1446                                         temperature = <110000>;
1447                                         hysteresis = <1000>;
1448                                         type = "critical";
1449                                 };
1450                         };
1451                 };
1452
1453                 cpuss1-thermal {
1454                         polling-delay-passive = <0>;
1455                         polling-delay = <0>;
1456
1457                         thermal-sensors = <&tsens0 4>;
1458
1459                         trips {
1460                                 cpuss1_alert0: trip-point0 {
1461                                         temperature = <90000>;
1462                                         hysteresis = <2000>;
1463                                         type = "passive";
1464                                 };
1465
1466                                 cpuss1_alert1: trip-point1 {
1467                                         temperature = <95000>;
1468                                         hysteresis = <2000>;
1469                                         type = "passive";
1470                                 };
1471
1472                                 cpuss1_crit: cpuss1-crit {
1473                                         temperature = <110000>;
1474                                         hysteresis = <1000>;
1475                                         type = "critical";
1476                                 };
1477                         };
1478                 };
1479
1480                 mdm0-thermal {
1481                         polling-delay-passive = <0>;
1482                         polling-delay = <0>;
1483
1484                         thermal-sensors = <&tsens0 5>;
1485
1486                         trips {
1487                                 mdm0_alert0: trip-point0 {
1488                                         temperature = <90000>;
1489                                         hysteresis = <2000>;
1490                                         type = "passive";
1491                                 };
1492
1493                                 mdm0_alert1: trip-point1 {
1494                                         temperature = <95000>;
1495                                         hysteresis = <2000>;
1496                                         type = "passive";
1497                                 };
1498
1499                                 mdm0_crit: mdm0-crit {
1500                                         temperature = <110000>;
1501                                         hysteresis = <1000>;
1502                                         type = "critical";
1503                                 };
1504                         };
1505                 };
1506
1507                 mdm1-thermal {
1508                         polling-delay-passive = <0>;
1509                         polling-delay = <0>;
1510
1511                         thermal-sensors = <&tsens0 6>;
1512
1513                         trips {
1514                                 mdm1_alert0: trip-point0 {
1515                                         temperature = <90000>;
1516                                         hysteresis = <2000>;
1517                                         type = "passive";
1518                                 };
1519
1520                                 mdm1_alert1: trip-point1 {
1521                                         temperature = <95000>;
1522                                         hysteresis = <2000>;
1523                                         type = "passive";
1524                                 };
1525
1526                                 mdm1_crit: mdm1-crit {
1527                                         temperature = <110000>;
1528                                         hysteresis = <1000>;
1529                                         type = "critical";
1530                                 };
1531                         };
1532                 };
1533
1534                 gpu-thermal {
1535                         polling-delay-passive = <0>;
1536                         polling-delay = <0>;
1537
1538                         thermal-sensors = <&tsens0 7>;
1539
1540                         trips {
1541                                 gpu_alert0: trip-point0 {
1542                                         temperature = <90000>;
1543                                         hysteresis = <2000>;
1544                                         type = "passive";
1545                                 };
1546
1547                                 gpu_alert1: trip-point1 {
1548                                         temperature = <95000>;
1549                                         hysteresis = <2000>;
1550                                         type = "passive";
1551                                 };
1552
1553                                 gpu_crit: gpu-crit {
1554                                         temperature = <110000>;
1555                                         hysteresis = <1000>;
1556                                         type = "critical";
1557                                 };
1558                         };
1559                 };
1560
1561                 hm-center-thermal {
1562                         polling-delay-passive = <0>;
1563                         polling-delay = <0>;
1564
1565                         thermal-sensors = <&tsens0 8>;
1566
1567                         trips {
1568                                 hm_center_alert0: trip-point0 {
1569                                         temperature = <90000>;
1570                                         hysteresis = <2000>;
1571                                         type = "passive";
1572                                 };
1573
1574                                 hm_center_alert1: trip-point1 {
1575                                         temperature = <95000>;
1576                                         hysteresis = <2000>;
1577                                         type = "passive";
1578                                 };
1579
1580                                 hm_center_crit: hm-center-crit {
1581                                         temperature = <110000>;
1582                                         hysteresis = <1000>;
1583                                         type = "critical";
1584                                 };
1585                         };
1586                 };
1587
1588                 camera-thermal {
1589                         polling-delay-passive = <0>;
1590                         polling-delay = <0>;
1591
1592                         thermal-sensors = <&tsens0 9>;
1593
1594                         trips {
1595                                 camera_alert0: trip-point0 {
1596                                         temperature = <90000>;
1597                                         hysteresis = <2000>;
1598                                         type = "passive";
1599                                 };
1600
1601                                 camera_alert1: trip-point1 {
1602                                         temperature = <95000>;
1603                                         hysteresis = <2000>;
1604                                         type = "passive";
1605                                 };
1606
1607                                 camera_crit: camera-crit {
1608                                         temperature = <110000>;
1609                                         hysteresis = <1000>;
1610                                         type = "critical";
1611                                 };
1612                         };
1613                 };
1614         };
1615
1616         timer {
1617                 compatible = "arm,armv8-timer";
1618                 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1619                              <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1620                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1621                              <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1622         };
1623 };