1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
28 compatible = "fixed-clock";
30 clock-frequency = <19200000>;
31 clock-output-names = "xo_board";
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
37 clock-frequency = <32768>;
38 clock-output-names = "sleep_clk";
48 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
61 compatible = "arm,cortex-a53";
63 enable-method = "psci";
64 next-level-cache = <&L2_0>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 next-level-cache = <&L2_0>;
77 compatible = "arm,cortex-a53";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
85 compatible = "arm,cortex-a57";
87 enable-method = "psci";
88 next-level-cache = <&L2_1>;
98 compatible = "arm,cortex-a57";
100 enable-method = "psci";
101 next-level-cache = <&L2_1>;
106 compatible = "arm,cortex-a57";
108 enable-method = "psci";
109 next-level-cache = <&L2_1>;
114 compatible = "arm,cortex-a57";
116 enable-method = "psci";
117 next-level-cache = <&L2_1>;
161 compatible = "qcom,scm-msm8994", "qcom,scm";
166 device_type = "memory";
167 /* We expect the bootloader to fill in the reg */
168 reg = <0 0x80000000 0 0>;
172 compatible = "arm,cortex-a53-pmu";
173 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
177 compatible = "arm,psci-0.2";
182 #address-cells = <2>;
186 dfps_data_mem: dfps_data_mem@3400000 {
187 reg = <0 0x03400000 0 0x1000>;
191 cont_splash_mem: memory@3401000 {
192 reg = <0 0x03401000 0 0x2200000>;
196 smem_mem: smem_region@6a00000 {
197 reg = <0 0x06a00000 0 0x200000>;
201 mpss_mem: memory@7000000 {
202 reg = <0 0x07000000 0 0x5a00000>;
206 peripheral_region: memory@ca00000 {
207 reg = <0 0x0ca00000 0 0x1f00000>;
211 rmtfs_mem: memory@c6400000 {
212 compatible = "qcom,rmtfs-mem";
213 reg = <0 0xc6400000 0 0x180000>;
216 qcom,client-id = <1>;
219 mba_mem: memory@c6700000 {
220 reg = <0 0xc6700000 0 0x100000>;
224 audio_mem: memory@c7000000 {
225 reg = <0 0xc7000000 0 0x800000>;
229 adsp_mem: memory@c9400000 {
230 reg = <0 0xc9400000 0 0x3f00000>;
235 reg = <0 0x06c00000 0 0x400000>;
241 compatible = "qcom,smd";
243 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
244 qcom,ipc = <&apcs 8 0>;
245 qcom,smd-edge = <15>;
246 qcom,remote-pid = <6>;
248 rpm_requests: rpm-requests {
249 compatible = "qcom,rpm-msm8994";
250 qcom,smd-channels = "rpm_requests";
252 rpmcc: clock-controller {
253 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
257 rpmpd: power-controller {
258 compatible = "qcom,msm8994-rpmpd";
259 #power-domain-cells = <1>;
260 operating-points-v2 = <&rpmpd_opp_table>;
262 rpmpd_opp_table: opp-table {
263 compatible = "operating-points-v2";
265 rpmpd_opp_ret: opp1 {
268 rpmpd_opp_svs_krait: opp2 {
271 rpmpd_opp_svs_soc: opp3 {
274 rpmpd_opp_nom: opp4 {
277 rpmpd_opp_turbo: opp5 {
280 rpmpd_opp_super_turbo: opp6 {
290 compatible = "qcom,smem";
291 memory-region = <&smem_mem>;
292 qcom,rpm-msg-ram = <&rpm_msg_ram>;
293 hwlocks = <&tcsr_mutex 3>;
297 compatible = "qcom,smp2p";
298 qcom,smem = <443>, <429>;
300 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
302 qcom,ipc = <&apcs 8 10>;
304 qcom,local-pid = <0>;
305 qcom,remote-pid = <2>;
307 adsp_smp2p_out: master-kernel {
308 qcom,entry-name = "master-kernel";
309 #qcom,smem-state-cells = <1>;
312 adsp_smp2p_in: slave-kernel {
313 qcom,entry-name = "slave-kernel";
315 interrupt-controller;
316 #interrupt-cells = <2>;
321 compatible = "qcom,smp2p";
322 qcom,smem = <435>, <428>;
324 interrupt-parent = <&intc>;
325 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
327 qcom,ipc = <&apcs 8 14>;
329 qcom,local-pid = <0>;
330 qcom,remote-pid = <1>;
332 modem_smp2p_out: master-kernel {
333 qcom,entry-name = "master-kernel";
334 #qcom,smem-state-cells = <1>;
337 modem_smp2p_in: slave-kernel {
338 qcom,entry-name = "slave-kernel";
340 interrupt-controller;
341 #interrupt-cells = <2>;
346 #address-cells = <1>;
348 ranges = <0 0 0 0xffffffff>;
349 compatible = "simple-bus";
351 intc: interrupt-controller@f9000000 {
352 compatible = "qcom,msm-qgic2";
353 interrupt-controller;
354 #interrupt-cells = <3>;
355 reg = <0xf9000000 0x1000>,
359 apcs: mailbox@f900d000 {
360 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
361 reg = <0xf900d000 0x2000>;
366 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
367 reg = <0xf9017000 0x1000>;
368 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
369 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
370 clocks = <&sleep_clk>;
375 #address-cells = <1>;
378 compatible = "arm,armv7-timer-mem";
379 reg = <0xf9020000 0x1000>;
383 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
385 reg = <0xf9021000 0x1000>,
391 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
392 reg = <0xf9023000 0x1000>;
398 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
399 reg = <0xf9024000 0x1000>;
405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
406 reg = <0xf9025000 0x1000>;
412 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
413 reg = <0xf9026000 0x1000>;
419 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
420 reg = <0xf9027000 0x1000>;
426 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
427 reg = <0xf9028000 0x1000>;
433 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
434 reg = <0xf92f8800 0x400>;
435 #address-cells = <1>;
439 clocks = <&gcc GCC_USB30_MASTER_CLK>,
440 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
441 <&gcc GCC_USB30_SLEEP_CLK>,
442 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
443 clock-names = "core",
448 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
449 <&gcc GCC_USB30_MASTER_CLK>;
450 assigned-clock-rates = <19200000>, <120000000>;
452 power-domains = <&gcc USB30_GDSC>;
453 qcom,select-utmi-as-pipe-clk;
456 compatible = "snps,dwc3";
457 reg = <0xf9200000 0xcc00>;
458 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
459 snps,dis_u2_susphy_quirk;
460 snps,dis_enblslpm_quirk;
461 maximum-speed = "high-speed";
462 dr_mode = "peripheral";
466 sdhc1: mmc@f9824900 {
467 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
468 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
469 reg-names = "hc", "core";
471 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
473 interrupt-names = "hc_irq", "pwr_irq";
475 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
476 <&gcc GCC_SDCC1_APPS_CLK>,
478 clock-names = "iface", "core", "xo";
480 pinctrl-names = "default", "sleep";
481 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
482 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
489 sdhc2: mmc@f98a4900 {
490 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
491 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
492 reg-names = "hc", "core";
494 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
496 interrupt-names = "hc_irq", "pwr_irq";
498 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
499 <&gcc GCC_SDCC2_APPS_CLK>,
501 clock-names = "iface", "core", "xo";
503 pinctrl-names = "default", "sleep";
504 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
505 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
507 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
512 blsp1_dma: dma-controller@f9904000 {
513 compatible = "qcom,bam-v1.7.0";
514 reg = <0xf9904000 0x19000>;
515 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
517 clock-names = "bam_clk";
520 qcom,controlled-remotely;
525 blsp1_uart2: serial@f991e000 {
526 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
527 reg = <0xf991e000 0x1000>;
528 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
529 clock-names = "core", "iface";
530 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
531 <&gcc GCC_BLSP1_AHB_CLK>;
532 pinctrl-names = "default", "sleep";
533 pinctrl-0 = <&blsp1_uart2_default>;
534 pinctrl-1 = <&blsp1_uart2_sleep>;
538 blsp1_i2c1: i2c@f9923000 {
539 compatible = "qcom,i2c-qup-v2.2.1";
540 reg = <0xf9923000 0x500>;
541 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
543 <&gcc GCC_BLSP1_AHB_CLK>;
544 clock-names = "core", "iface";
545 clock-frequency = <400000>;
546 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
547 dma-names = "tx", "rx";
548 pinctrl-names = "default", "sleep";
549 pinctrl-0 = <&i2c1_default>;
550 pinctrl-1 = <&i2c1_sleep>;
551 #address-cells = <1>;
556 blsp1_spi1: spi@f9923000 {
557 compatible = "qcom,spi-qup-v2.2.1";
558 reg = <0xf9923000 0x500>;
559 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
561 <&gcc GCC_BLSP1_AHB_CLK>;
562 clock-names = "core", "iface";
563 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
564 dma-names = "tx", "rx";
565 pinctrl-names = "default", "sleep";
566 pinctrl-0 = <&blsp1_spi1_default>;
567 pinctrl-1 = <&blsp1_spi1_sleep>;
568 #address-cells = <1>;
573 blsp1_i2c2: i2c@f9924000 {
574 compatible = "qcom,i2c-qup-v2.2.1";
575 reg = <0xf9924000 0x500>;
576 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
578 <&gcc GCC_BLSP1_AHB_CLK>;
579 clock-names = "core", "iface";
580 clock-frequency = <400000>;
581 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
582 dma-names = "tx", "rx";
583 pinctrl-names = "default", "sleep";
584 pinctrl-0 = <&i2c2_default>;
585 pinctrl-1 = <&i2c2_sleep>;
586 #address-cells = <1>;
591 /* I2C3 doesn't exist */
593 blsp1_i2c4: i2c@f9926000 {
594 compatible = "qcom,i2c-qup-v2.2.1";
595 reg = <0xf9926000 0x500>;
596 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
598 <&gcc GCC_BLSP1_AHB_CLK>;
599 clock-names = "core", "iface";
600 clock-frequency = <400000>;
601 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
602 dma-names = "tx", "rx";
603 pinctrl-names = "default", "sleep";
604 pinctrl-0 = <&i2c4_default>;
605 pinctrl-1 = <&i2c4_sleep>;
606 #address-cells = <1>;
611 blsp1_i2c5: i2c@f9927000 {
612 compatible = "qcom,i2c-qup-v2.2.1";
613 reg = <0xf9927000 0x500>;
614 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
616 <&gcc GCC_BLSP1_AHB_CLK>;
617 clock-names = "core", "iface";
618 clock-frequency = <400000>;
619 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
620 dma-names = "tx", "rx";
621 pinctrl-names = "default", "sleep";
622 pinctrl-0 = <&i2c5_default>;
623 pinctrl-1 = <&i2c5_sleep>;
624 #address-cells = <1>;
629 blsp1_i2c6: i2c@f9928000 {
630 compatible = "qcom,i2c-qup-v2.2.1";
631 reg = <0xf9928000 0x500>;
632 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
634 <&gcc GCC_BLSP1_AHB_CLK>;
635 clock-names = "core", "iface";
636 clock-frequency = <400000>;
637 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
638 dma-names = "tx", "rx";
639 pinctrl-names = "default", "sleep";
640 pinctrl-0 = <&i2c6_default>;
641 pinctrl-1 = <&i2c6_sleep>;
642 #address-cells = <1>;
647 blsp2_dma: dma-controller@f9944000 {
648 compatible = "qcom,bam-v1.7.0";
649 reg = <0xf9944000 0x19000>;
650 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
652 clock-names = "bam_clk";
655 qcom,controlled-remotely;
660 blsp2_uart2: serial@f995e000 {
661 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
662 reg = <0xf995e000 0x1000>;
663 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
664 clock-names = "core", "iface";
665 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
666 <&gcc GCC_BLSP2_AHB_CLK>;
667 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
668 dma-names = "tx", "rx";
669 pinctrl-names = "default", "sleep";
670 pinctrl-0 = <&blsp2_uart2_default>;
671 pinctrl-1 = <&blsp2_uart2_sleep>;
675 blsp2_i2c1: i2c@f9963000 {
676 compatible = "qcom,i2c-qup-v2.2.1";
677 reg = <0xf9963000 0x500>;
678 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
680 <&gcc GCC_BLSP2_AHB_CLK>;
681 clock-names = "core", "iface";
682 clock-frequency = <400000>;
683 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
684 dma-names = "tx", "rx";
685 pinctrl-names = "default", "sleep";
686 pinctrl-0 = <&i2c7_default>;
687 pinctrl-1 = <&i2c7_sleep>;
688 #address-cells = <1>;
693 blsp2_spi4: spi@f9966000 {
694 compatible = "qcom,spi-qup-v2.2.1";
695 reg = <0xf9966000 0x500>;
696 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
698 <&gcc GCC_BLSP2_AHB_CLK>;
699 clock-names = "core", "iface";
700 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>;
701 dma-names = "tx", "rx";
702 pinctrl-names = "default", "sleep";
703 pinctrl-0 = <&blsp2_spi10_default>;
704 pinctrl-1 = <&blsp2_spi10_sleep>;
705 #address-cells = <1>;
710 blsp2_i2c5: i2c@f9967000 {
711 compatible = "qcom,i2c-qup-v2.2.1";
712 reg = <0xf9967000 0x500>;
713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
715 <&gcc GCC_BLSP2_AHB_CLK>;
716 clock-names = "core", "iface";
717 clock-frequency = <355000>;
718 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
719 dma-names = "tx", "rx";
720 pinctrl-names = "default", "sleep";
721 pinctrl-0 = <&i2c11_default>;
722 pinctrl-1 = <&i2c11_sleep>;
723 #address-cells = <1>;
728 gcc: clock-controller@fc400000 {
729 compatible = "qcom,gcc-msm8994";
732 #power-domain-cells = <1>;
733 reg = <0xfc400000 0x2000>;
735 clock-names = "xo", "sleep";
736 clocks = <&xo_board>, <&sleep_clk>;
739 rpm_msg_ram: sram@fc428000 {
740 compatible = "qcom,rpm-msg-ram";
741 reg = <0xfc428000 0x4000>;
745 compatible = "qcom,pshold";
746 reg = <0xfc4ab000 0x4>;
749 spmi_bus: spmi@fc4cf000 {
750 compatible = "qcom,spmi-pmic-arb";
751 reg = <0xfc4cf000 0x1000>,
754 reg-names = "core", "intr", "cnfg";
755 interrupt-names = "periph_irq";
756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
759 #address-cells = <2>;
761 interrupt-controller;
762 #interrupt-cells = <4>;
765 tcsr_mutex: hwlock@fd484000 {
766 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
767 reg = <0xfd484000 0x1000>;
771 tlmm: pinctrl@fd510000 {
772 compatible = "qcom,msm8994-pinctrl";
773 reg = <0xfd510000 0x4000>;
774 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
776 gpio-ranges = <&tlmm 0 0 146>;
778 interrupt-controller;
779 #interrupt-cells = <2>;
781 blsp1_uart2_default: blsp1-uart2-default-state {
782 pins = "gpio4", "gpio5";
783 function = "blsp_uart2";
784 drive-strength = <16>;
788 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
789 pins = "gpio4", "gpio5";
791 drive-strength = <2>;
795 blsp2_uart2_default: blsp2-uart2-default-state {
796 pins = "gpio45", "gpio46", "gpio47", "gpio48";
797 function = "blsp_uart8";
798 drive-strength = <16>;
802 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
803 pins = "gpio45", "gpio46", "gpio47", "gpio48";
805 drive-strength = <2>;
809 i2c1_default: i2c1-default-state {
810 pins = "gpio2", "gpio3";
811 function = "blsp_i2c1";
812 drive-strength = <2>;
816 i2c1_sleep: i2c1-sleep-state {
817 pins = "gpio2", "gpio3";
819 drive-strength = <2>;
823 i2c2_default: i2c2-default-state {
824 pins = "gpio6", "gpio7";
825 function = "blsp_i2c2";
826 drive-strength = <2>;
830 i2c2_sleep: i2c2-sleep-state {
831 pins = "gpio6", "gpio7";
833 drive-strength = <2>;
837 i2c4_default: i2c4-default-state {
838 pins = "gpio19", "gpio20";
839 function = "blsp_i2c4";
840 drive-strength = <2>;
844 i2c4_sleep: i2c4-sleep-state {
845 pins = "gpio19", "gpio20";
847 drive-strength = <2>;
851 i2c5_default: i2c5-default-state {
852 pins = "gpio23", "gpio24";
853 function = "blsp_i2c5";
854 drive-strength = <2>;
858 i2c5_sleep: i2c5-sleep-state {
859 pins = "gpio23", "gpio24";
861 drive-strength = <2>;
865 i2c6_default: i2c6-default-state {
866 pins = "gpio28", "gpio27";
867 function = "blsp_i2c6";
868 drive-strength = <2>;
872 i2c6_sleep: i2c6-sleep-state {
873 pins = "gpio28", "gpio27";
875 drive-strength = <2>;
879 i2c7_default: i2c7-default-state {
880 pins = "gpio44", "gpio43";
881 function = "blsp_i2c7";
882 drive-strength = <2>;
886 i2c7_sleep: i2c7-sleep-state {
887 pins = "gpio44", "gpio43";
889 drive-strength = <2>;
893 blsp2_spi10_default: blsp2-spi10-default-state {
895 pins = "gpio53", "gpio54", "gpio55";
896 function = "blsp_spi10";
897 drive-strength = <10>;
904 drive-strength = <2>;
909 blsp2_spi10_sleep: blsp2-spi10-sleep-state {
910 pins = "gpio53", "gpio54", "gpio55";
912 drive-strength = <2>;
916 i2c11_default: i2c11-default-state {
917 pins = "gpio83", "gpio84";
918 function = "blsp_i2c11";
919 drive-strength = <2>;
923 i2c11_sleep: i2c11-sleep-state {
924 pins = "gpio83", "gpio84";
926 drive-strength = <2>;
930 blsp1_spi1_default: blsp1-spi1-default-state {
932 pins = "gpio0", "gpio1", "gpio3";
933 function = "blsp_spi1";
934 drive-strength = <10>;
941 drive-strength = <2>;
946 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
947 pins = "gpio0", "gpio1", "gpio3";
949 drive-strength = <2>;
953 sdc1_clk_on: clk-on-state {
956 drive-strength = <16>;
959 sdc1_clk_off: clk-off-state {
962 drive-strength = <2>;
965 sdc1_cmd_on: cmd-on-state {
968 drive-strength = <8>;
971 sdc1_cmd_off: cmd-off-state {
974 drive-strength = <2>;
977 sdc1_data_on: data-on-state {
980 drive-strength = <8>;
983 sdc1_data_off: data-off-state {
986 drive-strength = <2>;
989 sdc1_rclk_on: rclk-on-state {
994 sdc1_rclk_off: rclk-off-state {
999 sdc2_clk_on: sdc2-clk-on-state {
1002 drive-strength = <10>;
1005 sdc2_clk_off: sdc2-clk-off-state {
1008 drive-strength = <2>;
1011 sdc2_cmd_on: sdc2-cmd-on-state {
1014 drive-strength = <10>;
1017 sdc2_cmd_off: sdc2-cmd-off-state {
1020 drive-strength = <2>;
1023 sdc2_data_on: sdc2-data-on-state {
1026 drive-strength = <10>;
1029 sdc2_data_off: sdc2-data-off-state {
1032 drive-strength = <2>;
1036 mmcc: clock-controller@fd8c0000 {
1037 compatible = "qcom,mmcc-msm8994";
1038 reg = <0xfd8c0000 0x5200>;
1041 #power-domain-cells = <1>;
1046 "oxili_gfx3d_clk_src",
1052 clocks = <&xo_board>,
1053 <&gcc GPLL0_OUT_MMSSCC>,
1054 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>,
1055 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>,
1062 assigned-clocks = <&mmcc MMPLL0_PLL>,
1067 assigned-clock-rates = <800000000>,
1074 ocmem: sram@fdd00000 {
1075 compatible = "qcom,msm8974-ocmem";
1076 reg = <0xfdd00000 0x2000>,
1077 <0xfec00000 0x200000>;
1078 reg-names = "ctrl", "mem";
1079 ranges = <0 0xfec00000 0x200000>;
1080 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1081 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1082 clock-names = "core", "iface";
1084 #address-cells = <1>;
1087 gmu_sram: gmu-sram@0 {
1088 reg = <0x0 0x180000>;
1094 compatible = "arm,armv8-timer";
1095 interrupts = <GIC_PPI 2 0xff08>,
1101 vph_pwr: vph-pwr-regulator {
1102 compatible = "regulator-fixed";
1103 regulator-name = "vph_pwr";
1105 regulator-min-microvolt = <3600000>;
1106 regulator-max-microvolt = <3600000>;
1108 regulator-always-on;