1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/power/qcom-rpmpd.h>
9 #include <dt-bindings/soc/qcom,apr.h>
10 #include <dt-bindings/sound/qcom,q6afe.h>
11 #include <dt-bindings/sound/qcom,q6asm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&intc>;
23 sleep_clk: sleep-clk {
24 compatible = "fixed-clock";
26 clock-frequency = <32768>;
30 compatible = "fixed-clock";
32 clock-frequency = <19200000>;
33 clock-output-names = "xo";
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 capacity-dmips-mhz = <1024>;
47 next-level-cache = <&L2_0>;
53 compatible = "arm,cortex-a53";
55 enable-method = "psci";
56 capacity-dmips-mhz = <1024>;
57 next-level-cache = <&L2_0>;
63 compatible = "arm,cortex-a53";
65 enable-method = "psci";
66 capacity-dmips-mhz = <1024>;
67 next-level-cache = <&L2_0>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
83 compatible = "arm,cortex-a53";
85 enable-method = "psci";
86 capacity-dmips-mhz = <1024>;
87 next-level-cache = <&L2_1>;
93 compatible = "arm,cortex-a53";
95 enable-method = "psci";
96 capacity-dmips-mhz = <1024>;
97 next-level-cache = <&L2_1>;
103 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&L2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a53";
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
117 next-level-cache = <&L2_1>;
118 #cooling-cells = <2>;
154 compatible = "cache";
160 compatible = "cache";
168 compatible = "qcom,scm-msm8953", "qcom,scm";
169 clocks = <&gcc GCC_CRYPTO_CLK>,
170 <&gcc GCC_CRYPTO_AXI_CLK>,
171 <&gcc GCC_CRYPTO_AHB_CLK>;
172 clock-names = "core", "bus", "iface";
178 device_type = "memory";
179 /* We expect the bootloader to fill in the reg */
184 compatible = "arm,cortex-a53-pmu";
185 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
189 compatible = "arm,psci-1.0";
194 #address-cells = <2>;
198 zap_shader_region: zap@81800000 {
199 compatible = "shared-dma-pool";
200 reg = <0x0 0x81800000 0x0 0x2000>;
204 qseecom_mem: qseecom@85b00000 {
205 reg = <0x0 0x85b00000 0x0 0x800000>;
209 smem_mem: smem@86300000 {
210 compatible = "qcom,smem";
211 reg = <0x0 0x86300000 0x0 0x100000>;
212 qcom,rpm-msg-ram = <&rpm_msg_ram>;
213 hwlocks = <&tcsr_mutex 3>;
218 reg = <0x0 0x86400000 0x0 0x400000>;
222 mpss_mem: mpss@86c00000 {
223 reg = <0x0 0x86c00000 0x0 0x6a00000>;
227 adsp_fw_mem: adsp@8d600000 {
228 reg = <0x0 0x8d600000 0x0 0x1100000>;
232 wcnss_fw_mem: wcnss@8e700000 {
233 reg = <0x0 0x8e700000 0x0 0x700000>;
237 dfps_data_mem: dfps-data@90000000 {
238 reg = <0 0x90000000 0 0x1000>;
242 cont_splash_mem: cont-splash@90001000 {
243 reg = <0x0 0x90001000 0x0 0x13ff000>;
247 venus_mem: venus@91400000 {
248 reg = <0x0 0x91400000 0x0 0x700000>;
252 mba_mem: mba@92000000 {
253 reg = <0x0 0x92000000 0x0 0x100000>;
258 compatible = "qcom,rmtfs-mem";
259 reg = <0x0 0xf2d00000 0x0 0x180000>;
262 qcom,client-id = <1>;
267 compatible = "qcom,smd";
270 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
271 qcom,ipc = <&apcs 8 0>;
272 qcom,smd-edge = <15>;
274 rpm_requests: rpm-requests {
275 compatible = "qcom,rpm-msm8953";
276 qcom,smd-channels = "rpm_requests";
278 rpmcc: clock-controller {
279 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
280 clocks = <&xo_board>;
285 rpmpd: power-controller {
286 compatible = "qcom,msm8953-rpmpd";
287 #power-domain-cells = <1>;
288 operating-points-v2 = <&rpmpd_opp_table>;
290 rpmpd_opp_table: opp-table {
291 compatible = "operating-points-v2";
293 rpmpd_opp_ret: opp1 {
294 opp-level = <RPM_SMD_LEVEL_RETENTION>;
297 rpmpd_opp_ret_plus: opp2 {
298 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
301 rpmpd_opp_min_svs: opp3 {
302 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
305 rpmpd_opp_low_svs: opp4 {
306 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
309 rpmpd_opp_svs: opp5 {
310 opp-level = <RPM_SMD_LEVEL_SVS>;
313 rpmpd_opp_svs_plus: opp6 {
314 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
317 rpmpd_opp_nom: opp7 {
318 opp-level = <RPM_SMD_LEVEL_NOM>;
321 rpmpd_opp_nom_plus: opp8 {
322 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
325 rpmpd_opp_turbo: opp9 {
326 opp-level = <RPM_SMD_LEVEL_TURBO>;
335 compatible = "qcom,smp2p";
336 qcom,smem = <443>, <429>;
338 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <2>;
345 smp2p_adsp_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
350 smp2p_adsp_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
353 interrupt-controller;
354 #interrupt-cells = <2>;
359 compatible = "qcom,smp2p";
360 qcom,smem = <435>, <428>;
362 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
364 qcom,ipc = <&apcs 8 14>;
366 qcom,local-pid = <0>;
367 qcom,remote-pid = <1>;
369 smp2p_modem_out: master-kernel {
370 qcom,entry-name = "master-kernel";
372 #qcom,smem-state-cells = <1>;
375 smp2p_modem_in: slave-kernel {
376 qcom,entry-name = "slave-kernel";
378 interrupt-controller;
379 #interrupt-cells = <2>;
384 compatible = "qcom,smp2p";
385 qcom,smem = <451>, <431>;
387 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
389 qcom,ipc = <&apcs 8 18>;
391 qcom,local-pid = <0>;
392 qcom,remote-pid = <4>;
394 smp2p_wcnss_out: master-kernel {
395 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
400 smp2p_wcnss_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
409 compatible = "qcom,smsm";
411 #address-cells = <1>;
414 qcom,ipc-1 = <&apcs 8 13>;
415 qcom,ipc-3 = <&apcs 8 19>;
420 #qcom,smem-state-cells = <1>;
423 modem_smsm: modem@1 {
425 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
431 wcnss_smsm: wcnss@6 {
433 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
441 #address-cells = <1>;
443 ranges = <0 0 0 0xffffffff>;
444 compatible = "simple-bus";
446 rpm_msg_ram: sram@60000 {
447 compatible = "qcom,rpm-msg-ram";
448 reg = <0x00060000 0x8000>;
451 hsusb_phy: phy@79000 {
452 compatible = "qcom,msm8953-qusb2-phy";
453 reg = <0x00079000 0x180>;
456 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
457 <&gcc GCC_QUSB_REF_CLK>;
458 clock-names = "cfg_ahb", "ref";
460 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
462 resets = <&gcc GCC_QUSB2_PHY_BCR>;
468 compatible = "qcom,prng";
469 reg = <0x000e3000 0x1000>;
470 clocks = <&gcc GCC_PRNG_AHB_CLK>;
471 clock-names = "core";
474 tsens0: thermal-sensor@4a9000 {
475 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
476 reg = <0x004a9000 0x1000>, /* TM */
477 <0x004a8000 0x1000>; /* SROT */
478 #qcom,sensors = <16>;
479 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-names = "uplow", "critical";
482 #thermal-sensor-cells = <1>;
486 compatible = "qcom,pshold";
487 reg = <0x004ab000 0x4>;
490 tlmm: pinctrl@1000000 {
491 compatible = "qcom,msm8953-pinctrl";
492 reg = <0x01000000 0x300000>;
493 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
495 gpio-ranges = <&tlmm 0 0 142>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
500 uart_console_active: uart-console-active-state {
501 pins = "gpio4", "gpio5";
502 function = "blsp_uart2";
503 drive-strength = <2>;
507 uart_console_sleep: uart-console-sleep-state {
508 pins = "gpio4", "gpio5";
509 function = "blsp_uart2";
510 drive-strength = <2>;
514 sdc1_clk_on: sdc1-clk-on-state {
517 drive-strength = <16>;
520 sdc1_clk_off: sdc1-clk-off-state {
523 drive-strength = <2>;
526 sdc1_cmd_on: sdc1-cmd-on-state {
529 drive-strength = <10>;
532 sdc1_cmd_off: sdc1-cmd-off-state {
535 drive-strength = <2>;
538 sdc1_data_on: sdc1-data-on-state {
541 drive-strength = <10>;
544 sdc1_data_off: sdc1-data-off-state {
547 drive-strength = <2>;
550 sdc1_rclk_on: sdc1-rclk-on-state {
555 sdc1_rclk_off: sdc1-rclk-off-state {
560 sdc2_clk_on: sdc2-clk-on-state {
562 drive-strength = <16>;
566 sdc2_clk_off: sdc2-clk-off-state {
569 drive-strength = <2>;
572 sdc2_cmd_on: sdc2-cmd-on-state {
575 drive-strength = <10>;
578 sdc2_cmd_off: sdc2-cmd-off-state {
581 drive-strength = <2>;
584 sdc2_data_on: sdc2-data-on-state {
587 drive-strength = <10>;
590 sdc2_data_off: sdc2-data-off-state {
593 drive-strength = <2>;
596 sdc2_cd_on: cd-on-state {
599 drive-strength = <2>;
603 sdc2_cd_off: cd-off-state {
606 drive-strength = <2>;
610 gpio_key_default: gpio-key-default-state {
613 drive-strength = <2>;
617 i2c_1_default: i2c-1-default-state {
618 pins = "gpio2", "gpio3";
619 function = "blsp_i2c1";
620 drive-strength = <2>;
624 i2c_1_sleep: i2c-1-sleep-state {
625 pins = "gpio2", "gpio3";
627 drive-strength = <2>;
631 i2c_2_default: i2c-2-default-state {
632 pins = "gpio6", "gpio7";
633 function = "blsp_i2c2";
634 drive-strength = <2>;
638 i2c_2_sleep: i2c-2-sleep-state {
639 pins = "gpio6", "gpio7";
641 drive-strength = <2>;
645 i2c_3_default: i2c-3-default-state {
646 pins = "gpio10", "gpio11";
647 function = "blsp_i2c3";
648 drive-strength = <2>;
652 i2c_3_sleep: i2c-3-sleep-state {
653 pins = "gpio10", "gpio11";
655 drive-strength = <2>;
659 i2c_4_default: i2c-4-default-state {
660 pins = "gpio14", "gpio15";
661 function = "blsp_i2c4";
662 drive-strength = <2>;
666 i2c_4_sleep: i2c-4-sleep-state {
667 pins = "gpio14", "gpio15";
669 drive-strength = <2>;
673 i2c_5_default: i2c-5-default-state {
674 pins = "gpio18", "gpio19";
675 function = "blsp_i2c5";
676 drive-strength = <2>;
680 i2c_5_sleep: i2c-5-sleep-state {
681 pins = "gpio18", "gpio19";
683 drive-strength = <2>;
687 i2c_6_default: i2c-6-default-state {
688 pins = "gpio22", "gpio23";
689 function = "blsp_i2c6";
690 drive-strength = <2>;
694 i2c_6_sleep: i2c-6-sleep-state {
695 pins = "gpio22", "gpio23";
697 drive-strength = <2>;
701 i2c_7_default: i2c-7-default-state {
702 pins = "gpio135", "gpio136";
703 function = "blsp_i2c7";
704 drive-strength = <2>;
708 i2c_7_sleep: i2c-7-sleep-state {
709 pins = "gpio135", "gpio136";
711 drive-strength = <2>;
715 i2c_8_default: i2c-8-default-state {
716 pins = "gpio98", "gpio99";
717 function = "blsp_i2c8";
718 drive-strength = <2>;
722 i2c_8_sleep: i2c-8-sleep-state {
723 pins = "gpio98", "gpio99";
725 drive-strength = <2>;
729 wcnss_pin_a: wcnss-active-state {
733 function = "wcss_wlan2";
734 drive-strength = <6>;
740 function = "wcss_wlan1";
741 drive-strength = <6>;
747 function = "wcss_wlan0";
748 drive-strength = <6>;
753 pins = "gpio79", "gpio80";
754 function = "wcss_wlan";
755 drive-strength = <6>;
761 gcc: clock-controller@1800000 {
762 compatible = "qcom,gcc-msm8953";
763 reg = <0x01800000 0x80000>;
766 #power-domain-cells = <1>;
767 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
781 tcsr_mutex: hwlock@1905000 {
782 compatible = "qcom,tcsr-mutex";
783 reg = <0x01905000 0x20000>;
787 tcsr: syscon@1937000 {
788 compatible = "qcom,tcsr-msm8953", "syscon";
789 reg = <0x01937000 0x30000>;
792 tcsr_phy_clk_scheme_sel: syscon@193f044 {
793 compatible = "qcom,tcsr-msm8953", "syscon";
794 reg = <0x0193f044 0x4>;
797 mdss: display-subsystem@1a00000 {
798 compatible = "qcom,mdss";
800 reg = <0x01a00000 0x1000>,
802 reg-names = "mdss_phys",
805 power-domains = <&gcc MDSS_GDSC>;
806 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
808 interrupt-controller;
809 #interrupt-cells = <1>;
811 clocks = <&gcc GCC_MDSS_AHB_CLK>,
812 <&gcc GCC_MDSS_AXI_CLK>,
813 <&gcc GCC_MDSS_VSYNC_CLK>,
814 <&gcc GCC_MDSS_MDP_CLK>;
815 clock-names = "iface",
820 #address-cells = <1>;
826 mdp: display-controller@1a01000 {
827 compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
828 reg = <0x01a01000 0x89000>;
829 reg-names = "mdp_phys";
831 interrupt-parent = <&mdss>;
834 power-domains = <&gcc MDSS_GDSC>;
836 clocks = <&gcc GCC_MDSS_AHB_CLK>,
837 <&gcc GCC_MDSS_AXI_CLK>,
838 <&gcc GCC_MDSS_MDP_CLK>,
839 <&gcc GCC_MDSS_VSYNC_CLK>;
840 clock-names = "iface",
845 iommus = <&apps_iommu 0x15>;
848 #address-cells = <1>;
853 mdp5_intf1_out: endpoint {
854 remote-endpoint = <&mdss_dsi0_in>;
860 mdp5_intf2_out: endpoint {
861 remote-endpoint = <&mdss_dsi1_in>;
867 mdss_dsi0: dsi@1a94000 {
868 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
869 reg = <0x01a94000 0x400>;
870 reg-names = "dsi_ctrl";
872 interrupt-parent = <&mdss>;
875 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
876 <&gcc PCLK0_CLK_SRC>;
877 assigned-clock-parents = <&mdss_dsi0_phy 0>,
880 clocks = <&gcc GCC_MDSS_MDP_CLK>,
881 <&gcc GCC_MDSS_AHB_CLK>,
882 <&gcc GCC_MDSS_AXI_CLK>,
883 <&gcc GCC_MDSS_BYTE0_CLK>,
884 <&gcc GCC_MDSS_PCLK0_CLK>,
885 <&gcc GCC_MDSS_ESC0_CLK>;
886 clock-names = "mdp_core",
893 phys = <&mdss_dsi0_phy>;
895 #address-cells = <1>;
901 #address-cells = <1>;
906 mdss_dsi0_in: endpoint {
907 remote-endpoint = <&mdp5_intf1_out>;
913 mdss_dsi0_out: endpoint {
919 mdss_dsi0_phy: phy@1a94400 {
920 compatible = "qcom,dsi-phy-14nm-8953";
921 reg = <0x01a94400 0x100>,
924 reg-names = "dsi_phy",
931 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
932 clock-names = "iface", "ref";
937 mdss_dsi1: dsi@1a96000 {
938 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
939 reg = <0x01a96000 0x400>;
940 reg-names = "dsi_ctrl";
942 interrupt-parent = <&mdss>;
945 assigned-clocks = <&gcc BYTE1_CLK_SRC>,
946 <&gcc PCLK1_CLK_SRC>;
947 assigned-clock-parents = <&mdss_dsi1_phy 0>,
950 clocks = <&gcc GCC_MDSS_MDP_CLK>,
951 <&gcc GCC_MDSS_AHB_CLK>,
952 <&gcc GCC_MDSS_AXI_CLK>,
953 <&gcc GCC_MDSS_BYTE1_CLK>,
954 <&gcc GCC_MDSS_PCLK1_CLK>,
955 <&gcc GCC_MDSS_ESC1_CLK>;
956 clock-names = "mdp_core",
963 phys = <&mdss_dsi1_phy>;
968 #address-cells = <1>;
973 mdss_dsi1_in: endpoint {
974 remote-endpoint = <&mdp5_intf2_out>;
980 mdss_dsi1_out: endpoint {
986 mdss_dsi1_phy: phy@1a96400 {
987 compatible = "qcom,dsi-phy-14nm-8953";
988 reg = <0x01a96400 0x100>,
991 reg-names = "dsi_phy",
998 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
999 clock-names = "iface", "ref";
1001 status = "disabled";
1005 apps_iommu: iommu@1e20000 {
1006 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
1007 ranges = <0 0x01e20000 0x20000>;
1009 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1010 <&gcc GCC_APSS_TCU_ASYNC_CLK>;
1011 clock-names = "iface", "bus";
1013 qcom,iommu-secure-id = <17>;
1015 #address-cells = <1>;
1021 compatible = "qcom,msm-iommu-v1-ns";
1022 reg = <0x14000 0x1000>;
1023 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1028 compatible = "qcom,msm-iommu-v1-ns";
1029 reg = <0x15000 0x1000>;
1030 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1035 compatible = "qcom,msm-iommu-v1-ns";
1036 reg = <0x16000 0x1000>;
1037 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1041 spmi_bus: spmi@200f000 {
1042 compatible = "qcom,spmi-pmic-arb";
1043 reg = <0x0200f000 0x1000>,
1044 <0x02400000 0x800000>,
1045 <0x02c00000 0x800000>,
1046 <0x03800000 0x200000>,
1047 <0x0200a000 0x2100>;
1048 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1049 interrupt-names = "periph_irq";
1050 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1053 interrupt-controller;
1055 #interrupt-cells = <4>;
1056 #address-cells = <2>;
1060 mpss: remoteproc@4080000 {
1061 compatible = "qcom,msm8953-mss-pil";
1062 reg = <0x04080000 0x100>,
1064 reg-names = "qdsp6", "rmb";
1066 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1067 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
1068 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
1069 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
1070 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>;
1071 interrupt-names = "wdog", "fatal", "ready",
1072 "handover", "stop-ack";
1074 power-domains = <&rpmpd MSM8953_VDDCX>,
1075 <&rpmpd MSM8953_VDDMX>,
1076 <&rpmpd MSM8953_VDDMD>;
1077 power-domain-names = "cx", "mx","mss";
1079 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1080 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1081 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1082 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1083 clock-names = "iface", "bus", "mem", "xo";
1085 qcom,smem-states = <&smp2p_modem_out 0>;
1086 qcom,smem-state-names = "stop";
1088 resets = <&gcc GCC_MSS_BCR>;
1089 reset-names = "mss_restart";
1091 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1093 status = "disabled";
1096 memory-region = <&mba_mem>;
1100 memory-region = <&mpss_mem>;
1104 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1106 qcom,smd-edge = <0>;
1107 qcom,ipc = <&apcs 8 12>;
1108 qcom,remote-pid = <1>;
1115 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
1116 reg = <0x070f8800 0x400>;
1117 #address-cells = <1>;
1121 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1125 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
1126 <&gcc GCC_USB30_MASTER_CLK>,
1127 <&gcc GCC_PCNOC_USB3_AXI_CLK>,
1128 <&gcc GCC_USB30_SLEEP_CLK>,
1129 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1130 clock-names = "cfg_noc",
1136 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1137 <&gcc GCC_USB30_MASTER_CLK>;
1138 assigned-clock-rates = <19200000>, <133330000>;
1140 power-domains = <&gcc USB30_GDSC>;
1142 qcom,select-utmi-as-pipe-clk;
1144 status = "disabled";
1146 usb3_dwc3: usb@7000000 {
1147 compatible = "snps,dwc3";
1148 reg = <0x07000000 0xcc00>;
1149 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1150 phys = <&hsusb_phy>;
1151 phy-names = "usb2-phy";
1153 snps,usb2-gadget-lpm-disable;
1154 snps,dis-u1-entry-quirk;
1155 snps,dis-u2-entry-quirk;
1156 snps,is-utmi-l1-suspend;
1157 snps,hird-threshold = /bits/ 8 <0x00>;
1159 maximum-speed = "high-speed";
1163 sdhc_1: mmc@7824900 {
1164 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1166 reg = <0x07824900 0x500>, <0x07824000 0x800>;
1167 reg-names = "hc", "core";
1169 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "hc_irq", "pwr_irq";
1173 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1174 <&gcc GCC_SDCC1_APPS_CLK>,
1175 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1176 clock-names = "iface", "core", "xo";
1178 power-domains = <&rpmpd MSM8953_VDDCX>;
1179 operating-points-v2 = <&sdhc1_opp_table>;
1181 pinctrl-names = "default", "sleep";
1182 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
1183 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
1191 status = "disabled";
1193 sdhc1_opp_table: opp-table-sdhc1 {
1194 compatible = "operating-points-v2";
1197 opp-hz = /bits/ 64 <25000000>;
1198 required-opps = <&rpmpd_opp_low_svs>;
1202 opp-hz = /bits/ 64 <50000000>;
1203 required-opps = <&rpmpd_opp_svs>;
1207 opp-hz = /bits/ 64 <100000000>;
1208 required-opps = <&rpmpd_opp_svs>;
1212 opp-hz = /bits/ 64 <192000000>;
1213 required-opps = <&rpmpd_opp_nom>;
1217 opp-hz = /bits/ 64 <384000000>;
1218 required-opps = <&rpmpd_opp_nom>;
1223 sdhc_2: mmc@7864900 {
1224 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
1226 reg = <0x07864900 0x500>, <0x07864000 0x800>;
1227 reg-names = "hc", "core";
1229 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1231 interrupt-names = "hc_irq", "pwr_irq";
1233 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1234 <&gcc GCC_SDCC2_APPS_CLK>,
1235 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1236 clock-names = "iface", "core", "xo";
1238 power-domains = <&rpmpd MSM8953_VDDCX>;
1239 operating-points-v2 = <&sdhc2_opp_table>;
1241 pinctrl-names = "default", "sleep";
1242 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
1243 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
1247 status = "disabled";
1249 sdhc2_opp_table: opp-table-sdhc2 {
1250 compatible = "operating-points-v2";
1253 opp-hz = /bits/ 64 <25000000>;
1254 required-opps = <&rpmpd_opp_low_svs>;
1258 opp-hz = /bits/ 64 <50000000>;
1259 required-opps = <&rpmpd_opp_svs>;
1263 opp-hz = /bits/ 64 <100000000>;
1264 required-opps = <&rpmpd_opp_svs>;
1268 opp-hz = /bits/ 64 <177770000>;
1269 required-opps = <&rpmpd_opp_nom>;
1273 opp-hz = /bits/ 64 <200000000>;
1274 required-opps = <&rpmpd_opp_nom>;
1279 blsp1_dma: dma-controller@7884000 {
1280 compatible = "qcom,bam-v1.7.0";
1281 reg = <0x07884000 0x1f000>;
1282 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1284 clock-names = "bam_clk";
1285 num-channels = <12>;
1289 qcom,controlled-remotely;
1292 uart_0: serial@78af000 {
1293 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1294 reg = <0x078af000 0x200>;
1295 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
1297 <&gcc GCC_BLSP1_AHB_CLK>;
1298 clock-names = "core", "iface";
1300 status = "disabled";
1303 i2c_1: i2c@78b5000 {
1304 compatible = "qcom,i2c-qup-v2.2.1";
1305 reg = <0x078b5000 0x600>;
1306 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1307 clock-names = "core", "iface";
1308 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1309 <&gcc GCC_BLSP1_AHB_CLK>;
1310 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1311 dma-names = "tx", "rx";
1313 pinctrl-names = "default", "sleep";
1314 pinctrl-0 = <&i2c_1_default>;
1315 pinctrl-1 = <&i2c_1_sleep>;
1317 #address-cells = <1>;
1320 status = "disabled";
1323 i2c_2: i2c@78b6000 {
1324 compatible = "qcom,i2c-qup-v2.2.1";
1325 reg = <0x078b6000 0x600>;
1326 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1327 clock-names = "core", "iface";
1328 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1329 <&gcc GCC_BLSP1_AHB_CLK>;
1330 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
1331 dma-names = "tx", "rx";
1333 pinctrl-names = "default", "sleep";
1334 pinctrl-0 = <&i2c_2_default>;
1335 pinctrl-1 = <&i2c_2_sleep>;
1337 #address-cells = <1>;
1340 status = "disabled";
1343 i2c_3: i2c@78b7000 {
1344 compatible = "qcom,i2c-qup-v2.2.1";
1345 reg = <0x078b7000 0x600>;
1346 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1347 clock-names = "core", "iface";
1348 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1349 <&gcc GCC_BLSP1_AHB_CLK>;
1350 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
1351 dma-names = "tx", "rx";
1353 pinctrl-names = "default", "sleep";
1354 pinctrl-0 = <&i2c_3_default>;
1355 pinctrl-1 = <&i2c_3_sleep>;
1357 #address-cells = <1>;
1360 status = "disabled";
1363 i2c_4: i2c@78b8000 {
1364 compatible = "qcom,i2c-qup-v2.2.1";
1365 reg = <0x078b8000 0x600>;
1366 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1367 clock-names = "core", "iface";
1368 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1369 <&gcc GCC_BLSP1_AHB_CLK>;
1370 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1371 dma-names = "tx", "rx";
1373 pinctrl-names = "default", "sleep";
1374 pinctrl-0 = <&i2c_4_default>;
1375 pinctrl-1 = <&i2c_4_sleep>;
1377 #address-cells = <1>;
1380 status = "disabled";
1383 blsp2_dma: dma-controller@7ac4000 {
1384 compatible = "qcom,bam-v1.7.0";
1385 reg = <0x07ac4000 0x1f000>;
1386 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1387 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1388 clock-names = "bam_clk";
1389 num-channels = <12>;
1393 qcom,controlled-remotely;
1396 i2c_5: i2c@7af5000 {
1397 compatible = "qcom,i2c-qup-v2.2.1";
1398 reg = <0x07af5000 0x600>;
1399 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1400 clock-names = "core", "iface";
1401 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1402 <&gcc GCC_BLSP2_AHB_CLK>;
1403 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>;
1404 dma-names = "tx", "rx";
1406 pinctrl-names = "default", "sleep";
1407 pinctrl-0 = <&i2c_5_default>;
1408 pinctrl-1 = <&i2c_5_sleep>;
1410 #address-cells = <1>;
1413 status = "disabled";
1416 i2c_6: i2c@7af6000 {
1417 compatible = "qcom,i2c-qup-v2.2.1";
1418 reg = <0x07af6000 0x600>;
1419 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1420 clock-names = "core", "iface";
1421 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1422 <&gcc GCC_BLSP2_AHB_CLK>;
1423 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
1424 dma-names = "tx", "rx";
1426 pinctrl-names = "default", "sleep";
1427 pinctrl-0 = <&i2c_6_default>;
1428 pinctrl-1 = <&i2c_6_sleep>;
1430 #address-cells = <1>;
1433 status = "disabled";
1436 i2c_7: i2c@7af7000 {
1437 compatible = "qcom,i2c-qup-v2.2.1";
1438 reg = <0x07af7000 0x600>;
1439 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1440 clock-names = "core", "iface";
1441 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1442 <&gcc GCC_BLSP2_AHB_CLK>;
1443 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
1444 dma-names = "tx", "rx";
1446 pinctrl-names = "default", "sleep";
1447 pinctrl-0 = <&i2c_7_default>;
1448 pinctrl-1 = <&i2c_7_sleep>;
1450 #address-cells = <1>;
1453 status = "disabled";
1456 i2c_8: i2c@7af8000 {
1457 compatible = "qcom,i2c-qup-v2.2.1";
1458 reg = <0x07af8000 0x600>;
1459 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1460 clock-names = "core", "iface";
1461 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1462 <&gcc GCC_BLSP2_AHB_CLK>;
1463 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
1464 dma-names = "tx", "rx";
1466 pinctrl-names = "default", "sleep";
1467 pinctrl-0 = <&i2c_8_default>;
1468 pinctrl-1 = <&i2c_8_sleep>;
1470 #address-cells = <1>;
1473 status = "disabled";
1476 wcnss: remoteproc@a204000 {
1477 compatible = "qcom,pronto-v3-pil", "qcom,pronto";
1478 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1479 reg-names = "ccu", "dxe", "pmu";
1481 memory-region = <&wcnss_fw_mem>;
1483 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
1484 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>,
1485 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>,
1486 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>,
1487 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>;
1488 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1490 power-domains = <&rpmpd MSM8953_VDDCX>,
1491 <&rpmpd MSM8953_VDDMX>;
1492 power-domain-names = "cx", "mx";
1494 qcom,smem-states = <&smp2p_wcnss_out 0>;
1495 qcom,smem-state-names = "stop";
1497 pinctrl-names = "default";
1498 pinctrl-0 = <&wcnss_pin_a>;
1500 status = "disabled";
1503 /* Separate chip, compatible is board-specific */
1504 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1509 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
1511 qcom,ipc = <&apcs 8 17>;
1512 qcom,smd-edge = <6>;
1513 qcom,remote-pid = <4>;
1518 compatible = "qcom,wcnss";
1519 qcom,smd-channels = "WCNSS_CTRL";
1521 qcom,mmio = <&wcnss>;
1523 wcnss_bt: bluetooth {
1524 compatible = "qcom,wcnss-bt";
1528 compatible = "qcom,wcnss-wlan";
1530 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1532 interrupt-names = "tx", "rx";
1534 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1535 qcom,smem-state-names = "tx-enable",
1542 intc: interrupt-controller@b000000 {
1543 compatible = "qcom,msm-qgic2";
1544 interrupt-controller;
1545 #interrupt-cells = <3>;
1546 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1549 apcs: mailbox@b011000 {
1550 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1551 reg = <0x0b011000 0x1000>;
1556 compatible = "arm,armv7-timer-mem";
1557 reg = <0x0b120000 0x1000>;
1558 #address-cells = <1>;
1564 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1565 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1566 reg = <0x0b121000 0x1000>,
1567 <0x0b122000 0x1000>;
1572 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1573 reg = <0x0b123000 0x1000>;
1574 status = "disabled";
1579 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1580 reg = <0x0b124000 0x1000>;
1581 status = "disabled";
1586 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1587 reg = <0x0b125000 0x1000>;
1588 status = "disabled";
1593 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1594 reg = <0x0b126000 0x1000>;
1595 status = "disabled";
1600 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1601 reg = <0x0b127000 0x1000>;
1602 status = "disabled";
1607 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1608 reg = <0x0b128000 0x1000>;
1609 status = "disabled";
1613 lpass: remoteproc@c200000 {
1614 compatible = "qcom,msm8953-adsp-pil";
1615 reg = <0x0c200000 0x100>;
1617 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>,
1618 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
1619 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
1620 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
1621 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
1622 interrupt-names = "wdog", "fatal", "ready",
1623 "handover", "stop-ack";
1624 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1627 power-domains = <&rpmpd MSM8953_VDDCX>;
1628 power-domain-names = "cx";
1630 memory-region = <&adsp_fw_mem>;
1632 qcom,smem-states = <&smp2p_adsp_out 0>;
1633 qcom,smem-state-names = "stop";
1635 status = "disabled";
1638 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
1642 qcom,smd-edge = <1>;
1643 qcom,remote-pid = <2>;
1646 compatible = "qcom,apr-v2";
1647 qcom,smd-channels = "apr_audio_svc";
1648 qcom,apr-domain = <APR_DOMAIN_ADSP>;
1649 #address-cells = <1>;
1653 reg = <APR_SVC_ADSP_CORE>;
1654 compatible = "qcom,q6core";
1658 compatible = "qcom,q6afe";
1659 reg = <APR_SVC_AFE>;
1661 compatible = "qcom,q6afe-dais";
1662 #address-cells = <1>;
1664 #sound-dai-cells = <1>;
1667 reg = <PRIMARY_MI2S_RX>;
1668 qcom,sd-lines = <0 1>;
1671 reg = <TERTIARY_MI2S_TX>;
1672 qcom,sd-lines = <0 1>;
1675 reg = <QUINARY_MI2S_RX>;
1676 qcom,sd-lines = <0>;
1680 q6afecc: clock-controller {
1681 compatible = "qcom,q6afe-clocks";
1687 compatible = "qcom,q6asm";
1688 reg = <APR_SVC_ASM>;
1690 compatible = "qcom,q6asm-dais";
1691 #address-cells = <1>;
1693 #sound-dai-cells = <1>;
1697 direction = <Q6ASM_DAI_RX>;
1701 direction = <Q6ASM_DAI_TX>;
1705 direction = <Q6ASM_DAI_RX>;
1709 direction = <Q6ASM_DAI_RX>;
1716 compatible = "qcom,q6adm";
1717 reg = <APR_SVC_ADM>;
1718 q6routing: routing {
1719 compatible = "qcom,q6adm-routing";
1720 #sound-dai-cells = <0>;
1730 polling-delay-passive = <250>;
1731 polling-delay = <1000>;
1732 thermal-sensors = <&tsens0 9>;
1734 cpu0_alert: trip-point0 {
1735 temperature = <80000>;
1736 hysteresis = <2000>;
1740 temperature = <100000>;
1741 hysteresis = <2000>;
1747 trip = <&cpu0_alert>;
1748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1753 polling-delay-passive = <250>;
1754 polling-delay = <1000>;
1755 thermal-sensors = <&tsens0 10>;
1757 cpu1_alert: trip-point0 {
1758 temperature = <80000>;
1759 hysteresis = <2000>;
1763 temperature = <100000>;
1764 hysteresis = <2000>;
1770 trip = <&cpu1_alert>;
1771 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1776 polling-delay-passive = <250>;
1777 polling-delay = <1000>;
1778 thermal-sensors = <&tsens0 11>;
1780 cpu2_alert: trip-point0 {
1781 temperature = <80000>;
1782 hysteresis = <2000>;
1786 temperature = <100000>;
1787 hysteresis = <2000>;
1793 trip = <&cpu2_alert>;
1794 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1799 polling-delay-passive = <250>;
1800 polling-delay = <1000>;
1801 thermal-sensors = <&tsens0 12>;
1803 cpu3_alert: trip-point0 {
1804 temperature = <80000>;
1805 hysteresis = <2000>;
1809 temperature = <100000>;
1810 hysteresis = <2000>;
1816 trip = <&cpu3_alert>;
1817 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1822 polling-delay-passive = <250>;
1823 polling-delay = <1000>;
1824 thermal-sensors = <&tsens0 4>;
1826 cpu4_alert: trip-point0 {
1827 temperature = <80000>;
1828 hysteresis = <2000>;
1832 temperature = <100000>;
1833 hysteresis = <2000>;
1839 trip = <&cpu4_alert>;
1840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1845 polling-delay-passive = <250>;
1846 polling-delay = <1000>;
1847 thermal-sensors = <&tsens0 5>;
1849 cpu5_alert: trip-point0 {
1850 temperature = <80000>;
1851 hysteresis = <2000>;
1855 temperature = <100000>;
1856 hysteresis = <2000>;
1862 trip = <&cpu5_alert>;
1863 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1868 polling-delay-passive = <250>;
1869 polling-delay = <1000>;
1870 thermal-sensors = <&tsens0 6>;
1872 cpu6_alert: trip-point0 {
1873 temperature = <80000>;
1874 hysteresis = <2000>;
1878 temperature = <100000>;
1879 hysteresis = <2000>;
1885 trip = <&cpu6_alert>;
1886 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1891 polling-delay-passive = <250>;
1892 polling-delay = <1000>;
1893 thermal-sensors = <&tsens0 7>;
1895 cpu7_alert: trip-point0 {
1896 temperature = <80000>;
1897 hysteresis = <2000>;
1901 temperature = <100000>;
1902 hysteresis = <2000>;
1908 trip = <&cpu7_alert>;
1909 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1916 compatible = "arm,armv8-timer";
1917 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1918 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1919 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1920 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;