arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/interconnect/qcom,msm8916.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/power/qcom-rpmpd.h>
  12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         memory@80000000 {
  24                 device_type = "memory";
  25                 /* We expect the bootloader to fill in the reg */
  26                 reg = <0 0x80000000 0 0>;
  27         };
  28
  29         reserved-memory {
  30                 #address-cells = <2>;
  31                 #size-cells = <2>;
  32                 ranges;
  33
  34                 tz-apps@86000000 {
  35                         reg = <0x0 0x86000000 0x0 0x300000>;
  36                         no-map;
  37                 };
  38
  39                 smem@86300000 {
  40                         compatible = "qcom,smem";
  41                         reg = <0x0 0x86300000 0x0 0x100000>;
  42                         no-map;
  43
  44                         hwlocks = <&tcsr_mutex 3>;
  45                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
  46                 };
  47
  48                 hypervisor@86400000 {
  49                         reg = <0x0 0x86400000 0x0 0x100000>;
  50                         no-map;
  51                 };
  52
  53                 tz@86500000 {
  54                         reg = <0x0 0x86500000 0x0 0x180000>;
  55                         no-map;
  56                 };
  57
  58                 reserved@86680000 {
  59                         reg = <0x0 0x86680000 0x0 0x80000>;
  60                         no-map;
  61                 };
  62
  63                 rmtfs@86700000 {
  64                         compatible = "qcom,rmtfs-mem";
  65                         reg = <0x0 0x86700000 0x0 0xe0000>;
  66                         no-map;
  67
  68                         qcom,client-id = <1>;
  69                 };
  70
  71                 rfsa@867e0000 {
  72                         reg = <0x0 0x867e0000 0x0 0x20000>;
  73                         no-map;
  74                 };
  75
  76                 mpss_mem: mpss@86800000 {
  77                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  78                         no-map;
  79                 };
  80
  81                 wcnss_mem: wcnss@89300000 {
  82                         reg = <0x0 0x89300000 0x0 0x600000>;
  83                         no-map;
  84                 };
  85
  86                 venus_mem: venus@89900000 {
  87                         reg = <0x0 0x89900000 0x0 0x600000>;
  88                         no-map;
  89                 };
  90
  91                 mba_mem: mba@8ea00000 {
  92                         no-map;
  93                         reg = <0 0x8ea00000 0 0x100000>;
  94                 };
  95         };
  96
  97         clocks {
  98                 xo_board: xo-board {
  99                         compatible = "fixed-clock";
 100                         #clock-cells = <0>;
 101                         clock-frequency = <19200000>;
 102                 };
 103
 104                 sleep_clk: sleep-clk {
 105                         compatible = "fixed-clock";
 106                         #clock-cells = <0>;
 107                         clock-frequency = <32768>;
 108                 };
 109         };
 110
 111         cpus {
 112                 #address-cells = <1>;
 113                 #size-cells = <0>;
 114
 115                 CPU0: cpu@0 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53";
 118                         reg = <0x0>;
 119                         next-level-cache = <&L2_0>;
 120                         enable-method = "psci";
 121                         clocks = <&apcs>;
 122                         operating-points-v2 = <&cpu_opp_table>;
 123                         #cooling-cells = <2>;
 124                         power-domains = <&CPU_PD0>;
 125                         power-domain-names = "psci";
 126                         qcom,acc = <&cpu0_acc>;
 127                         qcom,saw = <&cpu0_saw>;
 128                 };
 129
 130                 CPU1: cpu@1 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53";
 133                         reg = <0x1>;
 134                         next-level-cache = <&L2_0>;
 135                         enable-method = "psci";
 136                         clocks = <&apcs>;
 137                         operating-points-v2 = <&cpu_opp_table>;
 138                         #cooling-cells = <2>;
 139                         power-domains = <&CPU_PD1>;
 140                         power-domain-names = "psci";
 141                         qcom,acc = <&cpu1_acc>;
 142                         qcom,saw = <&cpu1_saw>;
 143                 };
 144
 145                 CPU2: cpu@2 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a53";
 148                         reg = <0x2>;
 149                         next-level-cache = <&L2_0>;
 150                         enable-method = "psci";
 151                         clocks = <&apcs>;
 152                         operating-points-v2 = <&cpu_opp_table>;
 153                         #cooling-cells = <2>;
 154                         power-domains = <&CPU_PD2>;
 155                         power-domain-names = "psci";
 156                         qcom,acc = <&cpu2_acc>;
 157                         qcom,saw = <&cpu2_saw>;
 158                 };
 159
 160                 CPU3: cpu@3 {
 161                         device_type = "cpu";
 162                         compatible = "arm,cortex-a53";
 163                         reg = <0x3>;
 164                         next-level-cache = <&L2_0>;
 165                         enable-method = "psci";
 166                         clocks = <&apcs>;
 167                         operating-points-v2 = <&cpu_opp_table>;
 168                         #cooling-cells = <2>;
 169                         power-domains = <&CPU_PD3>;
 170                         power-domain-names = "psci";
 171                         qcom,acc = <&cpu3_acc>;
 172                         qcom,saw = <&cpu3_saw>;
 173                 };
 174
 175                 L2_0: l2-cache {
 176                         compatible = "cache";
 177                         cache-level = <2>;
 178                         cache-unified;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183
 184                         CPU_SLEEP_0: cpu-sleep-0 {
 185                                 compatible = "arm,idle-state";
 186                                 idle-state-name = "standalone-power-collapse";
 187                                 arm,psci-suspend-param = <0x40000002>;
 188                                 entry-latency-us = <130>;
 189                                 exit-latency-us = <150>;
 190                                 min-residency-us = <2000>;
 191                                 local-timer-stop;
 192                         };
 193                 };
 194
 195                 domain-idle-states {
 196
 197                         CLUSTER_RET: cluster-retention {
 198                                 compatible = "domain-idle-state";
 199                                 arm,psci-suspend-param = <0x41000012>;
 200                                 entry-latency-us = <500>;
 201                                 exit-latency-us = <500>;
 202                                 min-residency-us = <2000>;
 203                         };
 204
 205                         CLUSTER_PWRDN: cluster-gdhs {
 206                                 compatible = "domain-idle-state";
 207                                 arm,psci-suspend-param = <0x41000032>;
 208                                 entry-latency-us = <2000>;
 209                                 exit-latency-us = <2000>;
 210                                 min-residency-us = <6000>;
 211                         };
 212                 };
 213         };
 214
 215         cpu_opp_table: opp-table-cpu {
 216                 compatible = "operating-points-v2";
 217                 opp-shared;
 218
 219                 opp-200000000 {
 220                         opp-hz = /bits/ 64 <200000000>;
 221                 };
 222                 opp-400000000 {
 223                         opp-hz = /bits/ 64 <400000000>;
 224                 };
 225                 opp-800000000 {
 226                         opp-hz = /bits/ 64 <800000000>;
 227                 };
 228                 opp-998400000 {
 229                         opp-hz = /bits/ 64 <998400000>;
 230                 };
 231         };
 232
 233         firmware {
 234                 scm: scm {
 235                         compatible = "qcom,scm-msm8916", "qcom,scm";
 236                         clocks = <&gcc GCC_CRYPTO_CLK>,
 237                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 238                                  <&gcc GCC_CRYPTO_AHB_CLK>;
 239                         clock-names = "core", "bus", "iface";
 240                         #reset-cells = <1>;
 241
 242                         qcom,dload-mode = <&tcsr 0x6100>;
 243                 };
 244         };
 245
 246         pmu {
 247                 compatible = "arm,cortex-a53-pmu";
 248                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 249         };
 250
 251         psci {
 252                 compatible = "arm,psci-1.0";
 253                 method = "smc";
 254
 255                 CPU_PD0: power-domain-cpu0 {
 256                         #power-domain-cells = <0>;
 257                         power-domains = <&CLUSTER_PD>;
 258                         domain-idle-states = <&CPU_SLEEP_0>;
 259                 };
 260
 261                 CPU_PD1: power-domain-cpu1 {
 262                         #power-domain-cells = <0>;
 263                         power-domains = <&CLUSTER_PD>;
 264                         domain-idle-states = <&CPU_SLEEP_0>;
 265                 };
 266
 267                 CPU_PD2: power-domain-cpu2 {
 268                         #power-domain-cells = <0>;
 269                         power-domains = <&CLUSTER_PD>;
 270                         domain-idle-states = <&CPU_SLEEP_0>;
 271                 };
 272
 273                 CPU_PD3: power-domain-cpu3 {
 274                         #power-domain-cells = <0>;
 275                         power-domains = <&CLUSTER_PD>;
 276                         domain-idle-states = <&CPU_SLEEP_0>;
 277                 };
 278
 279                 CLUSTER_PD: power-domain-cluster {
 280                         #power-domain-cells = <0>;
 281                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 282                 };
 283         };
 284
 285         smd {
 286                 compatible = "qcom,smd";
 287
 288                 rpm {
 289                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 290                         qcom,ipc = <&apcs 8 0>;
 291                         qcom,smd-edge = <15>;
 292
 293                         rpm_requests: rpm-requests {
 294                                 compatible = "qcom,rpm-msm8916";
 295                                 qcom,smd-channels = "rpm_requests";
 296
 297                                 rpmcc: clock-controller {
 298                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 299                                         #clock-cells = <1>;
 300                                         clocks = <&xo_board>;
 301                                         clock-names = "xo";
 302                                 };
 303
 304                                 rpmpd: power-controller {
 305                                         compatible = "qcom,msm8916-rpmpd";
 306                                         #power-domain-cells = <1>;
 307                                         operating-points-v2 = <&rpmpd_opp_table>;
 308
 309                                         rpmpd_opp_table: opp-table {
 310                                                 compatible = "operating-points-v2";
 311
 312                                                 rpmpd_opp_ret: opp1 {
 313                                                         opp-level = <1>;
 314                                                 };
 315                                                 rpmpd_opp_svs_krait: opp2 {
 316                                                         opp-level = <2>;
 317                                                 };
 318                                                 rpmpd_opp_svs_soc: opp3 {
 319                                                         opp-level = <3>;
 320                                                 };
 321                                                 rpmpd_opp_nom: opp4 {
 322                                                         opp-level = <4>;
 323                                                 };
 324                                                 rpmpd_opp_turbo: opp5 {
 325                                                         opp-level = <5>;
 326                                                 };
 327                                                 rpmpd_opp_super_turbo: opp6 {
 328                                                         opp-level = <6>;
 329                                                 };
 330                                         };
 331                                 };
 332                         };
 333                 };
 334         };
 335
 336         smp2p-hexagon {
 337                 compatible = "qcom,smp2p";
 338                 qcom,smem = <435>, <428>;
 339
 340                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
 341
 342                 qcom,ipc = <&apcs 8 14>;
 343
 344                 qcom,local-pid = <0>;
 345                 qcom,remote-pid = <1>;
 346
 347                 hexagon_smp2p_out: master-kernel {
 348                         qcom,entry-name = "master-kernel";
 349
 350                         #qcom,smem-state-cells = <1>;
 351                 };
 352
 353                 hexagon_smp2p_in: slave-kernel {
 354                         qcom,entry-name = "slave-kernel";
 355
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359         };
 360
 361         smp2p-wcnss {
 362                 compatible = "qcom,smp2p";
 363                 qcom,smem = <451>, <431>;
 364
 365                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 366
 367                 qcom,ipc = <&apcs 8 18>;
 368
 369                 qcom,local-pid = <0>;
 370                 qcom,remote-pid = <4>;
 371
 372                 wcnss_smp2p_out: master-kernel {
 373                         qcom,entry-name = "master-kernel";
 374
 375                         #qcom,smem-state-cells = <1>;
 376                 };
 377
 378                 wcnss_smp2p_in: slave-kernel {
 379                         qcom,entry-name = "slave-kernel";
 380
 381                         interrupt-controller;
 382                         #interrupt-cells = <2>;
 383                 };
 384         };
 385
 386         smsm {
 387                 compatible = "qcom,smsm";
 388
 389                 #address-cells = <1>;
 390                 #size-cells = <0>;
 391
 392                 qcom,ipc-1 = <&apcs 8 13>;
 393                 qcom,ipc-3 = <&apcs 8 19>;
 394
 395                 apps_smsm: apps@0 {
 396                         reg = <0>;
 397
 398                         #qcom,smem-state-cells = <1>;
 399                 };
 400
 401                 hexagon_smsm: hexagon@1 {
 402                         reg = <1>;
 403                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 404
 405                         interrupt-controller;
 406                         #interrupt-cells = <2>;
 407                 };
 408
 409                 wcnss_smsm: wcnss@6 {
 410                         reg = <6>;
 411                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
 412
 413                         interrupt-controller;
 414                         #interrupt-cells = <2>;
 415                 };
 416         };
 417
 418         soc: soc@0 {
 419                 #address-cells = <1>;
 420                 #size-cells = <1>;
 421                 ranges = <0 0 0 0xffffffff>;
 422                 compatible = "simple-bus";
 423
 424                 rng@22000 {
 425                         compatible = "qcom,prng";
 426                         reg = <0x00022000 0x200>;
 427                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 428                         clock-names = "core";
 429                 };
 430
 431                 restart@4ab000 {
 432                         compatible = "qcom,pshold";
 433                         reg = <0x004ab000 0x4>;
 434                 };
 435
 436                 qfprom: qfprom@5c000 {
 437                         compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
 438                         reg = <0x0005c000 0x1000>;
 439                         #address-cells = <1>;
 440                         #size-cells = <1>;
 441
 442                         tsens_base1: base1@d0 {
 443                                 reg = <0xd0 0x1>;
 444                                 bits = <0 7>;
 445                         };
 446
 447                         tsens_s0_p1: s0-p1@d0 {
 448                                 reg = <0xd0 0x2>;
 449                                 bits = <7 5>;
 450                         };
 451
 452                         tsens_s0_p2: s0-p2@d1 {
 453                                 reg = <0xd1 0x2>;
 454                                 bits = <4 5>;
 455                         };
 456
 457                         tsens_s1_p1: s1-p1@d2 {
 458                                 reg = <0xd2 0x1>;
 459                                 bits = <1 5>;
 460                         };
 461                         tsens_s1_p2: s1-p2@d2 {
 462                                 reg = <0xd2 0x2>;
 463                                 bits = <6 5>;
 464                         };
 465                         tsens_s2_p1: s2-p1@d3 {
 466                                 reg = <0xd3 0x1>;
 467                                 bits = <3 5>;
 468                         };
 469
 470                         tsens_s2_p2: s2-p2@d4 {
 471                                 reg = <0xd4 0x1>;
 472                                 bits = <0 5>;
 473                         };
 474
 475                         // no tsens with hw_id 3
 476
 477                         tsens_s4_p1: s4-p1@d4 {
 478                                 reg = <0xd4 0x2>;
 479                                 bits = <5 5>;
 480                         };
 481
 482                         tsens_s4_p2: s4-p2@d5 {
 483                                 reg = <0xd5 0x1>;
 484                                 bits = <2 5>;
 485                         };
 486
 487                         tsens_s5_p1: s5-p1@d5 {
 488                                 reg = <0xd5 0x2>;
 489                                 bits = <7 5>;
 490                         };
 491
 492                         tsens_s5_p2: s5-p2@d6 {
 493                                 reg = <0xd6 0x2>;
 494                                 bits = <4 5>;
 495                         };
 496
 497                         tsens_base2: base2@d7 {
 498                                 reg = <0xd7 0x1>;
 499                                 bits = <1 7>;
 500                         };
 501
 502                         tsens_mode: mode@ef {
 503                                 reg = <0xef 0x1>;
 504                                 bits = <5 3>;
 505                         };
 506                 };
 507
 508                 rpm_msg_ram: sram@60000 {
 509                         compatible = "qcom,rpm-msg-ram";
 510                         reg = <0x00060000 0x8000>;
 511                 };
 512
 513                 sram@290000 {
 514                         compatible = "qcom,msm8916-rpm-stats";
 515                         reg = <0x00290000 0x10000>;
 516                 };
 517
 518                 bimc: interconnect@400000 {
 519                         compatible = "qcom,msm8916-bimc";
 520                         reg = <0x00400000 0x62000>;
 521                         #interconnect-cells = <1>;
 522                         clock-names = "bus", "bus_a";
 523                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
 524                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
 525                 };
 526
 527                 tsens: thermal-sensor@4a9000 {
 528                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 529                         reg = <0x004a9000 0x1000>, /* TM */
 530                               <0x004a8000 0x1000>; /* SROT */
 531
 532                         // no hw_id 3
 533                         nvmem-cells = <&tsens_mode>,
 534                                       <&tsens_base1>, <&tsens_base2>,
 535                                       <&tsens_s0_p1>, <&tsens_s0_p2>,
 536                                       <&tsens_s1_p1>, <&tsens_s1_p2>,
 537                                       <&tsens_s2_p1>, <&tsens_s2_p2>,
 538                                       <&tsens_s4_p1>, <&tsens_s4_p2>,
 539                                       <&tsens_s5_p1>, <&tsens_s5_p2>;
 540                         nvmem-cell-names = "mode",
 541                                            "base1", "base2",
 542                                            "s0_p1", "s0_p2",
 543                                            "s1_p1", "s1_p2",
 544                                            "s2_p1", "s2_p2",
 545                                            "s4_p1", "s4_p2",
 546                                            "s5_p1", "s5_p2";
 547                         #qcom,sensors = <5>;
 548                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 549                         interrupt-names = "uplow";
 550                         #thermal-sensor-cells = <1>;
 551                 };
 552
 553                 pcnoc: interconnect@500000 {
 554                         compatible = "qcom,msm8916-pcnoc";
 555                         reg = <0x00500000 0x11000>;
 556                         #interconnect-cells = <1>;
 557                         clock-names = "bus", "bus_a";
 558                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
 559                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
 560                 };
 561
 562                 snoc: interconnect@580000 {
 563                         compatible = "qcom,msm8916-snoc";
 564                         reg = <0x00580000 0x14000>;
 565                         #interconnect-cells = <1>;
 566                         clock-names = "bus", "bus_a";
 567                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
 568                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
 569                 };
 570
 571                 stm: stm@802000 {
 572                         compatible = "arm,coresight-stm", "arm,primecell";
 573                         reg = <0x00802000 0x1000>,
 574                               <0x09280000 0x180000>;
 575                         reg-names = "stm-base", "stm-stimulus-base";
 576
 577                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 578                         clock-names = "apb_pclk", "atclk";
 579
 580                         status = "disabled";
 581
 582                         out-ports {
 583                                 port {
 584                                         stm_out: endpoint {
 585                                                 remote-endpoint = <&funnel0_in7>;
 586                                         };
 587                                 };
 588                         };
 589                 };
 590
 591                 /* System CTIs */
 592                 /* CTI 0 - TMC connections */
 593                 cti0: cti@810000 {
 594                         compatible = "arm,coresight-cti", "arm,primecell";
 595                         reg = <0x00810000 0x1000>;
 596
 597                         clocks = <&rpmcc RPM_QDSS_CLK>;
 598                         clock-names = "apb_pclk";
 599
 600                         status = "disabled";
 601                 };
 602
 603                 /* CTI 1 - TPIU connections */
 604                 cti1: cti@811000 {
 605                         compatible = "arm,coresight-cti", "arm,primecell";
 606                         reg = <0x00811000 0x1000>;
 607
 608                         clocks = <&rpmcc RPM_QDSS_CLK>;
 609                         clock-names = "apb_pclk";
 610
 611                         status = "disabled";
 612                 };
 613
 614                 /* CTIs 2-11 - no information - not instantiated */
 615
 616                 tpiu: tpiu@820000 {
 617                         compatible = "arm,coresight-tpiu", "arm,primecell";
 618                         reg = <0x00820000 0x1000>;
 619
 620                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 621                         clock-names = "apb_pclk", "atclk";
 622
 623                         status = "disabled";
 624
 625                         in-ports {
 626                                 port {
 627                                         tpiu_in: endpoint {
 628                                                 remote-endpoint = <&replicator_out1>;
 629                                         };
 630                                 };
 631                         };
 632                 };
 633
 634                 funnel0: funnel@821000 {
 635                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 636                         reg = <0x00821000 0x1000>;
 637
 638                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 639                         clock-names = "apb_pclk", "atclk";
 640
 641                         status = "disabled";
 642
 643                         in-ports {
 644                                 #address-cells = <1>;
 645                                 #size-cells = <0>;
 646
 647                                 /*
 648                                  * Not described input ports:
 649                                  * 0 - connected to Resource and Power Manger CPU ETM
 650                                  * 1 - not-connected
 651                                  * 2 - connected to Modem CPU ETM
 652                                  * 3 - not-connected
 653                                  * 5 - not-connected
 654                                  * 6 - connected trought funnel to Wireless CPU ETM
 655                                  * 7 - connected to STM component
 656                                  */
 657
 658                                 port@4 {
 659                                         reg = <4>;
 660                                         funnel0_in4: endpoint {
 661                                                 remote-endpoint = <&funnel1_out>;
 662                                         };
 663                                 };
 664
 665                                 port@7 {
 666                                         reg = <7>;
 667                                         funnel0_in7: endpoint {
 668                                                 remote-endpoint = <&stm_out>;
 669                                         };
 670                                 };
 671                         };
 672
 673                         out-ports {
 674                                 port {
 675                                         funnel0_out: endpoint {
 676                                                 remote-endpoint = <&etf_in>;
 677                                         };
 678                                 };
 679                         };
 680                 };
 681
 682                 replicator: replicator@824000 {
 683                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 684                         reg = <0x00824000 0x1000>;
 685
 686                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 687                         clock-names = "apb_pclk", "atclk";
 688
 689                         status = "disabled";
 690
 691                         out-ports {
 692                                 #address-cells = <1>;
 693                                 #size-cells = <0>;
 694
 695                                 port@0 {
 696                                         reg = <0>;
 697                                         replicator_out0: endpoint {
 698                                                 remote-endpoint = <&etr_in>;
 699                                         };
 700                                 };
 701                                 port@1 {
 702                                         reg = <1>;
 703                                         replicator_out1: endpoint {
 704                                                 remote-endpoint = <&tpiu_in>;
 705                                         };
 706                                 };
 707                         };
 708
 709                         in-ports {
 710                                 port {
 711                                         replicator_in: endpoint {
 712                                                 remote-endpoint = <&etf_out>;
 713                                         };
 714                                 };
 715                         };
 716                 };
 717
 718                 etf: etf@825000 {
 719                         compatible = "arm,coresight-tmc", "arm,primecell";
 720                         reg = <0x00825000 0x1000>;
 721
 722                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 723                         clock-names = "apb_pclk", "atclk";
 724
 725                         status = "disabled";
 726
 727                         in-ports {
 728                                 port {
 729                                         etf_in: endpoint {
 730                                                 remote-endpoint = <&funnel0_out>;
 731                                         };
 732                                 };
 733                         };
 734
 735                         out-ports {
 736                                 port {
 737                                         etf_out: endpoint {
 738                                                 remote-endpoint = <&replicator_in>;
 739                                         };
 740                                 };
 741                         };
 742                 };
 743
 744                 etr: etr@826000 {
 745                         compatible = "arm,coresight-tmc", "arm,primecell";
 746                         reg = <0x00826000 0x1000>;
 747
 748                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 749                         clock-names = "apb_pclk", "atclk";
 750
 751                         status = "disabled";
 752
 753                         in-ports {
 754                                 port {
 755                                         etr_in: endpoint {
 756                                                 remote-endpoint = <&replicator_out0>;
 757                                         };
 758                                 };
 759                         };
 760                 };
 761
 762                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
 763                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 764                         reg = <0x00841000 0x1000>;
 765
 766                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 767                         clock-names = "apb_pclk", "atclk";
 768
 769                         status = "disabled";
 770
 771                         in-ports {
 772                                 #address-cells = <1>;
 773                                 #size-cells = <0>;
 774
 775                                 port@0 {
 776                                         reg = <0>;
 777                                         funnel1_in0: endpoint {
 778                                                 remote-endpoint = <&etm0_out>;
 779                                         };
 780                                 };
 781                                 port@1 {
 782                                         reg = <1>;
 783                                         funnel1_in1: endpoint {
 784                                                 remote-endpoint = <&etm1_out>;
 785                                         };
 786                                 };
 787                                 port@2 {
 788                                         reg = <2>;
 789                                         funnel1_in2: endpoint {
 790                                                 remote-endpoint = <&etm2_out>;
 791                                         };
 792                                 };
 793                                 port@3 {
 794                                         reg = <3>;
 795                                         funnel1_in3: endpoint {
 796                                                 remote-endpoint = <&etm3_out>;
 797                                         };
 798                                 };
 799                         };
 800
 801                         out-ports {
 802                                 port {
 803                                         funnel1_out: endpoint {
 804                                                 remote-endpoint = <&funnel0_in4>;
 805                                         };
 806                                 };
 807                         };
 808                 };
 809
 810                 debug0: debug@850000 {
 811                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 812                         reg = <0x00850000 0x1000>;
 813                         clocks = <&rpmcc RPM_QDSS_CLK>;
 814                         clock-names = "apb_pclk";
 815                         cpu = <&CPU0>;
 816                         status = "disabled";
 817                 };
 818
 819                 debug1: debug@852000 {
 820                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 821                         reg = <0x00852000 0x1000>;
 822                         clocks = <&rpmcc RPM_QDSS_CLK>;
 823                         clock-names = "apb_pclk";
 824                         cpu = <&CPU1>;
 825                         status = "disabled";
 826                 };
 827
 828                 debug2: debug@854000 {
 829                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 830                         reg = <0x00854000 0x1000>;
 831                         clocks = <&rpmcc RPM_QDSS_CLK>;
 832                         clock-names = "apb_pclk";
 833                         cpu = <&CPU2>;
 834                         status = "disabled";
 835                 };
 836
 837                 debug3: debug@856000 {
 838                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 839                         reg = <0x00856000 0x1000>;
 840                         clocks = <&rpmcc RPM_QDSS_CLK>;
 841                         clock-names = "apb_pclk";
 842                         cpu = <&CPU3>;
 843                         status = "disabled";
 844                 };
 845
 846                 /* Core CTIs; CTIs 12-15 */
 847                 /* CTI - CPU-0 */
 848                 cti12: cti@858000 {
 849                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 850                                      "arm,primecell";
 851                         reg = <0x00858000 0x1000>;
 852
 853                         clocks = <&rpmcc RPM_QDSS_CLK>;
 854                         clock-names = "apb_pclk";
 855
 856                         cpu = <&CPU0>;
 857                         arm,cs-dev-assoc = <&etm0>;
 858
 859                         status = "disabled";
 860                 };
 861
 862                 /* CTI - CPU-1 */
 863                 cti13: cti@859000 {
 864                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 865                                      "arm,primecell";
 866                         reg = <0x00859000 0x1000>;
 867
 868                         clocks = <&rpmcc RPM_QDSS_CLK>;
 869                         clock-names = "apb_pclk";
 870
 871                         cpu = <&CPU1>;
 872                         arm,cs-dev-assoc = <&etm1>;
 873
 874                         status = "disabled";
 875                 };
 876
 877                 /* CTI - CPU-2 */
 878                 cti14: cti@85a000 {
 879                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 880                                      "arm,primecell";
 881                         reg = <0x0085a000 0x1000>;
 882
 883                         clocks = <&rpmcc RPM_QDSS_CLK>;
 884                         clock-names = "apb_pclk";
 885
 886                         cpu = <&CPU2>;
 887                         arm,cs-dev-assoc = <&etm2>;
 888
 889                         status = "disabled";
 890                 };
 891
 892                 /* CTI - CPU-3 */
 893                 cti15: cti@85b000 {
 894                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
 895                                      "arm,primecell";
 896                         reg = <0x0085b000 0x1000>;
 897
 898                         clocks = <&rpmcc RPM_QDSS_CLK>;
 899                         clock-names = "apb_pclk";
 900
 901                         cpu = <&CPU3>;
 902                         arm,cs-dev-assoc = <&etm3>;
 903
 904                         status = "disabled";
 905                 };
 906
 907                 etm0: etm@85c000 {
 908                         compatible = "arm,coresight-etm4x", "arm,primecell";
 909                         reg = <0x0085c000 0x1000>;
 910
 911                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 912                         clock-names = "apb_pclk", "atclk";
 913                         arm,coresight-loses-context-with-cpu;
 914
 915                         cpu = <&CPU0>;
 916
 917                         status = "disabled";
 918
 919                         out-ports {
 920                                 port {
 921                                         etm0_out: endpoint {
 922                                                 remote-endpoint = <&funnel1_in0>;
 923                                         };
 924                                 };
 925                         };
 926                 };
 927
 928                 etm1: etm@85d000 {
 929                         compatible = "arm,coresight-etm4x", "arm,primecell";
 930                         reg = <0x0085d000 0x1000>;
 931
 932                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 933                         clock-names = "apb_pclk", "atclk";
 934                         arm,coresight-loses-context-with-cpu;
 935
 936                         cpu = <&CPU1>;
 937
 938                         status = "disabled";
 939
 940                         out-ports {
 941                                 port {
 942                                         etm1_out: endpoint {
 943                                                 remote-endpoint = <&funnel1_in1>;
 944                                         };
 945                                 };
 946                         };
 947                 };
 948
 949                 etm2: etm@85e000 {
 950                         compatible = "arm,coresight-etm4x", "arm,primecell";
 951                         reg = <0x0085e000 0x1000>;
 952
 953                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 954                         clock-names = "apb_pclk", "atclk";
 955                         arm,coresight-loses-context-with-cpu;
 956
 957                         cpu = <&CPU2>;
 958
 959                         status = "disabled";
 960
 961                         out-ports {
 962                                 port {
 963                                         etm2_out: endpoint {
 964                                                 remote-endpoint = <&funnel1_in2>;
 965                                         };
 966                                 };
 967                         };
 968                 };
 969
 970                 etm3: etm@85f000 {
 971                         compatible = "arm,coresight-etm4x", "arm,primecell";
 972                         reg = <0x0085f000 0x1000>;
 973
 974                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 975                         clock-names = "apb_pclk", "atclk";
 976                         arm,coresight-loses-context-with-cpu;
 977
 978                         cpu = <&CPU3>;
 979
 980                         status = "disabled";
 981
 982                         out-ports {
 983                                 port {
 984                                         etm3_out: endpoint {
 985                                                 remote-endpoint = <&funnel1_in3>;
 986                                         };
 987                                 };
 988                         };
 989                 };
 990
 991                 tlmm: pinctrl@1000000 {
 992                         compatible = "qcom,msm8916-pinctrl";
 993                         reg = <0x01000000 0x300000>;
 994                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 995                         gpio-controller;
 996                         gpio-ranges = <&tlmm 0 0 122>;
 997                         #gpio-cells = <2>;
 998                         interrupt-controller;
 999                         #interrupt-cells = <2>;
1000
1001                         blsp_i2c1_default: blsp-i2c1-default-state {
1002                                 pins = "gpio2", "gpio3";
1003                                 function = "blsp_i2c1";
1004                                 drive-strength = <2>;
1005                                 bias-disable;
1006                         };
1007
1008                         blsp_i2c1_sleep: blsp-i2c1-sleep-state {
1009                                 pins = "gpio2", "gpio3";
1010                                 function = "gpio";
1011                                 drive-strength = <2>;
1012                                 bias-disable;
1013                         };
1014
1015                         blsp_i2c2_default: blsp-i2c2-default-state {
1016                                 pins = "gpio6", "gpio7";
1017                                 function = "blsp_i2c2";
1018                                 drive-strength = <2>;
1019                                 bias-disable;
1020                         };
1021
1022                         blsp_i2c2_sleep: blsp-i2c2-sleep-state {
1023                                 pins = "gpio6", "gpio7";
1024                                 function = "gpio";
1025                                 drive-strength = <2>;
1026                                 bias-disable;
1027                         };
1028
1029                         blsp_i2c3_default: blsp-i2c3-default-state {
1030                                 pins = "gpio10", "gpio11";
1031                                 function = "blsp_i2c3";
1032                                 drive-strength = <2>;
1033                                 bias-disable;
1034                         };
1035
1036                         blsp_i2c3_sleep: blsp-i2c3-sleep-state {
1037                                 pins = "gpio10", "gpio11";
1038                                 function = "gpio";
1039                                 drive-strength = <2>;
1040                                 bias-disable;
1041                         };
1042
1043                         blsp_i2c4_default: blsp-i2c4-default-state {
1044                                 pins = "gpio14", "gpio15";
1045                                 function = "blsp_i2c4";
1046                                 drive-strength = <2>;
1047                                 bias-disable;
1048                         };
1049
1050                         blsp_i2c4_sleep: blsp-i2c4-sleep-state {
1051                                 pins = "gpio14", "gpio15";
1052                                 function = "gpio";
1053                                 drive-strength = <2>;
1054                                 bias-disable;
1055                         };
1056
1057                         blsp_i2c5_default: blsp-i2c5-default-state {
1058                                 pins = "gpio18", "gpio19";
1059                                 function = "blsp_i2c5";
1060                                 drive-strength = <2>;
1061                                 bias-disable;
1062                         };
1063
1064                         blsp_i2c5_sleep: blsp-i2c5-sleep-state {
1065                                 pins = "gpio18", "gpio19";
1066                                 function = "gpio";
1067                                 drive-strength = <2>;
1068                                 bias-disable;
1069                         };
1070
1071                         blsp_i2c6_default: blsp-i2c6-default-state {
1072                                 pins = "gpio22", "gpio23";
1073                                 function = "blsp_i2c6";
1074                                 drive-strength = <2>;
1075                                 bias-disable;
1076                         };
1077
1078                         blsp_i2c6_sleep: blsp-i2c6-sleep-state {
1079                                 pins = "gpio22", "gpio23";
1080                                 function = "gpio";
1081                                 drive-strength = <2>;
1082                                 bias-disable;
1083                         };
1084
1085                         blsp_spi1_default: blsp-spi1-default-state {
1086                                 spi-pins {
1087                                         pins = "gpio0", "gpio1", "gpio3";
1088                                         function = "blsp_spi1";
1089                                         drive-strength = <12>;
1090                                         bias-disable;
1091                                 };
1092                                 cs-pins {
1093                                         pins = "gpio2";
1094                                         function = "gpio";
1095                                         drive-strength = <16>;
1096                                         bias-disable;
1097                                         output-high;
1098                                 };
1099                         };
1100
1101                         blsp_spi1_sleep: blsp-spi1-sleep-state {
1102                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1103                                 function = "gpio";
1104                                 drive-strength = <2>;
1105                                 bias-pull-down;
1106                         };
1107
1108                         blsp_spi2_default: blsp-spi2-default-state {
1109                                 spi-pins {
1110                                         pins = "gpio4", "gpio5", "gpio7";
1111                                         function = "blsp_spi2";
1112                                         drive-strength = <12>;
1113                                         bias-disable;
1114                                 };
1115                                 cs-pins {
1116                                         pins = "gpio6";
1117                                         function = "gpio";
1118                                         drive-strength = <16>;
1119                                         bias-disable;
1120                                         output-high;
1121                                 };
1122                         };
1123
1124                         blsp_spi2_sleep: blsp-spi2-sleep-state {
1125                                 pins = "gpio4", "gpio5", "gpio6", "gpio7";
1126                                 function = "gpio";
1127                                 drive-strength = <2>;
1128                                 bias-pull-down;
1129                         };
1130
1131                         blsp_spi3_default: blsp-spi3-default-state {
1132                                 spi-pins {
1133                                         pins = "gpio8", "gpio9", "gpio11";
1134                                         function = "blsp_spi3";
1135                                         drive-strength = <12>;
1136                                         bias-disable;
1137                                 };
1138                                 cs-pins {
1139                                         pins = "gpio10";
1140                                         function = "gpio";
1141                                         drive-strength = <16>;
1142                                         bias-disable;
1143                                         output-high;
1144                                 };
1145                         };
1146
1147                         blsp_spi3_sleep: blsp-spi3-sleep-state {
1148                                 pins = "gpio8", "gpio9", "gpio10", "gpio11";
1149                                 function = "gpio";
1150                                 drive-strength = <2>;
1151                                 bias-pull-down;
1152                         };
1153
1154                         blsp_spi4_default: blsp-spi4-default-state {
1155                                 spi-pins {
1156                                         pins = "gpio12", "gpio13", "gpio15";
1157                                         function = "blsp_spi4";
1158                                         drive-strength = <12>;
1159                                         bias-disable;
1160                                 };
1161                                 cs-pins {
1162                                         pins = "gpio14";
1163                                         function = "gpio";
1164                                         drive-strength = <16>;
1165                                         bias-disable;
1166                                         output-high;
1167                                 };
1168                         };
1169
1170                         blsp_spi4_sleep: blsp-spi4-sleep-state {
1171                                 pins = "gpio12", "gpio13", "gpio14", "gpio15";
1172                                 function = "gpio";
1173                                 drive-strength = <2>;
1174                                 bias-pull-down;
1175                         };
1176
1177                         blsp_spi5_default: blsp-spi5-default-state {
1178                                 spi-pins {
1179                                         pins = "gpio16", "gpio17", "gpio19";
1180                                         function = "blsp_spi5";
1181                                         drive-strength = <12>;
1182                                         bias-disable;
1183                                 };
1184                                 cs-pins {
1185                                         pins = "gpio18";
1186                                         function = "gpio";
1187                                         drive-strength = <16>;
1188                                         bias-disable;
1189                                         output-high;
1190                                 };
1191                         };
1192
1193                         blsp_spi5_sleep: blsp-spi5-sleep-state {
1194                                 pins = "gpio16", "gpio17", "gpio18", "gpio19";
1195                                 function = "gpio";
1196                                 drive-strength = <2>;
1197                                 bias-pull-down;
1198                         };
1199
1200                         blsp_spi6_default: blsp-spi6-default-state {
1201                                 spi-pins {
1202                                         pins = "gpio20", "gpio21", "gpio23";
1203                                         function = "blsp_spi6";
1204                                         drive-strength = <12>;
1205                                         bias-disable;
1206                                 };
1207                                 cs-pins {
1208                                         pins = "gpio22";
1209                                         function = "gpio";
1210                                         drive-strength = <16>;
1211                                         bias-disable;
1212                                         output-high;
1213                                 };
1214                         };
1215
1216                         blsp_spi6_sleep: blsp-spi6-sleep-state {
1217                                 pins = "gpio20", "gpio21", "gpio22", "gpio23";
1218                                 function = "gpio";
1219                                 drive-strength = <2>;
1220                                 bias-pull-down;
1221                         };
1222
1223                         blsp_uart1_default: blsp-uart1-default-state {
1224                                 /* TX, RX, CTS_N, RTS_N */
1225                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1226                                 function = "blsp_uart1";
1227                                 drive-strength = <16>;
1228                                 bias-disable;
1229                         };
1230
1231                         blsp_uart1_sleep: blsp-uart1-sleep-state {
1232                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
1233                                 function = "gpio";
1234                                 drive-strength = <2>;
1235                                 bias-pull-down;
1236                         };
1237
1238                         blsp_uart2_default: blsp-uart2-default-state {
1239                                 pins = "gpio4", "gpio5";
1240                                 function = "blsp_uart2";
1241                                 drive-strength = <16>;
1242                                 bias-disable;
1243                         };
1244
1245                         blsp_uart2_sleep: blsp-uart2-sleep-state {
1246                                 pins = "gpio4", "gpio5";
1247                                 function = "gpio";
1248                                 drive-strength = <2>;
1249                                 bias-pull-down;
1250                         };
1251
1252                         camera_front_default: camera-front-default-state {
1253                                 pwdn-pins {
1254                                         pins = "gpio33";
1255                                         function = "gpio";
1256                                         drive-strength = <16>;
1257                                         bias-disable;
1258                                 };
1259                                 rst-pins {
1260                                         pins = "gpio28";
1261                                         function = "gpio";
1262                                         drive-strength = <16>;
1263                                         bias-disable;
1264                                 };
1265                                 mclk1-pins {
1266                                         pins = "gpio27";
1267                                         function = "cam_mclk1";
1268                                         drive-strength = <16>;
1269                                         bias-disable;
1270                                 };
1271                         };
1272
1273                         camera_rear_default: camera-rear-default-state {
1274                                 pwdn-pins {
1275                                         pins = "gpio34";
1276                                         function = "gpio";
1277                                         drive-strength = <16>;
1278                                         bias-disable;
1279                                 };
1280                                 rst-pins {
1281                                         pins = "gpio35";
1282                                         function = "gpio";
1283                                         drive-strength = <16>;
1284                                         bias-disable;
1285                                 };
1286                                 mclk0-pins {
1287                                         pins = "gpio26";
1288                                         function = "cam_mclk0";
1289                                         drive-strength = <16>;
1290                                         bias-disable;
1291                                 };
1292                         };
1293
1294                         cci0_default: cci0-default-state {
1295                                 pins = "gpio29", "gpio30";
1296                                 function = "cci_i2c";
1297                                 drive-strength = <16>;
1298                                 bias-disable;
1299                         };
1300
1301                         cdc_dmic_default: cdc-dmic-default-state {
1302                                 clk-pins {
1303                                         pins = "gpio0";
1304                                         function = "dmic0_clk";
1305                                         drive-strength = <8>;
1306                                 };
1307                                 data-pins {
1308                                         pins = "gpio1";
1309                                         function = "dmic0_data";
1310                                         drive-strength = <8>;
1311                                 };
1312                         };
1313
1314                         cdc_dmic_sleep: cdc-dmic-sleep-state {
1315                                 clk-pins {
1316                                         pins = "gpio0";
1317                                         function = "dmic0_clk";
1318                                         drive-strength = <2>;
1319                                         bias-disable;
1320                                 };
1321                                 data-pins {
1322                                         pins = "gpio1";
1323                                         function = "dmic0_data";
1324                                         drive-strength = <2>;
1325                                         bias-disable;
1326                                 };
1327                         };
1328
1329                         cdc_pdm_default: cdc-pdm-default-state {
1330                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1331                                        "gpio67", "gpio68";
1332                                 function = "cdc_pdm0";
1333                                 drive-strength = <8>;
1334                                 bias-disable;
1335                         };
1336
1337                         cdc_pdm_sleep: cdc-pdm-sleep-state {
1338                                 pins = "gpio63", "gpio64", "gpio65", "gpio66",
1339                                        "gpio67", "gpio68";
1340                                 function = "cdc_pdm0";
1341                                 drive-strength = <2>;
1342                                 bias-pull-down;
1343                         };
1344
1345                         pri_mi2s_default: mi2s-pri-default-state {
1346                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1347                                 function = "pri_mi2s";
1348                                 drive-strength = <8>;
1349                                 bias-disable;
1350                         };
1351
1352                         pri_mi2s_sleep: mi2s-pri-sleep-state {
1353                                 pins = "gpio113", "gpio114", "gpio115", "gpio116";
1354                                 function = "pri_mi2s";
1355                                 drive-strength = <2>;
1356                                 bias-disable;
1357                         };
1358
1359                         pri_mi2s_mclk_default: mi2s-pri-mclk-default-state {
1360                                 pins = "gpio116";
1361                                 function = "pri_mi2s";
1362                                 drive-strength = <8>;
1363                                 bias-disable;
1364                         };
1365
1366                         pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state {
1367                                 pins = "gpio116";
1368                                 function = "pri_mi2s";
1369                                 drive-strength = <2>;
1370                                 bias-disable;
1371                         };
1372
1373                         pri_mi2s_ws_default: mi2s-pri-ws-default-state {
1374                                 pins = "gpio110";
1375                                 function = "pri_mi2s_ws";
1376                                 drive-strength = <8>;
1377                                 bias-disable;
1378                         };
1379
1380                         pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state {
1381                                 pins = "gpio110";
1382                                 function = "pri_mi2s_ws";
1383                                 drive-strength = <2>;
1384                                 bias-disable;
1385                         };
1386
1387                         sec_mi2s_default: mi2s-sec-default-state {
1388                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1389                                 function = "sec_mi2s";
1390                                 drive-strength = <8>;
1391                                 bias-disable;
1392                         };
1393
1394                         sec_mi2s_sleep: mi2s-sec-sleep-state {
1395                                 pins = "gpio112", "gpio117", "gpio118", "gpio119";
1396                                 function = "sec_mi2s";
1397                                 drive-strength = <2>;
1398                                 bias-disable;
1399                         };
1400
1401                         sdc1_default: sdc1-default-state {
1402                                 clk-pins {
1403                                         pins = "sdc1_clk";
1404                                         bias-disable;
1405                                         drive-strength = <16>;
1406                                 };
1407                                 cmd-pins {
1408                                         pins = "sdc1_cmd";
1409                                         bias-pull-up;
1410                                         drive-strength = <10>;
1411                                 };
1412                                 data-pins {
1413                                         pins = "sdc1_data";
1414                                         bias-pull-up;
1415                                         drive-strength = <10>;
1416                                 };
1417                         };
1418
1419                         sdc1_sleep: sdc1-sleep-state {
1420                                 clk-pins {
1421                                         pins = "sdc1_clk";
1422                                         bias-disable;
1423                                         drive-strength = <2>;
1424                                 };
1425                                 cmd-pins {
1426                                         pins = "sdc1_cmd";
1427                                         bias-pull-up;
1428                                         drive-strength = <2>;
1429                                 };
1430                                 data-pins {
1431                                         pins = "sdc1_data";
1432                                         bias-pull-up;
1433                                         drive-strength = <2>;
1434                                 };
1435                         };
1436
1437                         sdc2_default: sdc2-default-state {
1438                                 clk-pins {
1439                                         pins = "sdc2_clk";
1440                                         bias-disable;
1441                                         drive-strength = <16>;
1442                                 };
1443                                 cmd-pins {
1444                                         pins = "sdc2_cmd";
1445                                         bias-pull-up;
1446                                         drive-strength = <10>;
1447                                 };
1448                                 data-pins {
1449                                         pins = "sdc2_data";
1450                                         bias-pull-up;
1451                                         drive-strength = <10>;
1452                                 };
1453                         };
1454
1455                         sdc2_sleep: sdc2-sleep-state {
1456                                 clk-pins {
1457                                         pins = "sdc2_clk";
1458                                         bias-disable;
1459                                         drive-strength = <2>;
1460                                 };
1461                                 cmd-pins {
1462                                         pins = "sdc2_cmd";
1463                                         bias-pull-up;
1464                                         drive-strength = <2>;
1465                                 };
1466                                 data-pins {
1467                                         pins = "sdc2_data";
1468                                         bias-pull-up;
1469                                         drive-strength = <2>;
1470                                 };
1471                         };
1472
1473                         wcss_wlan_default: wcss-wlan-default-state {
1474                                 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
1475                                 function = "wcss_wlan";
1476                                 drive-strength = <6>;
1477                                 bias-pull-up;
1478                         };
1479                 };
1480
1481                 gcc: clock-controller@1800000 {
1482                         compatible = "qcom,gcc-msm8916";
1483                         #clock-cells = <1>;
1484                         #reset-cells = <1>;
1485                         #power-domain-cells = <1>;
1486                         reg = <0x01800000 0x80000>;
1487                         clocks = <&xo_board>,
1488                                  <&sleep_clk>,
1489                                  <&mdss_dsi0_phy 1>,
1490                                  <&mdss_dsi0_phy 0>,
1491                                  <0>,
1492                                  <0>,
1493                                  <0>;
1494                         clock-names = "xo",
1495                                       "sleep_clk",
1496                                       "dsi0pll",
1497                                       "dsi0pllbyte",
1498                                       "ext_mclk",
1499                                       "ext_pri_i2s",
1500                                       "ext_sec_i2s";
1501                 };
1502
1503                 tcsr_mutex: hwlock@1905000 {
1504                         compatible = "qcom,tcsr-mutex";
1505                         reg = <0x01905000 0x20000>;
1506                         #hwlock-cells = <1>;
1507                 };
1508
1509                 tcsr: syscon@1937000 {
1510                         compatible = "qcom,tcsr-msm8916", "syscon";
1511                         reg = <0x01937000 0x30000>;
1512                 };
1513
1514                 mdss: display-subsystem@1a00000 {
1515                         status = "disabled";
1516                         compatible = "qcom,mdss";
1517                         reg = <0x01a00000 0x1000>,
1518                               <0x01ac8000 0x3000>;
1519                         reg-names = "mdss_phys", "vbif_phys";
1520
1521                         power-domains = <&gcc MDSS_GDSC>;
1522
1523                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
1524                                  <&gcc GCC_MDSS_AXI_CLK>,
1525                                  <&gcc GCC_MDSS_VSYNC_CLK>;
1526                         clock-names = "iface",
1527                                       "bus",
1528                                       "vsync";
1529
1530                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1531
1532                         interrupt-controller;
1533                         #interrupt-cells = <1>;
1534
1535                         #address-cells = <1>;
1536                         #size-cells = <1>;
1537                         ranges;
1538
1539                         mdss_mdp: display-controller@1a01000 {
1540                                 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
1541                                 reg = <0x01a01000 0x89000>;
1542                                 reg-names = "mdp_phys";
1543
1544                                 interrupt-parent = <&mdss>;
1545                                 interrupts = <0>;
1546
1547                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1548                                          <&gcc GCC_MDSS_AXI_CLK>,
1549                                          <&gcc GCC_MDSS_MDP_CLK>,
1550                                          <&gcc GCC_MDSS_VSYNC_CLK>;
1551                                 clock-names = "iface",
1552                                               "bus",
1553                                               "core",
1554                                               "vsync";
1555
1556                                 iommus = <&apps_iommu 4>;
1557
1558                                 ports {
1559                                         #address-cells = <1>;
1560                                         #size-cells = <0>;
1561
1562                                         port@0 {
1563                                                 reg = <0>;
1564                                                 mdss_mdp_intf1_out: endpoint {
1565                                                         remote-endpoint = <&mdss_dsi0_in>;
1566                                                 };
1567                                         };
1568                                 };
1569                         };
1570
1571                         mdss_dsi0: dsi@1a98000 {
1572                                 compatible = "qcom,msm8916-dsi-ctrl",
1573                                              "qcom,mdss-dsi-ctrl";
1574                                 reg = <0x01a98000 0x25c>;
1575                                 reg-names = "dsi_ctrl";
1576
1577                                 interrupt-parent = <&mdss>;
1578                                 interrupts = <4>;
1579
1580                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1581                                                   <&gcc PCLK0_CLK_SRC>;
1582                                 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1583                                                          <&mdss_dsi0_phy 1>;
1584
1585                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1586                                          <&gcc GCC_MDSS_AHB_CLK>,
1587                                          <&gcc GCC_MDSS_AXI_CLK>,
1588                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1589                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1590                                          <&gcc GCC_MDSS_ESC0_CLK>;
1591                                 clock-names = "mdp_core",
1592                                               "iface",
1593                                               "bus",
1594                                               "byte",
1595                                               "pixel",
1596                                               "core";
1597                                 phys = <&mdss_dsi0_phy>;
1598
1599                                 #address-cells = <1>;
1600                                 #size-cells = <0>;
1601
1602                                 ports {
1603                                         #address-cells = <1>;
1604                                         #size-cells = <0>;
1605
1606                                         port@0 {
1607                                                 reg = <0>;
1608                                                 mdss_dsi0_in: endpoint {
1609                                                         remote-endpoint = <&mdss_mdp_intf1_out>;
1610                                                 };
1611                                         };
1612
1613                                         port@1 {
1614                                                 reg = <1>;
1615                                                 mdss_dsi0_out: endpoint {
1616                                                 };
1617                                         };
1618                                 };
1619                         };
1620
1621                         mdss_dsi0_phy: phy@1a98300 {
1622                                 compatible = "qcom,dsi-phy-28nm-lp";
1623                                 reg = <0x01a98300 0xd4>,
1624                                       <0x01a98500 0x280>,
1625                                       <0x01a98780 0x30>;
1626                                 reg-names = "dsi_pll",
1627                                             "dsi_phy",
1628                                             "dsi_phy_regulator";
1629
1630                                 #clock-cells = <1>;
1631                                 #phy-cells = <0>;
1632
1633                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1634                                          <&xo_board>;
1635                                 clock-names = "iface", "ref";
1636                         };
1637                 };
1638
1639                 camss: camss@1b0ac00 {
1640                         compatible = "qcom,msm8916-camss";
1641                         reg = <0x01b0ac00 0x200>,
1642                                 <0x01b00030 0x4>,
1643                                 <0x01b0b000 0x200>,
1644                                 <0x01b00038 0x4>,
1645                                 <0x01b08000 0x100>,
1646                                 <0x01b08400 0x100>,
1647                                 <0x01b0a000 0x500>,
1648                                 <0x01b00020 0x10>,
1649                                 <0x01b10000 0x1000>;
1650                         reg-names = "csiphy0",
1651                                 "csiphy0_clk_mux",
1652                                 "csiphy1",
1653                                 "csiphy1_clk_mux",
1654                                 "csid0",
1655                                 "csid1",
1656                                 "ispif",
1657                                 "csi_clk_mux",
1658                                 "vfe0";
1659                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1660                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1661                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1662                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1663                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1664                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1665                         interrupt-names = "csiphy0",
1666                                 "csiphy1",
1667                                 "csid0",
1668                                 "csid1",
1669                                 "ispif",
1670                                 "vfe0";
1671                         power-domains = <&gcc VFE_GDSC>;
1672                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1673                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1674                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1675                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1676                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1677                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1678                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1679                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1680                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1681                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1682                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1683                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1684                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1685                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1686                                 <&gcc GCC_CAMSS_AHB_CLK>,
1687                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1688                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1689                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1690                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1691                         clock-names = "top_ahb",
1692                                 "ispif_ahb",
1693                                 "csiphy0_timer",
1694                                 "csiphy1_timer",
1695                                 "csi0_ahb",
1696                                 "csi0",
1697                                 "csi0_phy",
1698                                 "csi0_pix",
1699                                 "csi0_rdi",
1700                                 "csi1_ahb",
1701                                 "csi1",
1702                                 "csi1_phy",
1703                                 "csi1_pix",
1704                                 "csi1_rdi",
1705                                 "ahb",
1706                                 "vfe0",
1707                                 "csi_vfe0",
1708                                 "vfe_ahb",
1709                                 "vfe_axi";
1710                         iommus = <&apps_iommu 3>;
1711                         status = "disabled";
1712                         ports {
1713                                 #address-cells = <1>;
1714                                 #size-cells = <0>;
1715                         };
1716                 };
1717
1718                 cci: cci@1b0c000 {
1719                         compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
1720                         #address-cells = <1>;
1721                         #size-cells = <0>;
1722                         reg = <0x01b0c000 0x1000>;
1723                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1724                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1725                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1726                                 <&gcc GCC_CAMSS_CCI_CLK>,
1727                                 <&gcc GCC_CAMSS_AHB_CLK>;
1728                         clock-names = "camss_top_ahb", "cci_ahb",
1729                                           "cci", "camss_ahb";
1730                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1731                                           <&gcc GCC_CAMSS_CCI_CLK>;
1732                         assigned-clock-rates = <80000000>, <19200000>;
1733                         pinctrl-names = "default";
1734                         pinctrl-0 = <&cci0_default>;
1735                         status = "disabled";
1736
1737                         cci_i2c0: i2c-bus@0 {
1738                                 reg = <0>;
1739                                 clock-frequency = <400000>;
1740                                 #address-cells = <1>;
1741                                 #size-cells = <0>;
1742                         };
1743                 };
1744
1745                 gpu@1c00000 {
1746                         compatible = "qcom,adreno-306.0", "qcom,adreno";
1747                         reg = <0x01c00000 0x20000>;
1748                         reg-names = "kgsl_3d0_reg_memory";
1749                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1750                         interrupt-names = "kgsl_3d0_irq";
1751                         clock-names =
1752                             "core",
1753                             "iface",
1754                             "mem",
1755                             "mem_iface",
1756                             "alt_mem_iface",
1757                             "gfx3d";
1758                         clocks =
1759                             <&gcc GCC_OXILI_GFX3D_CLK>,
1760                             <&gcc GCC_OXILI_AHB_CLK>,
1761                             <&gcc GCC_OXILI_GMEM_CLK>,
1762                             <&gcc GCC_BIMC_GFX_CLK>,
1763                             <&gcc GCC_BIMC_GPU_CLK>,
1764                             <&gcc GFX3D_CLK_SRC>;
1765                         power-domains = <&gcc OXILI_GDSC>;
1766                         operating-points-v2 = <&gpu_opp_table>;
1767                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
1768
1769                         gpu_opp_table: opp-table {
1770                                 compatible = "operating-points-v2";
1771
1772                                 opp-400000000 {
1773                                         opp-hz = /bits/ 64 <400000000>;
1774                                 };
1775                                 opp-19200000 {
1776                                         opp-hz = /bits/ 64 <19200000>;
1777                                 };
1778                         };
1779                 };
1780
1781                 venus: video-codec@1d00000 {
1782                         compatible = "qcom,msm8916-venus";
1783                         reg = <0x01d00000 0xff000>;
1784                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1785                         power-domains = <&gcc VENUS_GDSC>;
1786                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1787                                  <&gcc GCC_VENUS0_AHB_CLK>,
1788                                  <&gcc GCC_VENUS0_AXI_CLK>;
1789                         clock-names = "core", "iface", "bus";
1790                         iommus = <&apps_iommu 5>;
1791                         memory-region = <&venus_mem>;
1792                         status = "okay";
1793
1794                         video-decoder {
1795                                 compatible = "venus-decoder";
1796                         };
1797
1798                         video-encoder {
1799                                 compatible = "venus-encoder";
1800                         };
1801                 };
1802
1803                 apps_iommu: iommu@1ef0000 {
1804                         #address-cells = <1>;
1805                         #size-cells = <1>;
1806                         #iommu-cells = <1>;
1807                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1808                         ranges = <0 0x01e20000 0x40000>;
1809                         reg = <0x01ef0000 0x3000>;
1810                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1811                                  <&gcc GCC_APSS_TCU_CLK>;
1812                         clock-names = "iface", "bus";
1813                         qcom,iommu-secure-id = <17>;
1814
1815                         /* VFE */
1816                         iommu-ctx@3000 {
1817                                 compatible = "qcom,msm-iommu-v1-sec";
1818                                 reg = <0x3000 0x1000>;
1819                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1820                         };
1821
1822                         /* MDP_0 */
1823                         iommu-ctx@4000 {
1824                                 compatible = "qcom,msm-iommu-v1-ns";
1825                                 reg = <0x4000 0x1000>;
1826                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1827                         };
1828
1829                         /* VENUS_NS */
1830                         iommu-ctx@5000 {
1831                                 compatible = "qcom,msm-iommu-v1-sec";
1832                                 reg = <0x5000 0x1000>;
1833                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1834                         };
1835                 };
1836
1837                 gpu_iommu: iommu@1f08000 {
1838                         #address-cells = <1>;
1839                         #size-cells = <1>;
1840                         #iommu-cells = <1>;
1841                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
1842                         ranges = <0 0x01f08000 0x10000>;
1843                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
1844                                  <&gcc GCC_GFX_TCU_CLK>;
1845                         clock-names = "iface", "bus";
1846                         qcom,iommu-secure-id = <18>;
1847
1848                         /* GFX3D_USER */
1849                         iommu-ctx@1000 {
1850                                 compatible = "qcom,msm-iommu-v1-ns";
1851                                 reg = <0x1000 0x1000>;
1852                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1853                         };
1854
1855                         /* GFX3D_PRIV */
1856                         iommu-ctx@2000 {
1857                                 compatible = "qcom,msm-iommu-v1-ns";
1858                                 reg = <0x2000 0x1000>;
1859                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1860                         };
1861                 };
1862
1863                 spmi_bus: spmi@200f000 {
1864                         compatible = "qcom,spmi-pmic-arb";
1865                         reg = <0x0200f000 0x001000>,
1866                               <0x02400000 0x400000>,
1867                               <0x02c00000 0x400000>,
1868                               <0x03800000 0x200000>,
1869                               <0x0200a000 0x002100>;
1870                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1871                         interrupt-names = "periph_irq";
1872                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1873                         qcom,ee = <0>;
1874                         qcom,channel = <0>;
1875                         #address-cells = <2>;
1876                         #size-cells = <0>;
1877                         interrupt-controller;
1878                         #interrupt-cells = <4>;
1879                 };
1880
1881                 bam_dmux_dma: dma-controller@4044000 {
1882                         compatible = "qcom,bam-v1.7.0";
1883                         reg = <0x04044000 0x19000>;
1884                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1885                         #dma-cells = <1>;
1886                         qcom,ee = <0>;
1887
1888                         num-channels = <6>;
1889                         qcom,num-ees = <1>;
1890                         qcom,powered-remotely;
1891
1892                         status = "disabled";
1893                 };
1894
1895                 mpss: remoteproc@4080000 {
1896                         compatible = "qcom,msm8916-mss-pil";
1897                         reg = <0x04080000 0x100>,
1898                               <0x04020000 0x040>;
1899
1900                         reg-names = "qdsp6", "rmb";
1901
1902                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
1903                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1904                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1905                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1906                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1907                         interrupt-names = "wdog", "fatal", "ready",
1908                                           "handover", "stop-ack";
1909
1910                         power-domains = <&rpmpd MSM8916_VDDCX>,
1911                                         <&rpmpd MSM8916_VDDMX>;
1912                         power-domain-names = "cx", "mx";
1913
1914                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1915                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1916                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1917                                  <&xo_board>;
1918                         clock-names = "iface", "bus", "mem", "xo";
1919
1920                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1921                         qcom,smem-state-names = "stop";
1922
1923                         resets = <&scm 0>;
1924                         reset-names = "mss_restart";
1925
1926                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1927
1928                         status = "disabled";
1929
1930                         mba {
1931                                 memory-region = <&mba_mem>;
1932                         };
1933
1934                         mpss {
1935                                 memory-region = <&mpss_mem>;
1936                         };
1937
1938                         bam_dmux: bam-dmux {
1939                                 compatible = "qcom,bam-dmux";
1940
1941                                 interrupt-parent = <&hexagon_smsm>;
1942                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
1943                                 interrupt-names = "pc", "pc-ack";
1944
1945                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
1946                                 qcom,smem-state-names = "pc", "pc-ack";
1947
1948                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
1949                                 dma-names = "tx", "rx";
1950
1951                                 status = "disabled";
1952                         };
1953
1954                         smd-edge {
1955                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1956
1957                                 qcom,smd-edge = <0>;
1958                                 qcom,ipc = <&apcs 8 12>;
1959                                 qcom,remote-pid = <1>;
1960
1961                                 label = "hexagon";
1962
1963                                 fastrpc {
1964                                         compatible = "qcom,fastrpc";
1965                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
1966                                         label = "adsp";
1967                                         qcom,non-secure-domain;
1968
1969                                         #address-cells = <1>;
1970                                         #size-cells = <0>;
1971
1972                                         cb@1 {
1973                                                 compatible = "qcom,fastrpc-compute-cb";
1974                                                 reg = <1>;
1975                                         };
1976                                 };
1977                         };
1978                 };
1979
1980                 sound: sound@7702000 {
1981                         status = "disabled";
1982                         compatible = "qcom,apq8016-sbc-sndcard";
1983                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
1984                         reg-names = "mic-iomux", "spkr-iomux";
1985                 };
1986
1987                 lpass: audio-controller@7708000 {
1988                         status = "disabled";
1989                         compatible = "qcom,apq8016-lpass-cpu";
1990
1991                         /*
1992                          * Note: Unlike the name would suggest, the SEC_I2S_CLK
1993                          * is actually only used by Tertiary MI2S while
1994                          * Primary/Secondary MI2S both use the PRI_I2S_CLK.
1995                          */
1996                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
1997                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1998                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
1999                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2000                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2001                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2002                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2003
2004                         clock-names = "ahbix-clk",
2005                                         "mi2s-bit-clk0",
2006                                         "mi2s-bit-clk1",
2007                                         "mi2s-bit-clk2",
2008                                         "mi2s-bit-clk3",
2009                                         "pcnoc-mport-clk",
2010                                         "pcnoc-sway-clk";
2011                         #sound-dai-cells = <1>;
2012
2013                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2014                         interrupt-names = "lpass-irq-lpaif";
2015                         reg = <0x07708000 0x10000>;
2016                         reg-names = "lpass-lpaif";
2017
2018                         #address-cells = <1>;
2019                         #size-cells = <0>;
2020                 };
2021
2022                 lpass_codec: audio-codec@771c000 {
2023                         compatible = "qcom,msm8916-wcd-digital-codec";
2024                         reg = <0x0771c000 0x400>;
2025                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2026                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
2027                         clock-names = "ahbix-clk", "mclk";
2028                         #sound-dai-cells = <1>;
2029                         status = "disabled";
2030                 };
2031
2032                 sdhc_1: mmc@7824900 {
2033                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2034                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
2035                         reg-names = "hc", "core";
2036
2037                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2038                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2039                         interrupt-names = "hc_irq", "pwr_irq";
2040                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2041                                  <&gcc GCC_SDCC1_APPS_CLK>,
2042                                  <&xo_board>;
2043                         clock-names = "iface", "core", "xo";
2044                         pinctrl-0 = <&sdc1_default>;
2045                         pinctrl-1 = <&sdc1_sleep>;
2046                         pinctrl-names = "default", "sleep";
2047                         mmc-ddr-1_8v;
2048                         bus-width = <8>;
2049                         non-removable;
2050                         status = "disabled";
2051                 };
2052
2053                 sdhc_2: mmc@7864900 {
2054                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
2055                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
2056                         reg-names = "hc", "core";
2057
2058                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2059                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2060                         interrupt-names = "hc_irq", "pwr_irq";
2061                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2062                                  <&gcc GCC_SDCC2_APPS_CLK>,
2063                                  <&xo_board>;
2064                         clock-names = "iface", "core", "xo";
2065                         pinctrl-0 = <&sdc2_default>;
2066                         pinctrl-1 = <&sdc2_sleep>;
2067                         pinctrl-names = "default", "sleep";
2068                         bus-width = <4>;
2069                         status = "disabled";
2070                 };
2071
2072                 blsp_dma: dma-controller@7884000 {
2073                         compatible = "qcom,bam-v1.7.0";
2074                         reg = <0x07884000 0x23000>;
2075                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2076                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2077                         clock-names = "bam_clk";
2078                         #dma-cells = <1>;
2079                         qcom,ee = <0>;
2080                 };
2081
2082                 blsp_uart1: serial@78af000 {
2083                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2084                         reg = <0x078af000 0x200>;
2085                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
2086                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2087                         clock-names = "core", "iface";
2088                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
2089                         dma-names = "tx", "rx";
2090                         pinctrl-names = "default", "sleep";
2091                         pinctrl-0 = <&blsp_uart1_default>;
2092                         pinctrl-1 = <&blsp_uart1_sleep>;
2093                         status = "disabled";
2094                 };
2095
2096                 blsp_uart2: serial@78b0000 {
2097                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2098                         reg = <0x078b0000 0x200>;
2099                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
2100                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2101                         clock-names = "core", "iface";
2102                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
2103                         dma-names = "tx", "rx";
2104                         pinctrl-names = "default", "sleep";
2105                         pinctrl-0 = <&blsp_uart2_default>;
2106                         pinctrl-1 = <&blsp_uart2_sleep>;
2107                         status = "disabled";
2108                 };
2109
2110                 blsp_i2c1: i2c@78b5000 {
2111                         compatible = "qcom,i2c-qup-v2.2.1";
2112                         reg = <0x078b5000 0x500>;
2113                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2114                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2115                                  <&gcc GCC_BLSP1_AHB_CLK>;
2116                         clock-names = "core", "iface";
2117                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2118                         dma-names = "tx", "rx";
2119                         pinctrl-names = "default", "sleep";
2120                         pinctrl-0 = <&blsp_i2c1_default>;
2121                         pinctrl-1 = <&blsp_i2c1_sleep>;
2122                         #address-cells = <1>;
2123                         #size-cells = <0>;
2124                         status = "disabled";
2125                 };
2126
2127                 blsp_spi1: spi@78b5000 {
2128                         compatible = "qcom,spi-qup-v2.2.1";
2129                         reg = <0x078b5000 0x500>;
2130                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2131                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2132                                  <&gcc GCC_BLSP1_AHB_CLK>;
2133                         clock-names = "core", "iface";
2134                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
2135                         dma-names = "tx", "rx";
2136                         pinctrl-names = "default", "sleep";
2137                         pinctrl-0 = <&blsp_spi1_default>;
2138                         pinctrl-1 = <&blsp_spi1_sleep>;
2139                         #address-cells = <1>;
2140                         #size-cells = <0>;
2141                         status = "disabled";
2142                 };
2143
2144                 blsp_i2c2: i2c@78b6000 {
2145                         compatible = "qcom,i2c-qup-v2.2.1";
2146                         reg = <0x078b6000 0x500>;
2147                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2148                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2149                                  <&gcc GCC_BLSP1_AHB_CLK>;
2150                         clock-names = "core", "iface";
2151                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2152                         dma-names = "tx", "rx";
2153                         pinctrl-names = "default", "sleep";
2154                         pinctrl-0 = <&blsp_i2c2_default>;
2155                         pinctrl-1 = <&blsp_i2c2_sleep>;
2156                         #address-cells = <1>;
2157                         #size-cells = <0>;
2158                         status = "disabled";
2159                 };
2160
2161                 blsp_spi2: spi@78b6000 {
2162                         compatible = "qcom,spi-qup-v2.2.1";
2163                         reg = <0x078b6000 0x500>;
2164                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2165                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2166                                  <&gcc GCC_BLSP1_AHB_CLK>;
2167                         clock-names = "core", "iface";
2168                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
2169                         dma-names = "tx", "rx";
2170                         pinctrl-names = "default", "sleep";
2171                         pinctrl-0 = <&blsp_spi2_default>;
2172                         pinctrl-1 = <&blsp_spi2_sleep>;
2173                         #address-cells = <1>;
2174                         #size-cells = <0>;
2175                         status = "disabled";
2176                 };
2177
2178                 blsp_i2c3: i2c@78b7000 {
2179                         compatible = "qcom,i2c-qup-v2.2.1";
2180                         reg = <0x078b7000 0x500>;
2181                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2182                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2183                                  <&gcc GCC_BLSP1_AHB_CLK>;
2184                         clock-names = "core", "iface";
2185                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2186                         dma-names = "tx", "rx";
2187                         pinctrl-names = "default", "sleep";
2188                         pinctrl-0 = <&blsp_i2c3_default>;
2189                         pinctrl-1 = <&blsp_i2c3_sleep>;
2190                         #address-cells = <1>;
2191                         #size-cells = <0>;
2192                         status = "disabled";
2193                 };
2194
2195                 blsp_spi3: spi@78b7000 {
2196                         compatible = "qcom,spi-qup-v2.2.1";
2197                         reg = <0x078b7000 0x500>;
2198                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2199                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2200                                  <&gcc GCC_BLSP1_AHB_CLK>;
2201                         clock-names = "core", "iface";
2202                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
2203                         dma-names = "tx", "rx";
2204                         pinctrl-names = "default", "sleep";
2205                         pinctrl-0 = <&blsp_spi3_default>;
2206                         pinctrl-1 = <&blsp_spi3_sleep>;
2207                         #address-cells = <1>;
2208                         #size-cells = <0>;
2209                         status = "disabled";
2210                 };
2211
2212                 blsp_i2c4: i2c@78b8000 {
2213                         compatible = "qcom,i2c-qup-v2.2.1";
2214                         reg = <0x078b8000 0x500>;
2215                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2216                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2217                                  <&gcc GCC_BLSP1_AHB_CLK>;
2218                         clock-names = "core", "iface";
2219                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2220                         dma-names = "tx", "rx";
2221                         pinctrl-names = "default", "sleep";
2222                         pinctrl-0 = <&blsp_i2c4_default>;
2223                         pinctrl-1 = <&blsp_i2c4_sleep>;
2224                         #address-cells = <1>;
2225                         #size-cells = <0>;
2226                         status = "disabled";
2227                 };
2228
2229                 blsp_spi4: spi@78b8000 {
2230                         compatible = "qcom,spi-qup-v2.2.1";
2231                         reg = <0x078b8000 0x500>;
2232                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2233                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2234                                  <&gcc GCC_BLSP1_AHB_CLK>;
2235                         clock-names = "core", "iface";
2236                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
2237                         dma-names = "tx", "rx";
2238                         pinctrl-names = "default", "sleep";
2239                         pinctrl-0 = <&blsp_spi4_default>;
2240                         pinctrl-1 = <&blsp_spi4_sleep>;
2241                         #address-cells = <1>;
2242                         #size-cells = <0>;
2243                         status = "disabled";
2244                 };
2245
2246                 blsp_i2c5: i2c@78b9000 {
2247                         compatible = "qcom,i2c-qup-v2.2.1";
2248                         reg = <0x078b9000 0x500>;
2249                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2250                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2251                                  <&gcc GCC_BLSP1_AHB_CLK>;
2252                         clock-names = "core", "iface";
2253                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2254                         dma-names = "tx", "rx";
2255                         pinctrl-names = "default", "sleep";
2256                         pinctrl-0 = <&blsp_i2c5_default>;
2257                         pinctrl-1 = <&blsp_i2c5_sleep>;
2258                         #address-cells = <1>;
2259                         #size-cells = <0>;
2260                         status = "disabled";
2261                 };
2262
2263                 blsp_spi5: spi@78b9000 {
2264                         compatible = "qcom,spi-qup-v2.2.1";
2265                         reg = <0x078b9000 0x500>;
2266                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2267                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2268                                  <&gcc GCC_BLSP1_AHB_CLK>;
2269                         clock-names = "core", "iface";
2270                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
2271                         dma-names = "tx", "rx";
2272                         pinctrl-names = "default", "sleep";
2273                         pinctrl-0 = <&blsp_spi5_default>;
2274                         pinctrl-1 = <&blsp_spi5_sleep>;
2275                         #address-cells = <1>;
2276                         #size-cells = <0>;
2277                         status = "disabled";
2278                 };
2279
2280                 blsp_i2c6: i2c@78ba000 {
2281                         compatible = "qcom,i2c-qup-v2.2.1";
2282                         reg = <0x078ba000 0x500>;
2283                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2284                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2285                                  <&gcc GCC_BLSP1_AHB_CLK>;
2286                         clock-names = "core", "iface";
2287                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2288                         dma-names = "tx", "rx";
2289                         pinctrl-names = "default", "sleep";
2290                         pinctrl-0 = <&blsp_i2c6_default>;
2291                         pinctrl-1 = <&blsp_i2c6_sleep>;
2292                         #address-cells = <1>;
2293                         #size-cells = <0>;
2294                         status = "disabled";
2295                 };
2296
2297                 blsp_spi6: spi@78ba000 {
2298                         compatible = "qcom,spi-qup-v2.2.1";
2299                         reg = <0x078ba000 0x500>;
2300                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2301                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2302                                  <&gcc GCC_BLSP1_AHB_CLK>;
2303                         clock-names = "core", "iface";
2304                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
2305                         dma-names = "tx", "rx";
2306                         pinctrl-names = "default", "sleep";
2307                         pinctrl-0 = <&blsp_spi6_default>;
2308                         pinctrl-1 = <&blsp_spi6_sleep>;
2309                         #address-cells = <1>;
2310                         #size-cells = <0>;
2311                         status = "disabled";
2312                 };
2313
2314                 usb: usb@78d9000 {
2315                         compatible = "qcom,ci-hdrc";
2316                         reg = <0x078d9000 0x200>,
2317                               <0x078d9200 0x200>;
2318                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2319                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2320                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2321                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
2322                         clock-names = "iface", "core";
2323                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2324                         assigned-clock-rates = <80000000>;
2325                         resets = <&gcc GCC_USB_HS_BCR>;
2326                         reset-names = "core";
2327                         phy_type = "ulpi";
2328                         dr_mode = "otg";
2329                         hnp-disable;
2330                         srp-disable;
2331                         adp-disable;
2332                         ahb-burst-config = <0>;
2333                         phy-names = "usb-phy";
2334                         phys = <&usb_hs_phy>;
2335                         status = "disabled";
2336                         #reset-cells = <1>;
2337
2338                         ulpi {
2339                                 usb_hs_phy: phy {
2340                                         compatible = "qcom,usb-hs-phy-msm8916",
2341                                                      "qcom,usb-hs-phy";
2342                                         #phy-cells = <0>;
2343                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2344                                         clock-names = "ref", "sleep";
2345                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2346                                         reset-names = "phy", "por";
2347                                         qcom,init-seq = /bits/ 8 <0x0 0x44>,
2348                                                                  <0x1 0x6b>,
2349                                                                  <0x2 0x24>,
2350                                                                  <0x3 0x13>;
2351                                 };
2352                         };
2353                 };
2354
2355                 wcnss: remoteproc@a204000 {
2356                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
2357                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
2358                         reg-names = "ccu", "dxe", "pmu";
2359
2360                         memory-region = <&wcnss_mem>;
2361
2362                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
2363                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2364                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2365                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2366                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2367                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
2368
2369                         power-domains = <&rpmpd MSM8916_VDDCX>,
2370                                         <&rpmpd MSM8916_VDDMX>;
2371                         power-domain-names = "cx", "mx";
2372
2373                         qcom,smem-states = <&wcnss_smp2p_out 0>;
2374                         qcom,smem-state-names = "stop";
2375
2376                         pinctrl-names = "default";
2377                         pinctrl-0 = <&wcss_wlan_default>;
2378
2379                         status = "disabled";
2380
2381                         wcnss_iris: iris {
2382                                 /* Separate chip, compatible is board-specific */
2383                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
2384                                 clock-names = "xo";
2385                         };
2386
2387                         smd-edge {
2388                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
2389
2390                                 qcom,ipc = <&apcs 8 17>;
2391                                 qcom,smd-edge = <6>;
2392                                 qcom,remote-pid = <4>;
2393
2394                                 label = "pronto";
2395
2396                                 wcnss_ctrl: wcnss {
2397                                         compatible = "qcom,wcnss";
2398                                         qcom,smd-channels = "WCNSS_CTRL";
2399
2400                                         qcom,mmio = <&wcnss>;
2401
2402                                         wcnss_bt: bluetooth {
2403                                                 compatible = "qcom,wcnss-bt";
2404                                         };
2405
2406                                         wcnss_wifi: wifi {
2407                                                 compatible = "qcom,wcnss-wlan";
2408
2409                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2410                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
2411                                                 interrupt-names = "tx", "rx";
2412
2413                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
2414                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
2415                                         };
2416                                 };
2417                         };
2418                 };
2419
2420                 intc: interrupt-controller@b000000 {
2421                         compatible = "qcom,msm-qgic2";
2422                         interrupt-controller;
2423                         #interrupt-cells = <3>;
2424                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
2425                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
2426                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
2427                 };
2428
2429                 apcs: mailbox@b011000 {
2430                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
2431                         reg = <0x0b011000 0x1000>;
2432                         #mbox-cells = <1>;
2433                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
2434                         clock-names = "pll", "aux";
2435                         #clock-cells = <0>;
2436                 };
2437
2438                 a53pll: clock@b016000 {
2439                         compatible = "qcom,msm8916-a53pll";
2440                         reg = <0x0b016000 0x40>;
2441                         #clock-cells = <0>;
2442                         clocks = <&xo_board>;
2443                         clock-names = "xo";
2444                 };
2445
2446                 timer@b020000 {
2447                         #address-cells = <1>;
2448                         #size-cells = <1>;
2449                         ranges;
2450                         compatible = "arm,armv7-timer-mem";
2451                         reg = <0x0b020000 0x1000>;
2452                         clock-frequency = <19200000>;
2453
2454                         frame@b021000 {
2455                                 frame-number = <0>;
2456                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
2457                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2458                                 reg = <0x0b021000 0x1000>,
2459                                       <0x0b022000 0x1000>;
2460                         };
2461
2462                         frame@b023000 {
2463                                 frame-number = <1>;
2464                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
2465                                 reg = <0x0b023000 0x1000>;
2466                                 status = "disabled";
2467                         };
2468
2469                         frame@b024000 {
2470                                 frame-number = <2>;
2471                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
2472                                 reg = <0x0b024000 0x1000>;
2473                                 status = "disabled";
2474                         };
2475
2476                         frame@b025000 {
2477                                 frame-number = <3>;
2478                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
2479                                 reg = <0x0b025000 0x1000>;
2480                                 status = "disabled";
2481                         };
2482
2483                         frame@b026000 {
2484                                 frame-number = <4>;
2485                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
2486                                 reg = <0x0b026000 0x1000>;
2487                                 status = "disabled";
2488                         };
2489
2490                         frame@b027000 {
2491                                 frame-number = <5>;
2492                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2493                                 reg = <0x0b027000 0x1000>;
2494                                 status = "disabled";
2495                         };
2496
2497                         frame@b028000 {
2498                                 frame-number = <6>;
2499                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2500                                 reg = <0x0b028000 0x1000>;
2501                                 status = "disabled";
2502                         };
2503                 };
2504
2505                 cpu0_acc: power-manager@b088000 {
2506                         compatible = "qcom,msm8916-acc";
2507                         reg = <0x0b088000 0x1000>;
2508                         status = "reserved"; /* Controlled by PSCI firmware */
2509                 };
2510
2511                 cpu0_saw: power-manager@b089000 {
2512                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2513                         reg = <0x0b089000 0x1000>;
2514                         status = "reserved"; /* Controlled by PSCI firmware */
2515                 };
2516
2517                 cpu1_acc: power-manager@b098000 {
2518                         compatible = "qcom,msm8916-acc";
2519                         reg = <0x0b098000 0x1000>;
2520                         status = "reserved"; /* Controlled by PSCI firmware */
2521                 };
2522
2523                 cpu1_saw: power-manager@b099000 {
2524                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2525                         reg = <0x0b099000 0x1000>;
2526                         status = "reserved"; /* Controlled by PSCI firmware */
2527                 };
2528
2529                 cpu2_acc: power-manager@b0a8000 {
2530                         compatible = "qcom,msm8916-acc";
2531                         reg = <0x0b0a8000 0x1000>;
2532                         status = "reserved"; /* Controlled by PSCI firmware */
2533                 };
2534
2535                 cpu2_saw: power-manager@b0a9000 {
2536                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2537                         reg = <0x0b0a9000 0x1000>;
2538                         status = "reserved"; /* Controlled by PSCI firmware */
2539                 };
2540
2541                 cpu3_acc: power-manager@b0b8000 {
2542                         compatible = "qcom,msm8916-acc";
2543                         reg = <0x0b0b8000 0x1000>;
2544                         status = "reserved"; /* Controlled by PSCI firmware */
2545                 };
2546
2547                 cpu3_saw: power-manager@b0b9000 {
2548                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
2549                         reg = <0x0b0b9000 0x1000>;
2550                         status = "reserved"; /* Controlled by PSCI firmware */
2551                 };
2552         };
2553
2554         thermal-zones {
2555                 cpu0-1-thermal {
2556                         polling-delay-passive = <250>;
2557                         polling-delay = <1000>;
2558
2559                         thermal-sensors = <&tsens 5>;
2560
2561                         trips {
2562                                 cpu0_1_alert0: trip-point0 {
2563                                         temperature = <75000>;
2564                                         hysteresis = <2000>;
2565                                         type = "passive";
2566                                 };
2567                                 cpu0_1_crit: cpu-crit {
2568                                         temperature = <110000>;
2569                                         hysteresis = <2000>;
2570                                         type = "critical";
2571                                 };
2572                         };
2573
2574                         cooling-maps {
2575                                 map0 {
2576                                         trip = <&cpu0_1_alert0>;
2577                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2578                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2579                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2580                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2581                                 };
2582                         };
2583                 };
2584
2585                 cpu2-3-thermal {
2586                         polling-delay-passive = <250>;
2587                         polling-delay = <1000>;
2588
2589                         thermal-sensors = <&tsens 4>;
2590
2591                         trips {
2592                                 cpu2_3_alert0: trip-point0 {
2593                                         temperature = <75000>;
2594                                         hysteresis = <2000>;
2595                                         type = "passive";
2596                                 };
2597                                 cpu2_3_crit: cpu-crit {
2598                                         temperature = <110000>;
2599                                         hysteresis = <2000>;
2600                                         type = "critical";
2601                                 };
2602                         };
2603
2604                         cooling-maps {
2605                                 map0 {
2606                                         trip = <&cpu2_3_alert0>;
2607                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2608                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2609                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2610                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2611                                 };
2612                         };
2613                 };
2614
2615                 gpu-thermal {
2616                         polling-delay-passive = <250>;
2617                         polling-delay = <1000>;
2618
2619                         thermal-sensors = <&tsens 2>;
2620
2621                         trips {
2622                                 gpu_alert0: trip-point0 {
2623                                         temperature = <75000>;
2624                                         hysteresis = <2000>;
2625                                         type = "passive";
2626                                 };
2627                                 gpu_crit: gpu-crit {
2628                                         temperature = <95000>;
2629                                         hysteresis = <2000>;
2630                                         type = "critical";
2631                                 };
2632                         };
2633                 };
2634
2635                 camera-thermal {
2636                         polling-delay-passive = <250>;
2637                         polling-delay = <1000>;
2638
2639                         thermal-sensors = <&tsens 1>;
2640
2641                         trips {
2642                                 cam_alert0: trip-point0 {
2643                                         temperature = <75000>;
2644                                         hysteresis = <2000>;
2645                                         type = "hot";
2646                                 };
2647                         };
2648                 };
2649
2650                 modem-thermal {
2651                         polling-delay-passive = <250>;
2652                         polling-delay = <1000>;
2653
2654                         thermal-sensors = <&tsens 0>;
2655
2656                         trips {
2657                                 modem_alert0: trip-point0 {
2658                                         temperature = <85000>;
2659                                         hysteresis = <2000>;
2660                                         type = "hot";
2661                                 };
2662                         };
2663                 };
2664         };
2665
2666         timer {
2667                 compatible = "arm,armv8-timer";
2668                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2669                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2670                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2671                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2672         };
2673 };