arch/arm64/boot/dts/qcom/ipq9574.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * IPQ9574 SoC device tree source
   4  *
   5  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
   6  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   7  */
   8
   9 #include <dt-bindings/clock/qcom,apss-ipq.h>
  10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         clocks {
  20                 sleep_clk: sleep-clk {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                 };
  24
  25                 xo_board_clk: xo-board-clk {
  26                         compatible = "fixed-clock";
  27                         #clock-cells = <0>;
  28                 };
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 CPU0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a73";
  38                         reg = <0x0>;
  39                         enable-method = "psci";
  40                         next-level-cache = <&L2_0>;
  41                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  42                         clock-names = "cpu";
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-supply = <&ipq9574_s1>;
  45                 };
  46
  47                 CPU1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a73";
  50                         reg = <0x1>;
  51                         enable-method = "psci";
  52                         next-level-cache = <&L2_0>;
  53                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  54                         clock-names = "cpu";
  55                         operating-points-v2 = <&cpu_opp_table>;
  56                         cpu-supply = <&ipq9574_s1>;
  57                 };
  58
  59                 CPU2: cpu@2 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a73";
  62                         reg = <0x2>;
  63                         enable-method = "psci";
  64                         next-level-cache = <&L2_0>;
  65                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  66                         clock-names = "cpu";
  67                         operating-points-v2 = <&cpu_opp_table>;
  68                         cpu-supply = <&ipq9574_s1>;
  69                 };
  70
  71                 CPU3: cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a73";
  74                         reg = <0x3>;
  75                         enable-method = "psci";
  76                         next-level-cache = <&L2_0>;
  77                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
  78                         clock-names = "cpu";
  79                         operating-points-v2 = <&cpu_opp_table>;
  80                         cpu-supply = <&ipq9574_s1>;
  81                 };
  82
  83                 L2_0: l2-cache {
  84                         compatible = "cache";
  85                         cache-level = <2>;
  86                 };
  87         };
  88
  89         firmware {
  90                 scm {
  91                         compatible = "qcom,scm-ipq9574", "qcom,scm";
  92                         qcom,dload-mode = <&tcsr 0x6100>;
  93                 };
  94         };
  95
  96         memory@40000000 {
  97                 device_type = "memory";
  98                 /* We expect the bootloader to fill in the size */
  99                 reg = <0x0 0x40000000 0x0 0x0>;
 100         };
 101
 102         cpu_opp_table: opp-table-cpu {
 103                 compatible = "operating-points-v2";
 104                 opp-shared;
 105
 106                 opp-936000000 {
 107                         opp-hz = /bits/ 64 <936000000>;
 108                         opp-microvolt = <725000>;
 109                         clock-latency-ns = <200000>;
 110                 };
 111
 112                 opp-1104000000 {
 113                         opp-hz = /bits/ 64 <1104000000>;
 114                         opp-microvolt = <787500>;
 115                         clock-latency-ns = <200000>;
 116                 };
 117
 118                 opp-1416000000 {
 119                         opp-hz = /bits/ 64 <1416000000>;
 120                         opp-microvolt = <862500>;
 121                         clock-latency-ns = <200000>;
 122                 };
 123
 124                 opp-1488000000 {
 125                         opp-hz = /bits/ 64 <1488000000>;
 126                         opp-microvolt = <925000>;
 127                         clock-latency-ns = <200000>;
 128                 };
 129
 130                 opp-1800000000 {
 131                         opp-hz = /bits/ 64 <1800000000>;
 132                         opp-microvolt = <987500>;
 133                         clock-latency-ns = <200000>;
 134                 };
 135
 136                 opp-2208000000 {
 137                         opp-hz = /bits/ 64 <2208000000>;
 138                         opp-microvolt = <1062500>;
 139                         clock-latency-ns = <200000>;
 140                 };
 141         };
 142
 143         pmu {
 144                 compatible = "arm,cortex-a73-pmu";
 145                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 146         };
 147
 148         psci {
 149                 compatible = "arm,psci-1.0";
 150                 method = "smc";
 151         };
 152
 153         reserved-memory {
 154                 #address-cells = <2>;
 155                 #size-cells = <2>;
 156                 ranges;
 157
 158                 bootloader@4a100000 {
 159                         reg = <0x0 0x4a100000 0x0 0x400000>;
 160                         no-map;
 161                 };
 162
 163                 sbl@4a500000 {
 164                         reg = <0x0 0x4a500000 0x0 0x100000>;
 165                         no-map;
 166                 };
 167
 168                 tz_region: tz@4a600000 {
 169                         reg = <0x0 0x4a600000 0x0 0x400000>;
 170                         no-map;
 171                 };
 172
 173                 smem@4aa00000 {
 174                         compatible = "qcom,smem";
 175                         reg = <0x0 0x4aa00000 0x0 0x100000>;
 176                         hwlocks = <&tcsr_mutex 0>;
 177                         no-map;
 178                 };
 179         };
 180
 181         rpm-glink {
 182                 compatible = "qcom,glink-rpm";
 183                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 184                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 185                 mboxes = <&apcs_glb 0>;
 186
 187                 rpm_requests: rpm-requests {
 188                         compatible = "qcom,rpm-ipq9574";
 189                         qcom,glink-channels = "rpm_requests";
 190                 };
 191         };
 192
 193         soc: soc@0 {
 194                 compatible = "simple-bus";
 195                 #address-cells = <1>;
 196                 #size-cells = <1>;
 197                 ranges = <0 0 0 0xffffffff>;
 198
 199                 rpm_msg_ram: sram@60000 {
 200                         compatible = "qcom,rpm-msg-ram";
 201                         reg = <0x00060000 0x6000>;
 202                 };
 203
 204                 rng: rng@e3000 {
 205                         compatible = "qcom,prng-ee";
 206                         reg = <0x000e3000 0x1000>;
 207                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 208                         clock-names = "core";
 209                 };
 210
 211                 qfprom: efuse@a4000 {
 212                         compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
 213                         reg = <0x000a4000 0x5a1>;
 214                         #address-cells = <1>;
 215                         #size-cells = <1>;
 216                 };
 217
 218                 cryptobam: dma-controller@704000 {
 219                         compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 220                         reg = <0x00704000 0x20000>;
 221                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 222                         #dma-cells = <1>;
 223                         qcom,ee = <1>;
 224                         qcom,controlled-remotely;
 225                 };
 226
 227                 crypto: crypto@73a000 {
 228                         compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
 229                         reg = <0x0073a000 0x6000>;
 230                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 231                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 232                                  <&gcc GCC_CRYPTO_CLK>;
 233                         clock-names = "iface", "bus", "core";
 234                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 235                         dma-names = "rx", "tx";
 236                 };
 237
 238                 tsens: thermal-sensor@4a9000 {
 239                         compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
 240                         reg = <0x004a9000 0x1000>,
 241                               <0x004a8000 0x1000>;
 242                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 243                         interrupt-names = "combined";
 244                         #qcom,sensors = <16>;
 245                         #thermal-sensor-cells = <1>;
 246                 };
 247
 248                 tlmm: pinctrl@1000000 {
 249                         compatible = "qcom,ipq9574-tlmm";
 250                         reg = <0x01000000 0x300000>;
 251                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                         gpio-ranges = <&tlmm 0 0 65>;
 255                         interrupt-controller;
 256                         #interrupt-cells = <2>;
 257
 258                         uart2_pins: uart2-state {
 259                                 pins = "gpio34", "gpio35";
 260                                 function = "blsp2_uart";
 261                                 drive-strength = <8>;
 262                                 bias-disable;
 263                         };
 264                 };
 265
 266                 gcc: clock-controller@1800000 {
 267                         compatible = "qcom,ipq9574-gcc";
 268                         reg = <0x01800000 0x80000>;
 269                         clocks = <&xo_board_clk>,
 270                                  <&sleep_clk>,
 271                                  <0>,
 272                                  <0>,
 273                                  <0>,
 274                                  <0>,
 275                                  <0>,
 276                                  <0>;
 277                         #clock-cells = <1>;
 278                         #reset-cells = <1>;
 279                         #power-domain-cells = <1>;
 280                 };
 281
 282                 tcsr_mutex: hwlock@1905000 {
 283                         compatible = "qcom,tcsr-mutex";
 284                         reg = <0x01905000 0x20000>;
 285                         #hwlock-cells = <1>;
 286                 };
 287
 288                 tcsr: syscon@1937000 {
 289                         compatible = "qcom,tcsr-ipq9574", "syscon";
 290                         reg = <0x01937000 0x21000>;
 291                 };
 292
 293                 sdhc_1: mmc@7804000 {
 294                         compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
 295                         reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
 296                         reg-names = "hc", "cqhci";
 297
 298                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 299                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 300                         interrupt-names = "hc_irq", "pwr_irq";
 301
 302                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 303                                  <&gcc GCC_SDCC1_APPS_CLK>,
 304                                  <&xo_board_clk>;
 305                         clock-names = "iface", "core", "xo";
 306                         non-removable;
 307                         status = "disabled";
 308                 };
 309
 310                 blsp_dma: dma-controller@7884000 {
 311                         compatible = "qcom,bam-v1.7.0";
 312                         reg = <0x07884000 0x2b000>;
 313                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 315                         clock-names = "bam_clk";
 316                         #dma-cells = <1>;
 317                         qcom,ee = <0>;
 318                 };
 319
 320                 blsp1_uart0: serial@78af000 {
 321                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 322                         reg = <0x078af000 0x200>;
 323                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 325                                  <&gcc GCC_BLSP1_AHB_CLK>;
 326                         clock-names = "core", "iface";
 327                         status = "disabled";
 328                 };
 329
 330                 blsp1_uart1: serial@78b0000 {
 331                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 332                         reg = <0x078b0000 0x200>;
 333                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 334                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 335                                  <&gcc GCC_BLSP1_AHB_CLK>;
 336                         clock-names = "core", "iface";
 337                         status = "disabled";
 338                 };
 339
 340                 blsp1_uart2: serial@78b1000 {
 341                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 342                         reg = <0x078b1000 0x200>;
 343                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 345                                  <&gcc GCC_BLSP1_AHB_CLK>;
 346                         clock-names = "core", "iface";
 347                         status = "disabled";
 348                 };
 349
 350                 blsp1_uart3: serial@78b2000 {
 351                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 352                         reg = <0x078b2000 0x200>;
 353                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
 355                                  <&gcc GCC_BLSP1_AHB_CLK>;
 356                         clock-names = "core", "iface";
 357                         status = "disabled";
 358                 };
 359
 360                 blsp1_uart4: serial@78b3000 {
 361                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 362                         reg = <0x078b3000 0x200>;
 363                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 365                                  <&gcc GCC_BLSP1_AHB_CLK>;
 366                         clock-names = "core", "iface";
 367                         status = "disabled";
 368                 };
 369
 370                 blsp1_uart5: serial@78b4000 {
 371                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 372                         reg = <0x078b4000 0x200>;
 373                         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
 375                                  <&gcc GCC_BLSP1_AHB_CLK>;
 376                         clock-names = "core", "iface";
 377                         status = "disabled";
 378                 };
 379
 380                 blsp1_spi0: spi@78b5000 {
 381                         compatible = "qcom,spi-qup-v2.2.1";
 382                         reg = <0x078b5000 0x600>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 387                                  <&gcc GCC_BLSP1_AHB_CLK>;
 388                         clock-names = "core", "iface";
 389                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 390                         dma-names = "tx", "rx";
 391                         status = "disabled";
 392                 };
 393
 394                 blsp1_i2c1: i2c@78b6000 {
 395                         compatible = "qcom,i2c-qup-v2.2.1";
 396                         reg = <0x078b6000 0x600>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 401                                  <&gcc GCC_BLSP1_AHB_CLK>;
 402                         clock-names = "core", "iface";
 403                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 404                         dma-names = "tx", "rx";
 405                         status = "disabled";
 406                 };
 407
 408                 blsp1_spi1: spi@78b6000 {
 409                         compatible = "qcom,spi-qup-v2.2.1";
 410                         reg = <0x078b6000 0x600>;
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 415                                  <&gcc GCC_BLSP1_AHB_CLK>;
 416                         clock-names = "core", "iface";
 417                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 418                         dma-names = "tx", "rx";
 419                         status = "disabled";
 420                 };
 421
 422                 blsp1_i2c2: i2c@78b7000 {
 423                         compatible = "qcom,i2c-qup-v2.2.1";
 424                         reg = <0x078b7000 0x600>;
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 429                                  <&gcc GCC_BLSP1_AHB_CLK>;
 430                         clock-names = "core", "iface";
 431                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 432                         dma-names = "tx", "rx";
 433                         status = "disabled";
 434                 };
 435
 436                 blsp1_spi2: spi@78b7000 {
 437                         compatible = "qcom,spi-qup-v2.2.1";
 438                         reg = <0x078b7000 0x600>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 442                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 443                                  <&gcc GCC_BLSP1_AHB_CLK>;
 444                         clock-names = "core", "iface";
 445                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
 446                         dma-names = "tx", "rx";
 447                         status = "disabled";
 448                 };
 449
 450                 blsp1_i2c3: i2c@78b8000 {
 451                         compatible = "qcom,i2c-qup-v2.2.1";
 452                         reg = <0x078b8000 0x600>;
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 457                                  <&gcc GCC_BLSP1_AHB_CLK>;
 458                         clock-names = "core", "iface";
 459                         dmas = <&blsp_dma 18>, <&blsp_dma 19>;
 460                         dma-names = "tx", "rx";
 461                         status = "disabled";
 462                 };
 463
 464                 blsp1_spi3: spi@78b8000 {
 465                         compatible = "qcom,spi-qup-v2.2.1";
 466                         reg = <0x078b8000 0x600>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 470                         spi-max-frequency = <50000000>;
 471                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 472                                  <&gcc GCC_BLSP1_AHB_CLK>;
 473                         clock-names = "core", "iface";
 474                         dmas = <&blsp_dma 18>, <&blsp_dma 19>;
 475                         dma-names = "tx", "rx";
 476                         status = "disabled";
 477                 };
 478
 479                 blsp1_i2c4: i2c@78b9000 {
 480                         compatible = "qcom,i2c-qup-v2.2.1";
 481                         reg = <0x078b9000 0x600>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 485                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 486                                  <&gcc GCC_BLSP1_AHB_CLK>;
 487                         clock-names = "core", "iface";
 488                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 489                         dma-names = "tx", "rx";
 490                         status = "disabled";
 491                 };
 492
 493                 blsp1_spi4: spi@78b9000 {
 494                         compatible = "qcom,spi-qup-v2.2.1";
 495                         reg = <0x078b9000 0x600>;
 496                         #address-cells = <1>;
 497                         #size-cells = <0>;
 498                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 500                                  <&gcc GCC_BLSP1_AHB_CLK>;
 501                         clock-names = "core", "iface";
 502                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
 503                         dma-names = "tx", "rx";
 504                         status = "disabled";
 505                 };
 506
 507                 intc: interrupt-controller@b000000 {
 508                         compatible = "qcom,msm-qgic2";
 509                         reg = <0x0b000000 0x1000>,  /* GICD */
 510                               <0x0b002000 0x2000>,  /* GICC */
 511                               <0x0b001000 0x1000>,  /* GICH */
 512                               <0x0b004000 0x2000>;  /* GICV */
 513                         #address-cells = <1>;
 514                         #size-cells = <1>;
 515                         interrupt-controller;
 516                         #interrupt-cells = <3>;
 517                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 518                         ranges = <0 0x0b00c000 0x3000>;
 519
 520                         v2m0: v2m@0 {
 521                                 compatible = "arm,gic-v2m-frame";
 522                                 reg = <0x00000000 0xffd>;
 523                                 msi-controller;
 524                         };
 525
 526                         v2m1: v2m@1000 {
 527                                 compatible = "arm,gic-v2m-frame";
 528                                 reg = <0x00001000 0xffd>;
 529                                 msi-controller;
 530                         };
 531
 532                         v2m2: v2m@2000 {
 533                                 compatible = "arm,gic-v2m-frame";
 534                                 reg = <0x00002000 0xffd>;
 535                                 msi-controller;
 536                         };
 537                 };
 538
 539                 watchdog: watchdog@b017000 {
 540                         compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
 541                         reg = <0x0b017000 0x1000>;
 542                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 543                         clocks = <&sleep_clk>;
 544                         timeout-sec = <30>;
 545                 };
 546
 547                 apcs_glb: mailbox@b111000 {
 548                         compatible = "qcom,ipq9574-apcs-apps-global",
 549                                      "qcom,ipq6018-apcs-apps-global";
 550                         reg = <0x0b111000 0x1000>;
 551                         #clock-cells = <1>;
 552                         clocks = <&a73pll>, <&xo_board_clk>;
 553                         clock-names = "pll", "xo";
 554                         #mbox-cells = <1>;
 555                 };
 556
 557                 a73pll: clock@b116000 {
 558                         compatible = "qcom,ipq9574-a73pll";
 559                         reg = <0x0b116000 0x40>;
 560                         #clock-cells = <0>;
 561                         clocks = <&xo_board_clk>;
 562                         clock-names = "xo";
 563                 };
 564
 565                 timer@b120000 {
 566                         compatible = "arm,armv7-timer-mem";
 567                         reg = <0x0b120000 0x1000>;
 568                         #address-cells = <1>;
 569                         #size-cells = <1>;
 570                         ranges;
 571
 572                         frame@b120000 {
 573                                 reg = <0x0b121000 0x1000>,
 574                                       <0x0b122000 0x1000>;
 575                                 frame-number = <0>;
 576                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 577                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 578                         };
 579
 580                         frame@b123000 {
 581                                 reg = <0x0b123000 0x1000>;
 582                                 frame-number = <1>;
 583                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 584                                 status = "disabled";
 585                         };
 586
 587                         frame@b124000 {
 588                                 reg = <0x0b124000 0x1000>;
 589                                 frame-number = <2>;
 590                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 591                                 status = "disabled";
 592                         };
 593
 594                         frame@b125000 {
 595                                 reg = <0x0b125000 0x1000>;
 596                                 frame-number = <3>;
 597                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 598                                 status = "disabled";
 599                         };
 600
 601                         frame@b126000 {
 602                                 reg = <0x0b126000 0x1000>;
 603                                 frame-number = <4>;
 604                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 605                                 status = "disabled";
 606                         };
 607
 608                         frame@b127000 {
 609                                 reg = <0x0b127000 0x1000>;
 610                                 frame-number = <5>;
 611                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 612                                 status = "disabled";
 613                         };
 614
 615                         frame@b128000 {
 616                                 reg = <0x0b128000 0x1000>;
 617                                 frame-number = <6>;
 618                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 619                                 status = "disabled";
 620                         };
 621                 };
 622         };
 623
 624         thermal-zones {
 625                 nss-top-thermal {
 626                         polling-delay-passive = <0>;
 627                         polling-delay = <0>;
 628                         thermal-sensors = <&tsens 3>;
 629
 630                         trips {
 631                                 nss-top-critical {
 632                                         temperature = <125000>;
 633                                         hysteresis = <1000>;
 634                                         type = "critical";
 635                                 };
 636                         };
 637                 };
 638
 639                 ubi-0-thermal {
 640                         polling-delay-passive = <0>;
 641                         polling-delay = <0>;
 642                         thermal-sensors = <&tsens 4>;
 643
 644                         trips {
 645                                 ubi_0-critical {
 646                                         temperature = <125000>;
 647                                         hysteresis = <1000>;
 648                                         type = "critical";
 649                                 };
 650                         };
 651                 };
 652
 653                 ubi-1-thermal {
 654                         polling-delay-passive = <0>;
 655                         polling-delay = <0>;
 656                         thermal-sensors = <&tsens 5>;
 657
 658                         trips {
 659                                 ubi_1-critical {
 660                                         temperature = <125000>;
 661                                         hysteresis = <1000>;
 662                                         type = "critical";
 663                                 };
 664                         };
 665                 };
 666
 667                 ubi-2-thermal {
 668                         polling-delay-passive = <0>;
 669                         polling-delay = <0>;
 670                         thermal-sensors = <&tsens 6>;
 671
 672                         trips {
 673                                 ubi_2-critical {
 674                                         temperature = <125000>;
 675                                         hysteresis = <1000>;
 676                                         type = "critical";
 677                                 };
 678                         };
 679                 };
 680
 681                 ubi-3-thermal {
 682                         polling-delay-passive = <0>;
 683                         polling-delay = <0>;
 684                         thermal-sensors = <&tsens 7>;
 685
 686                         trips {
 687                                 ubi_3-critical {
 688                                         temperature = <125000>;
 689                                         hysteresis = <1000>;
 690                                         type = "critical";
 691                                 };
 692                         };
 693                 };
 694
 695                 cpuss0-thermal {
 696                         polling-delay-passive = <0>;
 697                         polling-delay = <0>;
 698                         thermal-sensors = <&tsens 8>;
 699
 700                         trips {
 701                                 cpu-critical {
 702                                         temperature = <125000>;
 703                                         hysteresis = <1000>;
 704                                         type = "critical";
 705                                 };
 706                         };
 707                 };
 708
 709                 cpuss1-thermal {
 710                         polling-delay-passive = <0>;
 711                         polling-delay = <0>;
 712                         thermal-sensors = <&tsens 9>;
 713
 714                         trips {
 715                                 cpu-critical {
 716                                         temperature = <125000>;
 717                                         hysteresis = <1000>;
 718                                         type = "critical";
 719                                 };
 720                         };
 721                 };
 722
 723                 cpu0-thermal {
 724                         polling-delay-passive = <0>;
 725                         polling-delay = <0>;
 726                         thermal-sensors = <&tsens 10>;
 727
 728                         trips {
 729                                 cpu-critical {
 730                                         temperature = <120000>;
 731                                         hysteresis = <10000>;
 732                                         type = "critical";
 733                                 };
 734
 735                                 cpu-passive {
 736                                         temperature = <110000>;
 737                                         hysteresis = <1000>;
 738                                         type = "passive";
 739                                 };
 740                         };
 741                 };
 742
 743                 cpu1-thermal {
 744                         polling-delay-passive = <0>;
 745                         polling-delay = <0>;
 746                         thermal-sensors = <&tsens 11>;
 747
 748                         trips {
 749                                 cpu-critical {
 750                                         temperature = <120000>;
 751                                         hysteresis = <10000>;
 752                                         type = "critical";
 753                                 };
 754
 755                                 cpu-passive {
 756                                         temperature = <110000>;
 757                                         hysteresis = <1000>;
 758                                         type = "passive";
 759                                 };
 760                         };
 761                 };
 762
 763                 cpu2-thermal {
 764                         polling-delay-passive = <0>;
 765                         polling-delay = <0>;
 766                         thermal-sensors = <&tsens 12>;
 767
 768                         trips {
 769                                 cpu-critical {
 770                                         temperature = <120000>;
 771                                         hysteresis = <10000>;
 772                                         type = "critical";
 773                                 };
 774
 775                                 cpu-passive {
 776                                         temperature = <110000>;
 777                                         hysteresis = <1000>;
 778                                         type = "passive";
 779                                 };
 780                         };
 781                 };
 782
 783                 cpu3-thermal {
 784                         polling-delay-passive = <0>;
 785                         polling-delay = <0>;
 786                         thermal-sensors = <&tsens 13>;
 787
 788                         trips {
 789                                 cpu-critical {
 790                                         temperature = <120000>;
 791                                         hysteresis = <10000>;
 792                                         type = "critical";
 793                                 };
 794
 795                                 cpu-passive {
 796                                         temperature = <110000>;
 797                                         hysteresis = <1000>;
 798                                         type = "passive";
 799                                 };
 800                         };
 801                 };
 802
 803                 wcss-phyb-thermal {
 804                         polling-delay-passive = <0>;
 805                         polling-delay = <0>;
 806                         thermal-sensors = <&tsens 14>;
 807
 808                         trips {
 809                                 wcss_phyb-critical {
 810                                         temperature = <125000>;
 811                                         hysteresis = <1000>;
 812                                         type = "critical";
 813                                 };
 814                         };
 815                 };
 816
 817                 top-glue-thermal {
 818                         polling-delay-passive = <0>;
 819                         polling-delay = <0>;
 820                         thermal-sensors = <&tsens 15>;
 821
 822                         trips {
 823                                 top_glue-critical {
 824                                         temperature = <125000>;
 825                                         hysteresis = <1000>;
 826                                         type = "critical";
 827                                 };
 828                         };
 829                 };
 830         };
 831
 832         timer {
 833                 compatible = "arm,armv8-timer";
 834                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 835                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 836                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 837                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 838         };
 839 };