arch/arm64/boot/dts/qcom/ipq8074.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
   8
   9 / {
  10         model = "Qualcomm Technologies, Inc. IPQ8074";
  11         compatible = "qcom,ipq8074";
  12
  13         clocks {
  14                 sleep_clk: sleep_clk {
  15                         compatible = "fixed-clock";
  16                         clock-frequency = <32000>;
  17                         #clock-cells = <0>;
  18                 };
  19
  20                 xo: xo {
  21                         compatible = "fixed-clock";
  22                         clock-frequency = <19200000>;
  23                         #clock-cells = <0>;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <0x1>;
  29                 #size-cells = <0x0>;
  30
  31                 CPU0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         next-level-cache = <&L2_0>;
  36                         enable-method = "psci";
  37                 };
  38
  39                 CPU1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x1>;
  44                         next-level-cache = <&L2_0>;
  45                 };
  46
  47                 CPU2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         enable-method = "psci";
  51                         reg = <0x2>;
  52                         next-level-cache = <&L2_0>;
  53                 };
  54
  55                 CPU3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         enable-method = "psci";
  59                         reg = <0x3>;
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 L2_0: l2-cache {
  64                         compatible = "cache";
  65                         cache-level = <0x2>;
  66                 };
  67         };
  68
  69         pmu {
  70                 compatible = "arm,cortex-a53-pmu";
  71                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  72         };
  73
  74         psci {
  75                 compatible = "arm,psci-1.0";
  76                 method = "smc";
  77         };
  78
  79         firmware {
  80                 scm {
  81                         compatible = "qcom,scm-ipq8074", "qcom,scm";
  82                 };
  83         };
  84
  85         soc: soc {
  86                 #address-cells = <0x1>;
  87                 #size-cells = <0x1>;
  88                 ranges = <0 0 0 0xffffffff>;
  89                 compatible = "simple-bus";
  90
  91                 ssphy_1: phy@58000 {
  92                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  93                         reg = <0x00058000 0x1c4>;
  94                         #clock-cells = <1>;
  95                         #address-cells = <1>;
  96                         #size-cells = <1>;
  97                         ranges;
  98
  99                         clocks = <&gcc GCC_USB1_AUX_CLK>,
 100                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 101                                 <&xo>;
 102                         clock-names = "aux", "cfg_ahb", "ref";
 103
 104                         resets =  <&gcc GCC_USB1_PHY_BCR>,
 105                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
 106                         reset-names = "phy","common";
 107                         status = "disabled";
 108
 109                         usb1_ssphy: lane@58200 {
 110                                 reg = <0x00058200 0x130>,       /* Tx */
 111                                       <0x00058400 0x200>,     /* Rx */
 112                                       <0x00058800 0x1f8>,     /* PCS  */
 113                                       <0x00058600 0x044>;     /* PCS misc*/
 114                                 #phy-cells = <0>;
 115                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
 116                                 clock-names = "pipe0";
 117                                 clock-output-names = "gcc_usb1_pipe_clk_src";
 118                         };
 119                 };
 120
 121                 qusb_phy_1: phy@59000 {
 122                         compatible = "qcom,ipq8074-qusb2-phy";
 123                         reg = <0x00059000 0x180>;
 124                         #phy-cells = <0>;
 125
 126                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
 127                                  <&xo>;
 128                         clock-names = "cfg_ahb", "ref";
 129
 130                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
 131                         status = "disabled";
 132                 };
 133
 134                 ssphy_0: phy@78000 {
 135                         compatible = "qcom,ipq8074-qmp-usb3-phy";
 136                         reg = <0x00078000 0x1c4>;
 137                         #clock-cells = <1>;
 138                         #address-cells = <1>;
 139                         #size-cells = <1>;
 140                         ranges;
 141
 142                         clocks = <&gcc GCC_USB0_AUX_CLK>,
 143                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 144                                 <&xo>;
 145                         clock-names = "aux", "cfg_ahb", "ref";
 146
 147                         resets =  <&gcc GCC_USB0_PHY_BCR>,
 148                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
 149                         reset-names = "phy","common";
 150                         status = "disabled";
 151
 152                         usb0_ssphy: lane@78200 {
 153                                 reg = <0x00078200 0x130>,       /* Tx */
 154                                       <0x00078400 0x200>,     /* Rx */
 155                                       <0x00078800 0x1f8>,     /* PCS  */
 156                                       <0x00078600 0x044>;     /* PCS misc*/
 157                                 #phy-cells = <0>;
 158                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
 159                                 clock-names = "pipe0";
 160                                 clock-output-names = "gcc_usb0_pipe_clk_src";
 161                         };
 162                 };
 163
 164                 qusb_phy_0: phy@79000 {
 165                         compatible = "qcom,ipq8074-qusb2-phy";
 166                         reg = <0x00079000 0x180>;
 167                         #phy-cells = <0>;
 168
 169                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
 170                                  <&xo>;
 171                         clock-names = "cfg_ahb", "ref";
 172
 173                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
 174                         status = "disabled";
 175                 };
 176
 177                 pcie_phy0: phy@86000 {
 178                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 179                         reg = <0x00086000 0x1000>;
 180                         #phy-cells = <0>;
 181                         clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 182                         clock-names = "pipe_clk";
 183                         clock-output-names = "pcie20_phy0_pipe_clk";
 184
 185                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
 186                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
 187                         reset-names = "phy",
 188                                       "common";
 189                         status = "disabled";
 190                 };
 191
 192                 pcie_phy1: phy@8e000 {
 193                         compatible = "qcom,ipq8074-qmp-pcie-phy";
 194                         reg = <0x0008e000 0x1000>;
 195                         #phy-cells = <0>;
 196                         clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 197                         clock-names = "pipe_clk";
 198                         clock-output-names = "pcie20_phy1_pipe_clk";
 199
 200                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
 201                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
 202                         reset-names = "phy",
 203                                       "common";
 204                         status = "disabled";
 205                 };
 206
 207                 prng: rng@e3000 {
 208                         compatible = "qcom,prng-ee";
 209                         reg = <0x000e3000 0x1000>;
 210                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 211                         clock-names = "core";
 212                         status = "disabled";
 213                 };
 214
 215                 cryptobam: dma@704000 {
 216                         compatible = "qcom,bam-v1.7.0";
 217                         reg = <0x00704000 0x20000>;
 218                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
 220                         clock-names = "bam_clk";
 221                         #dma-cells = <1>;
 222                         qcom,ee = <1>;
 223                         qcom,controlled-remotely = <1>;
 224                         status = "disabled";
 225                 };
 226
 227                 crypto: crypto@73a000 {
 228                         compatible = "qcom,crypto-v5.1";
 229                         reg = <0x0073a000 0x6000>;
 230                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
 231                                  <&gcc GCC_CRYPTO_AXI_CLK>,
 232                                  <&gcc GCC_CRYPTO_CLK>;
 233                         clock-names = "iface", "bus", "core";
 234                         dmas = <&cryptobam 2>, <&cryptobam 3>;
 235                         dma-names = "rx", "tx";
 236                         status = "disabled";
 237                 };
 238
 239                 tlmm: pinctrl@1000000 {
 240                         compatible = "qcom,ipq8074-pinctrl";
 241                         reg = <0x01000000 0x300000>;
 242                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 243                         gpio-controller;
 244                         gpio-ranges = <&tlmm 0 0 70>;
 245                         #gpio-cells = <0x2>;
 246                         interrupt-controller;
 247                         #interrupt-cells = <0x2>;
 248
 249                         serial_4_pins: serial4-pinmux {
 250                                 pins = "gpio23", "gpio24";
 251                                 function = "blsp4_uart1";
 252                                 drive-strength = <8>;
 253                                 bias-disable;
 254                         };
 255
 256                         i2c_0_pins: i2c-0-pinmux {
 257                                 pins = "gpio42", "gpio43";
 258                                 function = "blsp1_i2c";
 259                                 drive-strength = <8>;
 260                                 bias-disable;
 261                         };
 262
 263                         spi_0_pins: spi-0-pins {
 264                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
 265                                 function = "blsp0_spi";
 266                                 drive-strength = <8>;
 267                                 bias-disable;
 268                         };
 269
 270                         hsuart_pins: hsuart-pins {
 271                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
 272                                 function = "blsp2_uart";
 273                                 drive-strength = <8>;
 274                                 bias-disable;
 275                         };
 276
 277                         qpic_pins: qpic-pins {
 278                                 pins = "gpio1", "gpio3", "gpio4",
 279                                        "gpio5", "gpio6", "gpio7",
 280                                        "gpio8", "gpio10", "gpio11",
 281                                        "gpio12", "gpio13", "gpio14",
 282                                        "gpio15", "gpio16", "gpio17";
 283                                 function = "qpic";
 284                                 drive-strength = <8>;
 285                                 bias-disable;
 286                         };
 287                 };
 288
 289                 gcc: gcc@1800000 {
 290                         compatible = "qcom,gcc-ipq8074";
 291                         reg = <0x01800000 0x80000>;
 292                         #clock-cells = <0x1>;
 293                         #reset-cells = <0x1>;
 294                 };
 295
 296                 sdhc_1: sdhci@7824900 {
 297                         compatible = "qcom,sdhci-msm-v4";
 298                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
 299                         reg-names = "hc_mem", "core_mem";
 300
 301                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 302                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 303                         interrupt-names = "hc_irq", "pwr_irq";
 304
 305                         clocks = <&xo>,
 306                                  <&gcc GCC_SDCC1_AHB_CLK>,
 307                                  <&gcc GCC_SDCC1_APPS_CLK>;
 308                         clock-names = "xo", "iface", "core";
 309                         max-frequency = <384000000>;
 310                         mmc-ddr-1_8v;
 311                         mmc-hs200-1_8v;
 312                         mmc-hs400-1_8v;
 313                         bus-width = <8>;
 314
 315                         status = "disabled";
 316                 };
 317
 318                 blsp_dma: dma-controller@7884000 {
 319                         compatible = "qcom,bam-v1.7.0";
 320                         reg = <0x07884000 0x2b000>;
 321                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 322                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 323                         clock-names = "bam_clk";
 324                         #dma-cells = <1>;
 325                         qcom,ee = <0>;
 326                 };
 327
 328                 blsp1_uart1: serial@78af000 {
 329                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 330                         reg = <0x078af000 0x200>;
 331                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 333                                  <&gcc GCC_BLSP1_AHB_CLK>;
 334                         clock-names = "core", "iface";
 335                         status = "disabled";
 336                 };
 337
 338                 blsp1_uart3: serial@78b1000 {
 339                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 340                         reg = <0x078b1000 0x200>;
 341                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 343                                 <&gcc GCC_BLSP1_AHB_CLK>;
 344                         clock-names = "core", "iface";
 345                         dmas = <&blsp_dma 4>,
 346                                 <&blsp_dma 5>;
 347                         dma-names = "tx", "rx";
 348                         pinctrl-0 = <&hsuart_pins>;
 349                         pinctrl-names = "default";
 350                         status = "disabled";
 351                 };
 352
 353                 blsp1_uart5: serial@78b3000 {
 354                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 355                         reg = <0x078b3000 0x200>;
 356                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 358                                  <&gcc GCC_BLSP1_AHB_CLK>;
 359                         clock-names = "core", "iface";
 360                         pinctrl-0 = <&serial_4_pins>;
 361                         pinctrl-names = "default";
 362                         status = "disabled";
 363                 };
 364
 365                 blsp1_spi1: spi@78b5000 {
 366                         compatible = "qcom,spi-qup-v2.2.1";
 367                         #address-cells = <1>;
 368                         #size-cells = <0>;
 369                         reg = <0x078b5000 0x600>;
 370                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 371                         spi-max-frequency = <50000000>;
 372                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 373                                 <&gcc GCC_BLSP1_AHB_CLK>;
 374                         clock-names = "core", "iface";
 375                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 376                         dma-names = "tx", "rx";
 377                         pinctrl-0 = <&spi_0_pins>;
 378                         pinctrl-names = "default";
 379                         status = "disabled";
 380                 };
 381
 382                 blsp1_i2c2: i2c@78b6000 {
 383                         compatible = "qcom,i2c-qup-v2.2.1";
 384                         #address-cells = <1>;
 385                         #size-cells = <0>;
 386                         reg = <0x078b6000 0x600>;
 387                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 389                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 390                         clock-names = "iface", "core";
 391                         clock-frequency = <400000>;
 392                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 393                         dma-names = "rx", "tx";
 394                         pinctrl-0 = <&i2c_0_pins>;
 395                         pinctrl-names = "default";
 396                         status = "disabled";
 397                 };
 398
 399                 blsp1_i2c3: i2c@78b7000 {
 400                         compatible = "qcom,i2c-qup-v2.2.1";
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         reg = <0x078b7000 0x600>;
 404                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 406                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 407                         clock-names = "iface", "core";
 408                         clock-frequency = <100000>;
 409                         dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 410                         dma-names = "rx", "tx";
 411                         status = "disabled";
 412                 };
 413
 414                 blsp1_i2c6: i2c@78ba000 {
 415                         compatible = "qcom,i2c-qup-v2.2.1";
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         reg = <0x078ba000 0x600>;
 419                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 421                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 422                         clock-names = "iface", "core";
 423                         clock-frequency = <100000>;
 424                         dmas = <&blsp_dma 23>, <&blsp_dma 22>;
 425                         dma-names = "rx", "tx";
 426                         status = "disabled";
 427                 };
 428
 429                 qpic_bam: dma-controller@7984000 {
 430                         compatible = "qcom,bam-v1.7.0";
 431                         reg = <0x07984000 0x1a000>;
 432                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
 434                         clock-names = "bam_clk";
 435                         #dma-cells = <1>;
 436                         qcom,ee = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 qpic_nand: nand@79b0000 {
 441                         compatible = "qcom,ipq8074-nand";
 442                         reg = <0x079b0000 0x10000>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         clocks = <&gcc GCC_QPIC_CLK>,
 446                                  <&gcc GCC_QPIC_AHB_CLK>;
 447                         clock-names = "core", "aon";
 448
 449                         dmas = <&qpic_bam 0>,
 450                                <&qpic_bam 1>,
 451                                <&qpic_bam 2>;
 452                         dma-names = "tx", "rx", "cmd";
 453                         pinctrl-0 = <&qpic_pins>;
 454                         pinctrl-names = "default";
 455                         status = "disabled";
 456                 };
 457
 458                 usb_0: usb@8af8800 {
 459                         compatible = "qcom,dwc3";
 460                         reg = <0x08af8800 0x400>;
 461                         #address-cells = <1>;
 462                         #size-cells = <1>;
 463                         ranges;
 464
 465                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 466                                 <&gcc GCC_USB0_MASTER_CLK>,
 467                                 <&gcc GCC_USB0_SLEEP_CLK>,
 468                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 469                         clock-names = "sys_noc_axi",
 470                                 "master",
 471                                 "sleep",
 472                                 "mock_utmi";
 473
 474                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 475                                           <&gcc GCC_USB0_MASTER_CLK>,
 476                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 477                         assigned-clock-rates = <133330000>,
 478                                                 <133330000>,
 479                                                 <19200000>;
 480
 481                         resets = <&gcc GCC_USB0_BCR>;
 482                         status = "disabled";
 483
 484                         dwc_0: dwc3@8a00000 {
 485                                 compatible = "snps,dwc3";
 486                                 reg = <0x8a00000 0xcd00>;
 487                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 488                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
 489                                 phy-names = "usb2-phy", "usb3-phy";
 490                                 snps,is-utmi-l1-suspend;
 491                                 snps,hird-threshold = /bits/ 8 <0x0>;
 492                                 snps,dis_u2_susphy_quirk;
 493                                 snps,dis_u3_susphy_quirk;
 494                                 dr_mode = "host";
 495                         };
 496                 };
 497
 498                 usb_1: usb@8cf8800 {
 499                         compatible = "qcom,dwc3";
 500                         reg = <0x08cf8800 0x400>;
 501                         #address-cells = <1>;
 502                         #size-cells = <1>;
 503                         ranges;
 504
 505                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 506                                 <&gcc GCC_USB1_MASTER_CLK>,
 507                                 <&gcc GCC_USB1_SLEEP_CLK>,
 508                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 509                         clock-names = "sys_noc_axi",
 510                                 "master",
 511                                 "sleep",
 512                                 "mock_utmi";
 513
 514                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
 515                                           <&gcc GCC_USB1_MASTER_CLK>,
 516                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
 517                         assigned-clock-rates = <133330000>,
 518                                                 <133330000>,
 519                                                 <19200000>;
 520
 521                         resets = <&gcc GCC_USB1_BCR>;
 522                         status = "disabled";
 523
 524                         dwc_1: dwc3@8c00000 {
 525                                 compatible = "snps,dwc3";
 526                                 reg = <0x8c00000 0xcd00>;
 527                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 528                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
 529                                 phy-names = "usb2-phy", "usb3-phy";
 530                                 snps,is-utmi-l1-suspend;
 531                                 snps,hird-threshold = /bits/ 8 <0x0>;
 532                                 snps,dis_u2_susphy_quirk;
 533                                 snps,dis_u3_susphy_quirk;
 534                                 dr_mode = "host";
 535                         };
 536                 };
 537
 538                 intc: interrupt-controller@b000000 {
 539                         compatible = "qcom,msm-qgic2";
 540                         interrupt-controller;
 541                         #interrupt-cells = <0x3>;
 542                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 543                 };
 544
 545                 timer {
 546                         compatible = "arm,armv8-timer";
 547                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 548                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 549                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 550                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 551                 };
 552
 553                 watchdog: watchdog@b017000 {
 554                         compatible = "qcom,kpss-wdt";
 555                         reg = <0xb017000 0x1000>;
 556                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
 557                         clocks = <&sleep_clk>;
 558                         timeout-sec = <30>;
 559                 };
 560
 561                 timer@b120000 {
 562                         #address-cells = <1>;
 563                         #size-cells = <1>;
 564                         ranges;
 565                         compatible = "arm,armv7-timer-mem";
 566                         reg = <0x0b120000 0x1000>;
 567                         clock-frequency = <19200000>;
 568
 569                         frame@b120000 {
 570                                 frame-number = <0>;
 571                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 572                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 573                                 reg = <0x0b121000 0x1000>,
 574                                       <0x0b122000 0x1000>;
 575                         };
 576
 577                         frame@b123000 {
 578                                 frame-number = <1>;
 579                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 580                                 reg = <0x0b123000 0x1000>;
 581                                 status = "disabled";
 582                         };
 583
 584                         frame@b124000 {
 585                                 frame-number = <2>;
 586                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 587                                 reg = <0x0b124000 0x1000>;
 588                                 status = "disabled";
 589                         };
 590
 591                         frame@b125000 {
 592                                 frame-number = <3>;
 593                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 594                                 reg = <0x0b125000 0x1000>;
 595                                 status = "disabled";
 596                         };
 597
 598                         frame@b126000 {
 599                                 frame-number = <4>;
 600                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 601                                 reg = <0x0b126000 0x1000>;
 602                                 status = "disabled";
 603                         };
 604
 605                         frame@b127000 {
 606                                 frame-number = <5>;
 607                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 608                                 reg = <0x0b127000 0x1000>;
 609                                 status = "disabled";
 610                         };
 611
 612                         frame@b128000 {
 613                                 frame-number = <6>;
 614                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 615                                 reg = <0x0b128000 0x1000>;
 616                                 status = "disabled";
 617                         };
 618                 };
 619
 620                 pcie1: pci@10000000 {
 621                         compatible = "qcom,pcie-ipq8074";
 622                         reg =  <0x10000000 0xf1d>,
 623                                <0x10000f20 0xa8>,
 624                                <0x00088000 0x2000>,
 625                                <0x10100000 0x1000>;
 626                         reg-names = "dbi", "elbi", "parf", "config";
 627                         device_type = "pci";
 628                         linux,pci-domain = <1>;
 629                         bus-range = <0x00 0xff>;
 630                         num-lanes = <1>;
 631                         #address-cells = <3>;
 632                         #size-cells = <2>;
 633
 634                         phys = <&pcie_phy1>;
 635                         phy-names = "pciephy";
 636
 637                         ranges = <0x81000000 0 0x10200000 0x10200000
 638                                   0 0x100000   /* downstream I/O */
 639                                   0x82000000 0 0x10300000 0x10300000
 640                                   0 0xd00000>; /* non-prefetchable memory */
 641
 642                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 643                         interrupt-names = "msi";
 644                         #interrupt-cells = <1>;
 645                         interrupt-map-mask = <0 0 0 0x7>;
 646                         interrupt-map = <0 0 0 1 &intc 0 142
 647                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 648                                         <0 0 0 2 &intc 0 143
 649                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 650                                         <0 0 0 3 &intc 0 144
 651                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 652                                         <0 0 0 4 &intc 0 145
 653                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 654
 655                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 656                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
 657                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
 658                                  <&gcc GCC_PCIE1_AHB_CLK>,
 659                                  <&gcc GCC_PCIE1_AUX_CLK>;
 660                         clock-names = "iface",
 661                                       "axi_m",
 662                                       "axi_s",
 663                                       "ahb",
 664                                       "aux";
 665                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 666                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
 667                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 668                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 669                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 670                                  <&gcc GCC_PCIE1_AHB_ARES>,
 671                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 672                         reset-names = "pipe",
 673                                       "sleep",
 674                                       "sticky",
 675                                       "axi_m",
 676                                       "axi_s",
 677                                       "ahb",
 678                                       "axi_m_sticky";
 679                         status = "disabled";
 680                 };
 681
 682                 pcie0: pci@20000000 {
 683                         compatible = "qcom,pcie-ipq8074";
 684                         reg = <0x20000000 0xf1d>,
 685                               <0x20000f20 0xa8>,
 686                               <0x00080000 0x2000>,
 687                               <0x20100000 0x1000>;
 688                         reg-names = "dbi", "elbi", "parf", "config";
 689                         device_type = "pci";
 690                         linux,pci-domain = <0>;
 691                         bus-range = <0x00 0xff>;
 692                         num-lanes = <1>;
 693                         #address-cells = <3>;
 694                         #size-cells = <2>;
 695
 696                         phys = <&pcie_phy0>;
 697                         phy-names = "pciephy";
 698
 699                         ranges = <0x81000000 0 0x20200000 0x20200000
 700                                   0 0x100000   /* downstream I/O */
 701                                   0x82000000 0 0x20300000 0x20300000
 702                                   0 0xd00000>; /* non-prefetchable memory */
 703
 704                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 705                         interrupt-names = "msi";
 706                         #interrupt-cells = <1>;
 707                         interrupt-map-mask = <0 0 0 0x7>;
 708                         interrupt-map = <0 0 0 1 &intc 0 75
 709                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 710                                         <0 0 0 2 &intc 0 78
 711                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 712                                         <0 0 0 3 &intc 0 79
 713                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 714                                         <0 0 0 4 &intc 0 83
 715                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 716
 717                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 718                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
 719                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
 720                                  <&gcc GCC_PCIE0_AHB_CLK>,
 721                                  <&gcc GCC_PCIE0_AUX_CLK>;
 722
 723                         clock-names = "iface",
 724                                       "axi_m",
 725                                       "axi_s",
 726                                       "ahb",
 727                                       "aux";
 728                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 729                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
 730                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 731                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 732                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 733                                  <&gcc GCC_PCIE0_AHB_ARES>,
 734                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
 735                         reset-names = "pipe",
 736                                       "sleep",
 737                                       "sticky",
 738                                       "axi_m",
 739                                       "axi_s",
 740                                       "ahb",
 741                                       "axi_m_sticky";
 742                         status = "disabled";
 743                 };
 744         };
 745 };