arch/arm64/boot/dts/mediatek/mt8195.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2021 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/mt8195-clk.h>
   9 #include <dt-bindings/gce/mt8195-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8195-memory-port.h>
  13 #include <dt-bindings/phy/phy.h>
  14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  15 #include <dt-bindings/power/mt8195-power.h>
  16 #include <dt-bindings/reset/mt8195-resets.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
  19
  20 / {
  21         compatible = "mediatek,mt8195";
  22         interrupt-parent = <&gic>;
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         aliases {
  27                 dp-intf0 = &dp_intf0;
  28                 dp-intf1 = &dp_intf1;
  29                 gce0 = &gce0;
  30                 gce1 = &gce1;
  31                 ethdr0 = &ethdr0;
  32                 mutex0 = &mutex;
  33                 mutex1 = &mutex1;
  34                 merge1 = &merge1;
  35                 merge2 = &merge2;
  36                 merge3 = &merge3;
  37                 merge4 = &merge4;
  38                 merge5 = &merge5;
  39                 vdo1-rdma0 = &vdo1_rdma0;
  40                 vdo1-rdma1 = &vdo1_rdma1;
  41                 vdo1-rdma2 = &vdo1_rdma2;
  42                 vdo1-rdma3 = &vdo1_rdma3;
  43                 vdo1-rdma4 = &vdo1_rdma4;
  44                 vdo1-rdma5 = &vdo1_rdma5;
  45                 vdo1-rdma6 = &vdo1_rdma6;
  46                 vdo1-rdma7 = &vdo1_rdma7;
  47         };
  48
  49         cpus {
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 cpu0: cpu@0 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a55";
  56                         reg = <0x000>;
  57                         enable-method = "psci";
  58                         performance-domains = <&performance 0>;
  59                         clock-frequency = <1701000000>;
  60                         capacity-dmips-mhz = <308>;
  61                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  62                         i-cache-size = <32768>;
  63                         i-cache-line-size = <64>;
  64                         i-cache-sets = <128>;
  65                         d-cache-size = <32768>;
  66                         d-cache-line-size = <64>;
  67                         d-cache-sets = <128>;
  68                         next-level-cache = <&l2_0>;
  69                         #cooling-cells = <2>;
  70                 };
  71
  72                 cpu1: cpu@100 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a55";
  75                         reg = <0x100>;
  76                         enable-method = "psci";
  77                         performance-domains = <&performance 0>;
  78                         clock-frequency = <1701000000>;
  79                         capacity-dmips-mhz = <308>;
  80                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
  81                         i-cache-size = <32768>;
  82                         i-cache-line-size = <64>;
  83                         i-cache-sets = <128>;
  84                         d-cache-size = <32768>;
  85                         d-cache-line-size = <64>;
  86                         d-cache-sets = <128>;
  87                         next-level-cache = <&l2_0>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 cpu2: cpu@200 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a55";
  94                         reg = <0x200>;
  95                         enable-method = "psci";
  96                         performance-domains = <&performance 0>;
  97                         clock-frequency = <1701000000>;
  98                         capacity-dmips-mhz = <308>;
  99                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 100                         i-cache-size = <32768>;
 101                         i-cache-line-size = <64>;
 102                         i-cache-sets = <128>;
 103                         d-cache-size = <32768>;
 104                         d-cache-line-size = <64>;
 105                         d-cache-sets = <128>;
 106                         next-level-cache = <&l2_0>;
 107                         #cooling-cells = <2>;
 108                 };
 109
 110                 cpu3: cpu@300 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a55";
 113                         reg = <0x300>;
 114                         enable-method = "psci";
 115                         performance-domains = <&performance 0>;
 116                         clock-frequency = <1701000000>;
 117                         capacity-dmips-mhz = <308>;
 118                         cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
 119                         i-cache-size = <32768>;
 120                         i-cache-line-size = <64>;
 121                         i-cache-sets = <128>;
 122                         d-cache-size = <32768>;
 123                         d-cache-line-size = <64>;
 124                         d-cache-sets = <128>;
 125                         next-level-cache = <&l2_0>;
 126                         #cooling-cells = <2>;
 127                 };
 128
 129                 cpu4: cpu@400 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a78";
 132                         reg = <0x400>;
 133                         enable-method = "psci";
 134                         performance-domains = <&performance 1>;
 135                         clock-frequency = <2171000000>;
 136                         capacity-dmips-mhz = <1024>;
 137                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 138                         i-cache-size = <65536>;
 139                         i-cache-line-size = <64>;
 140                         i-cache-sets = <256>;
 141                         d-cache-size = <65536>;
 142                         d-cache-line-size = <64>;
 143                         d-cache-sets = <256>;
 144                         next-level-cache = <&l2_1>;
 145                         #cooling-cells = <2>;
 146                 };
 147
 148                 cpu5: cpu@500 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a78";
 151                         reg = <0x500>;
 152                         enable-method = "psci";
 153                         performance-domains = <&performance 1>;
 154                         clock-frequency = <2171000000>;
 155                         capacity-dmips-mhz = <1024>;
 156                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 157                         i-cache-size = <65536>;
 158                         i-cache-line-size = <64>;
 159                         i-cache-sets = <256>;
 160                         d-cache-size = <65536>;
 161                         d-cache-line-size = <64>;
 162                         d-cache-sets = <256>;
 163                         next-level-cache = <&l2_1>;
 164                         #cooling-cells = <2>;
 165                 };
 166
 167                 cpu6: cpu@600 {
 168                         device_type = "cpu";
 169                         compatible = "arm,cortex-a78";
 170                         reg = <0x600>;
 171                         enable-method = "psci";
 172                         performance-domains = <&performance 1>;
 173                         clock-frequency = <2171000000>;
 174                         capacity-dmips-mhz = <1024>;
 175                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 176                         i-cache-size = <65536>;
 177                         i-cache-line-size = <64>;
 178                         i-cache-sets = <256>;
 179                         d-cache-size = <65536>;
 180                         d-cache-line-size = <64>;
 181                         d-cache-sets = <256>;
 182                         next-level-cache = <&l2_1>;
 183                         #cooling-cells = <2>;
 184                 };
 185
 186                 cpu7: cpu@700 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a78";
 189                         reg = <0x700>;
 190                         enable-method = "psci";
 191                         performance-domains = <&performance 1>;
 192                         clock-frequency = <2171000000>;
 193                         capacity-dmips-mhz = <1024>;
 194                         cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
 195                         i-cache-size = <65536>;
 196                         i-cache-line-size = <64>;
 197                         i-cache-sets = <256>;
 198                         d-cache-size = <65536>;
 199                         d-cache-line-size = <64>;
 200                         d-cache-sets = <256>;
 201                         next-level-cache = <&l2_1>;
 202                         #cooling-cells = <2>;
 203                 };
 204
 205                 cpu-map {
 206                         cluster0 {
 207                                 core0 {
 208                                         cpu = <&cpu0>;
 209                                 };
 210
 211                                 core1 {
 212                                         cpu = <&cpu1>;
 213                                 };
 214
 215                                 core2 {
 216                                         cpu = <&cpu2>;
 217                                 };
 218
 219                                 core3 {
 220                                         cpu = <&cpu3>;
 221                                 };
 222
 223                                 core4 {
 224                                         cpu = <&cpu4>;
 225                                 };
 226
 227                                 core5 {
 228                                         cpu = <&cpu5>;
 229                                 };
 230
 231                                 core6 {
 232                                         cpu = <&cpu6>;
 233                                 };
 234
 235                                 core7 {
 236                                         cpu = <&cpu7>;
 237                                 };
 238                         };
 239                 };
 240
 241                 idle-states {
 242                         entry-method = "psci";
 243
 244                         cpu_ret_l: cpu-retention-l {
 245                                 compatible = "arm,idle-state";
 246                                 arm,psci-suspend-param = <0x00010001>;
 247                                 local-timer-stop;
 248                                 entry-latency-us = <50>;
 249                                 exit-latency-us = <95>;
 250                                 min-residency-us = <580>;
 251                         };
 252
 253                         cpu_ret_b: cpu-retention-b {
 254                                 compatible = "arm,idle-state";
 255                                 arm,psci-suspend-param = <0x00010001>;
 256                                 local-timer-stop;
 257                                 entry-latency-us = <45>;
 258                                 exit-latency-us = <140>;
 259                                 min-residency-us = <740>;
 260                         };
 261
 262                         cpu_off_l: cpu-off-l {
 263                                 compatible = "arm,idle-state";
 264                                 arm,psci-suspend-param = <0x01010002>;
 265                                 local-timer-stop;
 266                                 entry-latency-us = <55>;
 267                                 exit-latency-us = <155>;
 268                                 min-residency-us = <840>;
 269                         };
 270
 271                         cpu_off_b: cpu-off-b {
 272                                 compatible = "arm,idle-state";
 273                                 arm,psci-suspend-param = <0x01010002>;
 274                                 local-timer-stop;
 275                                 entry-latency-us = <50>;
 276                                 exit-latency-us = <200>;
 277                                 min-residency-us = <1000>;
 278                         };
 279                 };
 280
 281                 l2_0: l2-cache0 {
 282                         compatible = "cache";
 283                         cache-level = <2>;
 284                         cache-size = <131072>;
 285                         cache-line-size = <64>;
 286                         cache-sets = <512>;
 287                         next-level-cache = <&l3_0>;
 288                         cache-unified;
 289                 };
 290
 291                 l2_1: l2-cache1 {
 292                         compatible = "cache";
 293                         cache-level = <2>;
 294                         cache-size = <262144>;
 295                         cache-line-size = <64>;
 296                         cache-sets = <512>;
 297                         next-level-cache = <&l3_0>;
 298                         cache-unified;
 299                 };
 300
 301                 l3_0: l3-cache {
 302                         compatible = "cache";
 303                         cache-level = <3>;
 304                         cache-size = <2097152>;
 305                         cache-line-size = <64>;
 306                         cache-sets = <2048>;
 307                         cache-unified;
 308                 };
 309         };
 310
 311         dsu-pmu {
 312                 compatible = "arm,dsu-pmu";
 313                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 314                 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
 315                        <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 316                 status = "fail";
 317         };
 318
 319         dmic_codec: dmic-codec {
 320                 compatible = "dmic-codec";
 321                 num-channels = <2>;
 322                 wakeup-delay-ms = <50>;
 323         };
 324
 325         sound: mt8195-sound {
 326                 mediatek,platform = <&afe>;
 327                 status = "disabled";
 328         };
 329
 330         clk13m: fixed-factor-clock-13m {
 331                 compatible = "fixed-factor-clock";
 332                 #clock-cells = <0>;
 333                 clocks = <&clk26m>;
 334                 clock-div = <2>;
 335                 clock-mult = <1>;
 336                 clock-output-names = "clk13m";
 337         };
 338
 339         clk26m: oscillator-26m {
 340                 compatible = "fixed-clock";
 341                 #clock-cells = <0>;
 342                 clock-frequency = <26000000>;
 343                 clock-output-names = "clk26m";
 344         };
 345
 346         clk32k: oscillator-32k {
 347                 compatible = "fixed-clock";
 348                 #clock-cells = <0>;
 349                 clock-frequency = <32768>;
 350                 clock-output-names = "clk32k";
 351         };
 352
 353         performance: performance-controller@11bc10 {
 354                 compatible = "mediatek,cpufreq-hw";
 355                 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
 356                 #performance-domain-cells = <1>;
 357         };
 358
 359         gpu_opp_table: opp-table-gpu {
 360                 compatible = "operating-points-v2";
 361                 opp-shared;
 362
 363                 opp-390000000 {
 364                         opp-hz = /bits/ 64 <390000000>;
 365                         opp-microvolt = <625000>;
 366                 };
 367                 opp-410000000 {
 368                         opp-hz = /bits/ 64 <410000000>;
 369                         opp-microvolt = <631250>;
 370                 };
 371                 opp-431000000 {
 372                         opp-hz = /bits/ 64 <431000000>;
 373                         opp-microvolt = <631250>;
 374                 };
 375                 opp-473000000 {
 376                         opp-hz = /bits/ 64 <473000000>;
 377                         opp-microvolt = <637500>;
 378                 };
 379                 opp-515000000 {
 380                         opp-hz = /bits/ 64 <515000000>;
 381                         opp-microvolt = <637500>;
 382                 };
 383                 opp-556000000 {
 384                         opp-hz = /bits/ 64 <556000000>;
 385                         opp-microvolt = <643750>;
 386                 };
 387                 opp-598000000 {
 388                         opp-hz = /bits/ 64 <598000000>;
 389                         opp-microvolt = <650000>;
 390                 };
 391                 opp-640000000 {
 392                         opp-hz = /bits/ 64 <640000000>;
 393                         opp-microvolt = <650000>;
 394                 };
 395                 opp-670000000 {
 396                         opp-hz = /bits/ 64 <670000000>;
 397                         opp-microvolt = <662500>;
 398                 };
 399                 opp-700000000 {
 400                         opp-hz = /bits/ 64 <700000000>;
 401                         opp-microvolt = <675000>;
 402                 };
 403                 opp-730000000 {
 404                         opp-hz = /bits/ 64 <730000000>;
 405                         opp-microvolt = <687500>;
 406                 };
 407                 opp-760000000 {
 408                         opp-hz = /bits/ 64 <760000000>;
 409                         opp-microvolt = <700000>;
 410                 };
 411                 opp-790000000 {
 412                         opp-hz = /bits/ 64 <790000000>;
 413                         opp-microvolt = <712500>;
 414                 };
 415                 opp-820000000 {
 416                         opp-hz = /bits/ 64 <820000000>;
 417                         opp-microvolt = <725000>;
 418                 };
 419                 opp-850000000 {
 420                         opp-hz = /bits/ 64 <850000000>;
 421                         opp-microvolt = <737500>;
 422                 };
 423                 opp-880000000 {
 424                         opp-hz = /bits/ 64 <880000000>;
 425                         opp-microvolt = <750000>;
 426                 };
 427         };
 428
 429         pmu-a55 {
 430                 compatible = "arm,cortex-a55-pmu";
 431                 interrupt-parent = <&gic>;
 432                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
 433         };
 434
 435         pmu-a78 {
 436                 compatible = "arm,cortex-a78-pmu";
 437                 interrupt-parent = <&gic>;
 438                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
 439         };
 440
 441         psci {
 442                 compatible = "arm,psci-1.0";
 443                 method = "smc";
 444         };
 445
 446         timer: timer {
 447                 compatible = "arm,armv8-timer";
 448                 interrupt-parent = <&gic>;
 449                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
 450                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
 451                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
 452                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 453         };
 454
 455         soc {
 456                 #address-cells = <2>;
 457                 #size-cells = <2>;
 458                 compatible = "simple-bus";
 459                 ranges;
 460                 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 461
 462                 gic: interrupt-controller@c000000 {
 463                         compatible = "arm,gic-v3";
 464                         #interrupt-cells = <4>;
 465                         #redistributor-regions = <1>;
 466                         interrupt-parent = <&gic>;
 467                         interrupt-controller;
 468                         reg = <0 0x0c000000 0 0x40000>,
 469                               <0 0x0c040000 0 0x200000>;
 470                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 471
 472                         ppi-partitions {
 473                                 ppi_cluster0: interrupt-partition-0 {
 474                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 475                                 };
 476
 477                                 ppi_cluster1: interrupt-partition-1 {
 478                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 479                                 };
 480                         };
 481                 };
 482
 483                 topckgen: syscon@10000000 {
 484                         compatible = "mediatek,mt8195-topckgen", "syscon";
 485                         reg = <0 0x10000000 0 0x1000>;
 486                         #clock-cells = <1>;
 487                 };
 488
 489                 infracfg_ao: syscon@10001000 {
 490                         compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 491                         reg = <0 0x10001000 0 0x1000>;
 492                         #clock-cells = <1>;
 493                         #reset-cells = <1>;
 494                 };
 495
 496                 pericfg: syscon@10003000 {
 497                         compatible = "mediatek,mt8195-pericfg", "syscon";
 498                         reg = <0 0x10003000 0 0x1000>;
 499                         #clock-cells = <1>;
 500                 };
 501
 502                 pio: pinctrl@10005000 {
 503                         compatible = "mediatek,mt8195-pinctrl";
 504                         reg = <0 0x10005000 0 0x1000>,
 505                               <0 0x11d10000 0 0x1000>,
 506                               <0 0x11d30000 0 0x1000>,
 507                               <0 0x11d40000 0 0x1000>,
 508                               <0 0x11e20000 0 0x1000>,
 509                               <0 0x11eb0000 0 0x1000>,
 510                               <0 0x11f40000 0 0x1000>,
 511                               <0 0x1000b000 0 0x1000>;
 512                         reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
 513                                     "iocfg_br", "iocfg_lm", "iocfg_rb",
 514                                     "iocfg_tl", "eint";
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517                         gpio-ranges = <&pio 0 0 144>;
 518                         interrupt-controller;
 519                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 520                         #interrupt-cells = <2>;
 521                 };
 522
 523                 scpsys: syscon@10006000 {
 524                         compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
 525                         reg = <0 0x10006000 0 0x1000>;
 526
 527                         /* System Power Manager */
 528                         spm: power-controller {
 529                                 compatible = "mediatek,mt8195-power-controller";
 530                                 #address-cells = <1>;
 531                                 #size-cells = <0>;
 532                                 #power-domain-cells = <1>;
 533
 534                                 /* power domain of the SoC */
 535                                 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
 536                                         reg = <MT8195_POWER_DOMAIN_MFG0>;
 537                                         #address-cells = <1>;
 538                                         #size-cells = <0>;
 539                                         #power-domain-cells = <1>;
 540
 541                                         power-domain@MT8195_POWER_DOMAIN_MFG1 {
 542                                                 reg = <MT8195_POWER_DOMAIN_MFG1>;
 543                                                 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>,
 544                                                          <&topckgen CLK_TOP_MFG_CORE_TMP>;
 545                                                 clock-names = "mfg", "alt";
 546                                                 mediatek,infracfg = <&infracfg_ao>;
 547                                                 #address-cells = <1>;
 548                                                 #size-cells = <0>;
 549                                                 #power-domain-cells = <1>;
 550
 551                                                 power-domain@MT8195_POWER_DOMAIN_MFG2 {
 552                                                         reg = <MT8195_POWER_DOMAIN_MFG2>;
 553                                                         #power-domain-cells = <0>;
 554                                                 };
 555
 556                                                 power-domain@MT8195_POWER_DOMAIN_MFG3 {
 557                                                         reg = <MT8195_POWER_DOMAIN_MFG3>;
 558                                                         #power-domain-cells = <0>;
 559                                                 };
 560
 561                                                 power-domain@MT8195_POWER_DOMAIN_MFG4 {
 562                                                         reg = <MT8195_POWER_DOMAIN_MFG4>;
 563                                                         #power-domain-cells = <0>;
 564                                                 };
 565
 566                                                 power-domain@MT8195_POWER_DOMAIN_MFG5 {
 567                                                         reg = <MT8195_POWER_DOMAIN_MFG5>;
 568                                                         #power-domain-cells = <0>;
 569                                                 };
 570
 571                                                 power-domain@MT8195_POWER_DOMAIN_MFG6 {
 572                                                         reg = <MT8195_POWER_DOMAIN_MFG6>;
 573                                                         #power-domain-cells = <0>;
 574                                                 };
 575                                         };
 576                                 };
 577
 578                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
 579                                         reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
 580                                         clocks = <&topckgen CLK_TOP_VPP>,
 581                                                  <&topckgen CLK_TOP_CAM>,
 582                                                  <&topckgen CLK_TOP_CCU>,
 583                                                  <&topckgen CLK_TOP_IMG>,
 584                                                  <&topckgen CLK_TOP_VENC>,
 585                                                  <&topckgen CLK_TOP_VDEC>,
 586                                                  <&topckgen CLK_TOP_WPE_VPP>,
 587                                                  <&topckgen CLK_TOP_CFG_VPP0>,
 588                                                  <&vppsys0 CLK_VPP0_SMI_COMMON>,
 589                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
 590                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
 591                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
 592                                                  <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
 593                                                  <&vppsys0 CLK_VPP0_GALS_INFRA>,
 594                                                  <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
 595                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
 596                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
 597                                                  <&vppsys0 CLK_VPP0_SMI_REORDER>,
 598                                                  <&vppsys0 CLK_VPP0_SMI_IOMMU>,
 599                                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
 600                                                  <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
 601                                                  <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
 602                                                  <&vppsys0 CLK_VPP0_SMI_RSI>,
 603                                                  <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
 604                                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
 605                                                  <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
 606                                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
 607                                         clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
 608                                                       "vppsys4", "vppsys5", "vppsys6", "vppsys7",
 609                                                       "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
 610                                                       "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
 611                                                       "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
 612                                                       "vppsys0-12", "vppsys0-13", "vppsys0-14",
 613                                                       "vppsys0-15", "vppsys0-16", "vppsys0-17",
 614                                                       "vppsys0-18";
 615                                         mediatek,infracfg = <&infracfg_ao>;
 616                                         #address-cells = <1>;
 617                                         #size-cells = <0>;
 618                                         #power-domain-cells = <1>;
 619
 620                                         power-domain@MT8195_POWER_DOMAIN_VDEC1 {
 621                                                 reg = <MT8195_POWER_DOMAIN_VDEC1>;
 622                                                 clocks = <&vdecsys CLK_VDEC_LARB1>;
 623                                                 clock-names = "vdec1-0";
 624                                                 mediatek,infracfg = <&infracfg_ao>;
 625                                                 #power-domain-cells = <0>;
 626                                         };
 627
 628                                         power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
 629                                                 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
 630                                                 mediatek,infracfg = <&infracfg_ao>;
 631                                                 #power-domain-cells = <0>;
 632                                         };
 633
 634                                         power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
 635                                                 reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
 636                                                 clocks = <&topckgen CLK_TOP_CFG_VDO0>,
 637                                                          <&vdosys0 CLK_VDO0_SMI_GALS>,
 638                                                          <&vdosys0 CLK_VDO0_SMI_COMMON>,
 639                                                          <&vdosys0 CLK_VDO0_SMI_EMI>,
 640                                                          <&vdosys0 CLK_VDO0_SMI_IOMMU>,
 641                                                          <&vdosys0 CLK_VDO0_SMI_LARB>,
 642                                                          <&vdosys0 CLK_VDO0_SMI_RSI>;
 643                                                 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
 644                                                               "vdosys0-2", "vdosys0-3",
 645                                                               "vdosys0-4", "vdosys0-5";
 646                                                 mediatek,infracfg = <&infracfg_ao>;
 647                                                 #address-cells = <1>;
 648                                                 #size-cells = <0>;
 649                                                 #power-domain-cells = <1>;
 650
 651                                                 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
 652                                                         reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
 653                                                         clocks = <&topckgen CLK_TOP_CFG_VPP1>,
 654                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
 655                                                                  <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
 656                                                         clock-names = "vppsys1", "vppsys1-0",
 657                                                                       "vppsys1-1";
 658                                                         mediatek,infracfg = <&infracfg_ao>;
 659                                                         #power-domain-cells = <0>;
 660                                                 };
 661
 662                                                 power-domain@MT8195_POWER_DOMAIN_WPESYS {
 663                                                         reg = <MT8195_POWER_DOMAIN_WPESYS>;
 664                                                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
 665                                                                  <&wpesys CLK_WPE_SMI_LARB8>,
 666                                                                  <&wpesys CLK_WPE_SMI_LARB7_P>,
 667                                                                  <&wpesys CLK_WPE_SMI_LARB8_P>;
 668                                                         clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
 669                                                                       "wepsys-3";
 670                                                         mediatek,infracfg = <&infracfg_ao>;
 671                                                         #power-domain-cells = <0>;
 672                                                 };
 673
 674                                                 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
 675                                                         reg = <MT8195_POWER_DOMAIN_VDEC0>;
 676                                                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
 677                                                         clock-names = "vdec0-0";
 678                                                         mediatek,infracfg = <&infracfg_ao>;
 679                                                         #power-domain-cells = <0>;
 680                                                 };
 681
 682                                                 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
 683                                                         reg = <MT8195_POWER_DOMAIN_VDEC2>;
 684                                                         clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
 685                                                         clock-names = "vdec2-0";
 686                                                         mediatek,infracfg = <&infracfg_ao>;
 687                                                         #power-domain-cells = <0>;
 688                                                 };
 689
 690                                                 power-domain@MT8195_POWER_DOMAIN_VENC {
 691                                                         reg = <MT8195_POWER_DOMAIN_VENC>;
 692                                                         mediatek,infracfg = <&infracfg_ao>;
 693                                                         #power-domain-cells = <0>;
 694                                                 };
 695
 696                                                 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
 697                                                         reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
 698                                                         clocks = <&topckgen CLK_TOP_CFG_VDO1>,
 699                                                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
 700                                                                  <&vdosys1 CLK_VDO1_SMI_LARB3>,
 701                                                                  <&vdosys1 CLK_VDO1_GALS>;
 702                                                         clock-names = "vdosys1", "vdosys1-0",
 703                                                                       "vdosys1-1", "vdosys1-2";
 704                                                         mediatek,infracfg = <&infracfg_ao>;
 705                                                         #address-cells = <1>;
 706                                                         #size-cells = <0>;
 707                                                         #power-domain-cells = <1>;
 708
 709                                                         power-domain@MT8195_POWER_DOMAIN_DP_TX {
 710                                                                 reg = <MT8195_POWER_DOMAIN_DP_TX>;
 711                                                                 mediatek,infracfg = <&infracfg_ao>;
 712                                                                 #power-domain-cells = <0>;
 713                                                         };
 714
 715                                                         power-domain@MT8195_POWER_DOMAIN_EPD_TX {
 716                                                                 reg = <MT8195_POWER_DOMAIN_EPD_TX>;
 717                                                                 mediatek,infracfg = <&infracfg_ao>;
 718                                                                 #power-domain-cells = <0>;
 719                                                         };
 720
 721                                                         power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
 722                                                                 reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
 723                                                                 clocks = <&topckgen CLK_TOP_HDMI_APB>;
 724                                                                 clock-names = "hdmi_tx";
 725                                                                 #power-domain-cells = <0>;
 726                                                         };
 727                                                 };
 728
 729                                                 power-domain@MT8195_POWER_DOMAIN_IMG {
 730                                                         reg = <MT8195_POWER_DOMAIN_IMG>;
 731                                                         clocks = <&imgsys CLK_IMG_LARB9>,
 732                                                                  <&imgsys CLK_IMG_GALS>;
 733                                                         clock-names = "img-0", "img-1";
 734                                                         mediatek,infracfg = <&infracfg_ao>;
 735                                                         #address-cells = <1>;
 736                                                         #size-cells = <0>;
 737                                                         #power-domain-cells = <1>;
 738
 739                                                         power-domain@MT8195_POWER_DOMAIN_DIP {
 740                                                                 reg = <MT8195_POWER_DOMAIN_DIP>;
 741                                                                 #power-domain-cells = <0>;
 742                                                         };
 743
 744                                                         power-domain@MT8195_POWER_DOMAIN_IPE {
 745                                                                 reg = <MT8195_POWER_DOMAIN_IPE>;
 746                                                                 clocks = <&topckgen CLK_TOP_IPE>,
 747                                                                          <&imgsys CLK_IMG_IPE>,
 748                                                                          <&ipesys CLK_IPE_SMI_LARB12>;
 749                                                                 clock-names = "ipe", "ipe-0", "ipe-1";
 750                                                                 mediatek,infracfg = <&infracfg_ao>;
 751                                                                 #power-domain-cells = <0>;
 752                                                         };
 753                                                 };
 754
 755                                                 power-domain@MT8195_POWER_DOMAIN_CAM {
 756                                                         reg = <MT8195_POWER_DOMAIN_CAM>;
 757                                                         clocks = <&camsys CLK_CAM_LARB13>,
 758                                                                  <&camsys CLK_CAM_LARB14>,
 759                                                                  <&camsys CLK_CAM_CAM2MM0_GALS>,
 760                                                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
 761                                                                  <&camsys CLK_CAM_CAM2SYS_GALS>;
 762                                                         clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
 763                                                                       "cam-4";
 764                                                         mediatek,infracfg = <&infracfg_ao>;
 765                                                         #address-cells = <1>;
 766                                                         #size-cells = <0>;
 767                                                         #power-domain-cells = <1>;
 768
 769                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
 770                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
 771                                                                 #power-domain-cells = <0>;
 772                                                         };
 773
 774                                                         power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
 775                                                                 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
 776                                                                 #power-domain-cells = <0>;
 777                                                         };
 778
 779                                                         power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
 780                                                                 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
 781                                                                 #power-domain-cells = <0>;
 782                                                         };
 783                                                 };
 784                                         };
 785                                 };
 786
 787                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
 788                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
 789                                         mediatek,infracfg = <&infracfg_ao>;
 790                                         #power-domain-cells = <0>;
 791                                 };
 792
 793                                 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
 794                                         reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
 795                                         mediatek,infracfg = <&infracfg_ao>;
 796                                         #power-domain-cells = <0>;
 797                                 };
 798
 799                                 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
 800                                         reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
 801                                         #power-domain-cells = <0>;
 802                                 };
 803
 804                                 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
 805                                         reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
 806                                         #power-domain-cells = <0>;
 807                                 };
 808
 809                                 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
 810                                         reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
 811                                         clocks = <&topckgen CLK_TOP_SENINF>,
 812                                                  <&topckgen CLK_TOP_SENINF2>;
 813                                         clock-names = "csi_rx_top", "csi_rx_top1";
 814                                         #power-domain-cells = <0>;
 815                                 };
 816
 817                                 power-domain@MT8195_POWER_DOMAIN_ETHER {
 818                                         reg = <MT8195_POWER_DOMAIN_ETHER>;
 819                                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
 820                                         clock-names = "ether";
 821                                         #power-domain-cells = <0>;
 822                                 };
 823
 824                                 power-domain@MT8195_POWER_DOMAIN_ADSP {
 825                                         reg = <MT8195_POWER_DOMAIN_ADSP>;
 826                                         clocks = <&topckgen CLK_TOP_ADSP>,
 827                                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
 828                                         clock-names = "adsp", "adsp1";
 829                                         #address-cells = <1>;
 830                                         #size-cells = <0>;
 831                                         mediatek,infracfg = <&infracfg_ao>;
 832                                         #power-domain-cells = <1>;
 833
 834                                         power-domain@MT8195_POWER_DOMAIN_AUDIO {
 835                                                 reg = <MT8195_POWER_DOMAIN_AUDIO>;
 836                                                 clocks = <&topckgen CLK_TOP_A1SYS_HP>,
 837                                                          <&topckgen CLK_TOP_AUD_INTBUS>,
 838                                                          <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 839                                                          <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
 840                                                 clock-names = "audio", "audio1", "audio2",
 841                                                               "audio3";
 842                                                 mediatek,infracfg = <&infracfg_ao>;
 843                                                 #power-domain-cells = <0>;
 844                                         };
 845                                 };
 846                         };
 847                 };
 848
 849                 watchdog: watchdog@10007000 {
 850                         compatible = "mediatek,mt8195-wdt";
 851                         mediatek,disable-extrst;
 852                         reg = <0 0x10007000 0 0x100>;
 853                         #reset-cells = <1>;
 854                 };
 855
 856                 apmixedsys: syscon@1000c000 {
 857                         compatible = "mediatek,mt8195-apmixedsys", "syscon";
 858                         reg = <0 0x1000c000 0 0x1000>;
 859                         #clock-cells = <1>;
 860                 };
 861
 862                 systimer: timer@10017000 {
 863                         compatible = "mediatek,mt8195-timer",
 864                                      "mediatek,mt6765-timer";
 865                         reg = <0 0x10017000 0 0x1000>;
 866                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
 867                         clocks = <&clk13m>;
 868                 };
 869
 870                 pwrap: pwrap@10024000 {
 871                         compatible = "mediatek,mt8195-pwrap", "syscon";
 872                         reg = <0 0x10024000 0 0x1000>;
 873                         reg-names = "pwrap";
 874                         interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
 875                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 876                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
 877                         clock-names = "spi", "wrap";
 878                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 879                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 880                 };
 881
 882                 spmi: spmi@10027000 {
 883                         compatible = "mediatek,mt8195-spmi";
 884                         reg = <0 0x10027000 0 0x000e00>,
 885                               <0 0x10029000 0 0x000100>;
 886                         reg-names = "pmif", "spmimst";
 887                         clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
 888                                  <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
 889                                  <&topckgen CLK_TOP_SPMI_M_MST>;
 890                         clock-names = "pmif_sys_ck",
 891                                       "pmif_tmr_ck",
 892                                       "spmimst_clk_mux";
 893                         assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
 894                         assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
 895                 };
 896
 897                 iommu_infra: infra-iommu@10315000 {
 898                         compatible = "mediatek,mt8195-iommu-infra";
 899                         reg = <0 0x10315000 0 0x5000>;
 900                         interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
 901                                      <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
 902                                      <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
 903                                      <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
 904                                      <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
 905                         #iommu-cells = <1>;
 906                 };
 907
 908                 gce0: mailbox@10320000 {
 909                         compatible = "mediatek,mt8195-gce";
 910                         reg = <0 0x10320000 0 0x4000>;
 911                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
 912                         #mbox-cells = <2>;
 913                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
 914                 };
 915
 916                 gce1: mailbox@10330000 {
 917                         compatible = "mediatek,mt8195-gce";
 918                         reg = <0 0x10330000 0 0x4000>;
 919                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
 920                         #mbox-cells = <2>;
 921                         clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
 922                 };
 923
 924                 scp: scp@10500000 {
 925                         compatible = "mediatek,mt8195-scp";
 926                         reg = <0 0x10500000 0 0x100000>,
 927                               <0 0x10720000 0 0xe0000>,
 928                               <0 0x10700000 0 0x8000>;
 929                         reg-names = "sram", "cfg", "l1tcm";
 930                         interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
 931                         status = "disabled";
 932                 };
 933
 934                 scp_adsp: clock-controller@10720000 {
 935                         compatible = "mediatek,mt8195-scp_adsp";
 936                         reg = <0 0x10720000 0 0x1000>;
 937                         #clock-cells = <1>;
 938                 };
 939
 940                 adsp: dsp@10803000 {
 941                         compatible = "mediatek,mt8195-dsp";
 942                         reg = <0 0x10803000 0 0x1000>,
 943                               <0 0x10840000 0 0x40000>;
 944                         reg-names = "cfg", "sram";
 945                         clocks = <&topckgen CLK_TOP_ADSP>,
 946                                  <&clk26m>,
 947                                  <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 948                                  <&topckgen CLK_TOP_MAINPLL_D7_D2>,
 949                                  <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
 950                                  <&topckgen CLK_TOP_AUDIO_H>;
 951                         clock-names = "adsp_sel",
 952                                  "clk26m_ck",
 953                                  "audio_local_bus",
 954                                  "mainpll_d7_d2",
 955                                  "scp_adsp_audiodsp",
 956                                  "audio_h";
 957                         power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
 958                         mbox-names = "rx", "tx";
 959                         mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
 960                         status = "disabled";
 961                 };
 962
 963                 adsp_mailbox0: mailbox@10816000 {
 964                         compatible = "mediatek,mt8195-adsp-mbox";
 965                         #mbox-cells = <0>;
 966                         reg = <0 0x10816000 0 0x1000>;
 967                         interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
 968                 };
 969
 970                 adsp_mailbox1: mailbox@10817000 {
 971                         compatible = "mediatek,mt8195-adsp-mbox";
 972                         #mbox-cells = <0>;
 973                         reg = <0 0x10817000 0 0x1000>;
 974                         interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
 975                 };
 976
 977                 afe: mt8195-afe-pcm@10890000 {
 978                         compatible = "mediatek,mt8195-audio";
 979                         reg = <0 0x10890000 0 0x10000>;
 980                         mediatek,topckgen = <&topckgen>;
 981                         power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
 982                         interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
 983                         resets = <&watchdog 14>;
 984                         reset-names = "audiosys";
 985                         clocks = <&clk26m>,
 986                                 <&apmixedsys CLK_APMIXED_APLL1>,
 987                                 <&apmixedsys CLK_APMIXED_APLL2>,
 988                                 <&topckgen CLK_TOP_APLL12_DIV0>,
 989                                 <&topckgen CLK_TOP_APLL12_DIV1>,
 990                                 <&topckgen CLK_TOP_APLL12_DIV2>,
 991                                 <&topckgen CLK_TOP_APLL12_DIV3>,
 992                                 <&topckgen CLK_TOP_APLL12_DIV9>,
 993                                 <&topckgen CLK_TOP_A1SYS_HP>,
 994                                 <&topckgen CLK_TOP_AUD_INTBUS>,
 995                                 <&topckgen CLK_TOP_AUDIO_H>,
 996                                 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
 997                                 <&topckgen CLK_TOP_DPTX_MCK>,
 998                                 <&topckgen CLK_TOP_I2SO1_MCK>,
 999                                 <&topckgen CLK_TOP_I2SO2_MCK>,
1000                                 <&topckgen CLK_TOP_I2SI1_MCK>,
1001                                 <&topckgen CLK_TOP_I2SI2_MCK>,
1002                                 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
1003                                 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1004                         clock-names = "clk26m",
1005                                 "apll1_ck",
1006                                 "apll2_ck",
1007                                 "apll12_div0",
1008                                 "apll12_div1",
1009                                 "apll12_div2",
1010                                 "apll12_div3",
1011                                 "apll12_div9",
1012                                 "a1sys_hp_sel",
1013                                 "aud_intbus_sel",
1014                                 "audio_h_sel",
1015                                 "audio_local_bus_sel",
1016                                 "dptx_m_sel",
1017                                 "i2so1_m_sel",
1018                                 "i2so2_m_sel",
1019                                 "i2si1_m_sel",
1020                                 "i2si2_m_sel",
1021                                 "infra_ao_audio_26m_b",
1022                                 "scp_adsp_audiodsp";
1023                         status = "disabled";
1024                 };
1025
1026                 uart0: serial@11001100 {
1027                         compatible = "mediatek,mt8195-uart",
1028                                      "mediatek,mt6577-uart";
1029                         reg = <0 0x11001100 0 0x100>;
1030                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
1031                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1032                         clock-names = "baud", "bus";
1033                         status = "disabled";
1034                 };
1035
1036                 uart1: serial@11001200 {
1037                         compatible = "mediatek,mt8195-uart",
1038                                      "mediatek,mt6577-uart";
1039                         reg = <0 0x11001200 0 0x100>;
1040                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
1041                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1042                         clock-names = "baud", "bus";
1043                         status = "disabled";
1044                 };
1045
1046                 uart2: serial@11001300 {
1047                         compatible = "mediatek,mt8195-uart",
1048                                      "mediatek,mt6577-uart";
1049                         reg = <0 0x11001300 0 0x100>;
1050                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1051                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1052                         clock-names = "baud", "bus";
1053                         status = "disabled";
1054                 };
1055
1056                 uart3: serial@11001400 {
1057                         compatible = "mediatek,mt8195-uart",
1058                                      "mediatek,mt6577-uart";
1059                         reg = <0 0x11001400 0 0x100>;
1060                         interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
1061                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
1062                         clock-names = "baud", "bus";
1063                         status = "disabled";
1064                 };
1065
1066                 uart4: serial@11001500 {
1067                         compatible = "mediatek,mt8195-uart",
1068                                      "mediatek,mt6577-uart";
1069                         reg = <0 0x11001500 0 0x100>;
1070                         interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
1071                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
1072                         clock-names = "baud", "bus";
1073                         status = "disabled";
1074                 };
1075
1076                 uart5: serial@11001600 {
1077                         compatible = "mediatek,mt8195-uart",
1078                                      "mediatek,mt6577-uart";
1079                         reg = <0 0x11001600 0 0x100>;
1080                         interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
1081                         clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
1082                         clock-names = "baud", "bus";
1083                         status = "disabled";
1084                 };
1085
1086                 auxadc: auxadc@11002000 {
1087                         compatible = "mediatek,mt8195-auxadc",
1088                                      "mediatek,mt8173-auxadc";
1089                         reg = <0 0x11002000 0 0x1000>;
1090                         clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1091                         clock-names = "main";
1092                         #io-channel-cells = <1>;
1093                         status = "disabled";
1094                 };
1095
1096                 pericfg_ao: syscon@11003000 {
1097                         compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1098                         reg = <0 0x11003000 0 0x1000>;
1099                         #clock-cells = <1>;
1100                 };
1101
1102                 spi0: spi@1100a000 {
1103                         compatible = "mediatek,mt8195-spi",
1104                                      "mediatek,mt6765-spi";
1105                         #address-cells = <1>;
1106                         #size-cells = <0>;
1107                         reg = <0 0x1100a000 0 0x1000>;
1108                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
1109                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1110                                  <&topckgen CLK_TOP_SPI>,
1111                                  <&infracfg_ao CLK_INFRA_AO_SPI0>;
1112                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1113                         status = "disabled";
1114                 };
1115
1116                 lvts_ap: thermal-sensor@1100b000 {
1117                         compatible = "mediatek,mt8195-lvts-ap";
1118                         reg = <0 0x1100b000 0 0x1000>;
1119                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1120                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1121                         resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>;
1122                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1123                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1124                         #thermal-sensor-cells = <1>;
1125                 };
1126
1127                 disp_pwm0: pwm@1100e000 {
1128                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1129                         reg = <0 0x1100e000 0 0x1000>;
1130                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
1131                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1132                         #pwm-cells = <2>;
1133                         clocks = <&topckgen CLK_TOP_DISP_PWM0>,
1134                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1135                         clock-names = "main", "mm";
1136                         status = "disabled";
1137                 };
1138
1139                 disp_pwm1: pwm@1100f000 {
1140                         compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1141                         reg = <0 0x1100f000 0 0x1000>;
1142                         interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
1143                         #pwm-cells = <2>;
1144                         clocks = <&topckgen CLK_TOP_DISP_PWM1>,
1145                                  <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
1146                         clock-names = "main", "mm";
1147                         status = "disabled";
1148                 };
1149
1150                 spi1: spi@11010000 {
1151                         compatible = "mediatek,mt8195-spi",
1152                                      "mediatek,mt6765-spi";
1153                         #address-cells = <1>;
1154                         #size-cells = <0>;
1155                         reg = <0 0x11010000 0 0x1000>;
1156                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
1157                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1158                                  <&topckgen CLK_TOP_SPI>,
1159                                  <&infracfg_ao CLK_INFRA_AO_SPI1>;
1160                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1161                         status = "disabled";
1162                 };
1163
1164                 spi2: spi@11012000 {
1165                         compatible = "mediatek,mt8195-spi",
1166                                      "mediatek,mt6765-spi";
1167                         #address-cells = <1>;
1168                         #size-cells = <0>;
1169                         reg = <0 0x11012000 0 0x1000>;
1170                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
1171                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1172                                  <&topckgen CLK_TOP_SPI>,
1173                                  <&infracfg_ao CLK_INFRA_AO_SPI2>;
1174                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1175                         status = "disabled";
1176                 };
1177
1178                 spi3: spi@11013000 {
1179                         compatible = "mediatek,mt8195-spi",
1180                                      "mediatek,mt6765-spi";
1181                         #address-cells = <1>;
1182                         #size-cells = <0>;
1183                         reg = <0 0x11013000 0 0x1000>;
1184                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1185                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1186                                  <&topckgen CLK_TOP_SPI>,
1187                                  <&infracfg_ao CLK_INFRA_AO_SPI3>;
1188                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1189                         status = "disabled";
1190                 };
1191
1192                 spi4: spi@11018000 {
1193                         compatible = "mediatek,mt8195-spi",
1194                                      "mediatek,mt6765-spi";
1195                         #address-cells = <1>;
1196                         #size-cells = <0>;
1197                         reg = <0 0x11018000 0 0x1000>;
1198                         interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
1199                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1200                                  <&topckgen CLK_TOP_SPI>,
1201                                  <&infracfg_ao CLK_INFRA_AO_SPI4>;
1202                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1203                         status = "disabled";
1204                 };
1205
1206                 spi5: spi@11019000 {
1207                         compatible = "mediatek,mt8195-spi",
1208                                      "mediatek,mt6765-spi";
1209                         #address-cells = <1>;
1210                         #size-cells = <0>;
1211                         reg = <0 0x11019000 0 0x1000>;
1212                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
1213                         clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
1214                                  <&topckgen CLK_TOP_SPI>,
1215                                  <&infracfg_ao CLK_INFRA_AO_SPI5>;
1216                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1217                         status = "disabled";
1218                 };
1219
1220                 spis0: spi@1101d000 {
1221                         compatible = "mediatek,mt8195-spi-slave";
1222                         reg = <0 0x1101d000 0 0x1000>;
1223                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
1224                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
1225                         clock-names = "spi";
1226                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1227                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1228                         status = "disabled";
1229                 };
1230
1231                 spis1: spi@1101e000 {
1232                         compatible = "mediatek,mt8195-spi-slave";
1233                         reg = <0 0x1101e000 0 0x1000>;
1234                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
1235                         clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
1236                         clock-names = "spi";
1237                         assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1238                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1239                         status = "disabled";
1240                 };
1241
1242                 eth: ethernet@11021000 {
1243                         compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1244                         reg = <0 0x11021000 0 0x4000>;
1245                         interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
1246                         interrupt-names = "macirq";
1247                         clock-names = "axi",
1248                                       "apb",
1249                                       "mac_main",
1250                                       "ptp_ref",
1251                                       "rmii_internal",
1252                                       "mac_cg";
1253                         clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
1254                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
1255                                  <&topckgen CLK_TOP_SNPS_ETH_250M>,
1256                                  <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1257                                  <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
1258                                  <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
1259                         assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1260                                           <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
1261                                           <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
1262                         assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1263                                                  <&topckgen CLK_TOP_ETHPLL_D8>,
1264                                                  <&topckgen CLK_TOP_ETHPLL_D10>;
1265                         power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1266                         mediatek,pericfg = <&infracfg_ao>;
1267                         snps,axi-config = <&stmmac_axi_setup>;
1268                         snps,mtl-rx-config = <&mtl_rx_setup>;
1269                         snps,mtl-tx-config = <&mtl_tx_setup>;
1270                         snps,txpbl = <16>;
1271                         snps,rxpbl = <16>;
1272                         snps,clk-csr = <0>;
1273                         status = "disabled";
1274
1275                         mdio {
1276                                 compatible = "snps,dwmac-mdio";
1277                                 #address-cells = <1>;
1278                                 #size-cells = <0>;
1279                         };
1280
1281                         stmmac_axi_setup: stmmac-axi-config {
1282                                 snps,wr_osr_lmt = <0x7>;
1283                                 snps,rd_osr_lmt = <0x7>;
1284                                 snps,blen = <0 0 0 0 16 8 4>;
1285                         };
1286
1287                         mtl_rx_setup: rx-queues-config {
1288                                 snps,rx-queues-to-use = <4>;
1289                                 snps,rx-sched-sp;
1290                                 queue0 {
1291                                         snps,dcb-algorithm;
1292                                         snps,map-to-dma-channel = <0x0>;
1293                                 };
1294                                 queue1 {
1295                                         snps,dcb-algorithm;
1296                                         snps,map-to-dma-channel = <0x0>;
1297                                 };
1298                                 queue2 {
1299                                         snps,dcb-algorithm;
1300                                         snps,map-to-dma-channel = <0x0>;
1301                                 };
1302                                 queue3 {
1303                                         snps,dcb-algorithm;
1304                                         snps,map-to-dma-channel = <0x0>;
1305                                 };
1306                         };
1307
1308                         mtl_tx_setup: tx-queues-config {
1309                                 snps,tx-queues-to-use = <4>;
1310                                 snps,tx-sched-wrr;
1311                                 queue0 {
1312                                         snps,weight = <0x10>;
1313                                         snps,dcb-algorithm;
1314                                         snps,priority = <0x0>;
1315                                 };
1316                                 queue1 {
1317                                         snps,weight = <0x11>;
1318                                         snps,dcb-algorithm;
1319                                         snps,priority = <0x1>;
1320                                 };
1321                                 queue2 {
1322                                         snps,weight = <0x12>;
1323                                         snps,dcb-algorithm;
1324                                         snps,priority = <0x2>;
1325                                 };
1326                                 queue3 {
1327                                         snps,weight = <0x13>;
1328                                         snps,dcb-algorithm;
1329                                         snps,priority = <0x3>;
1330                                 };
1331                         };
1332                 };
1333
1334                 xhci0: usb@11200000 {
1335                         compatible = "mediatek,mt8195-xhci",
1336                                      "mediatek,mtk-xhci";
1337                         reg = <0 0x11200000 0 0x1000>,
1338                               <0 0x11203e00 0 0x0100>;
1339                         reg-names = "mac", "ippc";
1340                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
1341                         phys = <&u2port0 PHY_TYPE_USB2>,
1342                                <&u3port0 PHY_TYPE_USB3>;
1343                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1344                                           <&topckgen CLK_TOP_SSUSB_XHCI>;
1345                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1346                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1347                         clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
1348                                  <&topckgen CLK_TOP_SSUSB_REF>,
1349                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1350                                  <&clk26m>,
1351                                  <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
1352                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1353                                       "xhci_ck";
1354                         mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1355                         wakeup-source;
1356                         status = "disabled";
1357                 };
1358
1359                 mmc0: mmc@11230000 {
1360                         compatible = "mediatek,mt8195-mmc",
1361                                      "mediatek,mt8183-mmc";
1362                         reg = <0 0x11230000 0 0x10000>,
1363                               <0 0x11f50000 0 0x1000>;
1364                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
1365                         clocks = <&topckgen CLK_TOP_MSDC50_0>,
1366                                  <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1367                                  <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
1368                         clock-names = "source", "hclk", "source_cg";
1369                         status = "disabled";
1370                 };
1371
1372                 mmc1: mmc@11240000 {
1373                         compatible = "mediatek,mt8195-mmc",
1374                                      "mediatek,mt8183-mmc";
1375                         reg = <0 0x11240000 0 0x1000>,
1376                               <0 0x11c70000 0 0x1000>;
1377                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
1378                         clocks = <&topckgen CLK_TOP_MSDC30_1>,
1379                                  <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1380                                  <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1381                         clock-names = "source", "hclk", "source_cg";
1382                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1383                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1384                         status = "disabled";
1385                 };
1386
1387                 mmc2: mmc@11250000 {
1388                         compatible = "mediatek,mt8195-mmc",
1389                                      "mediatek,mt8183-mmc";
1390                         reg = <0 0x11250000 0 0x1000>,
1391                               <0 0x11e60000 0 0x1000>;
1392                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
1393                         clocks = <&topckgen CLK_TOP_MSDC30_2>,
1394                                  <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
1395                                  <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
1396                         clock-names = "source", "hclk", "source_cg";
1397                         assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1398                         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1399                         status = "disabled";
1400                 };
1401
1402                 lvts_mcu: thermal-sensor@11278000 {
1403                         compatible = "mediatek,mt8195-lvts-mcu";
1404                         reg = <0 0x11278000 0 0x1000>;
1405                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1406                         clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
1407                         resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
1408                         nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1409                         nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1410                         #thermal-sensor-cells = <1>;
1411                 };
1412
1413                 xhci1: usb@11290000 {
1414                         compatible = "mediatek,mt8195-xhci",
1415                                      "mediatek,mtk-xhci";
1416                         reg = <0 0x11290000 0 0x1000>,
1417                               <0 0x11293e00 0 0x0100>;
1418                         reg-names = "mac", "ippc";
1419                         interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
1420                         phys = <&u2port1 PHY_TYPE_USB2>;
1421                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1422                                           <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
1423                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1424                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1425                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
1426                                  <&topckgen CLK_TOP_SSUSB_P1_REF>,
1427                                  <&apmixedsys CLK_APMIXED_USB1PLL>,
1428                                  <&clk26m>,
1429                                  <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
1430                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1431                                       "xhci_ck";
1432                         mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1433                         wakeup-source;
1434                         status = "disabled";
1435                 };
1436
1437                 xhci2: usb@112a0000 {
1438                         compatible = "mediatek,mt8195-xhci",
1439                                      "mediatek,mtk-xhci";
1440                         reg = <0 0x112a0000 0 0x1000>,
1441                               <0 0x112a3e00 0 0x0100>;
1442                         reg-names = "mac", "ippc";
1443                         interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
1444                         phys = <&u2port2 PHY_TYPE_USB2>;
1445                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1446                                           <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
1447                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1448                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1449                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
1450                                  <&topckgen CLK_TOP_SSUSB_P2_REF>,
1451                                  <&clk26m>,
1452                                  <&clk26m>,
1453                                  <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
1454                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1455                                       "xhci_ck";
1456                         mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1457                         wakeup-source;
1458                         status = "disabled";
1459                 };
1460
1461                 xhci3: usb@112b0000 {
1462                         compatible = "mediatek,mt8195-xhci",
1463                                      "mediatek,mtk-xhci";
1464                         reg = <0 0x112b0000 0 0x1000>,
1465                               <0 0x112b3e00 0 0x0100>;
1466                         reg-names = "mac", "ippc";
1467                         interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
1468                         phys = <&u2port3 PHY_TYPE_USB2>;
1469                         assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1470                                           <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
1471                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1472                                                  <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1473                         clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
1474                                  <&topckgen CLK_TOP_SSUSB_P3_REF>,
1475                                  <&clk26m>,
1476                                  <&clk26m>,
1477                                  <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
1478                         clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1479                                       "xhci_ck";
1480                         mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1481                         wakeup-source;
1482                         status = "disabled";
1483                 };
1484
1485                 pcie0: pcie@112f0000 {
1486                         compatible = "mediatek,mt8195-pcie",
1487                                      "mediatek,mt8192-pcie";
1488                         device_type = "pci";
1489                         #address-cells = <3>;
1490                         #size-cells = <2>;
1491                         reg = <0 0x112f0000 0 0x4000>;
1492                         reg-names = "pcie-mac";
1493                         interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
1494                         bus-range = <0x00 0xff>;
1495                         ranges = <0x81000000 0 0x20000000
1496                                   0x0 0x20000000 0 0x200000>,
1497                                  <0x82000000 0 0x20200000
1498                                   0x0 0x20200000 0 0x3e00000>;
1499
1500                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1501                         iommu-map-mask = <0x0>;
1502
1503                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
1504                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
1505                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
1506                                  <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
1507                                  <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
1508                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1509                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1510                                       "tl_32k", "peri_26m", "peri_mem";
1511                         assigned-clocks = <&topckgen CLK_TOP_TL>;
1512                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1513
1514                         phys = <&pciephy>;
1515                         phy-names = "pcie-phy";
1516
1517                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1518
1519                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>;
1520                         reset-names = "mac";
1521
1522                         #interrupt-cells = <1>;
1523                         interrupt-map-mask = <0 0 0 7>;
1524                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1525                                         <0 0 0 2 &pcie_intc0 1>,
1526                                         <0 0 0 3 &pcie_intc0 2>,
1527                                         <0 0 0 4 &pcie_intc0 3>;
1528                         status = "disabled";
1529
1530                         pcie_intc0: interrupt-controller {
1531                                 interrupt-controller;
1532                                 #address-cells = <0>;
1533                                 #interrupt-cells = <1>;
1534                         };
1535                 };
1536
1537                 pcie1: pcie@112f8000 {
1538                         compatible = "mediatek,mt8195-pcie",
1539                                      "mediatek,mt8192-pcie";
1540                         device_type = "pci";
1541                         #address-cells = <3>;
1542                         #size-cells = <2>;
1543                         reg = <0 0x112f8000 0 0x4000>;
1544                         reg-names = "pcie-mac";
1545                         interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
1546                         bus-range = <0x00 0xff>;
1547                         ranges = <0x81000000 0 0x24000000
1548                                   0x0 0x24000000 0 0x200000>,
1549                                  <0x82000000 0 0x24200000
1550                                   0x0 0x24200000 0 0x3e00000>;
1551
1552                         iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1553                         iommu-map-mask = <0x0>;
1554
1555                         clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
1556                                  <&clk26m>,
1557                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
1558                                  <&clk26m>,
1559                                  <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
1560                                  /* Designer has connect pcie1 with peri_mem_p0 clock */
1561                                  <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
1562                         clock-names = "pl_250m", "tl_26m", "tl_96m",
1563                                       "tl_32k", "peri_26m", "peri_mem";
1564                         assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1565                         assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1566
1567                         phys = <&u3port1 PHY_TYPE_PCIE>;
1568                         phy-names = "pcie-phy";
1569                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1570
1571                         resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
1572                         reset-names = "mac";
1573
1574                         #interrupt-cells = <1>;
1575                         interrupt-map-mask = <0 0 0 7>;
1576                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1577                                         <0 0 0 2 &pcie_intc1 1>,
1578                                         <0 0 0 3 &pcie_intc1 2>,
1579                                         <0 0 0 4 &pcie_intc1 3>;
1580                         status = "disabled";
1581
1582                         pcie_intc1: interrupt-controller {
1583                                 interrupt-controller;
1584                                 #address-cells = <0>;
1585                                 #interrupt-cells = <1>;
1586                         };
1587                 };
1588
1589                 nor_flash: spi@1132c000 {
1590                         compatible = "mediatek,mt8195-nor",
1591                                      "mediatek,mt8173-nor";
1592                         reg = <0 0x1132c000 0 0x1000>;
1593                         interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
1594                         clocks = <&topckgen CLK_TOP_SPINOR>,
1595                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
1596                                  <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
1597                         clock-names = "spi", "sf", "axi";
1598                         #address-cells = <1>;
1599                         #size-cells = <0>;
1600                         status = "disabled";
1601                 };
1602
1603                 efuse: efuse@11c10000 {
1604                         compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1605                         reg = <0 0x11c10000 0 0x1000>;
1606                         #address-cells = <1>;
1607                         #size-cells = <1>;
1608                         u3_tx_imp_p0: usb3-tx-imp@184,1 {
1609                                 reg = <0x184 0x1>;
1610                                 bits = <0 5>;
1611                         };
1612                         u3_rx_imp_p0: usb3-rx-imp@184,2 {
1613                                 reg = <0x184 0x2>;
1614                                 bits = <5 5>;
1615                         };
1616                         u3_intr_p0: usb3-intr@185 {
1617                                 reg = <0x185 0x1>;
1618                                 bits = <2 6>;
1619                         };
1620                         comb_tx_imp_p1: usb3-tx-imp@186,1 {
1621                                 reg = <0x186 0x1>;
1622                                 bits = <0 5>;
1623                         };
1624                         comb_rx_imp_p1: usb3-rx-imp@186,2 {
1625                                 reg = <0x186 0x2>;
1626                                 bits = <5 5>;
1627                         };
1628                         comb_intr_p1: usb3-intr@187 {
1629                                 reg = <0x187 0x1>;
1630                                 bits = <2 6>;
1631                         };
1632                         u2_intr_p0: usb2-intr-p0@188,1 {
1633                                 reg = <0x188 0x1>;
1634                                 bits = <0 5>;
1635                         };
1636                         u2_intr_p1: usb2-intr-p1@188,2 {
1637                                 reg = <0x188 0x2>;
1638                                 bits = <5 5>;
1639                         };
1640                         u2_intr_p2: usb2-intr-p2@189,1 {
1641                                 reg = <0x189 0x1>;
1642                                 bits = <2 5>;
1643                         };
1644                         u2_intr_p3: usb2-intr-p3@189,2 {
1645                                 reg = <0x189 0x2>;
1646                                 bits = <7 5>;
1647                         };
1648                         pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1649                                 reg = <0x190 0x1>;
1650                                 bits = <0 4>;
1651                         };
1652                         pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1653                                 reg = <0x190 0x1>;
1654                                 bits = <4 4>;
1655                         };
1656                         pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1657                                 reg = <0x191 0x1>;
1658                                 bits = <0 4>;
1659                         };
1660                         pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1661                                 reg = <0x191 0x1>;
1662                                 bits = <4 4>;
1663                         };
1664                         pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1665                                 reg = <0x192 0x1>;
1666                                 bits = <0 4>;
1667                         };
1668                         pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1669                                 reg = <0x192 0x1>;
1670                                 bits = <4 4>;
1671                         };
1672                         pciephy_glb_intr: pciephy-glb-intr@193 {
1673                                 reg = <0x193 0x1>;
1674                                 bits = <0 4>;
1675                         };
1676                         dp_calibration: dp-data@1ac {
1677                                 reg = <0x1ac 0x10>;
1678                         };
1679                         lvts_efuse_data1: lvts1-calib@1bc {
1680                                 reg = <0x1bc 0x14>;
1681                         };
1682                         lvts_efuse_data2: lvts2-calib@1d0 {
1683                                 reg = <0x1d0 0x38>;
1684                         };
1685                 };
1686
1687                 u3phy2: t-phy@11c40000 {
1688                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1689                         #address-cells = <1>;
1690                         #size-cells = <1>;
1691                         ranges = <0 0 0x11c40000 0x700>;
1692                         status = "disabled";
1693
1694                         u2port2: usb-phy@0 {
1695                                 reg = <0x0 0x700>;
1696                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
1697                                 clock-names = "ref";
1698                                 #phy-cells = <1>;
1699                         };
1700                 };
1701
1702                 u3phy3: t-phy@11c50000 {
1703                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1704                         #address-cells = <1>;
1705                         #size-cells = <1>;
1706                         ranges = <0 0 0x11c50000 0x700>;
1707                         status = "disabled";
1708
1709                         u2port3: usb-phy@0 {
1710                                 reg = <0x0 0x700>;
1711                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
1712                                 clock-names = "ref";
1713                                 #phy-cells = <1>;
1714                         };
1715                 };
1716
1717                 i2c5: i2c@11d00000 {
1718                         compatible = "mediatek,mt8195-i2c",
1719                                      "mediatek,mt8192-i2c";
1720                         reg = <0 0x11d00000 0 0x1000>,
1721                               <0 0x10220580 0 0x80>;
1722                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
1723                         clock-div = <1>;
1724                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
1725                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1726                         clock-names = "main", "dma";
1727                         #address-cells = <1>;
1728                         #size-cells = <0>;
1729                         status = "disabled";
1730                 };
1731
1732                 i2c6: i2c@11d01000 {
1733                         compatible = "mediatek,mt8195-i2c",
1734                                      "mediatek,mt8192-i2c";
1735                         reg = <0 0x11d01000 0 0x1000>,
1736                               <0 0x10220600 0 0x80>;
1737                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
1738                         clock-div = <1>;
1739                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
1740                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1741                         clock-names = "main", "dma";
1742                         #address-cells = <1>;
1743                         #size-cells = <0>;
1744                         status = "disabled";
1745                 };
1746
1747                 i2c7: i2c@11d02000 {
1748                         compatible = "mediatek,mt8195-i2c",
1749                                      "mediatek,mt8192-i2c";
1750                         reg = <0 0x11d02000 0 0x1000>,
1751                               <0 0x10220680 0 0x80>;
1752                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
1753                         clock-div = <1>;
1754                         clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
1755                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1756                         clock-names = "main", "dma";
1757                         #address-cells = <1>;
1758                         #size-cells = <0>;
1759                         status = "disabled";
1760                 };
1761
1762                 imp_iic_wrap_s: clock-controller@11d03000 {
1763                         compatible = "mediatek,mt8195-imp_iic_wrap_s";
1764                         reg = <0 0x11d03000 0 0x1000>;
1765                         #clock-cells = <1>;
1766                 };
1767
1768                 i2c0: i2c@11e00000 {
1769                         compatible = "mediatek,mt8195-i2c",
1770                                      "mediatek,mt8192-i2c";
1771                         reg = <0 0x11e00000 0 0x1000>,
1772                               <0 0x10220080 0 0x80>;
1773                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
1774                         clock-div = <1>;
1775                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
1776                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1777                         clock-names = "main", "dma";
1778                         #address-cells = <1>;
1779                         #size-cells = <0>;
1780                         status = "disabled";
1781                 };
1782
1783                 i2c1: i2c@11e01000 {
1784                         compatible = "mediatek,mt8195-i2c",
1785                                      "mediatek,mt8192-i2c";
1786                         reg = <0 0x11e01000 0 0x1000>,
1787                               <0 0x10220200 0 0x80>;
1788                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
1789                         clock-div = <1>;
1790                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
1791                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1792                         clock-names = "main", "dma";
1793                         #address-cells = <1>;
1794                         #size-cells = <0>;
1795                         status = "disabled";
1796                 };
1797
1798                 i2c2: i2c@11e02000 {
1799                         compatible = "mediatek,mt8195-i2c",
1800                                      "mediatek,mt8192-i2c";
1801                         reg = <0 0x11e02000 0 0x1000>,
1802                               <0 0x10220380 0 0x80>;
1803                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
1804                         clock-div = <1>;
1805                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
1806                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1807                         clock-names = "main", "dma";
1808                         #address-cells = <1>;
1809                         #size-cells = <0>;
1810                         status = "disabled";
1811                 };
1812
1813                 i2c3: i2c@11e03000 {
1814                         compatible = "mediatek,mt8195-i2c",
1815                                      "mediatek,mt8192-i2c";
1816                         reg = <0 0x11e03000 0 0x1000>,
1817                               <0 0x10220480 0 0x80>;
1818                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
1819                         clock-div = <1>;
1820                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
1821                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1822                         clock-names = "main", "dma";
1823                         #address-cells = <1>;
1824                         #size-cells = <0>;
1825                         status = "disabled";
1826                 };
1827
1828                 i2c4: i2c@11e04000 {
1829                         compatible = "mediatek,mt8195-i2c",
1830                                      "mediatek,mt8192-i2c";
1831                         reg = <0 0x11e04000 0 0x1000>,
1832                               <0 0x10220500 0 0x80>;
1833                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
1834                         clock-div = <1>;
1835                         clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
1836                                  <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
1837                         clock-names = "main", "dma";
1838                         #address-cells = <1>;
1839                         #size-cells = <0>;
1840                         status = "disabled";
1841                 };
1842
1843                 imp_iic_wrap_w: clock-controller@11e05000 {
1844                         compatible = "mediatek,mt8195-imp_iic_wrap_w";
1845                         reg = <0 0x11e05000 0 0x1000>;
1846                         #clock-cells = <1>;
1847                 };
1848
1849                 u3phy1: t-phy@11e30000 {
1850                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1851                         #address-cells = <1>;
1852                         #size-cells = <1>;
1853                         ranges = <0 0 0x11e30000 0xe00>;
1854                         power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1855                         status = "disabled";
1856
1857                         u2port1: usb-phy@0 {
1858                                 reg = <0x0 0x700>;
1859                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
1860                                          <&clk26m>;
1861                                 clock-names = "ref", "da_ref";
1862                                 #phy-cells = <1>;
1863                         };
1864
1865                         u3port1: usb-phy@700 {
1866                                 reg = <0x700 0x700>;
1867                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1868                                          <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
1869                                 clock-names = "ref", "da_ref";
1870                                 nvmem-cells = <&comb_intr_p1>,
1871                                               <&comb_rx_imp_p1>,
1872                                               <&comb_tx_imp_p1>;
1873                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1874                                 #phy-cells = <1>;
1875                         };
1876                 };
1877
1878                 u3phy0: t-phy@11e40000 {
1879                         compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1880                         #address-cells = <1>;
1881                         #size-cells = <1>;
1882                         ranges = <0 0 0x11e40000 0xe00>;
1883                         status = "disabled";
1884
1885                         u2port0: usb-phy@0 {
1886                                 reg = <0x0 0x700>;
1887                                 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
1888                                          <&clk26m>;
1889                                 clock-names = "ref", "da_ref";
1890                                 #phy-cells = <1>;
1891                         };
1892
1893                         u3port0: usb-phy@700 {
1894                                 reg = <0x700 0x700>;
1895                                 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
1896                                          <&topckgen CLK_TOP_SSUSB_PHY_REF>;
1897                                 clock-names = "ref", "da_ref";
1898                                 nvmem-cells = <&u3_intr_p0>,
1899                                               <&u3_rx_imp_p0>,
1900                                               <&u3_tx_imp_p0>;
1901                                 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1902                                 #phy-cells = <1>;
1903                         };
1904                 };
1905
1906                 pciephy: phy@11e80000 {
1907                         compatible = "mediatek,mt8195-pcie-phy";
1908                         reg = <0 0x11e80000 0 0x10000>;
1909                         reg-names = "sif";
1910                         nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1911                                       <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>,
1912                                       <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>,
1913                                       <&pciephy_rx_ln1>;
1914                         nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1915                                            "tx_ln0_nmos", "rx_ln0",
1916                                            "tx_ln1_pmos", "tx_ln1_nmos",
1917                                            "rx_ln1";
1918                         power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1919                         #phy-cells = <0>;
1920                         status = "disabled";
1921                 };
1922
1923                 ufsphy: ufs-phy@11fa0000 {
1924                         compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1925                         reg = <0 0x11fa0000 0 0xc000>;
1926                         clocks = <&clk26m>, <&clk26m>;
1927                         clock-names = "unipro", "mp";
1928                         #phy-cells = <0>;
1929                         status = "disabled";
1930                 };
1931
1932                 gpu: gpu@13000000 {
1933                         compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1934                                      "arm,mali-valhall-jm";
1935                         reg = <0 0x13000000 0 0x4000>;
1936
1937                         clocks = <&mfgcfg CLK_MFG_BG3D>;
1938                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>,
1939                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>,
1940                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>;
1941                         interrupt-names = "job", "mmu", "gpu";
1942                         operating-points-v2 = <&gpu_opp_table>;
1943                         power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1944                                         <&spm MT8195_POWER_DOMAIN_MFG3>,
1945                                         <&spm MT8195_POWER_DOMAIN_MFG4>,
1946                                         <&spm MT8195_POWER_DOMAIN_MFG5>,
1947                                         <&spm MT8195_POWER_DOMAIN_MFG6>;
1948                         power-domain-names = "core0", "core1", "core2", "core3", "core4";
1949                         status = "disabled";
1950                 };
1951
1952                 mfgcfg: clock-controller@13fbf000 {
1953                         compatible = "mediatek,mt8195-mfgcfg";
1954                         reg = <0 0x13fbf000 0 0x1000>;
1955                         #clock-cells = <1>;
1956                 };
1957
1958                 vppsys0: syscon@14000000 {
1959                         compatible = "mediatek,mt8195-vppsys0", "syscon";
1960                         reg = <0 0x14000000 0 0x1000>;
1961                         #clock-cells = <1>;
1962                 };
1963
1964                 mutex@1400f000 {
1965                         compatible = "mediatek,mt8195-vpp-mutex";
1966                         reg = <0 0x1400f000 0 0x1000>;
1967                         interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
1968                         mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1969                         clocks = <&vppsys0 CLK_VPP0_MUTEX>;
1970                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1971                 };
1972
1973                 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
1974                         compatible = "mediatek,mt8195-smi-sub-common";
1975                         reg = <0 0x14010000 0 0x1000>;
1976                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1977                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
1978                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
1979                         clock-names = "apb", "smi", "gals0";
1980                         mediatek,smi = <&smi_common_vpp>;
1981                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1982                 };
1983
1984                 smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
1985                         compatible = "mediatek,mt8195-smi-sub-common";
1986                         reg = <0 0x14011000 0 0x1000>;
1987                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1988                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
1989                                  <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
1990                         clock-names = "apb", "smi", "gals0";
1991                         mediatek,smi = <&smi_common_vpp>;
1992                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1993                 };
1994
1995                 smi_common_vpp: smi@14012000 {
1996                         compatible = "mediatek,mt8195-smi-common-vpp";
1997                         reg = <0 0x14012000 0 0x1000>;
1998                         clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
1999                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
2000                                <&vppsys0 CLK_VPP0_SMI_RSI>,
2001                                <&vppsys0 CLK_VPP0_SMI_RSI>;
2002                         clock-names = "apb", "smi", "gals0", "gals1";
2003                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2004                 };
2005
2006                 larb4: larb@14013000 {
2007                         compatible = "mediatek,mt8195-smi-larb";
2008                         reg = <0 0x14013000 0 0x1000>;
2009                         mediatek,larb-id = <4>;
2010                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2011                         clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
2012                                <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
2013                         clock-names = "apb", "smi";
2014                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2015                 };
2016
2017                 iommu_vpp: iommu@14018000 {
2018                         compatible = "mediatek,mt8195-iommu-vpp";
2019                         reg = <0 0x14018000 0 0x1000>;
2020                         mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
2021                                           &larb12 &larb14 &larb16 &larb18
2022                                           &larb20 &larb22 &larb23 &larb26
2023                                           &larb27>;
2024                         interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
2025                         clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
2026                         clock-names = "bclk";
2027                         #iommu-cells = <1>;
2028                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2029                 };
2030
2031                 wpesys: clock-controller@14e00000 {
2032                         compatible = "mediatek,mt8195-wpesys";
2033                         reg = <0 0x14e00000 0 0x1000>;
2034                         #clock-cells = <1>;
2035                 };
2036
2037                 wpesys_vpp0: clock-controller@14e02000 {
2038                         compatible = "mediatek,mt8195-wpesys_vpp0";
2039                         reg = <0 0x14e02000 0 0x1000>;
2040                         #clock-cells = <1>;
2041                 };
2042
2043                 wpesys_vpp1: clock-controller@14e03000 {
2044                         compatible = "mediatek,mt8195-wpesys_vpp1";
2045                         reg = <0 0x14e03000 0 0x1000>;
2046                         #clock-cells = <1>;
2047                 };
2048
2049                 larb7: larb@14e04000 {
2050                         compatible = "mediatek,mt8195-smi-larb";
2051                         reg = <0 0x14e04000 0 0x1000>;
2052                         mediatek,larb-id = <7>;
2053                         mediatek,smi = <&smi_common_vdo>;
2054                         clocks = <&wpesys CLK_WPE_SMI_LARB7>,
2055                                  <&wpesys CLK_WPE_SMI_LARB7>;
2056                         clock-names = "apb", "smi";
2057                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2058                 };
2059
2060                 larb8: larb@14e05000 {
2061                         compatible = "mediatek,mt8195-smi-larb";
2062                         reg = <0 0x14e05000 0 0x1000>;
2063                         mediatek,larb-id = <8>;
2064                         mediatek,smi = <&smi_common_vpp>;
2065                         clocks = <&wpesys CLK_WPE_SMI_LARB8>,
2066                                <&wpesys CLK_WPE_SMI_LARB8>,
2067                                <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
2068                         clock-names = "apb", "smi", "gals";
2069                         power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2070                 };
2071
2072                 vppsys1: syscon@14f00000 {
2073                         compatible = "mediatek,mt8195-vppsys1", "syscon";
2074                         reg = <0 0x14f00000 0 0x1000>;
2075                         #clock-cells = <1>;
2076                 };
2077
2078                 mutex@14f01000 {
2079                         compatible = "mediatek,mt8195-vpp-mutex";
2080                         reg = <0 0x14f01000 0 0x1000>;
2081                         interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
2082                         mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2083                         clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
2084                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2085                 };
2086
2087                 larb5: larb@14f02000 {
2088                         compatible = "mediatek,mt8195-smi-larb";
2089                         reg = <0 0x14f02000 0 0x1000>;
2090                         mediatek,larb-id = <5>;
2091                         mediatek,smi = <&smi_common_vdo>;
2092                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2093                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2094                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
2095                         clock-names = "apb", "smi", "gals";
2096                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2097                 };
2098
2099                 larb6: larb@14f03000 {
2100                         compatible = "mediatek,mt8195-smi-larb";
2101                         reg = <0 0x14f03000 0 0x1000>;
2102                         mediatek,larb-id = <6>;
2103                         mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
2104                         clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
2105                                <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
2106                                <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
2107                         clock-names = "apb", "smi", "gals";
2108                         power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2109                 };
2110
2111                 imgsys: clock-controller@15000000 {
2112                         compatible = "mediatek,mt8195-imgsys";
2113                         reg = <0 0x15000000 0 0x1000>;
2114                         #clock-cells = <1>;
2115                 };
2116
2117                 larb9: larb@15001000 {
2118                         compatible = "mediatek,mt8195-smi-larb";
2119                         reg = <0 0x15001000 0 0x1000>;
2120                         mediatek,larb-id = <9>;
2121                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2122                         clocks = <&imgsys CLK_IMG_LARB9>,
2123                                  <&imgsys CLK_IMG_LARB9>,
2124                                  <&imgsys CLK_IMG_GALS>;
2125                         clock-names = "apb", "smi", "gals";
2126                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2127                 };
2128
2129                 smi_sub_common_img0_3x1: smi@15002000 {
2130                         compatible = "mediatek,mt8195-smi-sub-common";
2131                         reg = <0 0x15002000 0 0x1000>;
2132                         clocks = <&imgsys CLK_IMG_IPE>,
2133                                  <&imgsys CLK_IMG_IPE>,
2134                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2135                         clock-names = "apb", "smi", "gals0";
2136                         mediatek,smi = <&smi_common_vpp>;
2137                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2138                 };
2139
2140                 smi_sub_common_img1_3x1: smi@15003000 {
2141                         compatible = "mediatek,mt8195-smi-sub-common";
2142                         reg = <0 0x15003000 0 0x1000>;
2143                         clocks = <&imgsys CLK_IMG_LARB9>,
2144                                  <&imgsys CLK_IMG_LARB9>,
2145                                  <&imgsys CLK_IMG_GALS>;
2146                         clock-names = "apb", "smi", "gals0";
2147                         mediatek,smi = <&smi_common_vdo>;
2148                         power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2149                 };
2150
2151                 imgsys1_dip_top: clock-controller@15110000 {
2152                         compatible = "mediatek,mt8195-imgsys1_dip_top";
2153                         reg = <0 0x15110000 0 0x1000>;
2154                         #clock-cells = <1>;
2155                 };
2156
2157                 larb10: larb@15120000 {
2158                         compatible = "mediatek,mt8195-smi-larb";
2159                         reg = <0 0x15120000 0 0x1000>;
2160                         mediatek,larb-id = <10>;
2161                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2162                         clocks = <&imgsys CLK_IMG_DIP0>,
2163                                <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
2164                         clock-names = "apb", "smi";
2165                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2166                 };
2167
2168                 imgsys1_dip_nr: clock-controller@15130000 {
2169                         compatible = "mediatek,mt8195-imgsys1_dip_nr";
2170                         reg = <0 0x15130000 0 0x1000>;
2171                         #clock-cells = <1>;
2172                 };
2173
2174                 imgsys1_wpe: clock-controller@15220000 {
2175                         compatible = "mediatek,mt8195-imgsys1_wpe";
2176                         reg = <0 0x15220000 0 0x1000>;
2177                         #clock-cells = <1>;
2178                 };
2179
2180                 larb11: larb@15230000 {
2181                         compatible = "mediatek,mt8195-smi-larb";
2182                         reg = <0 0x15230000 0 0x1000>;
2183                         mediatek,larb-id = <11>;
2184                         mediatek,smi = <&smi_sub_common_img1_3x1>;
2185                         clocks = <&imgsys CLK_IMG_WPE0>,
2186                                <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
2187                         clock-names = "apb", "smi";
2188                         power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2189                 };
2190
2191                 ipesys: clock-controller@15330000 {
2192                         compatible = "mediatek,mt8195-ipesys";
2193                         reg = <0 0x15330000 0 0x1000>;
2194                         #clock-cells = <1>;
2195                 };
2196
2197                 larb12: larb@15340000 {
2198                         compatible = "mediatek,mt8195-smi-larb";
2199                         reg = <0 0x15340000 0 0x1000>;
2200                         mediatek,larb-id = <12>;
2201                         mediatek,smi = <&smi_sub_common_img0_3x1>;
2202                         clocks = <&ipesys CLK_IPE_SMI_LARB12>,
2203                                  <&ipesys CLK_IPE_SMI_LARB12>;
2204                         clock-names = "apb", "smi";
2205                         power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2206                 };
2207
2208                 camsys: clock-controller@16000000 {
2209                         compatible = "mediatek,mt8195-camsys";
2210                         reg = <0 0x16000000 0 0x1000>;
2211                         #clock-cells = <1>;
2212                 };
2213
2214                 larb13: larb@16001000 {
2215                         compatible = "mediatek,mt8195-smi-larb";
2216                         reg = <0 0x16001000 0 0x1000>;
2217                         mediatek,larb-id = <13>;
2218                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2219                         clocks = <&camsys CLK_CAM_LARB13>,
2220                                <&camsys CLK_CAM_LARB13>,
2221                                <&camsys CLK_CAM_CAM2MM0_GALS>;
2222                         clock-names = "apb", "smi", "gals";
2223                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2224                 };
2225
2226                 larb14: larb@16002000 {
2227                         compatible = "mediatek,mt8195-smi-larb";
2228                         reg = <0 0x16002000 0 0x1000>;
2229                         mediatek,larb-id = <14>;
2230                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2231                         clocks = <&camsys CLK_CAM_LARB14>,
2232                                  <&camsys CLK_CAM_LARB14>;
2233                         clock-names = "apb", "smi";
2234                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2235                 };
2236
2237                 smi_sub_common_cam_4x1: smi@16004000 {
2238                         compatible = "mediatek,mt8195-smi-sub-common";
2239                         reg = <0 0x16004000 0 0x1000>;
2240                         clocks = <&camsys CLK_CAM_LARB13>,
2241                                  <&camsys CLK_CAM_LARB13>,
2242                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2243                         clock-names = "apb", "smi", "gals0";
2244                         mediatek,smi = <&smi_common_vdo>;
2245                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2246                 };
2247
2248                 smi_sub_common_cam_7x1: smi@16005000 {
2249                         compatible = "mediatek,mt8195-smi-sub-common";
2250                         reg = <0 0x16005000 0 0x1000>;
2251                         clocks = <&camsys CLK_CAM_LARB14>,
2252                                  <&camsys CLK_CAM_CAM2MM1_GALS>,
2253                                  <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
2254                         clock-names = "apb", "smi", "gals0";
2255                         mediatek,smi = <&smi_common_vpp>;
2256                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2257                 };
2258
2259                 larb16: larb@16012000 {
2260                         compatible = "mediatek,mt8195-smi-larb";
2261                         reg = <0 0x16012000 0 0x1000>;
2262                         mediatek,larb-id = <16>;
2263                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2264                         clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
2265                                  <&camsys_rawa CLK_CAM_RAWA_LARBX>;
2266                         clock-names = "apb", "smi";
2267                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2268                 };
2269
2270                 larb17: larb@16013000 {
2271                         compatible = "mediatek,mt8195-smi-larb";
2272                         reg = <0 0x16013000 0 0x1000>;
2273                         mediatek,larb-id = <17>;
2274                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2275                         clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
2276                                  <&camsys_yuva CLK_CAM_YUVA_LARBX>;
2277                         clock-names = "apb", "smi";
2278                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2279                 };
2280
2281                 larb27: larb@16014000 {
2282                         compatible = "mediatek,mt8195-smi-larb";
2283                         reg = <0 0x16014000 0 0x1000>;
2284                         mediatek,larb-id = <27>;
2285                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2286                         clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
2287                                  <&camsys_rawb CLK_CAM_RAWB_LARBX>;
2288                         clock-names = "apb", "smi";
2289                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2290                 };
2291
2292                 larb28: larb@16015000 {
2293                         compatible = "mediatek,mt8195-smi-larb";
2294                         reg = <0 0x16015000 0 0x1000>;
2295                         mediatek,larb-id = <28>;
2296                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2297                         clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
2298                                  <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
2299                         clock-names = "apb", "smi";
2300                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2301                 };
2302
2303                 camsys_rawa: clock-controller@1604f000 {
2304                         compatible = "mediatek,mt8195-camsys_rawa";
2305                         reg = <0 0x1604f000 0 0x1000>;
2306                         #clock-cells = <1>;
2307                 };
2308
2309                 camsys_yuva: clock-controller@1606f000 {
2310                         compatible = "mediatek,mt8195-camsys_yuva";
2311                         reg = <0 0x1606f000 0 0x1000>;
2312                         #clock-cells = <1>;
2313                 };
2314
2315                 camsys_rawb: clock-controller@1608f000 {
2316                         compatible = "mediatek,mt8195-camsys_rawb";
2317                         reg = <0 0x1608f000 0 0x1000>;
2318                         #clock-cells = <1>;
2319                 };
2320
2321                 camsys_yuvb: clock-controller@160af000 {
2322                         compatible = "mediatek,mt8195-camsys_yuvb";
2323                         reg = <0 0x160af000 0 0x1000>;
2324                         #clock-cells = <1>;
2325                 };
2326
2327                 camsys_mraw: clock-controller@16140000 {
2328                         compatible = "mediatek,mt8195-camsys_mraw";
2329                         reg = <0 0x16140000 0 0x1000>;
2330                         #clock-cells = <1>;
2331                 };
2332
2333                 larb25: larb@16141000 {
2334                         compatible = "mediatek,mt8195-smi-larb";
2335                         reg = <0 0x16141000 0 0x1000>;
2336                         mediatek,larb-id = <25>;
2337                         mediatek,smi = <&smi_sub_common_cam_4x1>;
2338                         clocks = <&camsys CLK_CAM_LARB13>,
2339                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2340                                  <&camsys CLK_CAM_CAM2MM0_GALS>;
2341                         clock-names = "apb", "smi", "gals";
2342                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2343                 };
2344
2345                 larb26: larb@16142000 {
2346                         compatible = "mediatek,mt8195-smi-larb";
2347                         reg = <0 0x16142000 0 0x1000>;
2348                         mediatek,larb-id = <26>;
2349                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2350                         clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
2351                                  <&camsys_mraw CLK_CAM_MRAW_LARBX>;
2352                         clock-names = "apb", "smi";
2353                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2354
2355                 };
2356
2357                 ccusys: clock-controller@17200000 {
2358                         compatible = "mediatek,mt8195-ccusys";
2359                         reg = <0 0x17200000 0 0x1000>;
2360                         #clock-cells = <1>;
2361                 };
2362
2363                 larb18: larb@17201000 {
2364                         compatible = "mediatek,mt8195-smi-larb";
2365                         reg = <0 0x17201000 0 0x1000>;
2366                         mediatek,larb-id = <18>;
2367                         mediatek,smi = <&smi_sub_common_cam_7x1>;
2368                         clocks = <&ccusys CLK_CCU_LARB18>,
2369                                  <&ccusys CLK_CCU_LARB18>;
2370                         clock-names = "apb", "smi";
2371                         power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2372                 };
2373
2374                 video-codec@18000000 {
2375                         compatible = "mediatek,mt8195-vcodec-dec";
2376                         mediatek,scp = <&scp>;
2377                         iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>;
2378                         #address-cells = <2>;
2379                         #size-cells = <2>;
2380                         reg = <0 0x18000000 0 0x1000>,
2381                               <0 0x18004000 0 0x1000>;
2382                         ranges = <0 0 0 0x18000000 0 0x26000>;
2383
2384                         video-codec@2000 {
2385                                 compatible = "mediatek,mtk-vcodec-lat-soc";
2386                                 reg = <0 0x2000 0 0x800>;
2387                                 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>,
2388                                          <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>;
2389                                 clocks = <&topckgen CLK_TOP_VDEC>,
2390                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2391                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2392                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2393                                 clock-names = "sel", "vdec", "lat", "top";
2394                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2395                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2396                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2397                         };
2398
2399                         video-codec@10000 {
2400                                 compatible = "mediatek,mtk-vcodec-lat";
2401                                 reg = <0 0x10000 0 0x800>;
2402                                 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>;
2403                                 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>,
2404                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>,
2405                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>,
2406                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>,
2407                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>,
2408                                          <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>;
2409                                 clocks = <&topckgen CLK_TOP_VDEC>,
2410                                          <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
2411                                          <&vdecsys_soc CLK_VDEC_SOC_LAT>,
2412                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2413                                 clock-names = "sel", "vdec", "lat", "top";
2414                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2415                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2416                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2417                         };
2418
2419                         video-codec@25000 {
2420                                 compatible = "mediatek,mtk-vcodec-core";
2421                                 reg = <0 0x25000 0 0x1000>;             /* VDEC_CORE_MISC */
2422                                 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>;
2423                                 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>,
2424                                          <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>,
2425                                          <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>,
2426                                          <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>,
2427                                          <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>,
2428                                          <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>,
2429                                          <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>,
2430                                          <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>,
2431                                          <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>,
2432                                          <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>;
2433                                 clocks = <&topckgen CLK_TOP_VDEC>,
2434                                          <&vdecsys CLK_VDEC_VDEC>,
2435                                          <&vdecsys CLK_VDEC_LAT>,
2436                                          <&topckgen CLK_TOP_UNIVPLL_D4>;
2437                                 clock-names = "sel", "vdec", "lat", "top";
2438                                 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2439                                 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2440                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2441                         };
2442                 };
2443
2444                 larb24: larb@1800d000 {
2445                         compatible = "mediatek,mt8195-smi-larb";
2446                         reg = <0 0x1800d000 0 0x1000>;
2447                         mediatek,larb-id = <24>;
2448                         mediatek,smi = <&smi_common_vdo>;
2449                         clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
2450                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2451                         clock-names = "apb", "smi";
2452                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2453                 };
2454
2455                 larb23: larb@1800e000 {
2456                         compatible = "mediatek,mt8195-smi-larb";
2457                         reg = <0 0x1800e000 0 0x1000>;
2458                         mediatek,larb-id = <23>;
2459                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2460                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2461                                  <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
2462                         clock-names = "apb", "smi";
2463                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2464                 };
2465
2466                 vdecsys_soc: clock-controller@1800f000 {
2467                         compatible = "mediatek,mt8195-vdecsys_soc";
2468                         reg = <0 0x1800f000 0 0x1000>;
2469                         #clock-cells = <1>;
2470                 };
2471
2472                 larb21: larb@1802e000 {
2473                         compatible = "mediatek,mt8195-smi-larb";
2474                         reg = <0 0x1802e000 0 0x1000>;
2475                         mediatek,larb-id = <21>;
2476                         mediatek,smi = <&smi_common_vdo>;
2477                         clocks = <&vdecsys CLK_VDEC_LARB1>,
2478                                  <&vdecsys CLK_VDEC_LARB1>;
2479                         clock-names = "apb", "smi";
2480                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2481                 };
2482
2483                 vdecsys: clock-controller@1802f000 {
2484                         compatible = "mediatek,mt8195-vdecsys";
2485                         reg = <0 0x1802f000 0 0x1000>;
2486                         #clock-cells = <1>;
2487                 };
2488
2489                 larb22: larb@1803e000 {
2490                         compatible = "mediatek,mt8195-smi-larb";
2491                         reg = <0 0x1803e000 0 0x1000>;
2492                         mediatek,larb-id = <22>;
2493                         mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
2494                         clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
2495                                  <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
2496                         clock-names = "apb", "smi";
2497                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2498                 };
2499
2500                 vdecsys_core1: clock-controller@1803f000 {
2501                         compatible = "mediatek,mt8195-vdecsys_core1";
2502                         reg = <0 0x1803f000 0 0x1000>;
2503                         #clock-cells = <1>;
2504                 };
2505
2506                 apusys_pll: clock-controller@190f3000 {
2507                         compatible = "mediatek,mt8195-apusys_pll";
2508                         reg = <0 0x190f3000 0 0x1000>;
2509                         #clock-cells = <1>;
2510                 };
2511
2512                 vencsys: clock-controller@1a000000 {
2513                         compatible = "mediatek,mt8195-vencsys";
2514                         reg = <0 0x1a000000 0 0x1000>;
2515                         #clock-cells = <1>;
2516                 };
2517
2518                 larb19: larb@1a010000 {
2519                         compatible = "mediatek,mt8195-smi-larb";
2520                         reg = <0 0x1a010000 0 0x1000>;
2521                         mediatek,larb-id = <19>;
2522                         mediatek,smi = <&smi_common_vdo>;
2523                         clocks = <&vencsys CLK_VENC_VENC>,
2524                                  <&vencsys CLK_VENC_GALS>;
2525                         clock-names = "apb", "smi";
2526                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2527                 };
2528
2529                 venc: video-codec@1a020000 {
2530                         compatible = "mediatek,mt8195-vcodec-enc";
2531                         reg = <0 0x1a020000 0 0x10000>;
2532                         iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
2533                                  <&iommu_vdo M4U_PORT_L19_VENC_REC>,
2534                                  <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
2535                                  <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
2536                                  <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
2537                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
2538                                  <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
2539                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
2540                                  <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
2541                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
2542                         mediatek,scp = <&scp>;
2543                         clocks = <&vencsys CLK_VENC_VENC>;
2544                         clock-names = "venc_sel";
2545                         assigned-clocks = <&topckgen CLK_TOP_VENC>;
2546                         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2547                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2548                         #address-cells = <2>;
2549                         #size-cells = <2>;
2550                 };
2551
2552                 jpgdec-master {
2553                         compatible = "mediatek,mt8195-jpgdec";
2554                         power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2555                         iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2556                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2557                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2558                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2559                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2560                                  <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2561                         #address-cells = <2>;
2562                         #size-cells = <2>;
2563                         ranges;
2564
2565                         jpgdec@1a040000 {
2566                                 compatible = "mediatek,mt8195-jpgdec-hw";
2567                                 reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
2568                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2569                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2570                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2571                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2572                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2573                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2574                                 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
2575                                 clocks = <&vencsys CLK_VENC_JPGDEC>;
2576                                 clock-names = "jpgdec";
2577                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2578                         };
2579
2580                         jpgdec@1a050000 {
2581                                 compatible = "mediatek,mt8195-jpgdec-hw";
2582                                 reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
2583                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
2584                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
2585                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
2586                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
2587                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
2588                                          <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
2589                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
2590                                 clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
2591                                 clock-names = "jpgdec";
2592                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2593                         };
2594
2595                         jpgdec@1b040000 {
2596                                 compatible = "mediatek,mt8195-jpgdec-hw";
2597                                 reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
2598                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
2599                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
2600                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
2601                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
2602                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
2603                                          <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
2604                                 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
2605                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
2606                                 clock-names = "jpgdec";
2607                                 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2608                         };
2609                 };
2610
2611                 vencsys_core1: clock-controller@1b000000 {
2612                         compatible = "mediatek,mt8195-vencsys_core1";
2613                         reg = <0 0x1b000000 0 0x1000>;
2614                         #clock-cells = <1>;
2615                 };
2616
2617                 vdosys0: syscon@1c01a000 {
2618                         compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2619                         reg = <0 0x1c01a000 0 0x1000>;
2620                         mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
2621                         #clock-cells = <1>;
2622                 };
2623
2624
2625                 jpgenc-master {
2626                         compatible = "mediatek,mt8195-jpgenc";
2627                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2628                         iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2629                                         <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2630                                         <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2631                                         <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2632                         #address-cells = <2>;
2633                         #size-cells = <2>;
2634                         ranges;
2635
2636                         jpgenc@1a030000 {
2637                                 compatible = "mediatek,mt8195-jpgenc-hw";
2638                                 reg = <0 0x1a030000 0 0x10000>;
2639                                 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
2640                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
2641                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
2642                                                 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
2643                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
2644                                 clocks = <&vencsys CLK_VENC_JPGENC>;
2645                                 clock-names = "jpgenc";
2646                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2647                         };
2648
2649                         jpgenc@1b030000 {
2650                                 compatible = "mediatek,mt8195-jpgenc-hw";
2651                                 reg = <0 0x1b030000 0 0x10000>;
2652                                 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
2653                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
2654                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
2655                                                 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
2656                                 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
2657                                 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
2658                                 clock-names = "jpgenc";
2659                                 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2660                         };
2661                 };
2662
2663                 larb20: larb@1b010000 {
2664                         compatible = "mediatek,mt8195-smi-larb";
2665                         reg = <0 0x1b010000 0 0x1000>;
2666                         mediatek,larb-id = <20>;
2667                         mediatek,smi = <&smi_common_vpp>;
2668                         clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
2669                                  <&vencsys_core1 CLK_VENC_CORE1_GALS>,
2670                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2671                         clock-names = "apb", "smi", "gals";
2672                         power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2673                 };
2674
2675                 ovl0: ovl@1c000000 {
2676                         compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
2677                         reg = <0 0x1c000000 0 0x1000>;
2678                         interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
2679                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2680                         clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
2681                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
2682                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2683                 };
2684
2685                 rdma0: rdma@1c002000 {
2686                         compatible = "mediatek,mt8195-disp-rdma";
2687                         reg = <0 0x1c002000 0 0x1000>;
2688                         interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
2689                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2690                         clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
2691                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
2692                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2693                 };
2694
2695                 color0: color@1c003000 {
2696                         compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2697                         reg = <0 0x1c003000 0 0x1000>;
2698                         interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
2699                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2700                         clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
2701                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2702                 };
2703
2704                 ccorr0: ccorr@1c004000 {
2705                         compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2706                         reg = <0 0x1c004000 0 0x1000>;
2707                         interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
2708                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2709                         clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
2710                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2711                 };
2712
2713                 aal0: aal@1c005000 {
2714                         compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2715                         reg = <0 0x1c005000 0 0x1000>;
2716                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
2717                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2718                         clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
2719                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2720                 };
2721
2722                 gamma0: gamma@1c006000 {
2723                         compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2724                         reg = <0 0x1c006000 0 0x1000>;
2725                         interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
2726                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2727                         clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
2728                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2729                 };
2730
2731                 dither0: dither@1c007000 {
2732                         compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2733                         reg = <0 0x1c007000 0 0x1000>;
2734                         interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
2735                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2736                         clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
2737                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2738                 };
2739
2740                 dsc0: dsc@1c009000 {
2741                         compatible = "mediatek,mt8195-disp-dsc";
2742                         reg = <0 0x1c009000 0 0x1000>;
2743                         interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
2744                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2745                         clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
2746                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2747                 };
2748
2749                 merge0: merge@1c014000 {
2750                         compatible = "mediatek,mt8195-disp-merge";
2751                         reg = <0 0x1c014000 0 0x1000>;
2752                         interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
2753                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2754                         clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
2755                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2756                 };
2757
2758                 dp_intf0: dp-intf@1c015000 {
2759                         compatible = "mediatek,mt8195-dp-intf";
2760                         reg = <0 0x1c015000 0 0x1000>;
2761                         interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
2762                         clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
2763                                  <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
2764                                  <&apmixedsys CLK_APMIXED_TVDPLL1>;
2765                         clock-names = "engine", "pixel", "pll";
2766                         status = "disabled";
2767                 };
2768
2769                 mutex: mutex@1c016000 {
2770                         compatible = "mediatek,mt8195-disp-mutex";
2771                         reg = <0 0x1c016000 0 0x1000>;
2772                         interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
2773                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2774                         clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
2775                         mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2776                 };
2777
2778                 larb0: larb@1c018000 {
2779                         compatible = "mediatek,mt8195-smi-larb";
2780                         reg = <0 0x1c018000 0 0x1000>;
2781                         mediatek,larb-id = <0>;
2782                         mediatek,smi = <&smi_common_vdo>;
2783                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2784                                  <&vdosys0 CLK_VDO0_SMI_LARB>,
2785                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
2786                         clock-names = "apb", "smi", "gals";
2787                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2788                 };
2789
2790                 larb1: larb@1c019000 {
2791                         compatible = "mediatek,mt8195-smi-larb";
2792                         reg = <0 0x1c019000 0 0x1000>;
2793                         mediatek,larb-id = <1>;
2794                         mediatek,smi = <&smi_common_vpp>;
2795                         clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
2796                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
2797                                  <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
2798                         clock-names = "apb", "smi", "gals";
2799                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2800                 };
2801
2802                 vdosys1: syscon@1c100000 {
2803                         compatible = "mediatek,mt8195-vdosys1", "syscon";
2804                         reg = <0 0x1c100000 0 0x1000>;
2805                         mboxes = <&gce0 1 CMDQ_THR_PRIO_4>;
2806                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
2807                         #clock-cells = <1>;
2808                         #reset-cells = <1>;
2809                 };
2810
2811                 smi_common_vdo: smi@1c01b000 {
2812                         compatible = "mediatek,mt8195-smi-common-vdo";
2813                         reg = <0 0x1c01b000 0 0x1000>;
2814                         clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
2815                                  <&vdosys0 CLK_VDO0_SMI_EMI>,
2816                                  <&vdosys0 CLK_VDO0_SMI_RSI>,
2817                                  <&vdosys0 CLK_VDO0_SMI_GALS>;
2818                         clock-names = "apb", "smi", "gals0", "gals1";
2819                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2820
2821                 };
2822
2823                 iommu_vdo: iommu@1c01f000 {
2824                         compatible = "mediatek,mt8195-iommu-vdo";
2825                         reg = <0 0x1c01f000 0 0x1000>;
2826                         mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
2827                                           &larb10 &larb11 &larb13 &larb17
2828                                           &larb19 &larb21 &larb24 &larb25
2829                                           &larb28>;
2830                         interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
2831                         #iommu-cells = <1>;
2832                         clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
2833                         clock-names = "bclk";
2834                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2835                 };
2836
2837                 mutex1: mutex@1c101000 {
2838                         compatible = "mediatek,mt8195-disp-mutex";
2839                         reg = <0 0x1c101000 0 0x1000>;
2840                         reg-names = "vdo1_mutex";
2841                         interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
2842                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2843                         clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
2844                         clock-names = "vdo1_mutex";
2845                         mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2846                 };
2847
2848                 larb2: larb@1c102000 {
2849                         compatible = "mediatek,mt8195-smi-larb";
2850                         reg = <0 0x1c102000 0 0x1000>;
2851                         mediatek,larb-id = <2>;
2852                         mediatek,smi = <&smi_common_vdo>;
2853                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
2854                                  <&vdosys1 CLK_VDO1_SMI_LARB2>,
2855                                  <&vdosys1 CLK_VDO1_GALS>;
2856                         clock-names = "apb", "smi", "gals";
2857                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2858                 };
2859
2860                 larb3: larb@1c103000 {
2861                         compatible = "mediatek,mt8195-smi-larb";
2862                         reg = <0 0x1c103000 0 0x1000>;
2863                         mediatek,larb-id = <3>;
2864                         mediatek,smi = <&smi_common_vpp>;
2865                         clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
2866                                  <&vdosys1 CLK_VDO1_GALS>,
2867                                  <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
2868                         clock-names = "apb", "smi", "gals";
2869                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2870                 };
2871
2872                 vdo1_rdma0: rdma@1c104000 {
2873                         compatible = "mediatek,mt8195-vdo1-rdma";
2874                         reg = <0 0x1c104000 0 0x1000>;
2875                         interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
2876                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
2877                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2878                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
2879                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2880                 };
2881
2882                 vdo1_rdma1: rdma@1c105000 {
2883                         compatible = "mediatek,mt8195-vdo1-rdma";
2884                         reg = <0 0x1c105000 0 0x1000>;
2885                         interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>;
2886                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>;
2887                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2888                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>;
2889                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2890                 };
2891
2892                 vdo1_rdma2: rdma@1c106000 {
2893                         compatible = "mediatek,mt8195-vdo1-rdma";
2894                         reg = <0 0x1c106000 0 0x1000>;
2895                         interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>;
2896                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>;
2897                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2898                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>;
2899                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2900                 };
2901
2902                 vdo1_rdma3: rdma@1c107000 {
2903                         compatible = "mediatek,mt8195-vdo1-rdma";
2904                         reg = <0 0x1c107000 0 0x1000>;
2905                         interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>;
2906                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>;
2907                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2908                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>;
2909                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2910                 };
2911
2912                 vdo1_rdma4: rdma@1c108000 {
2913                         compatible = "mediatek,mt8195-vdo1-rdma";
2914                         reg = <0 0x1c108000 0 0x1000>;
2915                         interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>;
2916                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>;
2917                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2918                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>;
2919                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2920                 };
2921
2922                 vdo1_rdma5: rdma@1c109000 {
2923                         compatible = "mediatek,mt8195-vdo1-rdma";
2924                         reg = <0 0x1c109000 0 0x1000>;
2925                         interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>;
2926                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>;
2927                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2928                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>;
2929                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2930                 };
2931
2932                 vdo1_rdma6: rdma@1c10a000 {
2933                         compatible = "mediatek,mt8195-vdo1-rdma";
2934                         reg = <0 0x1c10a000 0 0x1000>;
2935                         interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>;
2936                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>;
2937                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2938                         iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
2939                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2940                 };
2941
2942                 vdo1_rdma7: rdma@1c10b000 {
2943                         compatible = "mediatek,mt8195-vdo1-rdma";
2944                         reg = <0 0x1c10b000 0 0x1000>;
2945                         interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>;
2946                         clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>;
2947                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2948                         iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
2949                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2950                 };
2951
2952                 merge1: vpp-merge@1c10c000 {
2953                         compatible = "mediatek,mt8195-disp-merge";
2954                         reg = <0 0x1c10c000 0 0x1000>;
2955                         interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
2956                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>,
2957                                  <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>;
2958                         clock-names = "merge","merge_async";
2959                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2960                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2961                         mediatek,merge-mute = <1>;
2962                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>;
2963                 };
2964
2965                 merge2: vpp-merge@1c10d000 {
2966                         compatible = "mediatek,mt8195-disp-merge";
2967                         reg = <0 0x1c10d000 0 0x1000>;
2968                         interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>;
2969                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>,
2970                                  <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>;
2971                         clock-names = "merge","merge_async";
2972                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2973                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2974                         mediatek,merge-mute = <1>;
2975                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>;
2976                 };
2977
2978                 merge3: vpp-merge@1c10e000 {
2979                         compatible = "mediatek,mt8195-disp-merge";
2980                         reg = <0 0x1c10e000 0 0x1000>;
2981                         interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>;
2982                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>,
2983                                  <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>;
2984                         clock-names = "merge","merge_async";
2985                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2986                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2987                         mediatek,merge-mute = <1>;
2988                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>;
2989                 };
2990
2991                 merge4: vpp-merge@1c10f000 {
2992                         compatible = "mediatek,mt8195-disp-merge";
2993                         reg = <0 0x1c10f000 0 0x1000>;
2994                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>;
2995                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>,
2996                                  <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
2997                         clock-names = "merge","merge_async";
2998                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2999                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3000                         mediatek,merge-mute = <1>;
3001                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>;
3002                 };
3003
3004                 merge5: vpp-merge@1c110000 {
3005                         compatible = "mediatek,mt8195-disp-merge";
3006                         reg = <0 0x1c110000 0 0x1000>;
3007                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
3008                         clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
3009                                  <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
3010                         clock-names = "merge","merge_async";
3011                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3012                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3013                         mediatek,merge-fifo-en = <1>;
3014                         resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
3015                 };
3016
3017                 dp_intf1: dp-intf@1c113000 {
3018                         compatible = "mediatek,mt8195-dp-intf";
3019                         reg = <0 0x1c113000 0 0x1000>;
3020                         interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
3021                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3022                         clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
3023                                  <&vdosys1 CLK_VDO1_DPINTF>,
3024                                  <&apmixedsys CLK_APMIXED_TVDPLL2>;
3025                         clock-names = "engine", "pixel", "pll";
3026                         status = "disabled";
3027                 };
3028
3029                 ethdr0: hdr-engine@1c114000 {
3030                         compatible = "mediatek,mt8195-disp-ethdr";
3031                         reg = <0 0x1c114000 0 0x1000>,
3032                               <0 0x1c115000 0 0x1000>,
3033                               <0 0x1c117000 0 0x1000>,
3034                               <0 0x1c119000 0 0x1000>,
3035                               <0 0x1c11a000 0 0x1000>,
3036                               <0 0x1c11b000 0 0x1000>,
3037                               <0 0x1c11c000 0 0x1000>;
3038                         reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3039                                     "vdo_be", "adl_ds";
3040                         mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3041                                                   <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
3042                                                   <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
3043                                                   <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
3044                                                   <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
3045                                                   <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
3046                                                   <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
3047                         clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
3048                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
3049                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
3050                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
3051                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
3052                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
3053                                  <&vdosys1 CLK_VDO1_26M_SLOW>,
3054                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
3055                                  <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
3056                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
3057                                  <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
3058                                  <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
3059                                  <&topckgen CLK_TOP_ETHDR>;
3060                         clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3061                                       "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
3062                                       "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
3063                                       "ethdr_top";
3064                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3065                         iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
3066                                  <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
3067                         interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
3068                         resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
3069                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
3070                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
3071                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
3072                                  <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
3073                         reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3074                                       "gfx_fe1_async", "vdo_be_async";
3075                 };
3076
3077                 edp_tx: edp-tx@1c500000 {
3078                         compatible = "mediatek,mt8195-edp-tx";
3079                         reg = <0 0x1c500000 0 0x8000>;
3080                         nvmem-cells = <&dp_calibration>;
3081                         nvmem-cell-names = "dp_calibration_data";
3082                         power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3083                         interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
3084                         max-linkrate-mhz = <8100>;
3085                         status = "disabled";
3086                 };
3087
3088                 dp_tx: dp-tx@1c600000 {
3089                         compatible = "mediatek,mt8195-dp-tx";
3090                         reg = <0 0x1c600000 0 0x8000>;
3091                         nvmem-cells = <&dp_calibration>;
3092                         nvmem-cell-names = "dp_calibration_data";
3093                         power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3094                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
3095                         max-linkrate-mhz = <8100>;
3096                         status = "disabled";
3097                 };
3098         };
3099
3100         thermal_zones: thermal-zones {
3101                 cpu0-thermal {
3102                         polling-delay = <1000>;
3103                         polling-delay-passive = <250>;
3104                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3105
3106                         trips {
3107                                 cpu0_alert: trip-alert {
3108                                         temperature = <85000>;
3109                                         hysteresis = <2000>;
3110                                         type = "passive";
3111                                 };
3112
3113                                 cpu0_crit: trip-crit {
3114                                         temperature = <100000>;
3115                                         hysteresis = <2000>;
3116                                         type = "critical";
3117                                 };
3118                         };
3119
3120                         cooling-maps {
3121                                 map0 {
3122                                         trip = <&cpu0_alert>;
3123                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3124                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3125                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3126                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3127                                 };
3128                         };
3129                 };
3130
3131                 cpu1-thermal {
3132                         polling-delay = <1000>;
3133                         polling-delay-passive = <250>;
3134                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3135
3136                         trips {
3137                                 cpu1_alert: trip-alert {
3138                                         temperature = <85000>;
3139                                         hysteresis = <2000>;
3140                                         type = "passive";
3141                                 };
3142
3143                                 cpu1_crit: trip-crit {
3144                                         temperature = <100000>;
3145                                         hysteresis = <2000>;
3146                                         type = "critical";
3147                                 };
3148                         };
3149
3150                         cooling-maps {
3151                                 map0 {
3152                                         trip = <&cpu1_alert>;
3153                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3154                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3155                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3156                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3157                                 };
3158                         };
3159                 };
3160
3161                 cpu2-thermal {
3162                         polling-delay = <1000>;
3163                         polling-delay-passive = <250>;
3164                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3165
3166                         trips {
3167                                 cpu2_alert: trip-alert {
3168                                         temperature = <85000>;
3169                                         hysteresis = <2000>;
3170                                         type = "passive";
3171                                 };
3172
3173                                 cpu2_crit: trip-crit {
3174                                         temperature = <100000>;
3175                                         hysteresis = <2000>;
3176                                         type = "critical";
3177                                 };
3178                         };
3179
3180                         cooling-maps {
3181                                 map0 {
3182                                         trip = <&cpu2_alert>;
3183                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3184                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3185                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3186                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3187                                 };
3188                         };
3189                 };
3190
3191                 cpu3-thermal {
3192                         polling-delay = <1000>;
3193                         polling-delay-passive = <250>;
3194                         thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3195
3196                         trips {
3197                                 cpu3_alert: trip-alert {
3198                                         temperature = <85000>;
3199                                         hysteresis = <2000>;
3200                                         type = "passive";
3201                                 };
3202
3203                                 cpu3_crit: trip-crit {
3204                                         temperature = <100000>;
3205                                         hysteresis = <2000>;
3206                                         type = "critical";
3207                                 };
3208                         };
3209
3210                         cooling-maps {
3211                                 map0 {
3212                                         trip = <&cpu3_alert>;
3213                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3214                                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3215                                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3216                                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3217                                 };
3218                         };
3219                 };
3220
3221                 cpu4-thermal {
3222                         polling-delay = <1000>;
3223                         polling-delay-passive = <250>;
3224                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3225
3226                         trips {
3227                                 cpu4_alert: trip-alert {
3228                                         temperature = <85000>;
3229                                         hysteresis = <2000>;
3230                                         type = "passive";
3231                                 };
3232
3233                                 cpu4_crit: trip-crit {
3234                                         temperature = <100000>;
3235                                         hysteresis = <2000>;
3236                                         type = "critical";
3237                                 };
3238                         };
3239
3240                         cooling-maps {
3241                                 map0 {
3242                                         trip = <&cpu4_alert>;
3243                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3244                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3245                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3246                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3247                                 };
3248                         };
3249                 };
3250
3251                 cpu5-thermal {
3252                         polling-delay = <1000>;
3253                         polling-delay-passive = <250>;
3254                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3255
3256                         trips {
3257                                 cpu5_alert: trip-alert {
3258                                         temperature = <85000>;
3259                                         hysteresis = <2000>;
3260                                         type = "passive";
3261                                 };
3262
3263                                 cpu5_crit: trip-crit {
3264                                         temperature = <100000>;
3265                                         hysteresis = <2000>;
3266                                         type = "critical";
3267                                 };
3268                         };
3269
3270                         cooling-maps {
3271                                 map0 {
3272                                         trip = <&cpu5_alert>;
3273                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3274                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3275                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3276                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3277                                 };
3278                         };
3279                 };
3280
3281                 cpu6-thermal {
3282                         polling-delay = <1000>;
3283                         polling-delay-passive = <250>;
3284                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3285
3286                         trips {
3287                                 cpu6_alert: trip-alert {
3288                                         temperature = <85000>;
3289                                         hysteresis = <2000>;
3290                                         type = "passive";
3291                                 };
3292
3293                                 cpu6_crit: trip-crit {
3294                                         temperature = <100000>;
3295                                         hysteresis = <2000>;
3296                                         type = "critical";
3297                                 };
3298                         };
3299
3300                         cooling-maps {
3301                                 map0 {
3302                                         trip = <&cpu6_alert>;
3303                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3304                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3305                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3306                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3307                                 };
3308                         };
3309                 };
3310
3311                 cpu7-thermal {
3312                         polling-delay = <1000>;
3313                         polling-delay-passive = <250>;
3314                         thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3315
3316                         trips {
3317                                 cpu7_alert: trip-alert {
3318                                         temperature = <85000>;
3319                                         hysteresis = <2000>;
3320                                         type = "passive";
3321                                 };
3322
3323                                 cpu7_crit: trip-crit {
3324                                         temperature = <100000>;
3325                                         hysteresis = <2000>;
3326                                         type = "critical";
3327                                 };
3328                         };
3329
3330                         cooling-maps {
3331                                 map0 {
3332                                         trip = <&cpu7_alert>;
3333                                         cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3334                                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3335                                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3336                                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3337                                 };
3338                         };
3339                 };
3340
3341                 vpu0-thermal {
3342                         polling-delay = <1000>;
3343                         polling-delay-passive = <250>;
3344                         thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3345
3346                         trips {
3347                                 vpu0_alert: trip-alert {
3348                                         temperature = <85000>;
3349                                         hysteresis = <2000>;
3350                                         type = "passive";
3351                                 };
3352
3353                                 vpu0_crit: trip-crit {
3354                                         temperature = <100000>;
3355                                         hysteresis = <2000>;
3356                                         type = "critical";
3357                                 };
3358                         };
3359                 };
3360
3361                 vpu1-thermal {
3362                         polling-delay = <1000>;
3363                         polling-delay-passive = <250>;
3364                         thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3365
3366                         trips {
3367                                 vpu1_alert: trip-alert {
3368                                         temperature = <85000>;
3369                                         hysteresis = <2000>;
3370                                         type = "passive";
3371                                 };
3372
3373                                 vpu1_crit: trip-crit {
3374                                         temperature = <100000>;
3375                                         hysteresis = <2000>;
3376                                         type = "critical";
3377                                 };
3378                         };
3379                 };
3380
3381                 gpu0-thermal {
3382                         polling-delay = <1000>;
3383                         polling-delay-passive = <250>;
3384                         thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3385
3386                         trips {
3387                                 gpu0_alert: trip-alert {
3388                                         temperature = <85000>;
3389                                         hysteresis = <2000>;
3390                                         type = "passive";
3391                                 };
3392
3393                                 gpu0_crit: trip-crit {
3394                                         temperature = <100000>;
3395                                         hysteresis = <2000>;
3396                                         type = "critical";
3397                                 };
3398                         };
3399                 };
3400
3401                 gpu1-thermal {
3402                         polling-delay = <1000>;
3403                         polling-delay-passive = <250>;
3404                         thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3405
3406                         trips {
3407                                 gpu1_alert: trip-alert {
3408                                         temperature = <85000>;
3409                                         hysteresis = <2000>;
3410                                         type = "passive";
3411                                 };
3412
3413                                 gpu1_crit: trip-crit {
3414                                         temperature = <100000>;
3415                                         hysteresis = <2000>;
3416                                         type = "critical";
3417                                 };
3418                         };
3419                 };
3420
3421                 vdec-thermal {
3422                         polling-delay = <1000>;
3423                         polling-delay-passive = <250>;
3424                         thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3425
3426                         trips {
3427                                 vdec_alert: trip-alert {
3428                                         temperature = <85000>;
3429                                         hysteresis = <2000>;
3430                                         type = "passive";
3431                                 };
3432
3433                                 vdec_crit: trip-crit {
3434                                         temperature = <100000>;
3435                                         hysteresis = <2000>;
3436                                         type = "critical";
3437                                 };
3438                         };
3439                 };
3440
3441                 img-thermal {
3442                         polling-delay = <1000>;
3443                         polling-delay-passive = <250>;
3444                         thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3445
3446                         trips {
3447                                 img_alert: trip-alert {
3448                                         temperature = <85000>;
3449                                         hysteresis = <2000>;
3450                                         type = "passive";
3451                                 };
3452
3453                                 img_crit: trip-crit {
3454                                         temperature = <100000>;
3455                                         hysteresis = <2000>;
3456                                         type = "critical";
3457                                 };
3458                         };
3459                 };
3460
3461                 infra-thermal {
3462                         polling-delay = <1000>;
3463                         polling-delay-passive = <250>;
3464                         thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3465
3466                         trips {
3467                                 infra_alert: trip-alert {
3468                                         temperature = <85000>;
3469                                         hysteresis = <2000>;
3470                                         type = "passive";
3471                                 };
3472
3473                                 infra_crit: trip-crit {
3474                                         temperature = <100000>;
3475                                         hysteresis = <2000>;
3476                                         type = "critical";
3477                                 };
3478                         };
3479                 };
3480
3481                 cam0-thermal {
3482                         polling-delay = <1000>;
3483                         polling-delay-passive = <250>;
3484                         thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3485
3486                         trips {
3487                                 cam0_alert: trip-alert {
3488                                         temperature = <85000>;
3489                                         hysteresis = <2000>;
3490                                         type = "passive";
3491                                 };
3492
3493                                 cam0_crit: trip-crit {
3494                                         temperature = <100000>;
3495                                         hysteresis = <2000>;
3496                                         type = "critical";
3497                                 };
3498                         };
3499                 };
3500
3501                 cam1-thermal {
3502                         polling-delay = <1000>;
3503                         polling-delay-passive = <250>;
3504                         thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3505
3506                         trips {
3507                                 cam1_alert: trip-alert {
3508                                         temperature = <85000>;
3509                                         hysteresis = <2000>;
3510                                         type = "passive";
3511                                 };
3512
3513                                 cam1_crit: trip-crit {
3514                                         temperature = <100000>;
3515                                         hysteresis = <2000>;
3516                                         type = "critical";
3517                                 };
3518                         };
3519                 };
3520         };
3521 };