arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2020 MediaTek Inc.
   4  * Author: Seiya Wang <seiya.wang@mediatek.com>
   5  */
   6 /dts-v1/;
   7 #include "mt8192.dtsi"
   8 #include "mt6359.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/spmi/spmi.h>
  11
  12 / {
  13         aliases {
  14                 serial0 = &uart0;
  15         };
  16
  17         chosen {
  18                 stdout-path = "serial0:115200n8";
  19         };
  20
  21         memory@40000000 {
  22                 device_type = "memory";
  23                 reg = <0 0x40000000 0 0x80000000>;
  24         };
  25
  26         backlight_lcd0: backlight-lcd0 {
  27                 compatible = "pwm-backlight";
  28                 pwms = <&pwm0 0 500000>;
  29                 power-supply = <&ppvar_sys>;
  30                 enable-gpios = <&pio 152 0>;
  31                 brightness-levels = <0 1023>;
  32                 num-interpolated-steps = <1023>;
  33                 default-brightness-level = <576>;
  34         };
  35
  36         pp1000_dpbrdg: regulator-1v0-dpbrdg {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "pp1000_dpbrdg";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pp1000_dpbrdg_en_pins>;
  41                 regulator-min-microvolt = <1000000>;
  42                 regulator-max-microvolt = <1000000>;
  43                 enable-active-high;
  44                 regulator-boot-on;
  45                 gpio = <&pio 19 GPIO_ACTIVE_HIGH>;
  46                 vin-supply = <&mt6359_vs2_buck_reg>;
  47         };
  48
  49         pp1000_mipibrdg: regulator-1v0-mipibrdg {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "pp1000_mipibrdg";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pp1000_mipibrdg_en_pins>;
  54                 regulator-min-microvolt = <1000000>;
  55                 regulator-max-microvolt = <1000000>;
  56                 enable-active-high;
  57                 regulator-boot-on;
  58                 gpio = <&pio 129 GPIO_ACTIVE_HIGH>;
  59                 vin-supply = <&mt6359_vs2_buck_reg>;
  60         };
  61
  62         pp1800_dpbrdg: regulator-1v8-dpbrdg {
  63                 compatible = "regulator-fixed";
  64                 regulator-name = "pp1800_dpbrdg";
  65                 pinctrl-names = "default";
  66                 pinctrl-0 = <&pp1800_dpbrdg_en_pins>;
  67                 enable-active-high;
  68                 regulator-boot-on;
  69                 gpio = <&pio 126 GPIO_ACTIVE_HIGH>;
  70                 vin-supply = <&mt6359_vio18_ldo_reg>;
  71         };
  72
  73         /* system wide LDO 1.8V power rail */
  74         pp1800_ldo_g: regulator-1v8-g {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "pp1800_ldo_g";
  77                 regulator-always-on;
  78                 regulator-boot-on;
  79                 regulator-min-microvolt = <1800000>;
  80                 regulator-max-microvolt = <1800000>;
  81                 vin-supply = <&pp3300_g>;
  82         };
  83
  84         pp1800_mipibrdg: regulator-1v8-mipibrdg {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "pp1800_mipibrdg";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pp1800_mipibrdg_en_pins>;
  89                 enable-active-high;
  90                 regulator-boot-on;
  91                 gpio = <&pio 128 GPIO_ACTIVE_HIGH>;
  92                 vin-supply = <&mt6359_vio18_ldo_reg>;
  93         };
  94
  95         pp3300_dpbrdg: regulator-3v3-dpbrdg {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "pp3300_dpbrdg";
  98                 pinctrl-names = "default";
  99                 pinctrl-0 = <&pp3300_dpbrdg_en_pins>;
 100                 enable-active-high;
 101                 regulator-boot-on;
 102                 gpio = <&pio 26 GPIO_ACTIVE_HIGH>;
 103                 vin-supply = <&pp3300_g>;
 104         };
 105
 106         /* system wide switching 3.3V power rail */
 107         pp3300_g: regulator-3v3-g {
 108                 compatible = "regulator-fixed";
 109                 regulator-name = "pp3300_g";
 110                 regulator-always-on;
 111                 regulator-boot-on;
 112                 regulator-min-microvolt = <3300000>;
 113                 regulator-max-microvolt = <3300000>;
 114                 vin-supply = <&ppvar_sys>;
 115         };
 116
 117         /* system wide LDO 3.3V power rail */
 118         pp3300_ldo_z: regulator-3v3-z {
 119                 compatible = "regulator-fixed";
 120                 regulator-name = "pp3300_ldo_z";
 121                 regulator-always-on;
 122                 regulator-boot-on;
 123                 regulator-min-microvolt = <3300000>;
 124                 regulator-max-microvolt = <3300000>;
 125                 vin-supply = <&ppvar_sys>;
 126         };
 127
 128         pp3300_mipibrdg: regulator-3v3-mipibrdg {
 129                 compatible = "regulator-fixed";
 130                 regulator-name = "pp3300_mipibrdg";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pp3300_mipibrdg_en_pins>;
 133                 enable-active-high;
 134                 regulator-boot-on;
 135                 gpio = <&pio 127 GPIO_ACTIVE_HIGH>;
 136                 vin-supply = <&pp3300_g>;
 137         };
 138
 139         /* separately switched 3.3V power rail */
 140         pp3300_u: regulator-3v3-u {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "pp3300_u";
 143                 regulator-always-on;
 144                 regulator-boot-on;
 145                 regulator-min-microvolt = <3300000>;
 146                 regulator-max-microvolt = <3300000>;
 147                 /* enable pin wired to GPIO controlled by EC */
 148                 vin-supply = <&pp3300_g>;
 149         };
 150
 151         pp3300_wlan: regulator-3v3-wlan {
 152                 compatible = "regulator-fixed";
 153                 regulator-name = "pp3300_wlan";
 154                 regulator-always-on;
 155                 regulator-boot-on;
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 pinctrl-names = "default";
 159                 pinctrl-0 = <&pp3300_wlan_pins>;
 160                 enable-active-high;
 161                 gpio = <&pio 143 GPIO_ACTIVE_HIGH>;
 162         };
 163
 164         /* system wide switching 5.0V power rail */
 165         pp5000_a: regulator-5v0-a {
 166                 compatible = "regulator-fixed";
 167                 regulator-name = "pp5000_a";
 168                 regulator-always-on;
 169                 regulator-boot-on;
 170                 regulator-min-microvolt = <5000000>;
 171                 regulator-max-microvolt = <5000000>;
 172                 vin-supply = <&ppvar_sys>;
 173         };
 174
 175         /* system wide semi-regulated power rail from battery or USB */
 176         ppvar_sys: regulator-var-sys {
 177                 compatible = "regulator-fixed";
 178                 regulator-name = "ppvar_sys";
 179                 regulator-always-on;
 180                 regulator-boot-on;
 181         };
 182
 183         reserved_memory: reserved-memory {
 184                 #address-cells = <2>;
 185                 #size-cells = <2>;
 186                 ranges;
 187
 188                 scp_mem_reserved: scp@50000000 {
 189                         compatible = "shared-dma-pool";
 190                         reg = <0 0x50000000 0 0x2900000>;
 191                         no-map;
 192                 };
 193
 194                 wifi_restricted_dma_region: wifi@c0000000 {
 195                         compatible = "restricted-dma-pool";
 196                         reg = <0 0xc0000000 0 0x4000000>;
 197                 };
 198         };
 199 };
 200
 201 &i2c0 {
 202         status = "okay";
 203
 204         clock-frequency = <400000>;
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&i2c0_pins>;
 207
 208         touchscreen: touchscreen@10 {
 209                 reg = <0x10>;
 210                 interrupts-extended = <&pio 21 IRQ_TYPE_LEVEL_LOW>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&touchscreen_pins>;
 213         };
 214 };
 215
 216 &i2c1 {
 217         status = "okay";
 218
 219         clock-frequency = <400000>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&i2c1_pins>;
 222 };
 223
 224 &i2c2 {
 225         status = "okay";
 226
 227         clock-frequency = <400000>;
 228         clock-stretch-ns = <12600>;
 229         pinctrl-names = "default";
 230         pinctrl-0 = <&i2c2_pins>;
 231
 232         trackpad@15 {
 233                 compatible = "elan,ekth3000";
 234                 reg = <0x15>;
 235                 interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>;
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&trackpad_pins>;
 238                 vcc-supply = <&pp3300_u>;
 239                 wakeup-source;
 240         };
 241 };
 242
 243 &i2c3 {
 244         status = "okay";
 245
 246         clock-frequency = <400000>;
 247         pinctrl-names = "default";
 248         pinctrl-0 = <&i2c3_pins>;
 249 };
 250
 251 &i2c7 {
 252         status = "okay";
 253
 254         clock-frequency = <400000>;
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&i2c7_pins>;
 257 };
 258
 259 &mmc0 {
 260         status = "okay";
 261
 262         pinctrl-names = "default", "state_uhs";
 263         pinctrl-0 = <&mmc0_default_pins>;
 264         pinctrl-1 = <&mmc0_uhs_pins>;
 265         bus-width = <8>;
 266         max-frequency = <200000000>;
 267         vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
 268         vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 269         cap-mmc-highspeed;
 270         mmc-hs200-1_8v;
 271         mmc-hs400-1_8v;
 272         supports-cqe;
 273         cap-mmc-hw-reset;
 274         mmc-hs400-enhanced-strobe;
 275         hs400-ds-delay = <0x12814>;
 276         no-sdio;
 277         no-sd;
 278         non-removable;
 279 };
 280
 281 &mmc1 {
 282         status = "okay";
 283
 284         pinctrl-names = "default", "state_uhs";
 285         pinctrl-0 = <&mmc1_default_pins>;
 286         pinctrl-1 = <&mmc1_uhs_pins>;
 287         bus-width = <4>;
 288         max-frequency = <200000000>;
 289         cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
 290         vmmc-supply = <&mt6360_ldo5_reg>;
 291         vqmmc-supply = <&mt6360_ldo3_reg>;
 292         cap-sd-highspeed;
 293         sd-uhs-sdr50;
 294         sd-uhs-sdr104;
 295         no-sdio;
 296         no-mmc;
 297 };
 298
 299 /* for CORE */
 300 &mt6359_vgpu11_buck_reg {
 301         regulator-always-on;
 302 };
 303
 304 &mt6359_vgpu11_sshub_buck_reg {
 305         regulator-always-on;
 306         regulator-min-microvolt = <575000>;
 307         regulator-max-microvolt = <575000>;
 308 };
 309
 310 &mt6359_vrf12_ldo_reg {
 311         regulator-always-on;
 312 };
 313
 314 &mt6359_vufs_ldo_reg {
 315         regulator-always-on;
 316 };
 317
 318 &mt6359codec {
 319         mediatek,dmic-mode = <1>; /* one-wire */
 320         mediatek,mic-type-0 = <2>; /* DMIC */
 321         mediatek,mic-type-2 = <2>; /* DMIC */
 322 };
 323
 324 &nor_flash {
 325         status = "okay";
 326
 327         pinctrl-names = "default";
 328         pinctrl-0 = <&nor_flash_pins>;
 329         assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
 330         assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>;
 331
 332         flash@0 {
 333                 compatible = "winbond,w25q64jwm", "jedec,spi-nor";
 334                 reg = <0>;
 335                 spi-max-frequency = <52000000>;
 336                 spi-rx-bus-width = <2>;
 337                 spi-tx-bus-width = <2>;
 338         };
 339 };
 340
 341 &pcie {
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pcie_pins>;
 344
 345         pcie0: pcie@0,0 {
 346                 device_type = "pci";
 347                 reg = <0x0000 0 0 0 0>;
 348                 num-lanes = <1>;
 349                 bus-range = <0x1 0x1>;
 350
 351                 #address-cells = <3>;
 352                 #size-cells = <2>;
 353                 ranges;
 354
 355                 wifi: wifi@0,0 {
 356                         reg = <0x10000 0 0 0 0x100000>,
 357                               <0x10000 0 0x100000 0 0x100000>;
 358                         memory-region = <&wifi_restricted_dma_region>;
 359                 };
 360         };
 361 };
 362
 363 &pio {
 364         /* 220 lines */
 365         gpio-line-names = "I2S_DP_LRCK",
 366                           "IS_DP_BCLK",
 367                           "I2S_DP_MCLK",
 368                           "I2S_DP_DATAOUT",
 369                           "SAR0_INT_ODL",
 370                           "EC_AP_INT_ODL",
 371                           "EDPBRDG_INT_ODL",
 372                           "DPBRDG_INT_ODL",
 373                           "DPBRDG_PWREN",
 374                           "DPBRDG_RST_ODL",
 375                           "I2S_HP_MCLK",
 376                           "I2S_HP_BCK",
 377                           "I2S_HP_LRCK",
 378                           "I2S_HP_DATAIN",
 379                           /*
 380                            * AP_FLASH_WP_L is crossystem ABI. Schematics
 381                            * call it AP_FLASH_WP_ODL.
 382                            */
 383                           "AP_FLASH_WP_L",
 384                           "TRACKPAD_INT_ODL",
 385                           "EC_AP_HPD_OD",
 386                           "SD_CD_ODL",
 387                           "HP_INT_ODL_ALC",
 388                           "EN_PP1000_DPBRDG",
 389                           "AP_GPIO20",
 390                           "TOUCH_INT_L_1V8",
 391                           "UART_BT_WAKE_ODL",
 392                           "AP_GPIO23",
 393                           "AP_SPI_FLASH_CS_L",
 394                           "AP_SPI_FLASH_CLK",
 395                           "EN_PP3300_DPBRDG_DX",
 396                           "AP_SPI_FLASH_MOSI",
 397                           "AP_SPI_FLASH_MISO",
 398                           "I2S_HP_DATAOUT",
 399                           "AP_GPIO30",
 400                           "I2S_SPKR_MCLK",
 401                           "I2S_SPKR_BCLK",
 402                           "I2S_SPKR_LRCK",
 403                           "I2S_SPKR_DATAIN",
 404                           "I2S_SPKR_DATAOUT",
 405                           "AP_SPI_H1_TPM_CLK",
 406                           "AP_SPI_H1_TPM_CS_L",
 407                           "AP_SPI_H1_TPM_MISO",
 408                           "AP_SPI_H1_TPM_MOSI",
 409                           "BL_PWM",
 410                           "EDPBRDG_PWREN",
 411                           "EDPBRDG_RST_ODL",
 412                           "EN_PP3300_HUB",
 413                           "HUB_RST_L",
 414                           "",
 415                           "",
 416                           "",
 417                           "",
 418                           "",
 419                           "",
 420                           "SD_CLK",
 421                           "SD_CMD",
 422                           "SD_DATA3",
 423                           "SD_DATA0",
 424                           "SD_DATA2",
 425                           "SD_DATA1",
 426                           "",
 427                           "",
 428                           "",
 429                           "",
 430                           "",
 431                           "",
 432                           "PCIE_WAKE_ODL",
 433                           "PCIE_RST_L",
 434                           "PCIE_CLKREQ_ODL",
 435                           "",
 436                           "",
 437                           "",
 438                           "",
 439                           "",
 440                           "",
 441                           "",
 442                           "",
 443                           "",
 444                           "",
 445                           "",
 446                           "",
 447                           "",
 448                           "",
 449                           "",
 450                           "",
 451                           "",
 452                           "",
 453                           "",
 454                           "",
 455                           "",
 456                           "",
 457                           "",
 458                           "SPMI_SCL",
 459                           "SPMI_SDA",
 460                           "AP_GOOD",
 461                           "UART_DBG_TX_AP_RX",
 462                           "UART_AP_TX_DBG_RX",
 463                           "UART_AP_TX_BT_RX",
 464                           "UART_BT_TX_AP_RX",
 465                           "MIPI_DPI_D0_R",
 466                           "MIPI_DPI_D1_R",
 467                           "MIPI_DPI_D2_R",
 468                           "MIPI_DPI_D3_R",
 469                           "MIPI_DPI_D4_R",
 470                           "MIPI_DPI_D5_R",
 471                           "MIPI_DPI_D6_R",
 472                           "MIPI_DPI_D7_R",
 473                           "MIPI_DPI_D8_R",
 474                           "MIPI_DPI_D9_R",
 475                           "MIPI_DPI_D10_R",
 476                           "",
 477                           "",
 478                           "MIPI_DPI_DE_R",
 479                           "MIPI_DPI_D11_R",
 480                           "MIPI_DPI_VSYNC_R",
 481                           "MIPI_DPI_CLK_R",
 482                           "MIPI_DPI_HSYNC_R",
 483                           "PCM_BT_DATAIN",
 484                           "PCM_BT_SYNC",
 485                           "PCM_BT_DATAOUT",
 486                           "PCM_BT_CLK",
 487                           "AP_I2C_AUDIO_SCL",
 488                           "AP_I2C_AUDIO_SDA",
 489                           "SCP_I2C_SCL",
 490                           "SCP_I2C_SDA",
 491                           "AP_I2C_WLAN_SCL",
 492                           "AP_I2C_WLAN_SDA",
 493                           "AP_I2C_DPBRDG_SCL",
 494                           "AP_I2C_DPBRDG_SDA",
 495                           "EN_PP1800_DPBRDG_DX",
 496                           "EN_PP3300_EDP_DX",
 497                           "EN_PP1800_EDPBRDG_DX",
 498                           "EN_PP1000_EDPBRDG",
 499                           "SCP_JTAG0_TDO",
 500                           "SCP_JTAG0_TDI",
 501                           "SCP_JTAG0_TMS",
 502                           "SCP_JTAG0_TCK",
 503                           "SCP_JTAG0_TRSTN",
 504                           "EN_PP3000_VMC_PMU",
 505                           "EN_PP3300_DISPLAY_DX",
 506                           "TOUCH_RST_L_1V8",
 507                           "TOUCH_REPORT_DISABLE",
 508                           "",
 509                           "",
 510                           "AP_I2C_TRACKPAD_SCL_1V8",
 511                           "AP_I2C_TRACKPAD_SDA_1V8",
 512                           "EN_PP3300_WLAN",
 513                           "BT_KILL_L",
 514                           "WIFI_KILL_L",
 515                           "SET_VMC_VOLT_AT_1V8",
 516                           "EN_SPK",
 517                           "AP_WARM_RST_REQ",
 518                           "",
 519                           "",
 520                           "EN_PP3000_SD_S3",
 521                           "AP_EDP_BKLTEN",
 522                           "",
 523                           "",
 524                           "",
 525                           "AP_SPI_EC_CLK",
 526                           "AP_SPI_EC_CS_L",
 527                           "AP_SPI_EC_MISO",
 528                           "AP_SPI_EC_MOSI",
 529                           "AP_I2C_EDPBRDG_SCL",
 530                           "AP_I2C_EDPBRDG_SDA",
 531                           "MT6315_PROC_INT",
 532                           "MT6315_GPU_INT",
 533                           "UART_SERVO_TX_SCP_RX",
 534                           "UART_SCP_TX_SERVO_RX",
 535                           "BT_RTS_AP_CTS",
 536                           "AP_RTS_BT_CTS",
 537                           "UART_AP_WAKE_BT_ODL",
 538                           "WLAN_ALERT_ODL",
 539                           "EC_IN_RW_ODL",
 540                           "H1_AP_INT_ODL",
 541                           "",
 542                           "",
 543                           "",
 544                           "",
 545                           "",
 546                           "",
 547                           "",
 548                           "",
 549                           "",
 550                           "",
 551                           "",
 552                           "MSDC0_CMD",
 553                           "MSDC0_DAT0",
 554                           "MSDC0_DAT2",
 555                           "MSDC0_DAT4",
 556                           "MSDC0_DAT6",
 557                           "MSDC0_DAT1",
 558                           "MSDC0_DAT5",
 559                           "MSDC0_DAT7",
 560                           "MSDC0_DSL",
 561                           "MSDC0_CLK",
 562                           "MSDC0_DAT3",
 563                           "MSDC0_RST_L",
 564                           "SCP_VREQ_VAO",
 565                           "AUD_DAT_MOSI2",
 566                           "AUD_NLE_MOSI1",
 567                           "AUD_NLE_MOSI0",
 568                           "AUD_DAT_MISO2",
 569                           "AP_I2C_SAR_SDA",
 570                           "AP_I2C_SAR_SCL",
 571                           "AP_I2C_PWR_SCL",
 572                           "AP_I2C_PWR_SDA",
 573                           "AP_I2C_TS_SCL_1V8",
 574                           "AP_I2C_TS_SDA_1V8",
 575                           "SRCLKENA0",
 576                           "SRCLKENA1",
 577                           "AP_EC_WATCHDOG_L",
 578                           "PWRAP_SPI0_MI",
 579                           "PWRAP_SPI0_CSN",
 580                           "PWRAP_SPI0_MO",
 581                           "PWRAP_SPI0_CK",
 582                           "AP_RTC_CLK32K",
 583                           "AUD_CLK_MOSI",
 584                           "AUD_SYNC_MOSI",
 585                           "AUD_DAT_MOSI0",
 586                           "AUD_DAT_MOSI1",
 587                           "AUD_DAT_MISO0",
 588                           "AUD_DAT_MISO1";
 589
 590         cr50_int: cr50-irq-default-pins {
 591                 pins-gsc-ap-int-odl {
 592                         pinmux = <PINMUX_GPIO171__FUNC_GPIO171>;
 593                         input-enable;
 594                 };
 595         };
 596
 597         cros_ec_int: cros-ec-irq-default-pins {
 598                 pins-ec-ap-int-odl {
 599                         pinmux = <PINMUX_GPIO5__FUNC_GPIO5>;
 600                         input-enable;
 601                         bias-pull-up;
 602                 };
 603         };
 604
 605         i2c0_pins: i2c0-default-pins {
 606                 pins-bus {
 607                         pinmux = <PINMUX_GPIO204__FUNC_SCL0>,
 608                                  <PINMUX_GPIO205__FUNC_SDA0>;
 609                         bias-pull-up = <MTK_PULL_SET_RSEL_011>;
 610                         drive-strength-microamp = <1000>;
 611                 };
 612         };
 613
 614         i2c1_pins: i2c1-default-pins {
 615                 pins-bus {
 616                         pinmux = <PINMUX_GPIO118__FUNC_SCL1>,
 617                                  <PINMUX_GPIO119__FUNC_SDA1>;
 618                         bias-pull-up = <MTK_PULL_SET_RSEL_011>;
 619                         drive-strength-microamp = <1000>;
 620                 };
 621         };
 622
 623         i2c2_pins: i2c2-default-pins {
 624                 pins-bus {
 625                         pinmux = <PINMUX_GPIO141__FUNC_SCL2>,
 626                                  <PINMUX_GPIO142__FUNC_SDA2>;
 627                         bias-pull-up = <MTK_PULL_SET_RSEL_011>;
 628                 };
 629         };
 630
 631         i2c3_pins: i2c3-default-pins {
 632                 pins-bus {
 633                         pinmux = <PINMUX_GPIO160__FUNC_SCL3>,
 634                                  <PINMUX_GPIO161__FUNC_SDA3>;
 635                         bias-disable;
 636                         drive-strength-microamp = <1000>;
 637                 };
 638         };
 639
 640         i2c7_pins: i2c7-default-pins {
 641                 pins-bus {
 642                         pinmux = <PINMUX_GPIO124__FUNC_SCL7>,
 643                                  <PINMUX_GPIO125__FUNC_SDA7>;
 644                         bias-disable;
 645                         drive-strength-microamp = <1000>;
 646                 };
 647         };
 648
 649         mmc0_default_pins: mmc0-default-pins {
 650                 pins-cmd-dat {
 651                         pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
 652                                  <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
 653                                  <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
 654                                  <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
 655                                  <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
 656                                  <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
 657                                  <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
 658                                  <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
 659                                  <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
 660                         input-enable;
 661                         drive-strength = <8>;
 662                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 663                 };
 664
 665                 pins-clk {
 666                         pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
 667                         drive-strength = <8>;
 668                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 669                 };
 670
 671                 pins-rst {
 672                         pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
 673                         drive-strength = <8>;
 674                         bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 675                 };
 676         };
 677
 678         mmc0_uhs_pins: mmc0-uhs-pins {
 679                 pins-cmd-dat {
 680                         pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
 681                                  <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
 682                                  <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
 683                                  <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
 684                                  <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
 685                                  <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
 686                                  <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
 687                                  <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
 688                                  <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
 689                         input-enable;
 690                         drive-strength = <10>;
 691                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 692                 };
 693
 694                 pins-clk {
 695                         pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
 696                         drive-strength = <10>;
 697                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 698                 };
 699
 700                 pins-rst {
 701                         pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
 702                         drive-strength = <8>;
 703                         bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 704                 };
 705
 706                 pins-ds {
 707                         pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
 708                         drive-strength = <10>;
 709                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 710                 };
 711         };
 712
 713         mmc1_default_pins: mmc1-default-pins {
 714                 pins-cmd-dat {
 715                         pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
 716                                  <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
 717                                  <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
 718                                  <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
 719                                  <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
 720                         input-enable;
 721                         drive-strength = <8>;
 722                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 723                 };
 724
 725                 pins-clk {
 726                         pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
 727                         drive-strength = <8>;
 728                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 729                 };
 730
 731                 pins-insert {
 732                         pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
 733                         input-enable;
 734                         bias-pull-up;
 735                 };
 736         };
 737
 738         mmc1_uhs_pins: mmc1-uhs-pins {
 739                 pins-cmd-dat {
 740                         pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
 741                                  <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
 742                                  <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
 743                                  <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
 744                                  <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
 745                         input-enable;
 746                         drive-strength = <8>;
 747                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 748                 };
 749
 750                 pins-clk {
 751                         pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
 752                         input-enable;
 753                         drive-strength = <8>;
 754                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 755                 };
 756         };
 757
 758         nor_flash_pins: nor-flash-default-pins {
 759                 pins-cs-io1 {
 760                         pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>,
 761                                  <PINMUX_GPIO28__FUNC_SPINOR_IO1>;
 762                         input-enable;
 763                         bias-pull-up;
 764                         drive-strength = <10>;
 765                 };
 766
 767                 pins-io0 {
 768                         pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>;
 769                         bias-pull-up;
 770                         drive-strength = <10>;
 771                 };
 772
 773                 pins-clk {
 774                         pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>;
 775                         input-enable;
 776                         bias-pull-up;
 777                         drive-strength = <10>;
 778                 };
 779         };
 780
 781         pcie_pins: pcie-default-pins {
 782                 pins-pcie-wake {
 783                         pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
 784                         bias-pull-up;
 785                 };
 786
 787                 pins-pcie-pereset {
 788                         pinmux = <PINMUX_GPIO64__FUNC_PCIE_PERESET_N>;
 789                 };
 790
 791                 pins-pcie-clkreq {
 792                         pinmux = <PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N>;
 793                         bias-pull-up;
 794                 };
 795
 796                 pins-wifi-kill {
 797                         pinmux = <PINMUX_GPIO145__FUNC_GPIO145>; /* WIFI_KILL_L */
 798                         output-high;
 799                 };
 800         };
 801
 802         pp1000_dpbrdg_en_pins: pp1000-dpbrdg-en-pins {
 803                 pins-en {
 804                         pinmux = <PINMUX_GPIO19__FUNC_GPIO19>;
 805                         output-low;
 806                 };
 807         };
 808
 809         pp1000_mipibrdg_en_pins: pp1000-mipibrdg-en-pins {
 810                 pins-en {
 811                         pinmux = <PINMUX_GPIO129__FUNC_GPIO129>;
 812                         output-low;
 813                 };
 814         };
 815
 816         pp1800_dpbrdg_en_pins: pp1800-dpbrdg-en-pins {
 817                 pins-en {
 818                         pinmux = <PINMUX_GPIO126__FUNC_GPIO126>;
 819                         output-low;
 820                 };
 821         };
 822
 823         pp1800_mipibrdg_en_pins: pp1800-mipibrd-en-pins {
 824                 pins-en {
 825                         pinmux = <PINMUX_GPIO128__FUNC_GPIO128>;
 826                         output-low;
 827                 };
 828         };
 829
 830         pp3300_dpbrdg_en_pins: pp3300-dpbrdg-en-pins {
 831                 pins-en {
 832                         pinmux = <PINMUX_GPIO26__FUNC_GPIO26>;
 833                         output-low;
 834                 };
 835         };
 836
 837         pp3300_mipibrdg_en_pins: pp3300-mipibrdg-en-pins {
 838                 pins-en {
 839                         pinmux = <PINMUX_GPIO127__FUNC_GPIO127>;
 840                         output-low;
 841                 };
 842         };
 843
 844         pp3300_wlan_pins: pp3300-wlan-pins {
 845                 pins-pcie-en-pp3300-wlan {
 846                         pinmux = <PINMUX_GPIO143__FUNC_GPIO143>;
 847                         output-high;
 848                 };
 849         };
 850
 851         pwm0_pins: pwm0-default-pins {
 852                 pins-pwm {
 853                         pinmux = <PINMUX_GPIO40__FUNC_DISP_PWM>;
 854                 };
 855
 856                 pins-inhibit {
 857                         pinmux = <PINMUX_GPIO152__FUNC_GPIO152>;
 858                         output-high;
 859                 };
 860         };
 861
 862         scp_pins: scp-pins {
 863                 pins-vreq-vao {
 864                         pinmux = <PINMUX_GPIO195__FUNC_SCP_VREQ_VAO>;
 865                 };
 866         };
 867
 868         spi1_pins: spi1-default-pins {
 869                 pins-cs-mosi-clk {
 870                         pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
 871                                  <PINMUX_GPIO159__FUNC_SPI1_A_MO>,
 872                                  <PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
 873                         bias-disable;
 874                 };
 875
 876                 pins-miso {
 877                         pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
 878                         bias-pull-down;
 879                 };
 880         };
 881
 882         spi5_pins: spi5-default-pins {
 883                 pins-bus {
 884                         pinmux = <PINMUX_GPIO38__FUNC_SPI5_A_MI>,
 885                                  <PINMUX_GPIO37__FUNC_GPIO37>,
 886                                  <PINMUX_GPIO39__FUNC_SPI5_A_MO>,
 887                                  <PINMUX_GPIO36__FUNC_SPI5_A_CLK>;
 888                         bias-disable;
 889                 };
 890         };
 891
 892         trackpad_pins: trackpad-default-pins {
 893                 pins-int-n {
 894                         pinmux = <PINMUX_GPIO15__FUNC_GPIO15>;
 895                         input-enable;
 896                         bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
 897                 };
 898         };
 899
 900         touchscreen_pins: touchscreen-default-pins {
 901                 pins-irq {
 902                         pinmux = <PINMUX_GPIO21__FUNC_GPIO21>;
 903                         input-enable;
 904                         bias-pull-up;
 905                 };
 906
 907                 pins-reset {
 908                         pinmux = <PINMUX_GPIO137__FUNC_GPIO137>;
 909                         output-high;
 910                 };
 911
 912                 pins-report-sw {
 913                         pinmux = <PINMUX_GPIO138__FUNC_GPIO138>;
 914                         output-low;
 915                 };
 916         };
 917 };
 918
 919 &pmic {
 920         interrupts-extended = <&pio 214 IRQ_TYPE_LEVEL_HIGH>;
 921 };
 922
 923 &pwm0 {
 924         status = "okay";
 925
 926         pinctrl-names = "default";
 927         pinctrl-0 = <&pwm0_pins>;
 928 };
 929
 930 &scp {
 931         status = "okay";
 932
 933         firmware-name = "mediatek/mt8192/scp.img";
 934         memory-region = <&scp_mem_reserved>;
 935         pinctrl-names = "default";
 936         pinctrl-0 = <&scp_pins>;
 937
 938         cros-ec {
 939                 compatible = "google,cros-ec-rpmsg";
 940                 mediatek,rpmsg-name = "cros-ec-rpmsg";
 941         };
 942 };
 943
 944 &spi1 {
 945         status = "okay";
 946
 947         mediatek,pad-select = <0>;
 948         pinctrl-names = "default";
 949         pinctrl-0 = <&spi1_pins>;
 950
 951         cros_ec: ec@0 {
 952                 compatible = "google,cros-ec-spi";
 953                 reg = <0>;
 954                 interrupts-extended = <&pio 5 IRQ_TYPE_LEVEL_LOW>;
 955                 spi-max-frequency = <3000000>;
 956                 pinctrl-names = "default";
 957                 pinctrl-0 = <&cros_ec_int>;
 958
 959                 #address-cells = <1>;
 960                 #size-cells = <0>;
 961
 962                 base_detection: cbas {
 963                         compatible = "google,cros-cbas";
 964                 };
 965
 966                 cros_ec_pwm: pwm {
 967                         compatible = "google,cros-ec-pwm";
 968                         #pwm-cells = <1>;
 969
 970                         status = "disabled";
 971                 };
 972
 973                 i2c_tunnel: i2c-tunnel {
 974                         compatible = "google,cros-ec-i2c-tunnel";
 975                         google,remote-bus = <0>;
 976                         #address-cells = <1>;
 977                         #size-cells = <0>;
 978                 };
 979
 980                 mt6360_ldo3_reg: regulator@0 {
 981                         compatible = "google,cros-ec-regulator";
 982                         reg = <0>;
 983                         regulator-min-microvolt = <1800000>;
 984                         regulator-max-microvolt = <3300000>;
 985                 };
 986
 987                 mt6360_ldo5_reg: regulator@1 {
 988                         compatible = "google,cros-ec-regulator";
 989                         reg = <1>;
 990                         regulator-min-microvolt = <3300000>;
 991                         regulator-max-microvolt = <3300000>;
 992                 };
 993
 994                 typec {
 995                         compatible = "google,cros-ec-typec";
 996                         #address-cells = <1>;
 997                         #size-cells = <0>;
 998
 999                         usb_c0: connector@0 {
1000                                 compatible = "usb-c-connector";
1001                                 reg = <0>;
1002                                 label = "left";
1003                                 power-role = "dual";
1004                                 data-role = "host";
1005                                 try-power-role = "source";
1006                         };
1007
1008                         usb_c1: connector@1 {
1009                                 compatible = "usb-c-connector";
1010                                 reg = <1>;
1011                                 label = "right";
1012                                 power-role = "dual";
1013                                 data-role = "host";
1014                                 try-power-role = "source";
1015                         };
1016                 };
1017         };
1018 };
1019
1020 &spi5 {
1021         status = "okay";
1022
1023         cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>;
1024         mediatek,pad-select = <0>;
1025         pinctrl-names = "default";
1026         pinctrl-0 = <&spi5_pins>;
1027
1028         cr50@0 {
1029                 compatible = "google,cr50";
1030                 reg = <0>;
1031                 interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
1032                 spi-max-frequency = <1000000>;
1033                 pinctrl-names = "default";
1034                 pinctrl-0 = <&cr50_int>;
1035         };
1036 };
1037
1038 &spmi {
1039         #address-cells = <2>;
1040         #size-cells = <0>;
1041
1042         mt6315_6: pmic@6 {
1043                 compatible = "mediatek,mt6315-regulator";
1044                 reg = <0x6 SPMI_USID>;
1045
1046                 regulators {
1047                         mt6315_6_vbuck1: vbuck1 {
1048                                 regulator-compatible = "vbuck1";
1049                                 regulator-name = "Vbcpu";
1050                                 regulator-min-microvolt = <300000>;
1051                                 regulator-max-microvolt = <1193750>;
1052                                 regulator-enable-ramp-delay = <256>;
1053                                 regulator-allowed-modes = <0 1 2>;
1054                                 regulator-always-on;
1055                         };
1056
1057                         mt6315_6_vbuck3: vbuck3 {
1058                                 regulator-compatible = "vbuck3";
1059                                 regulator-name = "Vlcpu";
1060                                 regulator-min-microvolt = <300000>;
1061                                 regulator-max-microvolt = <1193750>;
1062                                 regulator-enable-ramp-delay = <256>;
1063                                 regulator-allowed-modes = <0 1 2>;
1064                                 regulator-always-on;
1065                         };
1066                 };
1067         };
1068
1069         mt6315_7: pmic@7 {
1070                 compatible = "mediatek,mt6315-regulator";
1071                 reg = <0x7 SPMI_USID>;
1072
1073                 regulators {
1074                         mt6315_7_vbuck1: vbuck1 {
1075                                 regulator-compatible = "vbuck1";
1076                                 regulator-name = "Vgpu";
1077                                 regulator-min-microvolt = <606250>;
1078                                 regulator-max-microvolt = <1193750>;
1079                                 regulator-enable-ramp-delay = <256>;
1080                                 regulator-allowed-modes = <0 1 2>;
1081                         };
1082                 };
1083         };
1084 };
1085
1086 &uart0 {
1087         status = "okay";
1088 };
1089
1090 &xhci {
1091         status = "okay";
1092
1093         wakeup-source;
1094         vusb33-supply = <&pp3300_g>;
1095         vbus-supply = <&pp5000_a>;
1096 };
1097
1098 #include <arm/cros-ec-keyboard.dtsi>
1099 #include <arm/cros-ec-sbs.dtsi>