1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
18 compatible = "mediatek,mt8186";
19 interrupt-parent = <&gic>;
31 compatible = "mediatek,mt8186-cci";
32 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>,
33 <&apmixedsys CLK_APMIXED_MAINPLL>;
34 clock-names = "cci", "intermediate";
35 operating-points-v2 = <&cci_opp>;
38 cci_opp: opp-table-cci {
39 compatible = "operating-points-v2";
42 cci_opp_0: opp-500000000 {
43 opp-hz = /bits/ 64 <500000000>;
44 opp-microvolt = <600000>;
47 cci_opp_1: opp-560000000 {
48 opp-hz = /bits/ 64 <560000000>;
49 opp-microvolt = <675000>;
52 cci_opp_2: opp-612000000 {
53 opp-hz = /bits/ 64 <612000000>;
54 opp-microvolt = <693750>;
57 cci_opp_3: opp-682000000 {
58 opp-hz = /bits/ 64 <682000000>;
59 opp-microvolt = <718750>;
62 cci_opp_4: opp-752000000 {
63 opp-hz = /bits/ 64 <752000000>;
64 opp-microvolt = <743750>;
67 cci_opp_5: opp-822000000 {
68 opp-hz = /bits/ 64 <822000000>;
69 opp-microvolt = <768750>;
72 cci_opp_6: opp-875000000 {
73 opp-hz = /bits/ 64 <875000000>;
74 opp-microvolt = <781250>;
77 cci_opp_7: opp-927000000 {
78 opp-hz = /bits/ 64 <927000000>;
79 opp-microvolt = <800000>;
82 cci_opp_8: opp-980000000 {
83 opp-hz = /bits/ 64 <980000000>;
84 opp-microvolt = <818750>;
87 cci_opp_9: opp-1050000000 {
88 opp-hz = /bits/ 64 <1050000000>;
89 opp-microvolt = <843750>;
92 cci_opp_10: opp-1120000000 {
93 opp-hz = /bits/ 64 <1120000000>;
94 opp-microvolt = <862500>;
97 cci_opp_11: opp-1155000000 {
98 opp-hz = /bits/ 64 <1155000000>;
99 opp-microvolt = <887500>;
102 cci_opp_12: opp-1190000000 {
103 opp-hz = /bits/ 64 <1190000000>;
104 opp-microvolt = <906250>;
107 cci_opp_13: opp-1260000000 {
108 opp-hz = /bits/ 64 <1260000000>;
109 opp-microvolt = <950000>;
112 cci_opp_14: opp-1330000000 {
113 opp-hz = /bits/ 64 <1330000000>;
114 opp-microvolt = <993750>;
117 cci_opp_15: opp-1400000000 {
118 opp-hz = /bits/ 64 <1400000000>;
119 opp-microvolt = <1031250>;
123 cluster0_opp: opp-table-cluster0 {
124 compatible = "operating-points-v2";
128 opp-hz = /bits/ 64 <500000000>;
129 opp-microvolt = <600000>;
130 required-opps = <&cci_opp_0>;
134 opp-hz = /bits/ 64 <774000000>;
135 opp-microvolt = <675000>;
136 required-opps = <&cci_opp_1>;
140 opp-hz = /bits/ 64 <875000000>;
141 opp-microvolt = <700000>;
142 required-opps = <&cci_opp_2>;
146 opp-hz = /bits/ 64 <975000000>;
147 opp-microvolt = <725000>;
148 required-opps = <&cci_opp_3>;
152 opp-hz = /bits/ 64 <1075000000>;
153 opp-microvolt = <750000>;
154 required-opps = <&cci_opp_4>;
158 opp-hz = /bits/ 64 <1175000000>;
159 opp-microvolt = <775000>;
160 required-opps = <&cci_opp_5>;
164 opp-hz = /bits/ 64 <1275000000>;
165 opp-microvolt = <800000>;
166 required-opps = <&cci_opp_6>;
170 opp-hz = /bits/ 64 <1375000000>;
171 opp-microvolt = <825000>;
172 required-opps = <&cci_opp_7>;
176 opp-hz = /bits/ 64 <1500000000>;
177 opp-microvolt = <856250>;
178 required-opps = <&cci_opp_8>;
182 opp-hz = /bits/ 64 <1618000000>;
183 opp-microvolt = <875000>;
184 required-opps = <&cci_opp_9>;
188 opp-hz = /bits/ 64 <1666000000>;
189 opp-microvolt = <900000>;
190 required-opps = <&cci_opp_10>;
194 opp-hz = /bits/ 64 <1733000000>;
195 opp-microvolt = <925000>;
196 required-opps = <&cci_opp_11>;
200 opp-hz = /bits/ 64 <1800000000>;
201 opp-microvolt = <950000>;
202 required-opps = <&cci_opp_12>;
206 opp-hz = /bits/ 64 <1866000000>;
207 opp-microvolt = <981250>;
208 required-opps = <&cci_opp_13>;
212 opp-hz = /bits/ 64 <1933000000>;
213 opp-microvolt = <1006250>;
214 required-opps = <&cci_opp_14>;
218 opp-hz = /bits/ 64 <2000000000>;
219 opp-microvolt = <1031250>;
220 required-opps = <&cci_opp_15>;
224 cluster1_opp: opp-table-cluster1 {
225 compatible = "operating-points-v2";
229 opp-hz = /bits/ 64 <774000000>;
230 opp-microvolt = <675000>;
231 required-opps = <&cci_opp_0>;
235 opp-hz = /bits/ 64 <835000000>;
236 opp-microvolt = <693750>;
237 required-opps = <&cci_opp_1>;
241 opp-hz = /bits/ 64 <919000000>;
242 opp-microvolt = <718750>;
243 required-opps = <&cci_opp_2>;
247 opp-hz = /bits/ 64 <1002000000>;
248 opp-microvolt = <743750>;
249 required-opps = <&cci_opp_3>;
253 opp-hz = /bits/ 64 <1085000000>;
254 opp-microvolt = <775000>;
255 required-opps = <&cci_opp_4>;
259 opp-hz = /bits/ 64 <1169000000>;
260 opp-microvolt = <800000>;
261 required-opps = <&cci_opp_5>;
265 opp-hz = /bits/ 64 <1308000000>;
266 opp-microvolt = <843750>;
267 required-opps = <&cci_opp_6>;
271 opp-hz = /bits/ 64 <1419000000>;
272 opp-microvolt = <875000>;
273 required-opps = <&cci_opp_7>;
277 opp-hz = /bits/ 64 <1530000000>;
278 opp-microvolt = <912500>;
279 required-opps = <&cci_opp_8>;
283 opp-hz = /bits/ 64 <1670000000>;
284 opp-microvolt = <956250>;
285 required-opps = <&cci_opp_9>;
289 opp-hz = /bits/ 64 <1733000000>;
290 opp-microvolt = <981250>;
291 required-opps = <&cci_opp_10>;
295 opp-hz = /bits/ 64 <1796000000>;
296 opp-microvolt = <1012500>;
297 required-opps = <&cci_opp_11>;
301 opp-hz = /bits/ 64 <1860000000>;
302 opp-microvolt = <1037500>;
303 required-opps = <&cci_opp_12>;
307 opp-hz = /bits/ 64 <1923000000>;
308 opp-microvolt = <1062500>;
309 required-opps = <&cci_opp_13>;
312 cluster1_opp_14: opp-1986000000 {
313 opp-hz = /bits/ 64 <1986000000>;
314 opp-microvolt = <1093750>;
315 required-opps = <&cci_opp_14>;
318 cluster1_opp_15: opp-2050000000 {
319 opp-hz = /bits/ 64 <2050000000>;
320 opp-microvolt = <1118750>;
321 required-opps = <&cci_opp_15>;
326 #address-cells = <1>;
367 compatible = "arm,cortex-a55";
369 enable-method = "psci";
370 clock-frequency = <2000000000>;
371 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
372 <&apmixedsys CLK_APMIXED_MAINPLL>;
373 clock-names = "cpu", "intermediate";
374 operating-points-v2 = <&cluster0_opp>;
375 dynamic-power-coefficient = <84>;
376 capacity-dmips-mhz = <382>;
377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
378 i-cache-size = <32768>;
379 i-cache-line-size = <64>;
380 i-cache-sets = <128>;
381 d-cache-size = <32768>;
382 d-cache-line-size = <64>;
383 d-cache-sets = <128>;
384 next-level-cache = <&l2_0>;
385 #cooling-cells = <2>;
386 mediatek,cci = <&cci>;
391 compatible = "arm,cortex-a55";
393 enable-method = "psci";
394 clock-frequency = <2000000000>;
395 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
396 <&apmixedsys CLK_APMIXED_MAINPLL>;
397 clock-names = "cpu", "intermediate";
398 operating-points-v2 = <&cluster0_opp>;
399 dynamic-power-coefficient = <84>;
400 capacity-dmips-mhz = <382>;
401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
402 i-cache-size = <32768>;
403 i-cache-line-size = <64>;
404 i-cache-sets = <128>;
405 d-cache-size = <32768>;
406 d-cache-line-size = <64>;
407 d-cache-sets = <128>;
408 next-level-cache = <&l2_0>;
409 #cooling-cells = <2>;
410 mediatek,cci = <&cci>;
415 compatible = "arm,cortex-a55";
417 enable-method = "psci";
418 clock-frequency = <2000000000>;
419 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
420 <&apmixedsys CLK_APMIXED_MAINPLL>;
421 clock-names = "cpu", "intermediate";
422 operating-points-v2 = <&cluster0_opp>;
423 dynamic-power-coefficient = <84>;
424 capacity-dmips-mhz = <382>;
425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
426 i-cache-size = <32768>;
427 i-cache-line-size = <64>;
428 i-cache-sets = <128>;
429 d-cache-size = <32768>;
430 d-cache-line-size = <64>;
431 d-cache-sets = <128>;
432 next-level-cache = <&l2_0>;
433 #cooling-cells = <2>;
434 mediatek,cci = <&cci>;
439 compatible = "arm,cortex-a55";
441 enable-method = "psci";
442 clock-frequency = <2000000000>;
443 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
444 <&apmixedsys CLK_APMIXED_MAINPLL>;
445 clock-names = "cpu", "intermediate";
446 operating-points-v2 = <&cluster0_opp>;
447 dynamic-power-coefficient = <84>;
448 capacity-dmips-mhz = <382>;
449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
450 i-cache-size = <32768>;
451 i-cache-line-size = <64>;
452 i-cache-sets = <128>;
453 d-cache-size = <32768>;
454 d-cache-line-size = <64>;
455 d-cache-sets = <128>;
456 next-level-cache = <&l2_0>;
457 #cooling-cells = <2>;
458 mediatek,cci = <&cci>;
463 compatible = "arm,cortex-a55";
465 enable-method = "psci";
466 clock-frequency = <2000000000>;
467 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
468 <&apmixedsys CLK_APMIXED_MAINPLL>;
469 clock-names = "cpu", "intermediate";
470 operating-points-v2 = <&cluster0_opp>;
471 dynamic-power-coefficient = <84>;
472 capacity-dmips-mhz = <382>;
473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
474 i-cache-size = <32768>;
475 i-cache-line-size = <64>;
476 i-cache-sets = <128>;
477 d-cache-size = <32768>;
478 d-cache-line-size = <64>;
479 d-cache-sets = <128>;
480 next-level-cache = <&l2_0>;
481 #cooling-cells = <2>;
482 mediatek,cci = <&cci>;
487 compatible = "arm,cortex-a55";
489 enable-method = "psci";
490 clock-frequency = <2000000000>;
491 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
492 <&apmixedsys CLK_APMIXED_MAINPLL>;
493 clock-names = "cpu", "intermediate";
494 operating-points-v2 = <&cluster0_opp>;
495 dynamic-power-coefficient = <84>;
496 capacity-dmips-mhz = <382>;
497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
498 i-cache-size = <32768>;
499 i-cache-line-size = <64>;
500 i-cache-sets = <128>;
501 d-cache-size = <32768>;
502 d-cache-line-size = <64>;
503 d-cache-sets = <128>;
504 next-level-cache = <&l2_0>;
505 #cooling-cells = <2>;
506 mediatek,cci = <&cci>;
511 compatible = "arm,cortex-a76";
513 enable-method = "psci";
514 clock-frequency = <2050000000>;
515 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
516 <&apmixedsys CLK_APMIXED_MAINPLL>;
517 clock-names = "cpu", "intermediate";
518 operating-points-v2 = <&cluster1_opp>;
519 dynamic-power-coefficient = <335>;
520 capacity-dmips-mhz = <1024>;
521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
522 i-cache-size = <65536>;
523 i-cache-line-size = <64>;
524 i-cache-sets = <256>;
525 d-cache-size = <65536>;
526 d-cache-line-size = <64>;
527 d-cache-sets = <256>;
528 next-level-cache = <&l2_1>;
529 #cooling-cells = <2>;
530 mediatek,cci = <&cci>;
535 compatible = "arm,cortex-a76";
537 enable-method = "psci";
538 clock-frequency = <2050000000>;
539 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
540 <&apmixedsys CLK_APMIXED_MAINPLL>;
541 clock-names = "cpu", "intermediate";
542 operating-points-v2 = <&cluster1_opp>;
543 dynamic-power-coefficient = <335>;
544 capacity-dmips-mhz = <1024>;
545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
546 i-cache-size = <65536>;
547 i-cache-line-size = <64>;
548 i-cache-sets = <256>;
549 d-cache-size = <65536>;
550 d-cache-line-size = <64>;
551 d-cache-sets = <256>;
552 next-level-cache = <&l2_1>;
553 #cooling-cells = <2>;
554 mediatek,cci = <&cci>;
558 entry-method = "psci";
560 cpu_ret_l: cpu-retention-l {
561 compatible = "arm,idle-state";
562 arm,psci-suspend-param = <0x00010001>;
564 entry-latency-us = <50>;
565 exit-latency-us = <100>;
566 min-residency-us = <1600>;
569 cpu_ret_b: cpu-retention-b {
570 compatible = "arm,idle-state";
571 arm,psci-suspend-param = <0x00010001>;
573 entry-latency-us = <50>;
574 exit-latency-us = <100>;
575 min-residency-us = <1400>;
578 cpu_off_l: cpu-off-l {
579 compatible = "arm,idle-state";
580 arm,psci-suspend-param = <0x01010001>;
582 entry-latency-us = <100>;
583 exit-latency-us = <250>;
584 min-residency-us = <2100>;
587 cpu_off_b: cpu-off-b {
588 compatible = "arm,idle-state";
589 arm,psci-suspend-param = <0x01010001>;
591 entry-latency-us = <100>;
592 exit-latency-us = <250>;
593 min-residency-us = <1900>;
598 compatible = "cache";
600 cache-size = <131072>;
601 cache-line-size = <64>;
603 next-level-cache = <&l3_0>;
608 compatible = "cache";
610 cache-size = <262144>;
611 cache-line-size = <64>;
613 next-level-cache = <&l3_0>;
618 compatible = "cache";
620 cache-size = <1048576>;
621 cache-line-size = <64>;
627 clk13m: fixed-factor-clock-13m {
628 compatible = "fixed-factor-clock";
633 clock-output-names = "clk13m";
636 clk26m: oscillator-26m {
637 compatible = "fixed-clock";
639 clock-frequency = <26000000>;
640 clock-output-names = "clk26m";
643 clk32k: oscillator-32k {
644 compatible = "fixed-clock";
646 clock-frequency = <32768>;
647 clock-output-names = "clk32k";
650 gpu_opp_table: opp-table-gpu {
651 compatible = "operating-points-v2";
654 opp-hz = /bits/ 64 <299000000>;
655 opp-microvolt = <612500>;
656 opp-supported-hw = <0xff>;
660 opp-hz = /bits/ 64 <332000000>;
661 opp-microvolt = <625000>;
662 opp-supported-hw = <0xff>;
666 opp-hz = /bits/ 64 <366000000>;
667 opp-microvolt = <637500>;
668 opp-supported-hw = <0xff>;
672 opp-hz = /bits/ 64 <400000000>;
673 opp-microvolt = <643750>;
674 opp-supported-hw = <0xff>;
678 opp-hz = /bits/ 64 <434000000>;
679 opp-microvolt = <656250>;
680 opp-supported-hw = <0xff>;
684 opp-hz = /bits/ 64 <484000000>;
685 opp-microvolt = <668750>;
686 opp-supported-hw = <0xff>;
690 opp-hz = /bits/ 64 <535000000>;
691 opp-microvolt = <687500>;
692 opp-supported-hw = <0xff>;
696 opp-hz = /bits/ 64 <586000000>;
697 opp-microvolt = <700000>;
698 opp-supported-hw = <0xff>;
702 opp-hz = /bits/ 64 <637000000>;
703 opp-microvolt = <712500>;
704 opp-supported-hw = <0xff>;
708 opp-hz = /bits/ 64 <690000000>;
709 opp-microvolt = <737500>;
710 opp-supported-hw = <0xff>;
714 opp-hz = /bits/ 64 <743000000>;
715 opp-microvolt = <756250>;
716 opp-supported-hw = <0xff>;
720 opp-hz = /bits/ 64 <796000000>;
721 opp-microvolt = <781250>;
722 opp-supported-hw = <0xff>;
726 opp-hz = /bits/ 64 <850000000>;
727 opp-microvolt = <800000>;
728 opp-supported-hw = <0xff>;
732 opp-hz = /bits/ 64 <900000000>;
733 opp-microvolt = <850000>;
734 opp-supported-hw = <0x8>;
738 opp-hz = /bits/ 64 <900000000>;
739 opp-microvolt = <837500>;
740 opp-supported-hw = <0x10>;
744 opp-hz = /bits/ 64 <900000000>;
745 opp-microvolt = <825000>;
746 opp-supported-hw = <0x30>;
750 opp-hz = /bits/ 64 <950000000>;
751 opp-microvolt = <900000>;
752 opp-supported-hw = <0x8>;
756 opp-hz = /bits/ 64 <950000000>;
757 opp-microvolt = <875000>;
758 opp-supported-hw = <0x10>;
762 opp-hz = /bits/ 64 <950000000>;
763 opp-microvolt = <850000>;
764 opp-supported-hw = <0x30>;
768 opp-hz = /bits/ 64 <1000000000>;
769 opp-microvolt = <950000>;
770 opp-supported-hw = <0x8>;
774 opp-hz = /bits/ 64 <1000000000>;
775 opp-microvolt = <912500>;
776 opp-supported-hw = <0x10>;
780 opp-hz = /bits/ 64 <1000000000>;
781 opp-microvolt = <875000>;
782 opp-supported-hw = <0x30>;
787 compatible = "arm,cortex-a55-pmu";
788 interrupt-parent = <&gic>;
789 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
793 compatible = "arm,cortex-a76-pmu";
794 interrupt-parent = <&gic>;
795 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
799 compatible = "arm,psci-1.0";
804 compatible = "arm,armv8-timer";
805 interrupt-parent = <&gic>;
806 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
807 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
808 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
809 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
813 #address-cells = <2>;
815 compatible = "simple-bus";
816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
819 gic: interrupt-controller@c000000 {
820 compatible = "arm,gic-v3";
821 #interrupt-cells = <4>;
822 #redistributor-regions = <1>;
823 interrupt-parent = <&gic>;
824 interrupt-controller;
825 reg = <0 0x0c000000 0 0x40000>,
826 <0 0x0c040000 0 0x200000>;
827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
830 ppi_cluster0: interrupt-partition-0 {
831 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
834 ppi_cluster1: interrupt-partition-1 {
835 affinity = <&cpu6 &cpu7>;
840 mcusys: syscon@c53a000 {
841 compatible = "mediatek,mt8186-mcusys", "syscon";
842 reg = <0 0xc53a000 0 0x1000>;
846 topckgen: syscon@10000000 {
847 compatible = "mediatek,mt8186-topckgen", "syscon";
848 reg = <0 0x10000000 0 0x1000>;
852 infracfg_ao: syscon@10001000 {
853 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
854 reg = <0 0x10001000 0 0x1000>;
859 pericfg: syscon@10003000 {
860 compatible = "mediatek,mt8186-pericfg", "syscon";
861 reg = <0 0x10003000 0 0x1000>;
864 pio: pinctrl@10005000 {
865 compatible = "mediatek,mt8186-pinctrl";
866 reg = <0 0x10005000 0 0x1000>,
867 <0 0x10002000 0 0x0200>,
868 <0 0x10002200 0 0x0200>,
869 <0 0x10002400 0 0x0200>,
870 <0 0x10002600 0 0x0200>,
871 <0 0x10002a00 0 0x0200>,
872 <0 0x10002c00 0 0x0200>,
873 <0 0x1000b000 0 0x1000>;
874 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
875 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
878 gpio-ranges = <&pio 0 0 185>;
879 interrupt-controller;
880 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
881 #interrupt-cells = <2>;
884 scpsys: syscon@10006000 {
885 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
886 reg = <0 0x10006000 0 0x1000>;
888 /* System Power Manager */
889 spm: power-controller {
890 compatible = "mediatek,mt8186-power-controller";
891 #address-cells = <1>;
893 #power-domain-cells = <1>;
895 /* power domain of the SoC */
896 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
897 reg = <MT8186_POWER_DOMAIN_MFG0>;
898 clocks = <&topckgen CLK_TOP_MFG>;
899 clock-names = "mfg00";
900 #address-cells = <1>;
902 #power-domain-cells = <1>;
904 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
905 reg = <MT8186_POWER_DOMAIN_MFG1>;
906 mediatek,infracfg = <&infracfg_ao>;
907 #address-cells = <1>;
909 #power-domain-cells = <1>;
911 power-domain@MT8186_POWER_DOMAIN_MFG2 {
912 reg = <MT8186_POWER_DOMAIN_MFG2>;
913 #power-domain-cells = <0>;
916 power-domain@MT8186_POWER_DOMAIN_MFG3 {
917 reg = <MT8186_POWER_DOMAIN_MFG3>;
918 #power-domain-cells = <0>;
923 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
924 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
925 clocks = <&topckgen CLK_TOP_SENINF>,
926 <&topckgen CLK_TOP_SENINF1>;
927 clock-names = "csirx_top0", "csirx_top1";
928 #power-domain-cells = <0>;
931 power-domain@MT8186_POWER_DOMAIN_SSUSB {
932 reg = <MT8186_POWER_DOMAIN_SSUSB>;
933 #power-domain-cells = <0>;
936 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
937 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
938 #power-domain-cells = <0>;
941 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
942 reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
943 clocks = <&topckgen CLK_TOP_AUDIODSP>,
944 <&topckgen CLK_TOP_ADSP_BUS>;
945 clock-names = "audioadsp", "adsp_bus";
946 #address-cells = <1>;
948 #power-domain-cells = <1>;
950 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
951 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
952 #address-cells = <1>;
954 #power-domain-cells = <1>;
956 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
957 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
958 mediatek,infracfg = <&infracfg_ao>;
959 #power-domain-cells = <0>;
964 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
965 reg = <MT8186_POWER_DOMAIN_CONN_ON>;
966 mediatek,infracfg = <&infracfg_ao>;
967 #power-domain-cells = <0>;
970 power-domain@MT8186_POWER_DOMAIN_DIS {
971 reg = <MT8186_POWER_DOMAIN_DIS>;
972 clocks = <&topckgen CLK_TOP_DISP>,
973 <&topckgen CLK_TOP_MDP>,
974 <&mmsys CLK_MM_SMI_INFRA>,
975 <&mmsys CLK_MM_SMI_COMMON>,
976 <&mmsys CLK_MM_SMI_GALS>,
977 <&mmsys CLK_MM_SMI_IOMMU>;
978 clock-names = "disp", "mdp", "smi_infra", "smi_common",
979 "smi_gals", "smi_iommu";
980 mediatek,infracfg = <&infracfg_ao>;
981 #address-cells = <1>;
983 #power-domain-cells = <1>;
985 power-domain@MT8186_POWER_DOMAIN_VDEC {
986 reg = <MT8186_POWER_DOMAIN_VDEC>;
987 clocks = <&topckgen CLK_TOP_VDEC>,
988 <&vdecsys CLK_VDEC_LARB1_CKEN>;
989 clock-names = "vdec0", "larb";
990 mediatek,infracfg = <&infracfg_ao>;
991 #power-domain-cells = <0>;
994 power-domain@MT8186_POWER_DOMAIN_CAM {
995 reg = <MT8186_POWER_DOMAIN_CAM>;
996 clocks = <&topckgen CLK_TOP_CAM>,
997 <&topckgen CLK_TOP_SENINF>,
998 <&topckgen CLK_TOP_SENINF1>,
999 <&topckgen CLK_TOP_SENINF2>,
1000 <&topckgen CLK_TOP_SENINF3>,
1001 <&topckgen CLK_TOP_CAMTM>,
1002 <&camsys CLK_CAM2MM_GALS>;
1003 clock-names = "cam-top", "cam0", "cam1", "cam2",
1004 "cam3", "cam-tm", "gals";
1005 mediatek,infracfg = <&infracfg_ao>;
1006 #address-cells = <1>;
1008 #power-domain-cells = <1>;
1010 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1011 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
1012 #power-domain-cells = <0>;
1015 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1016 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
1017 #power-domain-cells = <0>;
1021 power-domain@MT8186_POWER_DOMAIN_IMG {
1022 reg = <MT8186_POWER_DOMAIN_IMG>;
1023 clocks = <&topckgen CLK_TOP_IMG1>,
1024 <&imgsys1 CLK_IMG1_GALS_IMG1>;
1025 clock-names = "img-top", "gals";
1026 mediatek,infracfg = <&infracfg_ao>;
1027 #address-cells = <1>;
1029 #power-domain-cells = <1>;
1031 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1032 reg = <MT8186_POWER_DOMAIN_IMG2>;
1033 #power-domain-cells = <0>;
1037 power-domain@MT8186_POWER_DOMAIN_IPE {
1038 reg = <MT8186_POWER_DOMAIN_IPE>;
1039 clocks = <&topckgen CLK_TOP_IPE>,
1040 <&ipesys CLK_IPE_LARB19>,
1041 <&ipesys CLK_IPE_LARB20>,
1042 <&ipesys CLK_IPE_SMI_SUBCOM>,
1043 <&ipesys CLK_IPE_GALS_IPE>;
1044 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
1045 "ipe-smi", "ipe-gals";
1046 mediatek,infracfg = <&infracfg_ao>;
1047 #power-domain-cells = <0>;
1050 power-domain@MT8186_POWER_DOMAIN_VENC {
1051 reg = <MT8186_POWER_DOMAIN_VENC>;
1052 clocks = <&topckgen CLK_TOP_VENC>,
1053 <&vencsys CLK_VENC_CKE1_VENC>;
1054 clock-names = "venc0", "larb";
1055 mediatek,infracfg = <&infracfg_ao>;
1056 #power-domain-cells = <0>;
1059 power-domain@MT8186_POWER_DOMAIN_WPE {
1060 reg = <MT8186_POWER_DOMAIN_WPE>;
1061 clocks = <&topckgen CLK_TOP_WPE>,
1062 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1063 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
1064 clock-names = "wpe0", "larb-ck", "larb-pclk";
1065 mediatek,infracfg = <&infracfg_ao>;
1066 #power-domain-cells = <0>;
1072 watchdog: watchdog@10007000 {
1073 compatible = "mediatek,mt8186-wdt";
1074 mediatek,disable-extrst;
1075 reg = <0 0x10007000 0 0x1000>;
1079 apmixedsys: syscon@1000c000 {
1080 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1081 reg = <0 0x1000c000 0 0x1000>;
1085 pwrap: pwrap@1000d000 {
1086 compatible = "mediatek,mt8186-pwrap", "syscon";
1087 reg = <0 0x1000d000 0 0x1000>;
1088 reg-names = "pwrap";
1089 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
1090 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1091 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
1092 clock-names = "spi", "wrap";
1095 spmi: spmi@10015000 {
1096 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1097 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>;
1098 reg-names = "pmif", "spmimst";
1099 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
1100 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
1101 <&topckgen CLK_TOP_SPMI_MST>;
1102 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1103 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1104 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1105 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
1106 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>;
1107 status = "disabled";
1110 systimer: timer@10017000 {
1111 compatible = "mediatek,mt8186-timer",
1112 "mediatek,mt6765-timer";
1113 reg = <0 0x10017000 0 0x1000>;
1114 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
1118 gce: mailbox@1022c000 {
1119 compatible = "mediatek,mt8186-gce";
1120 reg = <0 0X1022c000 0 0x4000>;
1121 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
1122 clock-names = "gce";
1123 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
1128 compatible = "mediatek,mt8186-scp";
1129 reg = <0 0x10500000 0 0x40000>,
1130 <0 0x105c0000 0 0x19080>;
1131 reg-names = "sram", "cfg";
1132 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
1135 adsp: adsp@10680000 {
1136 compatible = "mediatek,mt8186-dsp";
1137 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>,
1138 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>;
1139 reg-names = "cfg", "sram", "sec", "bus";
1140 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>;
1141 clock-names = "audiodsp", "adsp_bus";
1142 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1143 <&topckgen CLK_TOP_ADSP_BUS>;
1144 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1145 mbox-names = "rx", "tx";
1146 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
1147 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1148 status = "disabled";
1151 adsp_mailbox0: mailbox@10686000 {
1152 compatible = "mediatek,mt8186-adsp-mbox";
1154 reg = <0 0x10686100 0 0x1000>;
1155 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
1158 adsp_mailbox1: mailbox@10687000 {
1159 compatible = "mediatek,mt8186-adsp-mbox";
1161 reg = <0 0x10687100 0 0x1000>;
1162 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
1165 nor_flash: spi@11000000 {
1166 compatible = "mediatek,mt8186-nor";
1167 reg = <0 0x11000000 0 0x1000>;
1168 clocks = <&topckgen CLK_TOP_SPINOR>,
1169 <&infracfg_ao CLK_INFRA_AO_SPINOR>,
1170 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
1171 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
1172 clock-names = "spi", "sf", "axi", "axi_s";
1173 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1174 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1175 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
1176 status = "disabled";
1179 auxadc: adc@11001000 {
1180 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1181 reg = <0 0x11001000 0 0x1000>;
1182 #io-channel-cells = <1>;
1183 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
1184 clock-names = "main";
1187 uart0: serial@11002000 {
1188 compatible = "mediatek,mt8186-uart",
1189 "mediatek,mt6577-uart";
1190 reg = <0 0x11002000 0 0x1000>;
1191 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
1192 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
1193 clock-names = "baud", "bus";
1194 status = "disabled";
1197 uart1: serial@11003000 {
1198 compatible = "mediatek,mt8186-uart",
1199 "mediatek,mt6577-uart";
1200 reg = <0 0x11003000 0 0x1000>;
1201 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1202 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
1203 clock-names = "baud", "bus";
1204 status = "disabled";
1207 i2c0: i2c@11007000 {
1208 compatible = "mediatek,mt8186-i2c";
1209 reg = <0 0x11007000 0 0x1000>,
1210 <0 0x10200100 0 0x100>;
1211 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
1212 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
1213 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1214 clock-names = "main", "dma";
1216 #address-cells = <1>;
1218 status = "disabled";
1221 i2c1: i2c@11008000 {
1222 compatible = "mediatek,mt8186-i2c";
1223 reg = <0 0x11008000 0 0x1000>,
1224 <0 0x10200200 0 0x100>;
1225 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1226 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
1227 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1228 clock-names = "main", "dma";
1230 #address-cells = <1>;
1232 status = "disabled";
1235 i2c2: i2c@11009000 {
1236 compatible = "mediatek,mt8186-i2c";
1237 reg = <0 0x11009000 0 0x1000>,
1238 <0 0x10200300 0 0x180>;
1239 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
1240 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
1241 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1242 clock-names = "main", "dma";
1244 #address-cells = <1>;
1246 status = "disabled";
1249 i2c3: i2c@1100f000 {
1250 compatible = "mediatek,mt8186-i2c";
1251 reg = <0 0x1100f000 0 0x1000>,
1252 <0 0x10200480 0 0x100>;
1253 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
1254 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
1255 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1256 clock-names = "main", "dma";
1258 #address-cells = <1>;
1260 status = "disabled";
1263 i2c4: i2c@11011000 {
1264 compatible = "mediatek,mt8186-i2c";
1265 reg = <0 0x11011000 0 0x1000>,
1266 <0 0x10200580 0 0x180>;
1267 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
1268 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
1269 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1270 clock-names = "main", "dma";
1272 #address-cells = <1>;
1274 status = "disabled";
1277 i2c5: i2c@11016000 {
1278 compatible = "mediatek,mt8186-i2c";
1279 reg = <0 0x11016000 0 0x1000>,
1280 <0 0x10200700 0 0x100>;
1281 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
1282 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
1283 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1284 clock-names = "main", "dma";
1286 #address-cells = <1>;
1288 status = "disabled";
1291 i2c6: i2c@1100d000 {
1292 compatible = "mediatek,mt8186-i2c";
1293 reg = <0 0x1100d000 0 0x1000>,
1294 <0 0x10200800 0 0x100>;
1295 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
1296 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
1297 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1298 clock-names = "main", "dma";
1300 #address-cells = <1>;
1302 status = "disabled";
1305 i2c7: i2c@11004000 {
1306 compatible = "mediatek,mt8186-i2c";
1307 reg = <0 0x11004000 0 0x1000>,
1308 <0 0x10200900 0 0x180>;
1309 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
1310 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
1311 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1312 clock-names = "main", "dma";
1314 #address-cells = <1>;
1316 status = "disabled";
1319 i2c8: i2c@11005000 {
1320 compatible = "mediatek,mt8186-i2c";
1321 reg = <0 0x11005000 0 0x1000>,
1322 <0 0x10200A80 0 0x180>;
1323 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1324 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
1325 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1326 clock-names = "main", "dma";
1328 #address-cells = <1>;
1330 status = "disabled";
1333 spi0: spi@1100a000 {
1334 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1335 #address-cells = <1>;
1337 reg = <0 0x1100a000 0 0x1000>;
1338 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
1339 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1340 <&topckgen CLK_TOP_SPI>,
1341 <&infracfg_ao CLK_INFRA_AO_SPI0>;
1342 clock-names = "parent-clk", "sel-clk", "spi-clk";
1343 status = "disabled";
1346 pwm0: pwm@1100e000 {
1347 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1348 reg = <0 0x1100e000 0 0x1000>;
1349 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
1351 clocks = <&topckgen CLK_TOP_DISP_PWM>,
1352 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
1353 clock-names = "main", "mm";
1354 status = "disabled";
1357 spi1: spi@11010000 {
1358 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1359 #address-cells = <1>;
1361 reg = <0 0x11010000 0 0x1000>;
1362 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
1363 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1364 <&topckgen CLK_TOP_SPI>,
1365 <&infracfg_ao CLK_INFRA_AO_SPI1>;
1366 clock-names = "parent-clk", "sel-clk", "spi-clk";
1367 status = "disabled";
1370 spi2: spi@11012000 {
1371 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1372 #address-cells = <1>;
1374 reg = <0 0x11012000 0 0x1000>;
1375 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
1376 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1377 <&topckgen CLK_TOP_SPI>,
1378 <&infracfg_ao CLK_INFRA_AO_SPI2>;
1379 clock-names = "parent-clk", "sel-clk", "spi-clk";
1380 status = "disabled";
1383 spi3: spi@11013000 {
1384 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1385 #address-cells = <1>;
1387 reg = <0 0x11013000 0 0x1000>;
1388 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
1389 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1390 <&topckgen CLK_TOP_SPI>,
1391 <&infracfg_ao CLK_INFRA_AO_SPI3>;
1392 clock-names = "parent-clk", "sel-clk", "spi-clk";
1393 status = "disabled";
1396 spi4: spi@11014000 {
1397 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1398 #address-cells = <1>;
1400 reg = <0 0x11014000 0 0x1000>;
1401 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1402 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1403 <&topckgen CLK_TOP_SPI>,
1404 <&infracfg_ao CLK_INFRA_AO_SPI4>;
1405 clock-names = "parent-clk", "sel-clk", "spi-clk";
1406 status = "disabled";
1409 spi5: spi@11015000 {
1410 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1411 #address-cells = <1>;
1413 reg = <0 0x11015000 0 0x1000>;
1414 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1415 clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
1416 <&topckgen CLK_TOP_SPI>,
1417 <&infracfg_ao CLK_INFRA_AO_SPI5>;
1418 clock-names = "parent-clk", "sel-clk", "spi-clk";
1419 status = "disabled";
1422 imp_iic_wrap: clock-controller@11017000 {
1423 compatible = "mediatek,mt8186-imp_iic_wrap";
1424 reg = <0 0x11017000 0 0x1000>;
1428 uart2: serial@11018000 {
1429 compatible = "mediatek,mt8186-uart",
1430 "mediatek,mt6577-uart";
1431 reg = <0 0x11018000 0 0x1000>;
1432 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
1433 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
1434 clock-names = "baud", "bus";
1435 status = "disabled";
1438 i2c9: i2c@11019000 {
1439 compatible = "mediatek,mt8186-i2c";
1440 reg = <0 0x11019000 0 0x1000>,
1441 <0 0x10200c00 0 0x180>;
1442 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
1443 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
1444 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
1445 clock-names = "main", "dma";
1447 #address-cells = <1>;
1449 status = "disabled";
1452 afe: audio-controller@11210000 {
1453 compatible = "mediatek,mt8186-sound";
1454 reg = <0 0x11210000 0 0x2000>;
1455 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
1456 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
1457 <&topckgen CLK_TOP_AUDIO>,
1458 <&topckgen CLK_TOP_AUD_INTBUS>,
1459 <&topckgen CLK_TOP_MAINPLL_D2_D4>,
1460 <&topckgen CLK_TOP_AUD_1>,
1461 <&apmixedsys CLK_APMIXED_APLL1>,
1462 <&topckgen CLK_TOP_AUD_2>,
1463 <&apmixedsys CLK_APMIXED_APLL2>,
1464 <&topckgen CLK_TOP_AUD_ENGEN1>,
1465 <&topckgen CLK_TOP_APLL1_D8>,
1466 <&topckgen CLK_TOP_AUD_ENGEN2>,
1467 <&topckgen CLK_TOP_APLL2_D8>,
1468 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
1469 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
1470 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
1471 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
1472 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
1473 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
1474 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
1475 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
1476 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
1477 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
1478 <&topckgen CLK_TOP_AUDIO_H>,
1480 clock-names = "aud_infra_clk",
1483 "top_mux_audio_int",
1484 "top_mainpll_d2_d4",
1502 "top_apll12_div_tdm",
1505 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
1506 mediatek,apmixedsys = <&apmixedsys>;
1507 mediatek,infracfg = <&infracfg_ao>;
1508 mediatek,topckgen = <&topckgen>;
1509 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
1510 reset-names = "audiosys";
1511 status = "disabled";
1514 ssusb0: usb@11201000 {
1515 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1516 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>;
1517 reg-names = "mac", "ippc";
1518 clocks = <&topckgen CLK_TOP_USB_TOP>,
1519 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1520 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1521 <&infracfg_ao CLK_INFRA_AO_ICUSB>;
1522 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1523 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
1524 phys = <&u2port0 PHY_TYPE_USB2>;
1525 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1526 #address-cells = <2>;
1529 status = "disabled";
1531 usb_host0: usb@11200000 {
1532 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1533 reg = <0 0x11200000 0 0x1000>;
1535 clocks = <&topckgen CLK_TOP_USB_TOP>,
1536 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>,
1537 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>,
1538 <&infracfg_ao CLK_INFRA_AO_ICUSB>,
1539 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
1540 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1541 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
1542 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1544 status = "disabled";
1548 mmc0: mmc@11230000 {
1549 compatible = "mediatek,mt8186-mmc",
1550 "mediatek,mt8183-mmc";
1551 reg = <0 0x11230000 0 0x10000>,
1552 <0 0x11cd0000 0 0x1000>;
1553 clocks = <&topckgen CLK_TOP_MSDC50_0>,
1554 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
1555 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
1556 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
1557 clock-names = "source", "hclk", "source_cg", "crypto";
1558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
1559 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1560 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1561 status = "disabled";
1564 mmc1: mmc@11240000 {
1565 compatible = "mediatek,mt8186-mmc",
1566 "mediatek,mt8183-mmc";
1567 reg = <0 0x11240000 0 0x1000>,
1568 <0 0x11c90000 0 0x1000>;
1569 clocks = <&topckgen CLK_TOP_MSDC30_1>,
1570 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1571 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1572 clock-names = "source", "hclk", "source_cg";
1573 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1574 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1575 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1576 status = "disabled";
1579 ssusb1: usb@11281000 {
1580 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1581 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>;
1582 reg-names = "mac", "ippc";
1583 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1584 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1585 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1587 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1588 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
1589 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1590 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1591 #address-cells = <2>;
1594 status = "disabled";
1596 usb_host1: usb@11280000 {
1597 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1598 reg = <0 0x11280000 0 0x1000>;
1600 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>,
1601 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>,
1602 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>,
1604 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
1605 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1606 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
1607 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1609 status = "disabled";
1613 u3phy0: t-phy@11c80000 {
1614 compatible = "mediatek,mt8186-tphy",
1615 "mediatek,generic-tphy-v2";
1616 #address-cells = <1>;
1618 ranges = <0x0 0x0 0x11c80000 0x1000>;
1619 status = "disabled";
1621 u2port1: usb-phy@0 {
1624 clock-names = "ref";
1628 u3port1: usb-phy@700 {
1629 reg = <0x700 0x900>;
1631 clock-names = "ref";
1636 u3phy1: t-phy@11ca0000 {
1637 compatible = "mediatek,mt8186-tphy",
1638 "mediatek,generic-tphy-v2";
1639 #address-cells = <1>;
1641 ranges = <0x0 0x0 0x11ca0000 0x1000>;
1642 status = "disabled";
1644 u2port0: usb-phy@0 {
1647 clock-names = "ref";
1649 mediatek,discth = <0x8>;
1653 efuse: efuse@11cb0000 {
1654 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1655 reg = <0 0x11cb0000 0 0x1000>;
1656 #address-cells = <1>;
1659 gpu_speedbin: gpu-speed-bin@59c {
1665 mipi_tx0: dsi-phy@11cc0000 {
1666 compatible = "mediatek,mt8183-mipi-tx";
1667 reg = <0 0x11cc0000 0 0x1000>;
1671 clock-output-names = "mipi_tx0_pll";
1672 status = "disabled";
1675 mfgsys: clock-controller@13000000 {
1676 compatible = "mediatek,mt8186-mfgsys";
1677 reg = <0 0x13000000 0 0x1000>;
1682 compatible = "mediatek,mt8186-mali",
1684 reg = <0 0x13040000 0 0x4000>;
1686 clocks = <&mfgsys CLK_MFG_BG3D>;
1687 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>,
1688 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
1689 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
1690 interrupt-names = "job", "mmu", "gpu";
1691 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1692 <&spm MT8186_POWER_DOMAIN_MFG3>;
1693 power-domain-names = "core0", "core1";
1694 #cooling-cells = <2>;
1695 nvmem-cells = <&gpu_speedbin>;
1696 nvmem-cell-names = "speed-bin";
1697 operating-points-v2 = <&gpu_opp_table>;
1698 dynamic-power-coefficient = <4687>;
1699 status = "disabled";
1702 mmsys: syscon@14000000 {
1703 compatible = "mediatek,mt8186-mmsys", "syscon";
1704 reg = <0 0x14000000 0 0x1000>;
1707 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1708 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1709 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1712 mutex: mutex@14001000 {
1713 compatible = "mediatek,mt8186-disp-mutex";
1714 reg = <0 0x14001000 0 0x1000>;
1715 clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
1716 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
1717 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1718 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1719 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
1720 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1723 smi_common: smi@14002000 {
1724 compatible = "mediatek,mt8186-smi-common";
1725 reg = <0 0x14002000 0 0x1000>;
1726 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1727 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1728 clock-names = "apb", "smi", "gals0", "gals1";
1729 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1732 larb0: smi@14003000 {
1733 compatible = "mediatek,mt8186-smi-larb";
1734 reg = <0 0x14003000 0 0x1000>;
1735 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1736 <&mmsys CLK_MM_SMI_COMMON>;
1737 clock-names = "apb", "smi";
1738 mediatek,larb-id = <0>;
1739 mediatek,smi = <&smi_common>;
1740 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1743 larb1: smi@14004000 {
1744 compatible = "mediatek,mt8186-smi-larb";
1745 reg = <0 0x14004000 0 0x1000>;
1746 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1747 <&mmsys CLK_MM_SMI_COMMON>;
1748 clock-names = "apb", "smi";
1749 mediatek,larb-id = <1>;
1750 mediatek,smi = <&smi_common>;
1751 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1754 ovl0: ovl@14005000 {
1755 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1756 reg = <0 0x14005000 0 0x1000>;
1757 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1758 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
1759 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
1760 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1761 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1764 ovl_2l0: ovl@14006000 {
1765 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1766 reg = <0 0x14006000 0 0x1000>;
1767 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1768 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
1769 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1771 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1774 rdma0: rdma@14007000 {
1775 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1776 reg = <0 0x14007000 0 0x1000>;
1777 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1778 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>;
1779 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>;
1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1784 color: color@14009000 {
1785 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1786 reg = <0 0x14009000 0 0x1000>;
1787 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1788 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>;
1789 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1790 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1794 compatible = "mediatek,mt8186-dpi";
1795 reg = <0 0x1400a000 0 0x1000>;
1796 clocks = <&topckgen CLK_TOP_DPI>,
1797 <&mmsys CLK_MM_DISP_DPI>,
1798 <&apmixedsys CLK_APMIXED_TVDPLL>;
1799 clock-names = "pixel", "engine", "pll";
1800 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1801 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1802 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1803 status = "disabled";
1806 dpi_out: endpoint { };
1810 ccorr: ccorr@1400b000 {
1811 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1812 reg = <0 0x1400b000 0 0x1000>;
1813 clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1814 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>;
1815 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1816 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1820 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1821 reg = <0 0x1400c000 0 0x1000>;
1822 clocks = <&mmsys CLK_MM_DISP_AAL0>;
1823 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>;
1824 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1825 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1828 gamma: gamma@1400d000 {
1829 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1830 reg = <0 0x1400d000 0 0x1000>;
1831 clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1832 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>;
1833 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1834 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1837 postmask: postmask@1400e000 {
1838 compatible = "mediatek,mt8186-disp-postmask",
1839 "mediatek,mt8192-disp-postmask";
1840 reg = <0 0x1400e000 0 0x1000>;
1841 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
1842 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>;
1843 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1844 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1847 dither: dither@1400f000 {
1848 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1849 reg = <0 0x1400f000 0 0x1000>;
1850 clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1851 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>;
1852 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1853 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1856 dsi0: dsi@14013000 {
1857 compatible = "mediatek,mt8186-dsi";
1858 reg = <0 0x14013000 0 0x1000>;
1859 clocks = <&mmsys CLK_MM_DSI0>,
1860 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1862 clock-names = "engine", "digital", "hs";
1863 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1865 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1868 status = "disabled";
1871 dsi_out: endpoint { };
1875 iommu_mm: iommu@14016000 {
1876 compatible = "mediatek,mt8186-iommu-mm";
1877 reg = <0 0x14016000 0 0x1000>;
1878 clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1879 clock-names = "bclk";
1880 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1881 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1882 &larb7 &larb8 &larb9 &larb11
1883 &larb13 &larb14 &larb16 &larb17
1885 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1889 rdma1: rdma@1401f000 {
1890 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1891 reg = <0 0x1401f000 0 0x1000>;
1892 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1893 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>;
1894 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>;
1895 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1896 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1899 wpesys: clock-controller@14020000 {
1900 compatible = "mediatek,mt8186-wpesys";
1901 reg = <0 0x14020000 0 0x1000>;
1905 larb8: smi@14023000 {
1906 compatible = "mediatek,mt8186-smi-larb";
1907 reg = <0 0x14023000 0 0x1000>;
1908 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1909 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1910 clock-names = "apb", "smi";
1911 mediatek,larb-id = <8>;
1912 mediatek,smi = <&smi_common>;
1913 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1916 imgsys1: clock-controller@15020000 {
1917 compatible = "mediatek,mt8186-imgsys1";
1918 reg = <0 0x15020000 0 0x1000>;
1922 larb9: smi@1502e000 {
1923 compatible = "mediatek,mt8186-smi-larb";
1924 reg = <0 0x1502e000 0 0x1000>;
1925 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1926 <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1927 clock-names = "apb", "smi";
1928 mediatek,larb-id = <9>;
1929 mediatek,smi = <&smi_common>;
1930 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1933 imgsys2: clock-controller@15820000 {
1934 compatible = "mediatek,mt8186-imgsys2";
1935 reg = <0 0x15820000 0 0x1000>;
1939 larb11: smi@1582e000 {
1940 compatible = "mediatek,mt8186-smi-larb";
1941 reg = <0 0x1582e000 0 0x1000>;
1942 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
1943 <&imgsys2 CLK_IMG2_LARB9_IMG2>;
1944 clock-names = "apb", "smi";
1945 mediatek,larb-id = <11>;
1946 mediatek,smi = <&smi_common>;
1947 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1950 larb4: smi@1602e000 {
1951 compatible = "mediatek,mt8186-smi-larb";
1952 reg = <0 0x1602e000 0 0x1000>;
1953 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
1954 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1955 clock-names = "apb", "smi";
1956 mediatek,larb-id = <4>;
1957 mediatek,smi = <&smi_common>;
1958 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1961 vdecsys: clock-controller@1602f000 {
1962 compatible = "mediatek,mt8186-vdecsys";
1963 reg = <0 0x1602f000 0 0x1000>;
1967 vencsys: clock-controller@17000000 {
1968 compatible = "mediatek,mt8186-vencsys";
1969 reg = <0 0x17000000 0 0x1000>;
1973 larb7: smi@17010000 {
1974 compatible = "mediatek,mt8186-smi-larb";
1975 reg = <0 0x17010000 0 0x1000>;
1976 clocks = <&vencsys CLK_VENC_CKE1_VENC>,
1977 <&vencsys CLK_VENC_CKE1_VENC>;
1978 clock-names = "apb", "smi";
1979 mediatek,larb-id = <7>;
1980 mediatek,smi = <&smi_common>;
1981 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
1984 camsys: clock-controller@1a000000 {
1985 compatible = "mediatek,mt8186-camsys";
1986 reg = <0 0x1a000000 0 0x1000>;
1990 larb13: smi@1a001000 {
1991 compatible = "mediatek,mt8186-smi-larb";
1992 reg = <0 0x1a001000 0 0x1000>;
1993 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
1994 clock-names = "apb", "smi";
1995 mediatek,larb-id = <13>;
1996 mediatek,smi = <&smi_common>;
1997 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2000 larb14: smi@1a002000 {
2001 compatible = "mediatek,mt8186-smi-larb";
2002 reg = <0 0x1a002000 0 0x1000>;
2003 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
2004 clock-names = "apb", "smi";
2005 mediatek,larb-id = <14>;
2006 mediatek,smi = <&smi_common>;
2007 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2010 larb16: smi@1a00f000 {
2011 compatible = "mediatek,mt8186-smi-larb";
2012 reg = <0 0x1a00f000 0 0x1000>;
2013 clocks = <&camsys CLK_CAM_LARB14>,
2014 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
2015 clock-names = "apb", "smi";
2016 mediatek,larb-id = <16>;
2017 mediatek,smi = <&smi_common>;
2018 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2021 larb17: smi@1a010000 {
2022 compatible = "mediatek,mt8186-smi-larb";
2023 reg = <0 0x1a010000 0 0x1000>;
2024 clocks = <&camsys CLK_CAM_LARB13>,
2025 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
2026 clock-names = "apb", "smi";
2027 mediatek,larb-id = <17>;
2028 mediatek,smi = <&smi_common>;
2029 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2032 camsys_rawa: clock-controller@1a04f000 {
2033 compatible = "mediatek,mt8186-camsys_rawa";
2034 reg = <0 0x1a04f000 0 0x1000>;
2038 camsys_rawb: clock-controller@1a06f000 {
2039 compatible = "mediatek,mt8186-camsys_rawb";
2040 reg = <0 0x1a06f000 0 0x1000>;
2044 mdpsys: clock-controller@1b000000 {
2045 compatible = "mediatek,mt8186-mdpsys";
2046 reg = <0 0x1b000000 0 0x1000>;
2050 larb2: smi@1b002000 {
2051 compatible = "mediatek,mt8186-smi-larb";
2052 reg = <0 0x1b002000 0 0x1000>;
2053 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
2054 clock-names = "apb", "smi";
2055 mediatek,larb-id = <2>;
2056 mediatek,smi = <&smi_common>;
2057 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2060 ipesys: clock-controller@1c000000 {
2061 compatible = "mediatek,mt8186-ipesys";
2062 reg = <0 0x1c000000 0 0x1000>;
2066 larb20: smi@1c00f000 {
2067 compatible = "mediatek,mt8186-smi-larb";
2068 reg = <0 0x1c00f000 0 0x1000>;
2069 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
2070 clock-names = "apb", "smi";
2071 mediatek,larb-id = <20>;
2072 mediatek,smi = <&smi_common>;
2073 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2076 larb19: smi@1c10f000 {
2077 compatible = "mediatek,mt8186-smi-larb";
2078 reg = <0 0x1c10f000 0 0x1000>;
2079 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
2080 clock-names = "apb", "smi";
2081 mediatek,larb-id = <19>;
2082 mediatek,smi = <&smi_common>;
2083 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;