arch/arm64/boot/dts/mediatek/mt8183.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Ben Ho <ben.ho@mediatek.com>
   5  *         Erin Lo <erin.lo@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt8183-clk.h>
   9 #include <dt-bindings/gce/mt8183-gce.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/memory/mt8183-larb-port.h>
  13 #include <dt-bindings/power/mt8183-power.h>
  14 #include <dt-bindings/reset/mt8183-resets.h>
  15 #include <dt-bindings/phy/phy.h>
  16 #include <dt-bindings/thermal/thermal.h>
  17 #include <dt-bindings/pinctrl/mt8183-pinfunc.h>
  18
  19 / {
  20         compatible = "mediatek,mt8183";
  21         interrupt-parent = <&sysirq>;
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         aliases {
  26                 i2c0 = &i2c0;
  27                 i2c1 = &i2c1;
  28                 i2c2 = &i2c2;
  29                 i2c3 = &i2c3;
  30                 i2c4 = &i2c4;
  31                 i2c5 = &i2c5;
  32                 i2c6 = &i2c6;
  33                 i2c7 = &i2c7;
  34                 i2c8 = &i2c8;
  35                 i2c9 = &i2c9;
  36                 i2c10 = &i2c10;
  37                 i2c11 = &i2c11;
  38                 ovl0 = &ovl0;
  39                 ovl-2l0 = &ovl_2l0;
  40                 ovl-2l1 = &ovl_2l1;
  41                 rdma0 = &rdma0;
  42                 rdma1 = &rdma1;
  43         };
  44
  45         cluster0_opp: opp-table-cluster0 {
  46                 compatible = "operating-points-v2";
  47                 opp-shared;
  48                 opp0-793000000 {
  49                         opp-hz = /bits/ 64 <793000000>;
  50                         opp-microvolt = <650000>;
  51                         required-opps = <&opp2_00>;
  52                 };
  53                 opp0-910000000 {
  54                         opp-hz = /bits/ 64 <910000000>;
  55                         opp-microvolt = <687500>;
  56                         required-opps = <&opp2_01>;
  57                 };
  58                 opp0-1014000000 {
  59                         opp-hz = /bits/ 64 <1014000000>;
  60                         opp-microvolt = <718750>;
  61                         required-opps = <&opp2_02>;
  62                 };
  63                 opp0-1131000000 {
  64                         opp-hz = /bits/ 64 <1131000000>;
  65                         opp-microvolt = <756250>;
  66                         required-opps = <&opp2_03>;
  67                 };
  68                 opp0-1248000000 {
  69                         opp-hz = /bits/ 64 <1248000000>;
  70                         opp-microvolt = <800000>;
  71                         required-opps = <&opp2_04>;
  72                 };
  73                 opp0-1326000000 {
  74                         opp-hz = /bits/ 64 <1326000000>;
  75                         opp-microvolt = <818750>;
  76                         required-opps = <&opp2_05>;
  77                 };
  78                 opp0-1417000000 {
  79                         opp-hz = /bits/ 64 <1417000000>;
  80                         opp-microvolt = <850000>;
  81                         required-opps = <&opp2_06>;
  82                 };
  83                 opp0-1508000000 {
  84                         opp-hz = /bits/ 64 <1508000000>;
  85                         opp-microvolt = <868750>;
  86                         required-opps = <&opp2_07>;
  87                 };
  88                 opp0-1586000000 {
  89                         opp-hz = /bits/ 64 <1586000000>;
  90                         opp-microvolt = <893750>;
  91                         required-opps = <&opp2_08>;
  92                 };
  93                 opp0-1625000000 {
  94                         opp-hz = /bits/ 64 <1625000000>;
  95                         opp-microvolt = <906250>;
  96                         required-opps = <&opp2_09>;
  97                 };
  98                 opp0-1677000000 {
  99                         opp-hz = /bits/ 64 <1677000000>;
 100                         opp-microvolt = <931250>;
 101                         required-opps = <&opp2_10>;
 102                 };
 103                 opp0-1716000000 {
 104                         opp-hz = /bits/ 64 <1716000000>;
 105                         opp-microvolt = <943750>;
 106                         required-opps = <&opp2_11>;
 107                 };
 108                 opp0-1781000000 {
 109                         opp-hz = /bits/ 64 <1781000000>;
 110                         opp-microvolt = <975000>;
 111                         required-opps = <&opp2_12>;
 112                 };
 113                 opp0-1846000000 {
 114                         opp-hz = /bits/ 64 <1846000000>;
 115                         opp-microvolt = <1000000>;
 116                         required-opps = <&opp2_13>;
 117                 };
 118                 opp0-1924000000 {
 119                         opp-hz = /bits/ 64 <1924000000>;
 120                         opp-microvolt = <1025000>;
 121                         required-opps = <&opp2_14>;
 122                 };
 123                 opp0-1989000000 {
 124                         opp-hz = /bits/ 64 <1989000000>;
 125                         opp-microvolt = <1050000>;
 126                         required-opps = <&opp2_15>;
 127                 };      };
 128
 129         cluster1_opp: opp-table-cluster1 {
 130                 compatible = "operating-points-v2";
 131                 opp-shared;
 132                 opp1-793000000 {
 133                         opp-hz = /bits/ 64 <793000000>;
 134                         opp-microvolt = <700000>;
 135                         required-opps = <&opp2_00>;
 136                 };
 137                 opp1-910000000 {
 138                         opp-hz = /bits/ 64 <910000000>;
 139                         opp-microvolt = <725000>;
 140                         required-opps = <&opp2_01>;
 141                 };
 142                 opp1-1014000000 {
 143                         opp-hz = /bits/ 64 <1014000000>;
 144                         opp-microvolt = <750000>;
 145                         required-opps = <&opp2_02>;
 146                 };
 147                 opp1-1131000000 {
 148                         opp-hz = /bits/ 64 <1131000000>;
 149                         opp-microvolt = <775000>;
 150                         required-opps = <&opp2_03>;
 151                 };
 152                 opp1-1248000000 {
 153                         opp-hz = /bits/ 64 <1248000000>;
 154                         opp-microvolt = <800000>;
 155                         required-opps = <&opp2_04>;
 156                 };
 157                 opp1-1326000000 {
 158                         opp-hz = /bits/ 64 <1326000000>;
 159                         opp-microvolt = <825000>;
 160                         required-opps = <&opp2_05>;
 161                 };
 162                 opp1-1417000000 {
 163                         opp-hz = /bits/ 64 <1417000000>;
 164                         opp-microvolt = <850000>;
 165                         required-opps = <&opp2_06>;
 166                 };
 167                 opp1-1508000000 {
 168                         opp-hz = /bits/ 64 <1508000000>;
 169                         opp-microvolt = <875000>;
 170                         required-opps = <&opp2_07>;
 171                 };
 172                 opp1-1586000000 {
 173                         opp-hz = /bits/ 64 <1586000000>;
 174                         opp-microvolt = <900000>;
 175                         required-opps = <&opp2_08>;
 176                 };
 177                 opp1-1625000000 {
 178                         opp-hz = /bits/ 64 <1625000000>;
 179                         opp-microvolt = <912500>;
 180                         required-opps = <&opp2_09>;
 181                 };
 182                 opp1-1677000000 {
 183                         opp-hz = /bits/ 64 <1677000000>;
 184                         opp-microvolt = <931250>;
 185                         required-opps = <&opp2_10>;
 186                 };
 187                 opp1-1716000000 {
 188                         opp-hz = /bits/ 64 <1716000000>;
 189                         opp-microvolt = <950000>;
 190                         required-opps = <&opp2_11>;
 191                 };
 192                 opp1-1781000000 {
 193                         opp-hz = /bits/ 64 <1781000000>;
 194                         opp-microvolt = <975000>;
 195                         required-opps = <&opp2_12>;
 196                 };
 197                 opp1-1846000000 {
 198                         opp-hz = /bits/ 64 <1846000000>;
 199                         opp-microvolt = <1000000>;
 200                         required-opps = <&opp2_13>;
 201                 };
 202                 opp1-1924000000 {
 203                         opp-hz = /bits/ 64 <1924000000>;
 204                         opp-microvolt = <1025000>;
 205                         required-opps = <&opp2_14>;
 206                 };
 207                 opp1-1989000000 {
 208                         opp-hz = /bits/ 64 <1989000000>;
 209                         opp-microvolt = <1050000>;
 210                         required-opps = <&opp2_15>;
 211                 };
 212         };
 213
 214         cci_opp: opp-table-cci {
 215                 compatible = "operating-points-v2";
 216                 opp-shared;
 217                 opp2_00: opp-273000000 {
 218                         opp-hz = /bits/ 64 <273000000>;
 219                         opp-microvolt = <650000>;
 220                 };
 221                 opp2_01: opp-338000000 {
 222                         opp-hz = /bits/ 64 <338000000>;
 223                         opp-microvolt = <687500>;
 224                 };
 225                 opp2_02: opp-403000000 {
 226                         opp-hz = /bits/ 64 <403000000>;
 227                         opp-microvolt = <718750>;
 228                 };
 229                 opp2_03: opp-463000000 {
 230                         opp-hz = /bits/ 64 <463000000>;
 231                         opp-microvolt = <756250>;
 232                 };
 233                 opp2_04: opp-546000000 {
 234                         opp-hz = /bits/ 64 <546000000>;
 235                         opp-microvolt = <800000>;
 236                 };
 237                 opp2_05: opp-624000000 {
 238                         opp-hz = /bits/ 64 <624000000>;
 239                         opp-microvolt = <818750>;
 240                 };
 241                 opp2_06: opp-689000000 {
 242                         opp-hz = /bits/ 64 <689000000>;
 243                         opp-microvolt = <850000>;
 244                 };
 245                 opp2_07: opp-767000000 {
 246                         opp-hz = /bits/ 64 <767000000>;
 247                         opp-microvolt = <868750>;
 248                 };
 249                 opp2_08: opp-845000000 {
 250                         opp-hz = /bits/ 64 <845000000>;
 251                         opp-microvolt = <893750>;
 252                 };
 253                 opp2_09: opp-871000000 {
 254                         opp-hz = /bits/ 64 <871000000>;
 255                         opp-microvolt = <906250>;
 256                 };
 257                 opp2_10: opp-923000000 {
 258                         opp-hz = /bits/ 64 <923000000>;
 259                         opp-microvolt = <931250>;
 260                 };
 261                 opp2_11: opp-962000000 {
 262                         opp-hz = /bits/ 64 <962000000>;
 263                         opp-microvolt = <943750>;
 264                 };
 265                 opp2_12: opp-1027000000 {
 266                         opp-hz = /bits/ 64 <1027000000>;
 267                         opp-microvolt = <975000>;
 268                 };
 269                 opp2_13: opp-1092000000 {
 270                         opp-hz = /bits/ 64 <1092000000>;
 271                         opp-microvolt = <1000000>;
 272                 };
 273                 opp2_14: opp-1144000000 {
 274                         opp-hz = /bits/ 64 <1144000000>;
 275                         opp-microvolt = <1025000>;
 276                 };
 277                 opp2_15: opp-1196000000 {
 278                         opp-hz = /bits/ 64 <1196000000>;
 279                         opp-microvolt = <1050000>;
 280                 };
 281         };
 282
 283         cci: cci {
 284                 compatible = "mediatek,mt8183-cci";
 285                 clocks = <&mcucfg CLK_MCU_BUS_SEL>,
 286                          <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 287                 clock-names = "cci", "intermediate";
 288                 operating-points-v2 = <&cci_opp>;
 289         };
 290
 291         cpus {
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294
 295                 cpu-map {
 296                         cluster0 {
 297                                 core0 {
 298                                         cpu = <&cpu0>;
 299                                 };
 300                                 core1 {
 301                                         cpu = <&cpu1>;
 302                                 };
 303                                 core2 {
 304                                         cpu = <&cpu2>;
 305                                 };
 306                                 core3 {
 307                                         cpu = <&cpu3>;
 308                                 };
 309                         };
 310
 311                         cluster1 {
 312                                 core0 {
 313                                         cpu = <&cpu4>;
 314                                 };
 315                                 core1 {
 316                                         cpu = <&cpu5>;
 317                                 };
 318                                 core2 {
 319                                         cpu = <&cpu6>;
 320                                 };
 321                                 core3 {
 322                                         cpu = <&cpu7>;
 323                                 };
 324                         };
 325                 };
 326
 327                 cpu0: cpu@0 {
 328                         device_type = "cpu";
 329                         compatible = "arm,cortex-a53";
 330                         reg = <0x000>;
 331                         enable-method = "psci";
 332                         capacity-dmips-mhz = <741>;
 333                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 334                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 335                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 336                         clock-names = "cpu", "intermediate";
 337                         operating-points-v2 = <&cluster0_opp>;
 338                         dynamic-power-coefficient = <84>;
 339                         #cooling-cells = <2>;
 340                         mediatek,cci = <&cci>;
 341                 };
 342
 343                 cpu1: cpu@1 {
 344                         device_type = "cpu";
 345                         compatible = "arm,cortex-a53";
 346                         reg = <0x001>;
 347                         enable-method = "psci";
 348                         capacity-dmips-mhz = <741>;
 349                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 350                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 351                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 352                         clock-names = "cpu", "intermediate";
 353                         operating-points-v2 = <&cluster0_opp>;
 354                         dynamic-power-coefficient = <84>;
 355                         #cooling-cells = <2>;
 356                         mediatek,cci = <&cci>;
 357                 };
 358
 359                 cpu2: cpu@2 {
 360                         device_type = "cpu";
 361                         compatible = "arm,cortex-a53";
 362                         reg = <0x002>;
 363                         enable-method = "psci";
 364                         capacity-dmips-mhz = <741>;
 365                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 366                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 367                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 368                         clock-names = "cpu", "intermediate";
 369                         operating-points-v2 = <&cluster0_opp>;
 370                         dynamic-power-coefficient = <84>;
 371                         #cooling-cells = <2>;
 372                         mediatek,cci = <&cci>;
 373                 };
 374
 375                 cpu3: cpu@3 {
 376                         device_type = "cpu";
 377                         compatible = "arm,cortex-a53";
 378                         reg = <0x003>;
 379                         enable-method = "psci";
 380                         capacity-dmips-mhz = <741>;
 381                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
 382                         clocks = <&mcucfg CLK_MCU_MP0_SEL>,
 383                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 384                         clock-names = "cpu", "intermediate";
 385                         operating-points-v2 = <&cluster0_opp>;
 386                         dynamic-power-coefficient = <84>;
 387                         #cooling-cells = <2>;
 388                         mediatek,cci = <&cci>;
 389                 };
 390
 391                 cpu4: cpu@100 {
 392                         device_type = "cpu";
 393                         compatible = "arm,cortex-a73";
 394                         reg = <0x100>;
 395                         enable-method = "psci";
 396                         capacity-dmips-mhz = <1024>;
 397                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 398                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 399                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 400                         clock-names = "cpu", "intermediate";
 401                         operating-points-v2 = <&cluster1_opp>;
 402                         dynamic-power-coefficient = <211>;
 403                         #cooling-cells = <2>;
 404                         mediatek,cci = <&cci>;
 405                 };
 406
 407                 cpu5: cpu@101 {
 408                         device_type = "cpu";
 409                         compatible = "arm,cortex-a73";
 410                         reg = <0x101>;
 411                         enable-method = "psci";
 412                         capacity-dmips-mhz = <1024>;
 413                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 414                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 415                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 416                         clock-names = "cpu", "intermediate";
 417                         operating-points-v2 = <&cluster1_opp>;
 418                         dynamic-power-coefficient = <211>;
 419                         #cooling-cells = <2>;
 420                         mediatek,cci = <&cci>;
 421                 };
 422
 423                 cpu6: cpu@102 {
 424                         device_type = "cpu";
 425                         compatible = "arm,cortex-a73";
 426                         reg = <0x102>;
 427                         enable-method = "psci";
 428                         capacity-dmips-mhz = <1024>;
 429                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 430                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 431                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 432                         clock-names = "cpu", "intermediate";
 433                         operating-points-v2 = <&cluster1_opp>;
 434                         dynamic-power-coefficient = <211>;
 435                         #cooling-cells = <2>;
 436                         mediatek,cci = <&cci>;
 437                 };
 438
 439                 cpu7: cpu@103 {
 440                         device_type = "cpu";
 441                         compatible = "arm,cortex-a73";
 442                         reg = <0x103>;
 443                         enable-method = "psci";
 444                         capacity-dmips-mhz = <1024>;
 445                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
 446                         clocks = <&mcucfg CLK_MCU_MP2_SEL>,
 447                                  <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
 448                         clock-names = "cpu", "intermediate";
 449                         operating-points-v2 = <&cluster1_opp>;
 450                         dynamic-power-coefficient = <211>;
 451                         #cooling-cells = <2>;
 452                         mediatek,cci = <&cci>;
 453                 };
 454
 455                 idle-states {
 456                         entry-method = "psci";
 457
 458                         CPU_SLEEP: cpu-sleep {
 459                                 compatible = "arm,idle-state";
 460                                 local-timer-stop;
 461                                 arm,psci-suspend-param = <0x00010001>;
 462                                 entry-latency-us = <200>;
 463                                 exit-latency-us = <200>;
 464                                 min-residency-us = <800>;
 465                         };
 466
 467                         CLUSTER_SLEEP0: cluster-sleep-0 {
 468                                 compatible = "arm,idle-state";
 469                                 local-timer-stop;
 470                                 arm,psci-suspend-param = <0x01010001>;
 471                                 entry-latency-us = <250>;
 472                                 exit-latency-us = <400>;
 473                                 min-residency-us = <1000>;
 474                         };
 475                         CLUSTER_SLEEP1: cluster-sleep-1 {
 476                                 compatible = "arm,idle-state";
 477                                 local-timer-stop;
 478                                 arm,psci-suspend-param = <0x01010001>;
 479                                 entry-latency-us = <250>;
 480                                 exit-latency-us = <400>;
 481                                 min-residency-us = <1300>;
 482                         };
 483                 };
 484         };
 485
 486         gpu_opp_table: opp-table-0 {
 487                 compatible = "operating-points-v2";
 488                 opp-shared;
 489
 490                 opp-300000000 {
 491                         opp-hz = /bits/ 64 <300000000>;
 492                         opp-microvolt = <625000>, <850000>;
 493                 };
 494
 495                 opp-320000000 {
 496                         opp-hz = /bits/ 64 <320000000>;
 497                         opp-microvolt = <631250>, <850000>;
 498                 };
 499
 500                 opp-340000000 {
 501                         opp-hz = /bits/ 64 <340000000>;
 502                         opp-microvolt = <637500>, <850000>;
 503                 };
 504
 505                 opp-360000000 {
 506                         opp-hz = /bits/ 64 <360000000>;
 507                         opp-microvolt = <643750>, <850000>;
 508                 };
 509
 510                 opp-380000000 {
 511                         opp-hz = /bits/ 64 <380000000>;
 512                         opp-microvolt = <650000>, <850000>;
 513                 };
 514
 515                 opp-400000000 {
 516                         opp-hz = /bits/ 64 <400000000>;
 517                         opp-microvolt = <656250>, <850000>;
 518                 };
 519
 520                 opp-420000000 {
 521                         opp-hz = /bits/ 64 <420000000>;
 522                         opp-microvolt = <662500>, <850000>;
 523                 };
 524
 525                 opp-460000000 {
 526                         opp-hz = /bits/ 64 <460000000>;
 527                         opp-microvolt = <675000>, <850000>;
 528                 };
 529
 530                 opp-500000000 {
 531                         opp-hz = /bits/ 64 <500000000>;
 532                         opp-microvolt = <687500>, <850000>;
 533                 };
 534
 535                 opp-540000000 {
 536                         opp-hz = /bits/ 64 <540000000>;
 537                         opp-microvolt = <700000>, <850000>;
 538                 };
 539
 540                 opp-580000000 {
 541                         opp-hz = /bits/ 64 <580000000>;
 542                         opp-microvolt = <712500>, <850000>;
 543                 };
 544
 545                 opp-620000000 {
 546                         opp-hz = /bits/ 64 <620000000>;
 547                         opp-microvolt = <725000>, <850000>;
 548                 };
 549
 550                 opp-653000000 {
 551                         opp-hz = /bits/ 64 <653000000>;
 552                         opp-microvolt = <743750>, <850000>;
 553                 };
 554
 555                 opp-698000000 {
 556                         opp-hz = /bits/ 64 <698000000>;
 557                         opp-microvolt = <768750>, <868750>;
 558                 };
 559
 560                 opp-743000000 {
 561                         opp-hz = /bits/ 64 <743000000>;
 562                         opp-microvolt = <793750>, <893750>;
 563                 };
 564
 565                 opp-800000000 {
 566                         opp-hz = /bits/ 64 <800000000>;
 567                         opp-microvolt = <825000>, <925000>;
 568                 };
 569         };
 570
 571         pmu-a53 {
 572                 compatible = "arm,cortex-a53-pmu";
 573                 interrupt-parent = <&gic>;
 574                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 575         };
 576
 577         pmu-a73 {
 578                 compatible = "arm,cortex-a73-pmu";
 579                 interrupt-parent = <&gic>;
 580                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 581         };
 582
 583         psci {
 584                 compatible = "arm,psci-1.0";
 585                 method = "smc";
 586         };
 587
 588         clk26m: oscillator {
 589                 compatible = "fixed-clock";
 590                 #clock-cells = <0>;
 591                 clock-frequency = <26000000>;
 592                 clock-output-names = "clk26m";
 593         };
 594
 595         timer {
 596                 compatible = "arm,armv8-timer";
 597                 interrupt-parent = <&gic>;
 598                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 599                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 600                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 601                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 602         };
 603
 604         soc {
 605                 #address-cells = <2>;
 606                 #size-cells = <2>;
 607                 compatible = "simple-bus";
 608                 ranges;
 609
 610                 soc_data: efuse@8000000 {
 611                         compatible = "mediatek,mt8183-efuse",
 612                                      "mediatek,efuse";
 613                         reg = <0 0x08000000 0 0x0010>;
 614                         #address-cells = <1>;
 615                         #size-cells = <1>;
 616                         status = "disabled";
 617                 };
 618
 619                 gic: interrupt-controller@c000000 {
 620                         compatible = "arm,gic-v3";
 621                         #interrupt-cells = <4>;
 622                         interrupt-parent = <&gic>;
 623                         interrupt-controller;
 624                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 625                               <0 0x0c100000 0 0x200000>, /* GICR */
 626                               <0 0x0c400000 0 0x2000>,   /* GICC */
 627                               <0 0x0c410000 0 0x1000>,   /* GICH */
 628                               <0 0x0c420000 0 0x2000>;   /* GICV */
 629
 630                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 631                         ppi-partitions {
 632                                 ppi_cluster0: interrupt-partition-0 {
 633                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 634                                 };
 635                                 ppi_cluster1: interrupt-partition-1 {
 636                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 637                                 };
 638                         };
 639                 };
 640
 641                 mcucfg: syscon@c530000 {
 642                         compatible = "mediatek,mt8183-mcucfg", "syscon";
 643                         reg = <0 0x0c530000 0 0x1000>;
 644                         #clock-cells = <1>;
 645                 };
 646
 647                 sysirq: interrupt-controller@c530a80 {
 648                         compatible = "mediatek,mt8183-sysirq",
 649                                      "mediatek,mt6577-sysirq";
 650                         interrupt-controller;
 651                         #interrupt-cells = <3>;
 652                         interrupt-parent = <&gic>;
 653                         reg = <0 0x0c530a80 0 0x50>;
 654                 };
 655
 656                 cpu_debug0: cpu-debug@d410000 {
 657                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 658                         reg = <0x0 0xd410000 0x0 0x1000>;
 659                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 660                         clock-names = "apb_pclk";
 661                         cpu = <&cpu0>;
 662                 };
 663
 664                 cpu_debug1: cpu-debug@d510000 {
 665                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 666                         reg = <0x0 0xd510000 0x0 0x1000>;
 667                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 668                         clock-names = "apb_pclk";
 669                         cpu = <&cpu1>;
 670                 };
 671
 672                 cpu_debug2: cpu-debug@d610000 {
 673                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 674                         reg = <0x0 0xd610000 0x0 0x1000>;
 675                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 676                         clock-names = "apb_pclk";
 677                         cpu = <&cpu2>;
 678                 };
 679
 680                 cpu_debug3: cpu-debug@d710000 {
 681                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 682                         reg = <0x0 0xd710000 0x0 0x1000>;
 683                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 684                         clock-names = "apb_pclk";
 685                         cpu = <&cpu3>;
 686                 };
 687
 688                 cpu_debug4: cpu-debug@d810000 {
 689                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 690                         reg = <0x0 0xd810000 0x0 0x1000>;
 691                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 692                         clock-names = "apb_pclk";
 693                         cpu = <&cpu4>;
 694                 };
 695
 696                 cpu_debug5: cpu-debug@d910000 {
 697                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 698                         reg = <0x0 0xd910000 0x0 0x1000>;
 699                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 700                         clock-names = "apb_pclk";
 701                         cpu = <&cpu5>;
 702                 };
 703
 704                 cpu_debug6: cpu-debug@da10000 {
 705                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 706                         reg = <0x0 0xda10000 0x0 0x1000>;
 707                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 708                         clock-names = "apb_pclk";
 709                         cpu = <&cpu6>;
 710                 };
 711
 712                 cpu_debug7: cpu-debug@db10000 {
 713                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 714                         reg = <0x0 0xdb10000 0x0 0x1000>;
 715                         clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
 716                         clock-names = "apb_pclk";
 717                         cpu = <&cpu7>;
 718                 };
 719
 720                 topckgen: syscon@10000000 {
 721                         compatible = "mediatek,mt8183-topckgen", "syscon";
 722                         reg = <0 0x10000000 0 0x1000>;
 723                         #clock-cells = <1>;
 724                 };
 725
 726                 infracfg: syscon@10001000 {
 727                         compatible = "mediatek,mt8183-infracfg", "syscon";
 728                         reg = <0 0x10001000 0 0x1000>;
 729                         #clock-cells = <1>;
 730                         #reset-cells = <1>;
 731                 };
 732
 733                 pericfg: syscon@10003000 {
 734                         compatible = "mediatek,mt8183-pericfg", "syscon";
 735                         reg = <0 0x10003000 0 0x1000>;
 736                         #clock-cells = <1>;
 737                 };
 738
 739                 pio: pinctrl@10005000 {
 740                         compatible = "mediatek,mt8183-pinctrl";
 741                         reg = <0 0x10005000 0 0x1000>,
 742                               <0 0x11f20000 0 0x1000>,
 743                               <0 0x11e80000 0 0x1000>,
 744                               <0 0x11e70000 0 0x1000>,
 745                               <0 0x11e90000 0 0x1000>,
 746                               <0 0x11d30000 0 0x1000>,
 747                               <0 0x11d20000 0 0x1000>,
 748                               <0 0x11c50000 0 0x1000>,
 749                               <0 0x11f30000 0 0x1000>,
 750                               <0 0x1000b000 0 0x1000>;
 751                         reg-names = "iocfg0", "iocfg1", "iocfg2",
 752                                     "iocfg3", "iocfg4", "iocfg5",
 753                                     "iocfg6", "iocfg7", "iocfg8",
 754                                     "eint";
 755                         gpio-controller;
 756                         #gpio-cells = <2>;
 757                         gpio-ranges = <&pio 0 0 192>;
 758                         interrupt-controller;
 759                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 760                         #interrupt-cells = <2>;
 761                 };
 762
 763                 scpsys: syscon@10006000 {
 764                         compatible = "syscon", "simple-mfd";
 765                         reg = <0 0x10006000 0 0x1000>;
 766                         #power-domain-cells = <1>;
 767
 768                         /* System Power Manager */
 769                         spm: power-controller {
 770                                 compatible = "mediatek,mt8183-power-controller";
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773                                 #power-domain-cells = <1>;
 774
 775                                 /* power domain of the SoC */
 776                                 power-domain@MT8183_POWER_DOMAIN_AUDIO {
 777                                         reg = <MT8183_POWER_DOMAIN_AUDIO>;
 778                                         clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
 779                                                  <&infracfg CLK_INFRA_AUDIO>,
 780                                                  <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
 781                                         clock-names = "audio", "audio1", "audio2";
 782                                         #power-domain-cells = <0>;
 783                                 };
 784
 785                                 power-domain@MT8183_POWER_DOMAIN_CONN {
 786                                         reg = <MT8183_POWER_DOMAIN_CONN>;
 787                                         mediatek,infracfg = <&infracfg>;
 788                                         #power-domain-cells = <0>;
 789                                 };
 790
 791                                 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
 792                                         reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
 793                                         clocks = <&topckgen CLK_TOP_MUX_MFG>;
 794                                         clock-names = "mfg";
 795                                         #address-cells = <1>;
 796                                         #size-cells = <0>;
 797                                         #power-domain-cells = <1>;
 798
 799                                         mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
 800                                                 reg = <MT8183_POWER_DOMAIN_MFG>;
 801                                                 #address-cells = <1>;
 802                                                 #size-cells = <0>;
 803                                                 #power-domain-cells = <1>;
 804
 805                                                 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
 806                                                         reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
 807                                                         #power-domain-cells = <0>;
 808                                                 };
 809
 810                                                 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
 811                                                         reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
 812                                                         #power-domain-cells = <0>;
 813                                                 };
 814
 815                                                 power-domain@MT8183_POWER_DOMAIN_MFG_2D {
 816                                                         reg = <MT8183_POWER_DOMAIN_MFG_2D>;
 817                                                         mediatek,infracfg = <&infracfg>;
 818                                                         #power-domain-cells = <0>;
 819                                                 };
 820                                         };
 821                                 };
 822
 823                                 power-domain@MT8183_POWER_DOMAIN_DISP {
 824                                         reg = <MT8183_POWER_DOMAIN_DISP>;
 825                                         clocks = <&topckgen CLK_TOP_MUX_MM>,
 826                                                  <&mmsys CLK_MM_SMI_COMMON>,
 827                                                  <&mmsys CLK_MM_SMI_LARB0>,
 828                                                  <&mmsys CLK_MM_SMI_LARB1>,
 829                                                  <&mmsys CLK_MM_GALS_COMM0>,
 830                                                  <&mmsys CLK_MM_GALS_COMM1>,
 831                                                  <&mmsys CLK_MM_GALS_CCU2MM>,
 832                                                  <&mmsys CLK_MM_GALS_IPU12MM>,
 833                                                  <&mmsys CLK_MM_GALS_IMG2MM>,
 834                                                  <&mmsys CLK_MM_GALS_CAM2MM>,
 835                                                  <&mmsys CLK_MM_GALS_IPU2MM>;
 836                                         clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
 837                                                       "mm-4", "mm-5", "mm-6", "mm-7",
 838                                                       "mm-8", "mm-9";
 839                                         mediatek,infracfg = <&infracfg>;
 840                                         mediatek,smi = <&smi_common>;
 841                                         #address-cells = <1>;
 842                                         #size-cells = <0>;
 843                                         #power-domain-cells = <1>;
 844
 845                                         power-domain@MT8183_POWER_DOMAIN_CAM {
 846                                                 reg = <MT8183_POWER_DOMAIN_CAM>;
 847                                                 clocks = <&topckgen CLK_TOP_MUX_CAM>,
 848                                                          <&camsys CLK_CAM_LARB6>,
 849                                                          <&camsys CLK_CAM_LARB3>,
 850                                                          <&camsys CLK_CAM_SENINF>,
 851                                                          <&camsys CLK_CAM_CAMSV0>,
 852                                                          <&camsys CLK_CAM_CAMSV1>,
 853                                                          <&camsys CLK_CAM_CAMSV2>,
 854                                                          <&camsys CLK_CAM_CCU>;
 855                                                 clock-names = "cam", "cam-0", "cam-1",
 856                                                               "cam-2", "cam-3", "cam-4",
 857                                                               "cam-5", "cam-6";
 858                                                 mediatek,infracfg = <&infracfg>;
 859                                                 mediatek,smi = <&smi_common>;
 860                                                 #power-domain-cells = <0>;
 861                                         };
 862
 863                                         power-domain@MT8183_POWER_DOMAIN_ISP {
 864                                                 reg = <MT8183_POWER_DOMAIN_ISP>;
 865                                                 clocks = <&topckgen CLK_TOP_MUX_IMG>,
 866                                                          <&imgsys CLK_IMG_LARB5>,
 867                                                          <&imgsys CLK_IMG_LARB2>;
 868                                                 clock-names = "isp", "isp-0", "isp-1";
 869                                                 mediatek,infracfg = <&infracfg>;
 870                                                 mediatek,smi = <&smi_common>;
 871                                                 #power-domain-cells = <0>;
 872                                         };
 873
 874                                         power-domain@MT8183_POWER_DOMAIN_VDEC {
 875                                                 reg = <MT8183_POWER_DOMAIN_VDEC>;
 876                                                 mediatek,smi = <&smi_common>;
 877                                                 #power-domain-cells = <0>;
 878                                         };
 879
 880                                         power-domain@MT8183_POWER_DOMAIN_VENC {
 881                                                 reg = <MT8183_POWER_DOMAIN_VENC>;
 882                                                 mediatek,smi = <&smi_common>;
 883                                                 #power-domain-cells = <0>;
 884                                         };
 885
 886                                         power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
 887                                                 reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
 888                                                 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
 889                                                          <&topckgen CLK_TOP_MUX_DSP>,
 890                                                          <&ipu_conn CLK_IPU_CONN_IPU>,
 891                                                          <&ipu_conn CLK_IPU_CONN_AHB>,
 892                                                          <&ipu_conn CLK_IPU_CONN_AXI>,
 893                                                          <&ipu_conn CLK_IPU_CONN_ISP>,
 894                                                          <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
 895                                                          <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
 896                                                 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
 897                                                               "vpu-2", "vpu-3", "vpu-4", "vpu-5";
 898                                                 mediatek,infracfg = <&infracfg>;
 899                                                 mediatek,smi = <&smi_common>;
 900                                                 #address-cells = <1>;
 901                                                 #size-cells = <0>;
 902                                                 #power-domain-cells = <1>;
 903
 904                                                 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
 905                                                         reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
 906                                                         clocks = <&topckgen CLK_TOP_MUX_DSP1>;
 907                                                         clock-names = "vpu2";
 908                                                         mediatek,infracfg = <&infracfg>;
 909                                                         #power-domain-cells = <0>;
 910                                                 };
 911
 912                                                 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
 913                                                         reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
 914                                                         clocks = <&topckgen CLK_TOP_MUX_DSP2>;
 915                                                         clock-names = "vpu3";
 916                                                         mediatek,infracfg = <&infracfg>;
 917                                                         #power-domain-cells = <0>;
 918                                                 };
 919                                         };
 920                                 };
 921                         };
 922                 };
 923
 924                 watchdog: watchdog@10007000 {
 925                         compatible = "mediatek,mt8183-wdt";
 926                         reg = <0 0x10007000 0 0x100>;
 927                         #reset-cells = <1>;
 928                 };
 929
 930                 apmixedsys: syscon@1000c000 {
 931                         compatible = "mediatek,mt8183-apmixedsys", "syscon";
 932                         reg = <0 0x1000c000 0 0x1000>;
 933                         #clock-cells = <1>;
 934                 };
 935
 936                 pwrap: pwrap@1000d000 {
 937                         compatible = "mediatek,mt8183-pwrap";
 938                         reg = <0 0x1000d000 0 0x1000>;
 939                         reg-names = "pwrap";
 940                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 941                         clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
 942                                  <&infracfg CLK_INFRA_PMIC_AP>;
 943                         clock-names = "spi", "wrap";
 944                 };
 945
 946                 scp: scp@10500000 {
 947                         compatible = "mediatek,mt8183-scp";
 948                         reg = <0 0x10500000 0 0x80000>,
 949                               <0 0x105c0000 0 0x19080>;
 950                         reg-names = "sram", "cfg";
 951                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 952                         clocks = <&infracfg CLK_INFRA_SCPSYS>;
 953                         clock-names = "main";
 954                         memory-region = <&scp_mem_reserved>;
 955                         status = "disabled";
 956                 };
 957
 958                 systimer: timer@10017000 {
 959                         compatible = "mediatek,mt8183-timer",
 960                                      "mediatek,mt6765-timer";
 961                         reg = <0 0x10017000 0 0x1000>;
 962                         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 963                         clocks = <&topckgen CLK_TOP_CLK13M>;
 964                         clock-names = "clk13m";
 965                 };
 966
 967                 iommu: iommu@10205000 {
 968                         compatible = "mediatek,mt8183-m4u";
 969                         reg = <0 0x10205000 0 0x1000>;
 970                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
 971                         mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
 972                                          <&larb4>, <&larb5>, <&larb6>;
 973                         #iommu-cells = <1>;
 974                 };
 975
 976                 gce: mailbox@10238000 {
 977                         compatible = "mediatek,mt8183-gce";
 978                         reg = <0 0x10238000 0 0x4000>;
 979                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
 980                         #mbox-cells = <2>;
 981                         clocks = <&infracfg CLK_INFRA_GCE>;
 982                         clock-names = "gce";
 983                 };
 984
 985                 auxadc: auxadc@11001000 {
 986                         compatible = "mediatek,mt8183-auxadc",
 987                                      "mediatek,mt8173-auxadc";
 988                         reg = <0 0x11001000 0 0x1000>;
 989                         clocks = <&infracfg CLK_INFRA_AUXADC>;
 990                         clock-names = "main";
 991                         #io-channel-cells = <1>;
 992                         status = "disabled";
 993                 };
 994
 995                 uart0: serial@11002000 {
 996                         compatible = "mediatek,mt8183-uart",
 997                                      "mediatek,mt6577-uart";
 998                         reg = <0 0x11002000 0 0x1000>;
 999                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
1000                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
1001                         clock-names = "baud", "bus";
1002                         status = "disabled";
1003                 };
1004
1005                 uart1: serial@11003000 {
1006                         compatible = "mediatek,mt8183-uart",
1007                                      "mediatek,mt6577-uart";
1008                         reg = <0 0x11003000 0 0x1000>;
1009                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
1010                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
1011                         clock-names = "baud", "bus";
1012                         status = "disabled";
1013                 };
1014
1015                 uart2: serial@11004000 {
1016                         compatible = "mediatek,mt8183-uart",
1017                                      "mediatek,mt6577-uart";
1018                         reg = <0 0x11004000 0 0x1000>;
1019                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
1020                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
1021                         clock-names = "baud", "bus";
1022                         status = "disabled";
1023                 };
1024
1025                 i2c6: i2c@11005000 {
1026                         compatible = "mediatek,mt8183-i2c";
1027                         reg = <0 0x11005000 0 0x1000>,
1028                               <0 0x11000600 0 0x80>;
1029                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
1030                         clocks = <&infracfg CLK_INFRA_I2C6>,
1031                                  <&infracfg CLK_INFRA_AP_DMA>;
1032                         clock-names = "main", "dma";
1033                         clock-div = <1>;
1034                         #address-cells = <1>;
1035                         #size-cells = <0>;
1036                         status = "disabled";
1037                 };
1038
1039                 i2c0: i2c@11007000 {
1040                         compatible = "mediatek,mt8183-i2c";
1041                         reg = <0 0x11007000 0 0x1000>,
1042                               <0 0x11000080 0 0x80>;
1043                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
1044                         clocks = <&infracfg CLK_INFRA_I2C0>,
1045                                  <&infracfg CLK_INFRA_AP_DMA>;
1046                         clock-names = "main", "dma";
1047                         clock-div = <1>;
1048                         #address-cells = <1>;
1049                         #size-cells = <0>;
1050                         status = "disabled";
1051                 };
1052
1053                 i2c4: i2c@11008000 {
1054                         compatible = "mediatek,mt8183-i2c";
1055                         reg = <0 0x11008000 0 0x1000>,
1056                               <0 0x11000100 0 0x80>;
1057                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
1058                         clocks = <&infracfg CLK_INFRA_I2C1>,
1059                                  <&infracfg CLK_INFRA_AP_DMA>,
1060                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
1061                         clock-names = "main", "dma","arb";
1062                         clock-div = <1>;
1063                         #address-cells = <1>;
1064                         #size-cells = <0>;
1065                         status = "disabled";
1066                 };
1067
1068                 i2c2: i2c@11009000 {
1069                         compatible = "mediatek,mt8183-i2c";
1070                         reg = <0 0x11009000 0 0x1000>,
1071                               <0 0x11000280 0 0x80>;
1072                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
1073                         clocks = <&infracfg CLK_INFRA_I2C2>,
1074                                  <&infracfg CLK_INFRA_AP_DMA>,
1075                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
1076                         clock-names = "main", "dma", "arb";
1077                         clock-div = <1>;
1078                         #address-cells = <1>;
1079                         #size-cells = <0>;
1080                         status = "disabled";
1081                 };
1082
1083                 spi0: spi@1100a000 {
1084                         compatible = "mediatek,mt8183-spi";
1085                         #address-cells = <1>;
1086                         #size-cells = <0>;
1087                         reg = <0 0x1100a000 0 0x1000>;
1088                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
1089                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1090                                  <&topckgen CLK_TOP_MUX_SPI>,
1091                                  <&infracfg CLK_INFRA_SPI0>;
1092                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1093                         status = "disabled";
1094                 };
1095
1096                 svs: svs@1100b000 {
1097                         compatible = "mediatek,mt8183-svs";
1098                         reg = <0 0x1100b000 0 0x1000>;
1099                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
1100                         clocks = <&infracfg CLK_INFRA_THERM>;
1101                         clock-names = "main";
1102                         nvmem-cells = <&svs_calibration>,
1103                                       <&thermal_calibration>;
1104                         nvmem-cell-names = "svs-calibration-data",
1105                                            "t-calibration-data";
1106                 };
1107
1108                 thermal: thermal@1100b000 {
1109                         #thermal-sensor-cells = <1>;
1110                         compatible = "mediatek,mt8183-thermal";
1111                         reg = <0 0x1100b000 0 0x1000>;
1112                         clocks = <&infracfg CLK_INFRA_THERM>,
1113                                  <&infracfg CLK_INFRA_AUXADC>;
1114                         clock-names = "therm", "auxadc";
1115                         resets = <&infracfg  MT8183_INFRACFG_AO_THERM_SW_RST>;
1116                         interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
1117                         mediatek,auxadc = <&auxadc>;
1118                         mediatek,apmixedsys = <&apmixedsys>;
1119                         nvmem-cells = <&thermal_calibration>;
1120                         nvmem-cell-names = "calibration-data";
1121                 };
1122
1123                 thermal_zones: thermal-zones {
1124                         cpu_thermal: cpu-thermal {
1125                                 polling-delay-passive = <100>;
1126                                 polling-delay = <500>;
1127                                 thermal-sensors = <&thermal 0>;
1128                                 sustainable-power = <5000>;
1129
1130                                 trips {
1131                                         threshold: trip-point0 {
1132                                                 temperature = <68000>;
1133                                                 hysteresis = <2000>;
1134                                                 type = "passive";
1135                                         };
1136
1137                                         target: trip-point1 {
1138                                                 temperature = <80000>;
1139                                                 hysteresis = <2000>;
1140                                                 type = "passive";
1141                                         };
1142
1143                                         cpu_crit: cpu-crit {
1144                                                 temperature = <115000>;
1145                                                 hysteresis = <2000>;
1146                                                 type = "critical";
1147                                         };
1148                                 };
1149
1150                                 cooling-maps {
1151                                         map0 {
1152                                                 trip = <&target>;
1153                                                 cooling-device = <&cpu0
1154                                                         THERMAL_NO_LIMIT
1155                                                         THERMAL_NO_LIMIT>,
1156                                                                  <&cpu1
1157                                                         THERMAL_NO_LIMIT
1158                                                         THERMAL_NO_LIMIT>,
1159                                                                  <&cpu2
1160                                                         THERMAL_NO_LIMIT
1161                                                         THERMAL_NO_LIMIT>,
1162                                                                  <&cpu3
1163                                                         THERMAL_NO_LIMIT
1164                                                         THERMAL_NO_LIMIT>;
1165                                                 contribution = <3072>;
1166                                         };
1167                                         map1 {
1168                                                 trip = <&target>;
1169                                                 cooling-device = <&cpu4
1170                                                         THERMAL_NO_LIMIT
1171                                                         THERMAL_NO_LIMIT>,
1172                                                                  <&cpu5
1173                                                         THERMAL_NO_LIMIT
1174                                                         THERMAL_NO_LIMIT>,
1175                                                                  <&cpu6
1176                                                         THERMAL_NO_LIMIT
1177                                                         THERMAL_NO_LIMIT>,
1178                                                                  <&cpu7
1179                                                         THERMAL_NO_LIMIT
1180                                                         THERMAL_NO_LIMIT>;
1181                                                 contribution = <1024>;
1182                                         };
1183                                 };
1184                         };
1185
1186                         /* The tzts1 ~ tzts6 don't need to polling */
1187                         /* The tzts1 ~ tzts6 don't need to thermal throttle */
1188
1189                         tzts1: tzts1 {
1190                                 polling-delay-passive = <0>;
1191                                 polling-delay = <0>;
1192                                 thermal-sensors = <&thermal 1>;
1193                                 sustainable-power = <5000>;
1194                                 trips {};
1195                                 cooling-maps {};
1196                         };
1197
1198                         tzts2: tzts2 {
1199                                 polling-delay-passive = <0>;
1200                                 polling-delay = <0>;
1201                                 thermal-sensors = <&thermal 2>;
1202                                 sustainable-power = <5000>;
1203                                 trips {};
1204                                 cooling-maps {};
1205                         };
1206
1207                         tzts3: tzts3 {
1208                                 polling-delay-passive = <0>;
1209                                 polling-delay = <0>;
1210                                 thermal-sensors = <&thermal 3>;
1211                                 sustainable-power = <5000>;
1212                                 trips {};
1213                                 cooling-maps {};
1214                         };
1215
1216                         tzts4: tzts4 {
1217                                 polling-delay-passive = <0>;
1218                                 polling-delay = <0>;
1219                                 thermal-sensors = <&thermal 4>;
1220                                 sustainable-power = <5000>;
1221                                 trips {};
1222                                 cooling-maps {};
1223                         };
1224
1225                         tzts5: tzts5 {
1226                                 polling-delay-passive = <0>;
1227                                 polling-delay = <0>;
1228                                 thermal-sensors = <&thermal 5>;
1229                                 sustainable-power = <5000>;
1230                                 trips {};
1231                                 cooling-maps {};
1232                         };
1233
1234                         tztsABB: tztsABB {
1235                                 polling-delay-passive = <0>;
1236                                 polling-delay = <0>;
1237                                 thermal-sensors = <&thermal 6>;
1238                                 sustainable-power = <5000>;
1239                                 trips {};
1240                                 cooling-maps {};
1241                         };
1242                 };
1243
1244                 pwm0: pwm@1100e000 {
1245                         compatible = "mediatek,mt8183-disp-pwm";
1246                         reg = <0 0x1100e000 0 0x1000>;
1247                         interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
1248                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1249                         #pwm-cells = <2>;
1250                         clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
1251                                         <&infracfg CLK_INFRA_DISP_PWM>;
1252                         clock-names = "main", "mm";
1253                 };
1254
1255                 pwm1: pwm@11006000 {
1256                         compatible = "mediatek,mt8183-pwm";
1257                         reg = <0 0x11006000 0 0x1000>;
1258                         #pwm-cells = <2>;
1259                         clocks = <&infracfg CLK_INFRA_PWM>,
1260                                  <&infracfg CLK_INFRA_PWM_HCLK>,
1261                                  <&infracfg CLK_INFRA_PWM1>,
1262                                  <&infracfg CLK_INFRA_PWM2>,
1263                                  <&infracfg CLK_INFRA_PWM3>,
1264                                  <&infracfg CLK_INFRA_PWM4>;
1265                         clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
1266                                       "pwm4";
1267                 };
1268
1269                 i2c3: i2c@1100f000 {
1270                         compatible = "mediatek,mt8183-i2c";
1271                         reg = <0 0x1100f000 0 0x1000>,
1272                               <0 0x11000400 0 0x80>;
1273                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
1274                         clocks = <&infracfg CLK_INFRA_I2C3>,
1275                                  <&infracfg CLK_INFRA_AP_DMA>;
1276                         clock-names = "main", "dma";
1277                         clock-div = <1>;
1278                         #address-cells = <1>;
1279                         #size-cells = <0>;
1280                         status = "disabled";
1281                 };
1282
1283                 spi1: spi@11010000 {
1284                         compatible = "mediatek,mt8183-spi";
1285                         #address-cells = <1>;
1286                         #size-cells = <0>;
1287                         reg = <0 0x11010000 0 0x1000>;
1288                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
1289                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1290                                  <&topckgen CLK_TOP_MUX_SPI>,
1291                                  <&infracfg CLK_INFRA_SPI1>;
1292                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1293                         status = "disabled";
1294                 };
1295
1296                 i2c1: i2c@11011000 {
1297                         compatible = "mediatek,mt8183-i2c";
1298                         reg = <0 0x11011000 0 0x1000>,
1299                               <0 0x11000480 0 0x80>;
1300                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
1301                         clocks = <&infracfg CLK_INFRA_I2C4>,
1302                                  <&infracfg CLK_INFRA_AP_DMA>;
1303                         clock-names = "main", "dma";
1304                         clock-div = <1>;
1305                         #address-cells = <1>;
1306                         #size-cells = <0>;
1307                         status = "disabled";
1308                 };
1309
1310                 spi2: spi@11012000 {
1311                         compatible = "mediatek,mt8183-spi";
1312                         #address-cells = <1>;
1313                         #size-cells = <0>;
1314                         reg = <0 0x11012000 0 0x1000>;
1315                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
1316                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1317                                  <&topckgen CLK_TOP_MUX_SPI>,
1318                                  <&infracfg CLK_INFRA_SPI2>;
1319                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1320                         status = "disabled";
1321                 };
1322
1323                 spi3: spi@11013000 {
1324                         compatible = "mediatek,mt8183-spi";
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327                         reg = <0 0x11013000 0 0x1000>;
1328                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
1329                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1330                                  <&topckgen CLK_TOP_MUX_SPI>,
1331                                  <&infracfg CLK_INFRA_SPI3>;
1332                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1333                         status = "disabled";
1334                 };
1335
1336                 i2c9: i2c@11014000 {
1337                         compatible = "mediatek,mt8183-i2c";
1338                         reg = <0 0x11014000 0 0x1000>,
1339                               <0 0x11000180 0 0x80>;
1340                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
1341                         clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
1342                                  <&infracfg CLK_INFRA_AP_DMA>,
1343                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
1344                         clock-names = "main", "dma", "arb";
1345                         clock-div = <1>;
1346                         #address-cells = <1>;
1347                         #size-cells = <0>;
1348                         status = "disabled";
1349                 };
1350
1351                 i2c10: i2c@11015000 {
1352                         compatible = "mediatek,mt8183-i2c";
1353                         reg = <0 0x11015000 0 0x1000>,
1354                               <0 0x11000300 0 0x80>;
1355                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
1356                         clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
1357                                  <&infracfg CLK_INFRA_AP_DMA>,
1358                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
1359                         clock-names = "main", "dma", "arb";
1360                         clock-div = <1>;
1361                         #address-cells = <1>;
1362                         #size-cells = <0>;
1363                         status = "disabled";
1364                 };
1365
1366                 i2c5: i2c@11016000 {
1367                         compatible = "mediatek,mt8183-i2c";
1368                         reg = <0 0x11016000 0 0x1000>,
1369                               <0 0x11000500 0 0x80>;
1370                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
1371                         clocks = <&infracfg CLK_INFRA_I2C5>,
1372                                  <&infracfg CLK_INFRA_AP_DMA>,
1373                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
1374                         clock-names = "main", "dma", "arb";
1375                         clock-div = <1>;
1376                         #address-cells = <1>;
1377                         #size-cells = <0>;
1378                         status = "disabled";
1379                 };
1380
1381                 i2c11: i2c@11017000 {
1382                         compatible = "mediatek,mt8183-i2c";
1383                         reg = <0 0x11017000 0 0x1000>,
1384                               <0 0x11000580 0 0x80>;
1385                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
1386                         clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
1387                                  <&infracfg CLK_INFRA_AP_DMA>,
1388                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
1389                         clock-names = "main", "dma", "arb";
1390                         clock-div = <1>;
1391                         #address-cells = <1>;
1392                         #size-cells = <0>;
1393                         status = "disabled";
1394                 };
1395
1396                 spi4: spi@11018000 {
1397                         compatible = "mediatek,mt8183-spi";
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400                         reg = <0 0x11018000 0 0x1000>;
1401                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
1402                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1403                                  <&topckgen CLK_TOP_MUX_SPI>,
1404                                  <&infracfg CLK_INFRA_SPI4>;
1405                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1406                         status = "disabled";
1407                 };
1408
1409                 spi5: spi@11019000 {
1410                         compatible = "mediatek,mt8183-spi";
1411                         #address-cells = <1>;
1412                         #size-cells = <0>;
1413                         reg = <0 0x11019000 0 0x1000>;
1414                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
1415                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
1416                                  <&topckgen CLK_TOP_MUX_SPI>,
1417                                  <&infracfg CLK_INFRA_SPI5>;
1418                         clock-names = "parent-clk", "sel-clk", "spi-clk";
1419                         status = "disabled";
1420                 };
1421
1422                 i2c7: i2c@1101a000 {
1423                         compatible = "mediatek,mt8183-i2c";
1424                         reg = <0 0x1101a000 0 0x1000>,
1425                               <0 0x11000680 0 0x80>;
1426                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
1427                         clocks = <&infracfg CLK_INFRA_I2C7>,
1428                                  <&infracfg CLK_INFRA_AP_DMA>;
1429                         clock-names = "main", "dma";
1430                         clock-div = <1>;
1431                         #address-cells = <1>;
1432                         #size-cells = <0>;
1433                         status = "disabled";
1434                 };
1435
1436                 i2c8: i2c@1101b000 {
1437                         compatible = "mediatek,mt8183-i2c";
1438                         reg = <0 0x1101b000 0 0x1000>,
1439                               <0 0x11000700 0 0x80>;
1440                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
1441                         clocks = <&infracfg CLK_INFRA_I2C8>,
1442                                  <&infracfg CLK_INFRA_AP_DMA>;
1443                         clock-names = "main", "dma";
1444                         clock-div = <1>;
1445                         #address-cells = <1>;
1446                         #size-cells = <0>;
1447                         status = "disabled";
1448                 };
1449
1450                 ssusb: usb@11201000 {
1451                         compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
1452                         reg = <0 0x11201000 0 0x2e00>,
1453                               <0 0x11203e00 0 0x0100>;
1454                         reg-names = "mac", "ippc";
1455                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
1456                         phys = <&u2port0 PHY_TYPE_USB2>,
1457                                <&u3port0 PHY_TYPE_USB3>;
1458                         clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1459                                  <&infracfg CLK_INFRA_USB>;
1460                         clock-names = "sys_ck", "ref_ck";
1461                         mediatek,syscon-wakeup = <&pericfg 0x420 101>;
1462                         #address-cells = <2>;
1463                         #size-cells = <2>;
1464                         ranges;
1465                         status = "disabled";
1466
1467                         usb_host: usb@11200000 {
1468                                 compatible = "mediatek,mt8183-xhci",
1469                                              "mediatek,mtk-xhci";
1470                                 reg = <0 0x11200000 0 0x1000>;
1471                                 reg-names = "mac";
1472                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
1473                                 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
1474                                          <&infracfg CLK_INFRA_USB>;
1475                                 clock-names = "sys_ck", "ref_ck";
1476                                 status = "disabled";
1477                         };
1478                 };
1479
1480                 audiosys: audio-controller@11220000 {
1481                         compatible = "mediatek,mt8183-audiosys", "syscon";
1482                         reg = <0 0x11220000 0 0x1000>;
1483                         #clock-cells = <1>;
1484                         afe: mt8183-afe-pcm {
1485                                 compatible = "mediatek,mt8183-audio";
1486                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
1487                                 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
1488                                 reset-names = "audiosys";
1489                                 power-domains =
1490                                         <&spm MT8183_POWER_DOMAIN_AUDIO>;
1491                                 clocks = <&audiosys CLK_AUDIO_AFE>,
1492                                          <&audiosys CLK_AUDIO_DAC>,
1493                                          <&audiosys CLK_AUDIO_DAC_PREDIS>,
1494                                          <&audiosys CLK_AUDIO_ADC>,
1495                                          <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
1496                                          <&audiosys CLK_AUDIO_22M>,
1497                                          <&audiosys CLK_AUDIO_24M>,
1498                                          <&audiosys CLK_AUDIO_APLL_TUNER>,
1499                                          <&audiosys CLK_AUDIO_APLL2_TUNER>,
1500                                          <&audiosys CLK_AUDIO_I2S1>,
1501                                          <&audiosys CLK_AUDIO_I2S2>,
1502                                          <&audiosys CLK_AUDIO_I2S3>,
1503                                          <&audiosys CLK_AUDIO_I2S4>,
1504                                          <&audiosys CLK_AUDIO_TDM>,
1505                                          <&audiosys CLK_AUDIO_TML>,
1506                                          <&infracfg CLK_INFRA_AUDIO>,
1507                                          <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
1508                                          <&topckgen CLK_TOP_MUX_AUDIO>,
1509                                          <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
1510                                          <&topckgen CLK_TOP_SYSPLL_D2_D4>,
1511                                          <&topckgen CLK_TOP_MUX_AUD_1>,
1512                                          <&topckgen CLK_TOP_APLL1_CK>,
1513                                          <&topckgen CLK_TOP_MUX_AUD_2>,
1514                                          <&topckgen CLK_TOP_APLL2_CK>,
1515                                          <&topckgen CLK_TOP_MUX_AUD_ENG1>,
1516                                          <&topckgen CLK_TOP_APLL1_D8>,
1517                                          <&topckgen CLK_TOP_MUX_AUD_ENG2>,
1518                                          <&topckgen CLK_TOP_APLL2_D8>,
1519                                          <&topckgen CLK_TOP_MUX_APLL_I2S0>,
1520                                          <&topckgen CLK_TOP_MUX_APLL_I2S1>,
1521                                          <&topckgen CLK_TOP_MUX_APLL_I2S2>,
1522                                          <&topckgen CLK_TOP_MUX_APLL_I2S3>,
1523                                          <&topckgen CLK_TOP_MUX_APLL_I2S4>,
1524                                          <&topckgen CLK_TOP_MUX_APLL_I2S5>,
1525                                          <&topckgen CLK_TOP_APLL12_DIV0>,
1526                                          <&topckgen CLK_TOP_APLL12_DIV1>,
1527                                          <&topckgen CLK_TOP_APLL12_DIV2>,
1528                                          <&topckgen CLK_TOP_APLL12_DIV3>,
1529                                          <&topckgen CLK_TOP_APLL12_DIV4>,
1530                                          <&topckgen CLK_TOP_APLL12_DIVB>,
1531                                          /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
1532                                          <&clk26m>;
1533                                 clock-names = "aud_afe_clk",
1534                                                   "aud_dac_clk",
1535                                                   "aud_dac_predis_clk",
1536                                                   "aud_adc_clk",
1537                                                   "aud_adc_adda6_clk",
1538                                                   "aud_apll22m_clk",
1539                                                   "aud_apll24m_clk",
1540                                                   "aud_apll1_tuner_clk",
1541                                                   "aud_apll2_tuner_clk",
1542                                                   "aud_i2s1_bclk_sw",
1543                                                   "aud_i2s2_bclk_sw",
1544                                                   "aud_i2s3_bclk_sw",
1545                                                   "aud_i2s4_bclk_sw",
1546                                                   "aud_tdm_clk",
1547                                                   "aud_tml_clk",
1548                                                   "aud_infra_clk",
1549                                                   "mtkaif_26m_clk",
1550                                                   "top_mux_audio",
1551                                                   "top_mux_aud_intbus",
1552                                                   "top_syspll_d2_d4",
1553                                                   "top_mux_aud_1",
1554                                                   "top_apll1_ck",
1555                                                   "top_mux_aud_2",
1556                                                   "top_apll2_ck",
1557                                                   "top_mux_aud_eng1",
1558                                                   "top_apll1_d8",
1559                                                   "top_mux_aud_eng2",
1560                                                   "top_apll2_d8",
1561                                                   "top_i2s0_m_sel",
1562                                                   "top_i2s1_m_sel",
1563                                                   "top_i2s2_m_sel",
1564                                                   "top_i2s3_m_sel",
1565                                                   "top_i2s4_m_sel",
1566                                                   "top_i2s5_m_sel",
1567                                                   "top_apll12_div0",
1568                                                   "top_apll12_div1",
1569                                                   "top_apll12_div2",
1570                                                   "top_apll12_div3",
1571                                                   "top_apll12_div4",
1572                                                   "top_apll12_divb",
1573                                                   /*"top_apll12_div5",*/
1574                                                   "top_clk26m_clk";
1575                         };
1576                 };
1577
1578                 mmc0: mmc@11230000 {
1579                         compatible = "mediatek,mt8183-mmc";
1580                         reg = <0 0x11230000 0 0x1000>,
1581                               <0 0x11f50000 0 0x1000>;
1582                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
1583                         clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
1584                                  <&infracfg CLK_INFRA_MSDC0>,
1585                                  <&infracfg CLK_INFRA_MSDC0_SCK>;
1586                         clock-names = "source", "hclk", "source_cg";
1587                         status = "disabled";
1588                 };
1589
1590                 mmc1: mmc@11240000 {
1591                         compatible = "mediatek,mt8183-mmc";
1592                         reg = <0 0x11240000 0 0x1000>,
1593                               <0 0x11e10000 0 0x1000>;
1594                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
1595                         clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
1596                                  <&infracfg CLK_INFRA_MSDC1>,
1597                                  <&infracfg CLK_INFRA_MSDC1_SCK>;
1598                         clock-names = "source", "hclk", "source_cg";
1599                         status = "disabled";
1600                 };
1601
1602                 mipi_tx0: dsi-phy@11e50000 {
1603                         compatible = "mediatek,mt8183-mipi-tx";
1604                         reg = <0 0x11e50000 0 0x1000>;
1605                         clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
1606                         #clock-cells = <0>;
1607                         #phy-cells = <0>;
1608                         clock-output-names = "mipi_tx0_pll";
1609                         nvmem-cells = <&mipi_tx_calibration>;
1610                         nvmem-cell-names = "calibration-data";
1611                 };
1612
1613                 efuse: efuse@11f10000 {
1614                         compatible = "mediatek,mt8183-efuse",
1615                                      "mediatek,efuse";
1616                         reg = <0 0x11f10000 0 0x1000>;
1617                         #address-cells = <1>;
1618                         #size-cells = <1>;
1619                         thermal_calibration: calib@180 {
1620                                 reg = <0x180 0xc>;
1621                         };
1622
1623                         mipi_tx_calibration: calib@190 {
1624                                 reg = <0x190 0xc>;
1625                         };
1626
1627                         svs_calibration: calib@580 {
1628                                 reg = <0x580 0x64>;
1629                         };
1630                 };
1631
1632                 u3phy: t-phy@11f40000 {
1633                         compatible = "mediatek,mt8183-tphy",
1634                                      "mediatek,generic-tphy-v2";
1635                         #address-cells = <1>;
1636                         #size-cells = <1>;
1637                         ranges = <0 0 0x11f40000 0x1000>;
1638                         status = "okay";
1639
1640                         u2port0: usb-phy@0 {
1641                                 reg = <0x0 0x700>;
1642                                 clocks = <&clk26m>;
1643                                 clock-names = "ref";
1644                                 #phy-cells = <1>;
1645                                 mediatek,discth = <15>;
1646                                 status = "okay";
1647                         };
1648
1649                         u3port0: usb-phy@700 {
1650                                 reg = <0x0700 0x900>;
1651                                 clocks = <&clk26m>;
1652                                 clock-names = "ref";
1653                                 #phy-cells = <1>;
1654                                 status = "okay";
1655                         };
1656                 };
1657
1658                 mfgcfg: syscon@13000000 {
1659                         compatible = "mediatek,mt8183-mfgcfg", "syscon";
1660                         reg = <0 0x13000000 0 0x1000>;
1661                         #clock-cells = <1>;
1662                 };
1663
1664                 gpu: gpu@13040000 {
1665                         compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
1666                         reg = <0 0x13040000 0 0x4000>;
1667                         interrupts =
1668                                 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
1669                                 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
1670                                 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
1671                         interrupt-names = "job", "mmu", "gpu";
1672
1673                         clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
1674
1675                         power-domains =
1676                                 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
1677                                 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
1678                                 <&spm MT8183_POWER_DOMAIN_MFG_2D>;
1679                         power-domain-names = "core0", "core1", "core2";
1680
1681                         operating-points-v2 = <&gpu_opp_table>;
1682                 };
1683
1684                 mmsys: syscon@14000000 {
1685                         compatible = "mediatek,mt8183-mmsys", "syscon";
1686                         reg = <0 0x14000000 0 0x1000>;
1687                         #clock-cells = <1>;
1688                         #reset-cells = <1>;
1689                         mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1690                                  <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1691                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1692                 };
1693
1694                 ovl0: ovl@14008000 {
1695                         compatible = "mediatek,mt8183-disp-ovl";
1696                         reg = <0 0x14008000 0 0x1000>;
1697                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
1698                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1699                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
1700                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
1701                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1702                 };
1703
1704                 ovl_2l0: ovl@14009000 {
1705                         compatible = "mediatek,mt8183-disp-ovl-2l";
1706                         reg = <0 0x14009000 0 0x1000>;
1707                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
1708                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1709                         clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
1710                         iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
1711                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
1712                 };
1713
1714                 ovl_2l1: ovl@1400a000 {
1715                         compatible = "mediatek,mt8183-disp-ovl-2l";
1716                         reg = <0 0x1400a000 0 0x1000>;
1717                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
1718                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1719                         clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
1720                         iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
1721                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
1722                 };
1723
1724                 rdma0: rdma@1400b000 {
1725                         compatible = "mediatek,mt8183-disp-rdma";
1726                         reg = <0 0x1400b000 0 0x1000>;
1727                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
1728                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1729                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1730                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1731                         mediatek,rdma-fifo-size = <5120>;
1732                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1733                 };
1734
1735                 rdma1: rdma@1400c000 {
1736                         compatible = "mediatek,mt8183-disp-rdma";
1737                         reg = <0 0x1400c000 0 0x1000>;
1738                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
1739                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1740                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1741                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1742                         mediatek,rdma-fifo-size = <2048>;
1743                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1744                 };
1745
1746                 color0: color@1400e000 {
1747                         compatible = "mediatek,mt8183-disp-color",
1748                                      "mediatek,mt8173-disp-color";
1749                         reg = <0 0x1400e000 0 0x1000>;
1750                         interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
1751                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1752                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1753                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1754                 };
1755
1756                 ccorr0: ccorr@1400f000 {
1757                         compatible = "mediatek,mt8183-disp-ccorr";
1758                         reg = <0 0x1400f000 0 0x1000>;
1759                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
1760                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1761                         clocks = <&mmsys CLK_MM_DISP_CCORR0>;
1762                         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1763                 };
1764
1765                 aal0: aal@14010000 {
1766                         compatible = "mediatek,mt8183-disp-aal";
1767                         reg = <0 0x14010000 0 0x1000>;
1768                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
1769                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1770                         clocks = <&mmsys CLK_MM_DISP_AAL0>;
1771                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1772                 };
1773
1774                 gamma0: gamma@14011000 {
1775                         compatible = "mediatek,mt8183-disp-gamma";
1776                         reg = <0 0x14011000 0 0x1000>;
1777                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
1778                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1779                         clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
1780                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1781                 };
1782
1783                 dither0: dither@14012000 {
1784                         compatible = "mediatek,mt8183-disp-dither";
1785                         reg = <0 0x14012000 0 0x1000>;
1786                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
1787                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1788                         clocks = <&mmsys CLK_MM_DISP_DITHER0>;
1789                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1790                 };
1791
1792                 dsi0: dsi@14014000 {
1793                         compatible = "mediatek,mt8183-dsi";
1794                         reg = <0 0x14014000 0 0x1000>;
1795                         interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
1796                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1797                         clocks = <&mmsys CLK_MM_DSI0_MM>,
1798                                  <&mmsys CLK_MM_DSI0_IF>,
1799                                  <&mipi_tx0>;
1800                         clock-names = "engine", "digital", "hs";
1801                         resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
1802                         phys = <&mipi_tx0>;
1803                         phy-names = "dphy";
1804                 };
1805
1806                 mutex: mutex@14016000 {
1807                         compatible = "mediatek,mt8183-disp-mutex";
1808                         reg = <0 0x14016000 0 0x1000>;
1809                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
1810                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1811                         mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
1812                                               <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
1813                         mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1814                 };
1815
1816                 larb0: larb@14017000 {
1817                         compatible = "mediatek,mt8183-smi-larb";
1818                         reg = <0 0x14017000 0 0x1000>;
1819                         mediatek,smi = <&smi_common>;
1820                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1821                                  <&mmsys CLK_MM_SMI_LARB0>;
1822                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1823                         clock-names = "apb", "smi";
1824                 };
1825
1826                 smi_common: smi@14019000 {
1827                         compatible = "mediatek,mt8183-smi-common";
1828                         reg = <0 0x14019000 0 0x1000>;
1829                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1830                                  <&mmsys CLK_MM_SMI_COMMON>,
1831                                  <&mmsys CLK_MM_GALS_COMM0>,
1832                                  <&mmsys CLK_MM_GALS_COMM1>;
1833                         clock-names = "apb", "smi", "gals0", "gals1";
1834                         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
1835                 };
1836
1837                 imgsys: syscon@15020000 {
1838                         compatible = "mediatek,mt8183-imgsys", "syscon";
1839                         reg = <0 0x15020000 0 0x1000>;
1840                         #clock-cells = <1>;
1841                 };
1842
1843                 larb5: larb@15021000 {
1844                         compatible = "mediatek,mt8183-smi-larb";
1845                         reg = <0 0x15021000 0 0x1000>;
1846                         mediatek,smi = <&smi_common>;
1847                         clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
1848                                  <&mmsys CLK_MM_GALS_IMG2MM>;
1849                         clock-names = "apb", "smi", "gals";
1850                         power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1851                 };
1852
1853                 larb2: larb@1502f000 {
1854                         compatible = "mediatek,mt8183-smi-larb";
1855                         reg = <0 0x1502f000 0 0x1000>;
1856                         mediatek,smi = <&smi_common>;
1857                         clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
1858                                  <&mmsys CLK_MM_GALS_IPU2MM>;
1859                         clock-names = "apb", "smi", "gals";
1860                         power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
1861                 };
1862
1863                 vdecsys: syscon@16000000 {
1864                         compatible = "mediatek,mt8183-vdecsys", "syscon";
1865                         reg = <0 0x16000000 0 0x1000>;
1866                         #clock-cells = <1>;
1867                 };
1868
1869                 larb1: larb@16010000 {
1870                         compatible = "mediatek,mt8183-smi-larb";
1871                         reg = <0 0x16010000 0 0x1000>;
1872                         mediatek,smi = <&smi_common>;
1873                         clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
1874                         clock-names = "apb", "smi";
1875                         power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
1876                 };
1877
1878                 vencsys: syscon@17000000 {
1879                         compatible = "mediatek,mt8183-vencsys", "syscon";
1880                         reg = <0 0x17000000 0 0x1000>;
1881                         #clock-cells = <1>;
1882                 };
1883
1884                 larb4: larb@17010000 {
1885                         compatible = "mediatek,mt8183-smi-larb";
1886                         reg = <0 0x17010000 0 0x1000>;
1887                         mediatek,smi = <&smi_common>;
1888                         clocks = <&vencsys CLK_VENC_LARB>,
1889                                  <&vencsys CLK_VENC_LARB>;
1890                         clock-names = "apb", "smi";
1891                         power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1892                 };
1893
1894                 venc_jpg: venc_jpg@17030000 {
1895                         compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
1896                         reg = <0 0x17030000 0 0x1000>;
1897                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
1898                         iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
1899                                  <&iommu M4U_PORT_JPGENC_BSDMA>;
1900                         power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
1901                         clocks = <&vencsys CLK_VENC_JPGENC>;
1902                         clock-names = "jpgenc";
1903                 };
1904
1905                 ipu_conn: syscon@19000000 {
1906                         compatible = "mediatek,mt8183-ipu_conn", "syscon";
1907                         reg = <0 0x19000000 0 0x1000>;
1908                         #clock-cells = <1>;
1909                 };
1910
1911                 ipu_adl: syscon@19010000 {
1912                         compatible = "mediatek,mt8183-ipu_adl", "syscon";
1913                         reg = <0 0x19010000 0 0x1000>;
1914                         #clock-cells = <1>;
1915                 };
1916
1917                 ipu_core0: syscon@19180000 {
1918                         compatible = "mediatek,mt8183-ipu_core0", "syscon";
1919                         reg = <0 0x19180000 0 0x1000>;
1920                         #clock-cells = <1>;
1921                 };
1922
1923                 ipu_core1: syscon@19280000 {
1924                         compatible = "mediatek,mt8183-ipu_core1", "syscon";
1925                         reg = <0 0x19280000 0 0x1000>;
1926                         #clock-cells = <1>;
1927                 };
1928
1929                 camsys: syscon@1a000000 {
1930                         compatible = "mediatek,mt8183-camsys", "syscon";
1931                         reg = <0 0x1a000000 0 0x1000>;
1932                         #clock-cells = <1>;
1933                 };
1934
1935                 larb6: larb@1a001000 {
1936                         compatible = "mediatek,mt8183-smi-larb";
1937                         reg = <0 0x1a001000 0 0x1000>;
1938                         mediatek,smi = <&smi_common>;
1939                         clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
1940                                  <&mmsys CLK_MM_GALS_CAM2MM>;
1941                         clock-names = "apb", "smi", "gals";
1942                         power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1943                 };
1944
1945                 larb3: larb@1a002000 {
1946                         compatible = "mediatek,mt8183-smi-larb";
1947                         reg = <0 0x1a002000 0 0x1000>;
1948                         mediatek,smi = <&smi_common>;
1949                         clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
1950                                  <&mmsys CLK_MM_GALS_IPU12MM>;
1951                         clock-names = "apb", "smi", "gals";
1952                         power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
1953                 };
1954         };
1955 };