2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
26 compatible = "mediatek,mt8173";
27 interrupt-parent = <&sysirq>;
46 mdp-rdma0 = &mdp_rdma0;
47 mdp-rdma1 = &mdp_rdma1;
51 mdp-wdma0 = &mdp_wdma0;
52 mdp-wrot0 = &mdp_wrot0;
53 mdp-wrot1 = &mdp_wrot1;
60 cluster0_opp: opp-table-0 {
61 compatible = "operating-points-v2";
64 opp-hz = /bits/ 64 <507000000>;
65 opp-microvolt = <859000>;
68 opp-hz = /bits/ 64 <702000000>;
69 opp-microvolt = <908000>;
72 opp-hz = /bits/ 64 <1001000000>;
73 opp-microvolt = <983000>;
76 opp-hz = /bits/ 64 <1105000000>;
77 opp-microvolt = <1009000>;
80 opp-hz = /bits/ 64 <1209000000>;
81 opp-microvolt = <1034000>;
84 opp-hz = /bits/ 64 <1300000000>;
85 opp-microvolt = <1057000>;
88 opp-hz = /bits/ 64 <1508000000>;
89 opp-microvolt = <1109000>;
92 opp-hz = /bits/ 64 <1703000000>;
93 opp-microvolt = <1125000>;
97 cluster1_opp: opp-table-1 {
98 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <507000000>;
102 opp-microvolt = <828000>;
105 opp-hz = /bits/ 64 <702000000>;
106 opp-microvolt = <867000>;
109 opp-hz = /bits/ 64 <1001000000>;
110 opp-microvolt = <927000>;
113 opp-hz = /bits/ 64 <1209000000>;
114 opp-microvolt = <968000>;
117 opp-hz = /bits/ 64 <1404000000>;
118 opp-microvolt = <1007000>;
121 opp-hz = /bits/ 64 <1612000000>;
122 opp-microvolt = <1049000>;
125 opp-hz = /bits/ 64 <1807000000>;
126 opp-microvolt = <1089000>;
129 opp-hz = /bits/ 64 <2106000000>;
130 opp-microvolt = <1125000>;
135 #address-cells = <1>;
160 compatible = "arm,cortex-a53";
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0>;
164 #cooling-cells = <2>;
165 dynamic-power-coefficient = <263>;
166 clocks = <&infracfg CLK_INFRA_CA53SEL>,
167 <&apmixedsys CLK_APMIXED_MAINPLL>;
168 clock-names = "cpu", "intermediate";
169 operating-points-v2 = <&cluster0_opp>;
170 capacity-dmips-mhz = <740>;
175 compatible = "arm,cortex-a53";
177 enable-method = "psci";
178 cpu-idle-states = <&CPU_SLEEP_0>;
179 #cooling-cells = <2>;
180 dynamic-power-coefficient = <263>;
181 clocks = <&infracfg CLK_INFRA_CA53SEL>,
182 <&apmixedsys CLK_APMIXED_MAINPLL>;
183 clock-names = "cpu", "intermediate";
184 operating-points-v2 = <&cluster0_opp>;
185 capacity-dmips-mhz = <740>;
190 compatible = "arm,cortex-a72";
192 enable-method = "psci";
193 cpu-idle-states = <&CPU_SLEEP_0>;
194 #cooling-cells = <2>;
195 dynamic-power-coefficient = <530>;
196 clocks = <&infracfg CLK_INFRA_CA72SEL>,
197 <&apmixedsys CLK_APMIXED_MAINPLL>;
198 clock-names = "cpu", "intermediate";
199 operating-points-v2 = <&cluster1_opp>;
200 capacity-dmips-mhz = <1024>;
205 compatible = "arm,cortex-a72";
207 enable-method = "psci";
208 cpu-idle-states = <&CPU_SLEEP_0>;
209 #cooling-cells = <2>;
210 dynamic-power-coefficient = <530>;
211 clocks = <&infracfg CLK_INFRA_CA72SEL>,
212 <&apmixedsys CLK_APMIXED_MAINPLL>;
213 clock-names = "cpu", "intermediate";
214 operating-points-v2 = <&cluster1_opp>;
215 capacity-dmips-mhz = <1024>;
219 entry-method = "psci";
221 CPU_SLEEP_0: cpu-sleep-0 {
222 compatible = "arm,idle-state";
224 entry-latency-us = <639>;
225 exit-latency-us = <680>;
226 min-residency-us = <1088>;
227 arm,psci-suspend-param = <0x0010000>;
233 compatible = "arm,cortex-a53-pmu";
234 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
235 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
236 interrupt-affinity = <&cpu0>, <&cpu1>;
240 compatible = "arm,cortex-a72-pmu";
241 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
242 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
243 interrupt-affinity = <&cpu2>, <&cpu3>;
247 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
249 cpu_suspend = <0x84000001>;
250 cpu_off = <0x84000002>;
251 cpu_on = <0x84000003>;
254 clk26m: oscillator0 {
255 compatible = "fixed-clock";
257 clock-frequency = <26000000>;
258 clock-output-names = "clk26m";
261 clk32k: oscillator1 {
262 compatible = "fixed-clock";
264 clock-frequency = <32000>;
265 clock-output-names = "clk32k";
268 cpum_ck: oscillator2 {
269 compatible = "fixed-clock";
271 clock-frequency = <0>;
272 clock-output-names = "cpum_ck";
276 cpu_thermal: cpu-thermal {
277 polling-delay-passive = <1000>; /* milliseconds */
278 polling-delay = <1000>; /* milliseconds */
280 thermal-sensors = <&thermal>;
281 sustainable-power = <1500>; /* milliwatts */
284 threshold: trip-point0 {
285 temperature = <68000>;
290 target: trip-point1 {
291 temperature = <85000>;
296 cpu_crit: cpu_crit0 {
297 temperature = <115000>;
306 cooling-device = <&cpu0 THERMAL_NO_LIMIT
308 <&cpu1 THERMAL_NO_LIMIT
310 contribution = <3072>;
314 cooling-device = <&cpu2 THERMAL_NO_LIMIT
316 <&cpu3 THERMAL_NO_LIMIT
318 contribution = <1024>;
325 #address-cells = <2>;
328 vpu_dma_reserved: vpu_dma_mem_region@b7000000 {
329 compatible = "shared-dma-pool";
330 reg = <0 0xb7000000 0 0x500000>;
331 alignment = <0x1000>;
337 compatible = "arm,armv8-timer";
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_PPI 13
340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
344 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
346 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
347 arm,no-tick-in-suspend;
351 #address-cells = <2>;
353 compatible = "simple-bus";
356 topckgen: clock-controller@10000000 {
357 compatible = "mediatek,mt8173-topckgen";
358 reg = <0 0x10000000 0 0x1000>;
362 infracfg: power-controller@10001000 {
363 compatible = "mediatek,mt8173-infracfg", "syscon";
364 reg = <0 0x10001000 0 0x1000>;
369 pericfg: power-controller@10003000 {
370 compatible = "mediatek,mt8173-pericfg", "syscon";
371 reg = <0 0x10003000 0 0x1000>;
376 syscfg_pctl_a: syscfg_pctl_a@10005000 {
377 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
378 reg = <0 0x10005000 0 0x1000>;
381 pio: pinctrl@1000b000 {
382 compatible = "mediatek,mt8173-pinctrl";
383 reg = <0 0x1000b000 0 0x1000>;
384 mediatek,pctl-regmap = <&syscfg_pctl_a>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
390 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
398 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
406 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
407 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
414 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
415 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
422 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
423 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
430 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
431 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
438 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
439 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
446 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
447 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
453 scpsys: syscon@10006000 {
454 compatible = "syscon", "simple-mfd";
455 reg = <0 0x10006000 0 0x1000>;
456 #power-domain-cells = <1>;
458 /* System Power Manager */
459 spm: power-controller {
460 compatible = "mediatek,mt8173-power-controller";
461 #address-cells = <1>;
463 #power-domain-cells = <1>;
465 /* power domains of the SoC */
466 power-domain@MT8173_POWER_DOMAIN_VDEC {
467 reg = <MT8173_POWER_DOMAIN_VDEC>;
468 clocks = <&topckgen CLK_TOP_MM_SEL>;
470 #power-domain-cells = <0>;
472 power-domain@MT8173_POWER_DOMAIN_VENC {
473 reg = <MT8173_POWER_DOMAIN_VENC>;
474 clocks = <&topckgen CLK_TOP_MM_SEL>,
475 <&topckgen CLK_TOP_VENC_SEL>;
476 clock-names = "mm", "venc";
477 #power-domain-cells = <0>;
479 power-domain@MT8173_POWER_DOMAIN_ISP {
480 reg = <MT8173_POWER_DOMAIN_ISP>;
481 clocks = <&topckgen CLK_TOP_MM_SEL>;
483 #power-domain-cells = <0>;
485 power-domain@MT8173_POWER_DOMAIN_MM {
486 reg = <MT8173_POWER_DOMAIN_MM>;
487 clocks = <&topckgen CLK_TOP_MM_SEL>;
489 #power-domain-cells = <0>;
490 mediatek,infracfg = <&infracfg>;
492 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
493 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
494 clocks = <&topckgen CLK_TOP_MM_SEL>,
495 <&topckgen CLK_TOP_VENC_LT_SEL>;
496 clock-names = "mm", "venclt";
497 #power-domain-cells = <0>;
499 power-domain@MT8173_POWER_DOMAIN_AUDIO {
500 reg = <MT8173_POWER_DOMAIN_AUDIO>;
501 #power-domain-cells = <0>;
503 power-domain@MT8173_POWER_DOMAIN_USB {
504 reg = <MT8173_POWER_DOMAIN_USB>;
505 #power-domain-cells = <0>;
507 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
508 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
511 #address-cells = <1>;
513 #power-domain-cells = <1>;
515 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
516 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
517 #address-cells = <1>;
519 #power-domain-cells = <1>;
521 power-domain@MT8173_POWER_DOMAIN_MFG {
522 reg = <MT8173_POWER_DOMAIN_MFG>;
523 #power-domain-cells = <0>;
524 mediatek,infracfg = <&infracfg>;
531 watchdog: watchdog@10007000 {
532 compatible = "mediatek,mt8173-wdt",
533 "mediatek,mt6589-wdt";
534 reg = <0 0x10007000 0 0x100>;
537 timer: timer@10008000 {
538 compatible = "mediatek,mt8173-timer",
539 "mediatek,mt6577-timer";
540 reg = <0 0x10008000 0 0x1000>;
541 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
542 clocks = <&infracfg CLK_INFRA_CLK_13M>,
543 <&topckgen CLK_TOP_RTC_SEL>;
546 pwrap: pwrap@1000d000 {
547 compatible = "mediatek,mt8173-pwrap";
548 reg = <0 0x1000d000 0 0x1000>;
550 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
551 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
552 reset-names = "pwrap";
553 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
554 clock-names = "spi", "wrap";
558 compatible = "mediatek,mt8173-cec";
559 reg = <0 0x10013000 0 0xbc>;
560 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
561 clocks = <&infracfg CLK_INFRA_CEC>;
566 compatible = "mediatek,mt8173-vpu";
567 reg = <0 0x10020000 0 0x30000>,
568 <0 0x10050000 0 0x100>;
569 reg-names = "tcm", "cfg_reg";
570 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&topckgen CLK_TOP_SCP_SEL>;
572 clock-names = "main";
573 memory-region = <&vpu_dma_reserved>;
576 sysirq: intpol-controller@10200620 {
577 compatible = "mediatek,mt8173-sysirq",
578 "mediatek,mt6577-sysirq";
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 interrupt-parent = <&gic>;
582 reg = <0 0x10200620 0 0x20>;
585 iommu: iommu@10205000 {
586 compatible = "mediatek,mt8173-m4u";
587 reg = <0 0x10205000 0 0x1000>;
588 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
589 clocks = <&infracfg CLK_INFRA_M4U>;
590 clock-names = "bclk";
591 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
592 <&larb3>, <&larb4>, <&larb5>;
596 efuse: efuse@10206000 {
597 compatible = "mediatek,mt8173-efuse";
598 reg = <0 0x10206000 0 0x1000>;
599 #address-cells = <1>;
601 thermal_calibration: calib@528 {
606 apmixedsys: clock-controller@10209000 {
607 compatible = "mediatek,mt8173-apmixedsys";
608 reg = <0 0x10209000 0 0x1000>;
612 hdmi_phy: hdmi-phy@10209100 {
613 compatible = "mediatek,mt8173-hdmi-phy";
614 reg = <0 0x10209100 0 0x24>;
615 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
616 clock-names = "pll_ref";
617 clock-output-names = "hdmitx_dig_cts";
618 mediatek,ibias = <0xa>;
619 mediatek,ibias_up = <0x1c>;
625 gce: mailbox@10212000 {
626 compatible = "mediatek,mt8173-gce";
627 reg = <0 0x10212000 0 0x1000>;
628 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
629 clocks = <&infracfg CLK_INFRA_GCE>;
634 mipi_tx0: dsi-phy@10215000 {
635 compatible = "mediatek,mt8173-mipi-tx";
636 reg = <0 0x10215000 0 0x1000>;
638 clock-output-names = "mipi_tx0_pll";
644 mipi_tx1: dsi-phy@10216000 {
645 compatible = "mediatek,mt8173-mipi-tx";
646 reg = <0 0x10216000 0 0x1000>;
648 clock-output-names = "mipi_tx1_pll";
654 gic: interrupt-controller@10221000 {
655 compatible = "arm,gic-400";
656 #interrupt-cells = <3>;
657 interrupt-parent = <&gic>;
658 interrupt-controller;
659 reg = <0 0x10221000 0 0x1000>,
660 <0 0x10222000 0 0x2000>,
661 <0 0x10224000 0 0x2000>,
662 <0 0x10226000 0 0x2000>;
663 interrupts = <GIC_PPI 9
664 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
667 auxadc: auxadc@11001000 {
668 compatible = "mediatek,mt8173-auxadc";
669 reg = <0 0x11001000 0 0x1000>;
670 clocks = <&pericfg CLK_PERI_AUXADC>;
671 clock-names = "main";
672 #io-channel-cells = <1>;
675 uart0: serial@11002000 {
676 compatible = "mediatek,mt8173-uart",
677 "mediatek,mt6577-uart";
678 reg = <0 0x11002000 0 0x400>;
679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
680 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
681 clock-names = "baud", "bus";
685 uart1: serial@11003000 {
686 compatible = "mediatek,mt8173-uart",
687 "mediatek,mt6577-uart";
688 reg = <0 0x11003000 0 0x400>;
689 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
690 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
691 clock-names = "baud", "bus";
695 uart2: serial@11004000 {
696 compatible = "mediatek,mt8173-uart",
697 "mediatek,mt6577-uart";
698 reg = <0 0x11004000 0 0x400>;
699 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
700 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
701 clock-names = "baud", "bus";
705 uart3: serial@11005000 {
706 compatible = "mediatek,mt8173-uart",
707 "mediatek,mt6577-uart";
708 reg = <0 0x11005000 0 0x400>;
709 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
710 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
711 clock-names = "baud", "bus";
716 compatible = "mediatek,mt8173-i2c";
717 reg = <0 0x11007000 0 0x70>,
718 <0 0x11000100 0 0x80>;
719 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
721 clocks = <&pericfg CLK_PERI_I2C0>,
722 <&pericfg CLK_PERI_AP_DMA>;
723 clock-names = "main", "dma";
724 pinctrl-names = "default";
725 pinctrl-0 = <&i2c0_pins_a>;
726 #address-cells = <1>;
732 compatible = "mediatek,mt8173-i2c";
733 reg = <0 0x11008000 0 0x70>,
734 <0 0x11000180 0 0x80>;
735 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
737 clocks = <&pericfg CLK_PERI_I2C1>,
738 <&pericfg CLK_PERI_AP_DMA>;
739 clock-names = "main", "dma";
740 pinctrl-names = "default";
741 pinctrl-0 = <&i2c1_pins_a>;
742 #address-cells = <1>;
748 compatible = "mediatek,mt8173-i2c";
749 reg = <0 0x11009000 0 0x70>,
750 <0 0x11000200 0 0x80>;
751 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
753 clocks = <&pericfg CLK_PERI_I2C2>,
754 <&pericfg CLK_PERI_AP_DMA>;
755 clock-names = "main", "dma";
756 pinctrl-names = "default";
757 pinctrl-0 = <&i2c2_pins_a>;
758 #address-cells = <1>;
764 compatible = "mediatek,mt8173-spi";
765 #address-cells = <1>;
767 reg = <0 0x1100a000 0 0x1000>;
768 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
769 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
770 <&topckgen CLK_TOP_SPI_SEL>,
771 <&pericfg CLK_PERI_SPI0>;
772 clock-names = "parent-clk", "sel-clk", "spi-clk";
776 thermal: thermal@1100b000 {
777 #thermal-sensor-cells = <0>;
778 compatible = "mediatek,mt8173-thermal";
779 reg = <0 0x1100b000 0 0x1000>;
780 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
781 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
782 clock-names = "therm", "auxadc";
783 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
784 mediatek,auxadc = <&auxadc>;
785 mediatek,apmixedsys = <&apmixedsys>;
786 nvmem-cells = <&thermal_calibration>;
787 nvmem-cell-names = "calibration-data";
790 nor_flash: spi@1100d000 {
791 compatible = "mediatek,mt8173-nor";
792 reg = <0 0x1100d000 0 0xe0>;
793 clocks = <&pericfg CLK_PERI_SPI>,
794 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
795 clock-names = "spi", "sf";
796 #address-cells = <1>;
802 compatible = "mediatek,mt8173-i2c";
803 reg = <0 0x11010000 0 0x70>,
804 <0 0x11000280 0 0x80>;
805 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
807 clocks = <&pericfg CLK_PERI_I2C3>,
808 <&pericfg CLK_PERI_AP_DMA>;
809 clock-names = "main", "dma";
810 pinctrl-names = "default";
811 pinctrl-0 = <&i2c3_pins_a>;
812 #address-cells = <1>;
818 compatible = "mediatek,mt8173-i2c";
819 reg = <0 0x11011000 0 0x70>,
820 <0 0x11000300 0 0x80>;
821 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
823 clocks = <&pericfg CLK_PERI_I2C4>,
824 <&pericfg CLK_PERI_AP_DMA>;
825 clock-names = "main", "dma";
826 pinctrl-names = "default";
827 pinctrl-0 = <&i2c4_pins_a>;
828 #address-cells = <1>;
833 hdmiddc0: i2c@11012000 {
834 compatible = "mediatek,mt8173-hdmi-ddc";
835 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
836 reg = <0 0x11012000 0 0x1C>;
837 clocks = <&pericfg CLK_PERI_I2C5>;
838 clock-names = "ddc-i2c";
842 compatible = "mediatek,mt8173-i2c";
843 reg = <0 0x11013000 0 0x70>,
844 <0 0x11000080 0 0x80>;
845 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
847 clocks = <&pericfg CLK_PERI_I2C6>,
848 <&pericfg CLK_PERI_AP_DMA>;
849 clock-names = "main", "dma";
850 pinctrl-names = "default";
851 pinctrl-0 = <&i2c6_pins_a>;
852 #address-cells = <1>;
857 afe: audio-controller@11220000 {
858 compatible = "mediatek,mt8173-afe-pcm";
859 reg = <0 0x11220000 0 0x1000>;
860 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
861 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>;
862 clocks = <&infracfg CLK_INFRA_AUDIO>,
863 <&topckgen CLK_TOP_AUDIO_SEL>,
864 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
865 <&topckgen CLK_TOP_APLL1_DIV0>,
866 <&topckgen CLK_TOP_APLL2_DIV0>,
867 <&topckgen CLK_TOP_I2S0_M_SEL>,
868 <&topckgen CLK_TOP_I2S1_M_SEL>,
869 <&topckgen CLK_TOP_I2S2_M_SEL>,
870 <&topckgen CLK_TOP_I2S3_M_SEL>,
871 <&topckgen CLK_TOP_I2S3_B_SEL>;
872 clock-names = "infra_sys_audio_clk",
874 "top_pdn_aud_intbus",
882 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
883 <&topckgen CLK_TOP_AUD_2_SEL>;
884 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
885 <&topckgen CLK_TOP_APLL2>;
889 compatible = "mediatek,mt8173-mmc";
890 reg = <0 0x11230000 0 0x1000>;
891 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
892 clocks = <&pericfg CLK_PERI_MSDC30_0>,
893 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
894 clock-names = "source", "hclk";
899 compatible = "mediatek,mt8173-mmc";
900 reg = <0 0x11240000 0 0x1000>;
901 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
902 clocks = <&pericfg CLK_PERI_MSDC30_1>,
903 <&topckgen CLK_TOP_AXI_SEL>;
904 clock-names = "source", "hclk";
909 compatible = "mediatek,mt8173-mmc";
910 reg = <0 0x11250000 0 0x1000>;
911 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
912 clocks = <&pericfg CLK_PERI_MSDC30_2>,
913 <&topckgen CLK_TOP_AXI_SEL>;
914 clock-names = "source", "hclk";
919 compatible = "mediatek,mt8173-mmc";
920 reg = <0 0x11260000 0 0x1000>;
921 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
922 clocks = <&pericfg CLK_PERI_MSDC30_3>,
923 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
924 clock-names = "source", "hclk";
928 ssusb: usb@11271000 {
929 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
930 reg = <0 0x11271000 0 0x3000>,
931 <0 0x11280700 0 0x0100>;
932 reg-names = "mac", "ippc";
933 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
934 phys = <&u2port0 PHY_TYPE_USB2>,
935 <&u3port0 PHY_TYPE_USB3>,
936 <&u2port1 PHY_TYPE_USB2>;
937 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
938 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
939 clock-names = "sys_ck", "ref_ck";
940 mediatek,syscon-wakeup = <&pericfg 0x400 1>;
941 #address-cells = <2>;
946 usb_host: usb@11270000 {
947 compatible = "mediatek,mt8173-xhci",
949 reg = <0 0x11270000 0 0x1000>;
951 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
952 power-domains = <&spm MT8173_POWER_DOMAIN_USB>;
953 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
954 clock-names = "sys_ck", "ref_ck";
959 u3phy: t-phy@11290000 {
960 compatible = "mediatek,mt8173-u3phy";
961 reg = <0 0x11290000 0 0x800>;
962 #address-cells = <2>;
967 u2port0: usb-phy@11290800 {
968 reg = <0 0x11290800 0 0x100>;
969 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
975 u3port0: usb-phy@11290900 {
976 reg = <0 0x11290900 0 0x700>;
983 u2port1: usb-phy@11291000 {
984 reg = <0 0x11291000 0 0x100>;
985 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
992 mmsys: syscon@14000000 {
993 compatible = "mediatek,mt8173-mmsys", "syscon";
994 reg = <0 0x14000000 0 0x1000>;
995 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
996 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
997 assigned-clock-rates = <400000000>;
1000 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
1001 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
1002 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1005 mdp_rdma0: rdma@14001000 {
1006 compatible = "mediatek,mt8173-mdp-rdma",
1007 "mediatek,mt8173-mdp";
1008 reg = <0 0x14001000 0 0x1000>;
1009 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
1010 <&mmsys CLK_MM_MUTEX_32K>;
1011 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1012 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
1013 mediatek,vpu = <&vpu>;
1016 mdp_rdma1: rdma@14002000 {
1017 compatible = "mediatek,mt8173-mdp-rdma";
1018 reg = <0 0x14002000 0 0x1000>;
1019 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
1020 <&mmsys CLK_MM_MUTEX_32K>;
1021 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1022 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
1025 mdp_rsz0: rsz@14003000 {
1026 compatible = "mediatek,mt8173-mdp-rsz";
1027 reg = <0 0x14003000 0 0x1000>;
1028 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
1029 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1032 mdp_rsz1: rsz@14004000 {
1033 compatible = "mediatek,mt8173-mdp-rsz";
1034 reg = <0 0x14004000 0 0x1000>;
1035 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
1036 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1039 mdp_rsz2: rsz@14005000 {
1040 compatible = "mediatek,mt8173-mdp-rsz";
1041 reg = <0 0x14005000 0 0x1000>;
1042 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
1043 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1046 mdp_wdma0: wdma@14006000 {
1047 compatible = "mediatek,mt8173-mdp-wdma";
1048 reg = <0 0x14006000 0 0x1000>;
1049 clocks = <&mmsys CLK_MM_MDP_WDMA>;
1050 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1051 iommus = <&iommu M4U_PORT_MDP_WDMA>;
1054 mdp_wrot0: wrot@14007000 {
1055 compatible = "mediatek,mt8173-mdp-wrot";
1056 reg = <0 0x14007000 0 0x1000>;
1057 clocks = <&mmsys CLK_MM_MDP_WROT0>;
1058 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1059 iommus = <&iommu M4U_PORT_MDP_WROT0>;
1062 mdp_wrot1: wrot@14008000 {
1063 compatible = "mediatek,mt8173-mdp-wrot";
1064 reg = <0 0x14008000 0 0x1000>;
1065 clocks = <&mmsys CLK_MM_MDP_WROT1>;
1066 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1067 iommus = <&iommu M4U_PORT_MDP_WROT1>;
1070 ovl0: ovl@1400c000 {
1071 compatible = "mediatek,mt8173-disp-ovl";
1072 reg = <0 0x1400c000 0 0x1000>;
1073 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1074 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1075 clocks = <&mmsys CLK_MM_DISP_OVL0>;
1076 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1077 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1080 ovl1: ovl@1400d000 {
1081 compatible = "mediatek,mt8173-disp-ovl";
1082 reg = <0 0x1400d000 0 0x1000>;
1083 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
1084 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1085 clocks = <&mmsys CLK_MM_DISP_OVL1>;
1086 iommus = <&iommu M4U_PORT_DISP_OVL1>;
1087 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1090 rdma0: rdma@1400e000 {
1091 compatible = "mediatek,mt8173-disp-rdma";
1092 reg = <0 0x1400e000 0 0x1000>;
1093 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
1094 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1095 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
1096 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
1097 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1100 rdma1: rdma@1400f000 {
1101 compatible = "mediatek,mt8173-disp-rdma";
1102 reg = <0 0x1400f000 0 0x1000>;
1103 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1104 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1105 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1106 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1107 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1110 rdma2: rdma@14010000 {
1111 compatible = "mediatek,mt8173-disp-rdma";
1112 reg = <0 0x14010000 0 0x1000>;
1113 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1114 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1115 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1116 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1117 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
1120 wdma0: wdma@14011000 {
1121 compatible = "mediatek,mt8173-disp-wdma";
1122 reg = <0 0x14011000 0 0x1000>;
1123 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1124 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1125 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1126 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1127 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1130 wdma1: wdma@14012000 {
1131 compatible = "mediatek,mt8173-disp-wdma";
1132 reg = <0 0x14012000 0 0x1000>;
1133 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1134 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1135 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1136 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1137 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
1140 color0: color@14013000 {
1141 compatible = "mediatek,mt8173-disp-color";
1142 reg = <0 0x14013000 0 0x1000>;
1143 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1144 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1145 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1146 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
1149 color1: color@14014000 {
1150 compatible = "mediatek,mt8173-disp-color";
1151 reg = <0 0x14014000 0 0x1000>;
1152 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1153 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1154 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1155 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
1159 compatible = "mediatek,mt8173-disp-aal";
1160 reg = <0 0x14015000 0 0x1000>;
1161 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1162 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1163 clocks = <&mmsys CLK_MM_DISP_AAL>;
1164 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
1168 compatible = "mediatek,mt8173-disp-gamma";
1169 reg = <0 0x14016000 0 0x1000>;
1170 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1171 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1172 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1173 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
1177 compatible = "mediatek,mt8173-disp-merge";
1178 reg = <0 0x14017000 0 0x1000>;
1179 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1180 clocks = <&mmsys CLK_MM_DISP_MERGE>;
1183 split0: split@14018000 {
1184 compatible = "mediatek,mt8173-disp-split";
1185 reg = <0 0x14018000 0 0x1000>;
1186 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1187 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1190 split1: split@14019000 {
1191 compatible = "mediatek,mt8173-disp-split";
1192 reg = <0 0x14019000 0 0x1000>;
1193 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1194 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1198 compatible = "mediatek,mt8173-disp-ufoe";
1199 reg = <0 0x1401a000 0 0x1000>;
1200 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1201 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1202 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1203 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
1206 dsi0: dsi@1401b000 {
1207 compatible = "mediatek,mt8173-dsi";
1208 reg = <0 0x1401b000 0 0x1000>;
1209 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1210 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1211 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1212 <&mmsys CLK_MM_DSI0_DIGITAL>,
1214 clock-names = "engine", "digital", "hs";
1215 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
1218 status = "disabled";
1221 dsi1: dsi@1401c000 {
1222 compatible = "mediatek,mt8173-dsi";
1223 reg = <0 0x1401c000 0 0x1000>;
1224 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1225 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1226 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1227 <&mmsys CLK_MM_DSI1_DIGITAL>,
1229 clock-names = "engine", "digital", "hs";
1232 status = "disabled";
1235 dpi0: dpi@1401d000 {
1236 compatible = "mediatek,mt8173-dpi";
1237 reg = <0 0x1401d000 0 0x1000>;
1238 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1239 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1240 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1241 <&mmsys CLK_MM_DPI_ENGINE>,
1242 <&apmixedsys CLK_APMIXED_TVDPLL>;
1243 clock-names = "pixel", "engine", "pll";
1244 status = "disabled";
1247 dpi0_out: endpoint {
1248 remote-endpoint = <&hdmi0_in>;
1253 pwm0: pwm@1401e000 {
1254 compatible = "mediatek,mt8173-disp-pwm",
1255 "mediatek,mt6595-disp-pwm";
1256 reg = <0 0x1401e000 0 0x1000>;
1258 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1259 <&mmsys CLK_MM_DISP_PWM0MM>;
1260 clock-names = "main", "mm";
1261 status = "disabled";
1264 pwm1: pwm@1401f000 {
1265 compatible = "mediatek,mt8173-disp-pwm",
1266 "mediatek,mt6595-disp-pwm";
1267 reg = <0 0x1401f000 0 0x1000>;
1269 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1270 <&mmsys CLK_MM_DISP_PWM1MM>;
1271 clock-names = "main", "mm";
1272 status = "disabled";
1275 mutex: mutex@14020000 {
1276 compatible = "mediatek,mt8173-disp-mutex";
1277 reg = <0 0x14020000 0 0x1000>;
1278 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1279 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1280 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1281 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>;
1282 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
1283 <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
1286 larb0: larb@14021000 {
1287 compatible = "mediatek,mt8173-smi-larb";
1288 reg = <0 0x14021000 0 0x1000>;
1289 mediatek,smi = <&smi_common>;
1290 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1291 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1292 <&mmsys CLK_MM_SMI_LARB0>;
1293 clock-names = "apb", "smi";
1296 smi_common: smi@14022000 {
1297 compatible = "mediatek,mt8173-smi-common";
1298 reg = <0 0x14022000 0 0x1000>;
1299 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1300 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1301 <&mmsys CLK_MM_SMI_COMMON>;
1302 clock-names = "apb", "smi";
1306 compatible = "mediatek,mt8173-disp-od";
1307 reg = <0 0x14023000 0 0x1000>;
1308 clocks = <&mmsys CLK_MM_DISP_OD>;
1309 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>;
1312 hdmi0: hdmi@14025000 {
1313 compatible = "mediatek,mt8173-hdmi";
1314 reg = <0 0x14025000 0 0x400>;
1315 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1316 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1317 <&mmsys CLK_MM_HDMI_PLLCK>,
1318 <&mmsys CLK_MM_HDMI_AUDIO>,
1319 <&mmsys CLK_MM_HDMI_SPDIF>;
1320 clock-names = "pixel", "pll", "bclk", "spdif";
1321 pinctrl-names = "default";
1322 pinctrl-0 = <&hdmi_pin>;
1325 mediatek,syscon-hdmi = <&mmsys 0x900>;
1326 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1327 assigned-clock-parents = <&hdmi_phy>;
1328 status = "disabled";
1331 #address-cells = <1>;
1337 hdmi0_in: endpoint {
1338 remote-endpoint = <&dpi0_out>;
1344 larb4: larb@14027000 {
1345 compatible = "mediatek,mt8173-smi-larb";
1346 reg = <0 0x14027000 0 0x1000>;
1347 mediatek,smi = <&smi_common>;
1348 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
1349 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1350 <&mmsys CLK_MM_SMI_LARB4>;
1351 clock-names = "apb", "smi";
1354 imgsys: clock-controller@15000000 {
1355 compatible = "mediatek,mt8173-imgsys", "syscon";
1356 reg = <0 0x15000000 0 0x1000>;
1360 larb2: larb@15001000 {
1361 compatible = "mediatek,mt8173-smi-larb";
1362 reg = <0 0x15001000 0 0x1000>;
1363 mediatek,smi = <&smi_common>;
1364 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>;
1365 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1366 <&imgsys CLK_IMG_LARB2_SMI>;
1367 clock-names = "apb", "smi";
1370 vdecsys: clock-controller@16000000 {
1371 compatible = "mediatek,mt8173-vdecsys", "syscon";
1372 reg = <0 0x16000000 0 0x1000>;
1376 vcodec_dec: vcodec@16000000 {
1377 compatible = "mediatek,mt8173-vcodec-dec";
1378 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1379 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1380 <0 0x16021000 0 0x800>, /* VDEC_LD */
1381 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1382 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1383 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1384 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1385 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1386 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1387 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1388 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1389 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1390 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1391 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1392 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1393 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1394 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1395 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1396 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1397 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1398 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1399 mediatek,vpu = <&vpu>;
1400 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1401 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1402 <&topckgen CLK_TOP_UNIVPLL_D2>,
1403 <&topckgen CLK_TOP_CCI400_SEL>,
1404 <&topckgen CLK_TOP_VDEC_SEL>,
1405 <&topckgen CLK_TOP_VCODECPLL>,
1406 <&apmixedsys CLK_APMIXED_VENCPLL>,
1407 <&topckgen CLK_TOP_VENC_LT_SEL>,
1408 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1409 clock-names = "vcodecpll",
1417 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
1418 <&topckgen CLK_TOP_CCI400_SEL>,
1419 <&topckgen CLK_TOP_VDEC_SEL>,
1420 <&apmixedsys CLK_APMIXED_VCODECPLL>,
1421 <&apmixedsys CLK_APMIXED_VENCPLL>;
1422 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
1423 <&topckgen CLK_TOP_UNIVPLL_D2>,
1424 <&topckgen CLK_TOP_VCODECPLL>;
1425 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
1428 larb1: larb@16010000 {
1429 compatible = "mediatek,mt8173-smi-larb";
1430 reg = <0 0x16010000 0 0x1000>;
1431 mediatek,smi = <&smi_common>;
1432 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>;
1433 clocks = <&vdecsys CLK_VDEC_CKEN>,
1434 <&vdecsys CLK_VDEC_LARB_CKEN>;
1435 clock-names = "apb", "smi";
1438 vencsys: clock-controller@18000000 {
1439 compatible = "mediatek,mt8173-vencsys", "syscon";
1440 reg = <0 0x18000000 0 0x1000>;
1444 larb3: larb@18001000 {
1445 compatible = "mediatek,mt8173-smi-larb";
1446 reg = <0 0x18001000 0 0x1000>;
1447 mediatek,smi = <&smi_common>;
1448 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1449 clocks = <&vencsys CLK_VENC_CKE1>,
1450 <&vencsys CLK_VENC_CKE0>;
1451 clock-names = "apb", "smi";
1454 vcodec_enc_avc: vcodec@18002000 {
1455 compatible = "mediatek,mt8173-vcodec-enc";
1456 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
1457 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1458 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1459 <&iommu M4U_PORT_VENC_REC>,
1460 <&iommu M4U_PORT_VENC_BSDMA>,
1461 <&iommu M4U_PORT_VENC_SV_COMV>,
1462 <&iommu M4U_PORT_VENC_RD_COMV>,
1463 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1464 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1465 <&iommu M4U_PORT_VENC_REF_LUMA>,
1466 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1467 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1468 <&iommu M4U_PORT_VENC_NBM_WDMA>;
1469 mediatek,vpu = <&vpu>;
1470 clocks = <&topckgen CLK_TOP_VENC_SEL>;
1471 clock-names = "venc_sel";
1472 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
1473 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
1474 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1477 jpegdec: jpegdec@18004000 {
1478 compatible = "mediatek,mt8173-jpgdec";
1479 reg = <0 0x18004000 0 0x1000>;
1480 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
1481 clocks = <&vencsys CLK_VENC_CKE0>,
1482 <&vencsys CLK_VENC_CKE3>;
1483 clock-names = "jpgdec-smi",
1485 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>;
1486 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>,
1487 <&iommu M4U_PORT_JPGDEC_BSDMA>;
1490 vencltsys: clock-controller@19000000 {
1491 compatible = "mediatek,mt8173-vencltsys", "syscon";
1492 reg = <0 0x19000000 0 0x1000>;
1496 larb5: larb@19001000 {
1497 compatible = "mediatek,mt8173-smi-larb";
1498 reg = <0 0x19001000 0 0x1000>;
1499 mediatek,smi = <&smi_common>;
1500 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>;
1501 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1502 <&vencltsys CLK_VENCLT_CKE0>;
1503 clock-names = "apb", "smi";
1506 vcodec_enc_vp8: vcodec@19002000 {
1507 compatible = "mediatek,mt8173-vcodec-enc-vp8";
1508 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1509 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1510 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
1511 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1512 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1513 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1514 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1515 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1516 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1517 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1518 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1519 mediatek,vpu = <&vpu>;
1520 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1521 clock-names = "venc_lt_sel";
1522 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
1523 assigned-clock-parents =
1524 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1525 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;