arch/arm64/boot/dts/mediatek/mt7986a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2021 MediaTek Inc.
   4  * Author: Sam.Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7986-clk.h>
  10
  11 / {
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         clk40m: oscillator@0 {
  17                 compatible = "fixed-clock";
  18                 clock-frequency = <40000000>;
  19                 #clock-cells = <0>;
  20                 clock-output-names = "clkxtal";
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a53";
  29                         enable-method = "psci";
  30                         reg = <0x0>;
  31                         #cooling-cells = <2>;
  32                 };
  33
  34                 cpu1: cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53";
  37                         enable-method = "psci";
  38                         reg = <0x1>;
  39                         #cooling-cells = <2>;
  40                 };
  41
  42                 cpu2: cpu@2 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53";
  45                         enable-method = "psci";
  46                         reg = <0x2>;
  47                         #cooling-cells = <2>;
  48                 };
  49
  50                 cpu3: cpu@3 {
  51                         device_type = "cpu";
  52                         enable-method = "psci";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x3>;
  55                         #cooling-cells = <2>;
  56                 };
  57         };
  58
  59         psci {
  60                 compatible  = "arm,psci-0.2";
  61                 method      = "smc";
  62         };
  63
  64         reserved-memory {
  65                 #address-cells = <2>;
  66                 #size-cells = <2>;
  67                 ranges;
  68                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
  69                 secmon_reserved: secmon@43000000 {
  70                         reg = <0 0x43000000 0 0x30000>;
  71                         no-map;
  72                 };
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv8-timer";
  77                 interrupt-parent = <&gic>;
  78                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  79                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  80                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  81                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  82         };
  83
  84         soc {
  85                 #address-cells = <2>;
  86                 #size-cells = <2>;
  87                 compatible = "simple-bus";
  88                 ranges;
  89
  90                 gic: interrupt-controller@c000000 {
  91                         compatible = "arm,gic-v3";
  92                         #interrupt-cells = <3>;
  93                         interrupt-parent = <&gic>;
  94                         interrupt-controller;
  95                         reg = <0 0x0c000000 0 0x10000>,  /* GICD */
  96                               <0 0x0c080000 0 0x80000>,  /* GICR */
  97                               <0 0x0c400000 0 0x2000>,   /* GICC */
  98                               <0 0x0c410000 0 0x1000>,   /* GICH */
  99                               <0 0x0c420000 0 0x2000>;   /* GICV */
 100                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 101                 };
 102
 103                 infracfg: infracfg@10001000 {
 104                         compatible = "mediatek,mt7986-infracfg", "syscon";
 105                         reg = <0 0x10001000 0 0x1000>;
 106                         #clock-cells = <1>;
 107                 };
 108
 109                 topckgen: topckgen@1001b000 {
 110                         compatible = "mediatek,mt7986-topckgen", "syscon";
 111                         reg = <0 0x1001B000 0 0x1000>;
 112                         #clock-cells = <1>;
 113                 };
 114
 115                 watchdog: watchdog@1001c000 {
 116                         compatible = "mediatek,mt7986-wdt",
 117                                      "mediatek,mt6589-wdt";
 118                         reg = <0 0x1001c000 0 0x1000>;
 119                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 120                         #reset-cells = <1>;
 121                         status = "disabled";
 122                 };
 123
 124                 apmixedsys: apmixedsys@1001e000 {
 125                         compatible = "mediatek,mt7986-apmixedsys";
 126                         reg = <0 0x1001E000 0 0x1000>;
 127                         #clock-cells = <1>;
 128                 };
 129
 130                 pio: pinctrl@1001f000 {
 131                         compatible = "mediatek,mt7986a-pinctrl";
 132                         reg = <0 0x1001f000 0 0x1000>,
 133                               <0 0x11c30000 0 0x1000>,
 134                               <0 0x11c40000 0 0x1000>,
 135                               <0 0x11e20000 0 0x1000>,
 136                               <0 0x11e30000 0 0x1000>,
 137                               <0 0x11f00000 0 0x1000>,
 138                               <0 0x11f10000 0 0x1000>,
 139                               <0 0x1000b000 0 0x1000>;
 140                         reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
 141                                     "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
 142                         gpio-controller;
 143                         #gpio-cells = <2>;
 144                         gpio-ranges = <&pio 0 0 100>;
 145                         interrupt-controller;
 146                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 147                         interrupt-parent = <&gic>;
 148                         #interrupt-cells = <2>;
 149                 };
 150
 151                 sgmiisys0: syscon@10060000 {
 152                         compatible = "mediatek,mt7986-sgmiisys_0",
 153                                      "syscon";
 154                         reg = <0 0x10060000 0 0x1000>;
 155                         #clock-cells = <1>;
 156                 };
 157
 158                 sgmiisys1: syscon@10070000 {
 159                         compatible = "mediatek,mt7986-sgmiisys_1",
 160                                      "syscon";
 161                         reg = <0 0x10070000 0 0x1000>;
 162                         #clock-cells = <1>;
 163                 };
 164
 165                 trng: trng@1020f000 {
 166                         compatible = "mediatek,mt7986-rng",
 167                                      "mediatek,mt7623-rng";
 168                         reg = <0 0x1020f000 0 0x100>;
 169                         clocks = <&infracfg CLK_INFRA_TRNG_CK>;
 170                         clock-names = "rng";
 171                         status = "disabled";
 172                 };
 173
 174                 uart0: serial@11002000 {
 175                         compatible = "mediatek,mt7986-uart",
 176                                      "mediatek,mt6577-uart";
 177                         reg = <0 0x11002000 0 0x400>;
 178                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 179                         clocks = <&infracfg CLK_INFRA_UART0_SEL>,
 180                                  <&infracfg CLK_INFRA_UART0_CK>;
 181                         clock-names = "baud", "bus";
 182                         assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
 183                                           <&infracfg CLK_INFRA_UART0_SEL>;
 184                         assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
 185                                                  <&topckgen CLK_TOP_UART_SEL>;
 186                         status = "disabled";
 187                 };
 188
 189                 uart1: serial@11003000 {
 190                         compatible = "mediatek,mt7986-uart",
 191                                      "mediatek,mt6577-uart";
 192                         reg = <0 0x11003000 0 0x400>;
 193                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 194                         clocks = <&infracfg CLK_INFRA_UART1_SEL>,
 195                                  <&infracfg CLK_INFRA_UART1_CK>;
 196                         clock-names = "baud", "bus";
 197                         assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
 198                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 199                         status = "disabled";
 200                 };
 201
 202                 uart2: serial@11004000 {
 203                         compatible = "mediatek,mt7986-uart",
 204                                      "mediatek,mt6577-uart";
 205                         reg = <0 0x11004000 0 0x400>;
 206                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&infracfg CLK_INFRA_UART2_SEL>,
 208                                  <&infracfg CLK_INFRA_UART2_CK>;
 209                         clock-names = "baud", "bus";
 210                         assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
 211                         assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
 212                         status = "disabled";
 213                 };
 214
 215                 ethsys: syscon@15000000 {
 216                          #address-cells = <1>;
 217                          #size-cells = <1>;
 218                          compatible = "mediatek,mt7986-ethsys",
 219                                       "syscon";
 220                          reg = <0 0x15000000 0 0x1000>;
 221                          #clock-cells = <1>;
 222                          #reset-cells = <1>;
 223                 };
 224
 225         };
 226
 227 };