1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Authors: Sam.Shih <sam.shih@mediatek.com>
5 * Frank Wunderlich <frank-w@public-files.de>
6 * Daniel Golle <daniel@makrotopia.org>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
15 #include "mt7986a.dtsi"
18 model = "Bananapi BPI-R3";
19 chassis-type = "embedded";
20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
29 stdout-path = "serial0:115200n8";
32 dcin: regulator-12vd {
33 compatible = "regulator-fixed";
34 regulator-name = "12vd";
35 regulator-min-microvolt = <12000000>;
36 regulator-max-microvolt = <12000000>;
42 compatible = "pwm-fan";
44 /* cooling level (0, 1, 2) - pwm inverted */
45 cooling-levels = <255 96 0>;
46 pwms = <&pwm 0 10000 0>;
51 compatible = "gpio-keys";
55 linux,code = <KEY_RESTART>;
56 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_WPS_BUTTON>;
62 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
66 /* i2c of the left SFP cage (wan) */
67 i2c_sfp1: i2c-gpio-0 {
68 compatible = "i2c-gpio";
69 sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
70 scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
71 i2c-gpio,delay-us = <2>;
76 /* i2c of the right SFP cage (lan) */
77 i2c_sfp2: i2c-gpio-1 {
78 compatible = "i2c-gpio";
79 sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
80 scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
81 i2c-gpio,delay-us = <2>;
87 compatible = "gpio-leds";
90 color = <LED_COLOR_ID_GREEN>;
91 function = LED_FUNCTION_POWER;
92 gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
97 color = <LED_COLOR_ID_BLUE>;
98 function = LED_FUNCTION_STATUS;
99 gpios = <&pio 86 GPIO_ACTIVE_HIGH>;
100 default-state = "off";
104 reg_1p8v: regulator-1p8v {
105 compatible = "regulator-fixed";
106 regulator-name = "1.8vd";
107 regulator-min-microvolt = <1800000>;
108 regulator-max-microvolt = <1800000>;
111 vin-supply = <&dcin>;
114 reg_3p3v: regulator-3p3v {
115 compatible = "regulator-fixed";
116 regulator-name = "3.3vd";
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
121 vin-supply = <&dcin>;
124 /* left SFP cage (wan) */
126 compatible = "sff,sfp";
127 i2c-bus = <&i2c_sfp1>;
128 los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
129 mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
130 tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
131 tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
134 /* right SFP cage (lan) */
136 compatible = "sff,sfp";
137 i2c-bus = <&i2c_sfp2>;
138 los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
139 mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
140 tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
141 tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
148 /* active: set fan to cooling level 2 */
149 cooling-device = <&fan 2 2>;
150 trip = <&cpu_trip_active_high>;
154 /* active: set fan to cooling level 1 */
155 cooling-device = <&fan 1 1>;
156 trip = <&cpu_trip_active_low>;
160 /* passive: set fan to cooling level 0 */
161 cooling-device = <&fan 0 0>;
162 trip = <&cpu_trip_passive>;
175 compatible = "mediatek,eth-mac";
177 phy-mode = "2500base-x";
187 compatible = "mediatek,eth-mac";
189 phy-mode = "2500base-x";
191 managed = "in-band-status";
195 #address-cells = <1>;
202 compatible = "mediatek,mt7531";
204 interrupt-controller;
205 #interrupt-cells = <1>;
206 interrupt-parent = <&pio>;
207 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
208 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
213 pinctrl-names = "default", "state_uhs";
214 pinctrl-0 = <&mmc0_pins_default>;
215 pinctrl-1 = <&mmc0_pins_uhs>;
216 vmmc-supply = <®_3p3v>;
217 vqmmc-supply = <®_1p8v>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&i2c_pins>;
227 pinctrl-names = "default";
228 pinctrl-0 = <&pcie_pins>;
244 mmc0_pins_default: mmc0-pins {
250 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
251 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
252 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
254 drive-strength = <4>;
255 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
259 drive-strength = <6>;
260 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
264 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
268 drive-strength = <4>;
269 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
273 mmc0_pins_uhs: mmc0-uhs-pins {
279 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
280 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
281 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
283 drive-strength = <4>;
284 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
288 drive-strength = <6>;
289 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
293 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
297 drive-strength = <4>;
298 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
302 pcie_pins: pcie-pins {
305 groups = "pcie_clk", "pcie_pereset";
312 groups = "pwm0", "pwm1_0";
316 spi_flash_pins: spi-flash-pins {
319 groups = "spi0", "spi0_wp_hold";
323 spic_pins: spic-pins {
330 uart1_pins: uart1-pins {
333 groups = "uart1_rx_tx";
337 uart2_pins: uart2-pins {
340 groups = "uart2_0_rx_tx";
344 wf_2g_5g_pins: wf-2g-5g-pins {
347 groups = "wf_2g", "wf_5g";
350 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
351 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
352 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
353 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
354 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
355 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
356 "WF1_TOP_CLK", "WF1_TOP_DATA";
357 drive-strength = <4>;
361 wf_dbdc_pins: wf-dbdc-pins {
367 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
368 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
369 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
370 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
371 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
372 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
373 "WF1_TOP_CLK", "WF1_TOP_DATA";
374 drive-strength = <4>;
378 wf_led_pins: wf-led-pins {
387 pinctrl-names = "default";
388 pinctrl-0 = <&pwm_pins>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&spi_flash_pins>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&spic_pins>;
410 #address-cells = <1>;
441 phy-mode = "2500base-x";
443 managed = "in-band-status";
450 phy-mode = "2500base-x";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart1_pins>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&uart2_pins>;
491 pinctrl-names = "default", "dbdc";
492 pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
493 pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;