2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
73 compatible = "arm,cortex-a53";
75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
83 next-level-cache = <&L2>;
88 compatible = "arm,cortex-a53";
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
91 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
92 clock-names = "cpu", "intermediate";
93 operating-points-v2 = <&cpu_opp_table>;
95 enable-method = "psci";
96 clock-frequency = <1300000000>;
97 cci-control-port = <&cci_control2>;
98 next-level-cache = <&L2>;
102 compatible = "cache";
107 pwrap_clk: dummy40m {
108 compatible = "fixed-clock";
109 clock-frequency = <40000000>;
114 compatible = "fixed-clock";
116 clock-frequency = <25000000>;
117 clock-output-names = "clkxtal";
121 compatible = "arm,psci-0.2";
126 compatible = "arm,cortex-a53-pmu";
127 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
129 interrupt-affinity = <&cpu0>, <&cpu1>;
133 #address-cells = <2>;
137 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
138 secmon_reserved: secmon@43000000 {
139 reg = <0 0x43000000 0 0x30000>;
145 cpu_thermal: cpu-thermal {
146 polling-delay-passive = <1000>;
147 polling-delay = <1000>;
149 thermal-sensors = <&thermal 0>;
152 cpu_passive: cpu-passive {
153 temperature = <47000>;
158 cpu_active: cpu-active {
159 temperature = <67000>;
165 temperature = <87000>;
171 temperature = <107000>;
179 trip = <&cpu_passive>;
180 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
181 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
185 trip = <&cpu_active>;
186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
192 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
200 compatible = "arm,armv8-timer";
201 interrupt-parent = <&gic>;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
203 IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
205 IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
207 IRQ_TYPE_LEVEL_HIGH)>,
208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
209 IRQ_TYPE_LEVEL_HIGH)>;
212 infracfg: infracfg@10000000 {
213 compatible = "mediatek,mt7622-infracfg",
215 reg = <0 0x10000000 0 0x1000>;
220 pwrap: pwrap@10001000 {
221 compatible = "mediatek,mt7622-pwrap";
222 reg = <0 0x10001000 0 0x250>;
224 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
225 clock-names = "spi", "wrap";
226 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
227 reset-names = "pwrap";
228 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
232 pericfg: pericfg@10002000 {
233 compatible = "mediatek,mt7622-pericfg",
235 reg = <0 0x10002000 0 0x1000>;
240 scpsys: power-controller@10006000 {
241 compatible = "mediatek,mt7622-scpsys",
243 #power-domain-cells = <1>;
244 reg = <0 0x10006000 0 0x1000>;
245 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
246 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
247 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
248 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
249 infracfg = <&infracfg>;
250 clocks = <&topckgen CLK_TOP_HIF_SEL>;
251 clock-names = "hif_sel";
255 compatible = "mediatek,mt7622-cir";
256 reg = <0 0x10009000 0 0x1000>;
257 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
258 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
259 <&topckgen CLK_TOP_AXI_SEL>;
260 clock-names = "clk", "bus";
264 sysirq: interrupt-controller@10200620 {
265 compatible = "mediatek,mt7622-sysirq",
266 "mediatek,mt6577-sysirq";
267 interrupt-controller;
268 #interrupt-cells = <3>;
269 interrupt-parent = <&gic>;
270 reg = <0 0x10200620 0 0x20>;
273 efuse: efuse@10206000 {
274 compatible = "mediatek,mt7622-efuse",
276 reg = <0 0x10206000 0 0x1000>;
277 #address-cells = <1>;
280 thermal_calibration: calib@198 {
285 apmixedsys: apmixedsys@10209000 {
286 compatible = "mediatek,mt7622-apmixedsys",
288 reg = <0 0x10209000 0 0x1000>;
292 topckgen: topckgen@10210000 {
293 compatible = "mediatek,mt7622-topckgen",
295 reg = <0 0x10210000 0 0x1000>;
300 compatible = "mediatek,mt7622-rng",
301 "mediatek,mt7623-rng";
302 reg = <0 0x1020f000 0 0x1000>;
303 clocks = <&infracfg CLK_INFRA_TRNG>;
307 pio: pinctrl@10211000 {
308 compatible = "mediatek,mt7622-pinctrl";
309 reg = <0 0x10211000 0 0x1000>,
310 <0 0x10005000 0 0x1000>;
311 reg-names = "base", "eint";
314 gpio-ranges = <&pio 0 0 103>;
315 interrupt-controller;
316 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
317 interrupt-parent = <&gic>;
318 #interrupt-cells = <2>;
321 watchdog: watchdog@10212000 {
322 compatible = "mediatek,mt7622-wdt",
323 "mediatek,mt6589-wdt";
324 reg = <0 0x10212000 0 0x800>;
328 compatible = "mediatek,mt7622-rtc",
330 reg = <0 0x10212800 0 0x200>;
331 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
332 clocks = <&topckgen CLK_TOP_RTC>;
336 gic: interrupt-controller@10300000 {
337 compatible = "arm,gic-400";
338 interrupt-controller;
339 #interrupt-cells = <3>;
340 interrupt-parent = <&gic>;
341 reg = <0 0x10310000 0 0x1000>,
342 <0 0x10320000 0 0x1000>,
343 <0 0x10340000 0 0x2000>,
344 <0 0x10360000 0 0x2000>;
348 compatible = "arm,cci-400";
349 #address-cells = <1>;
351 reg = <0 0x10390000 0 0x1000>;
352 ranges = <0 0 0x10390000 0x10000>;
354 cci_control0: slave-if@1000 {
355 compatible = "arm,cci-400-ctrl-if";
356 interface-type = "ace-lite";
357 reg = <0x1000 0x1000>;
360 cci_control1: slave-if@4000 {
361 compatible = "arm,cci-400-ctrl-if";
362 interface-type = "ace";
363 reg = <0x4000 0x1000>;
366 cci_control2: slave-if@5000 {
367 compatible = "arm,cci-400-ctrl-if", "syscon";
368 interface-type = "ace";
369 reg = <0x5000 0x1000>;
373 compatible = "arm,cci-400-pmu,r1";
374 reg = <0x9000 0x5000>;
375 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
383 auxadc: adc@11001000 {
384 compatible = "mediatek,mt7622-auxadc";
385 reg = <0 0x11001000 0 0x1000>;
386 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
387 clock-names = "main";
388 #io-channel-cells = <1>;
391 uart0: serial@11002000 {
392 compatible = "mediatek,mt7622-uart",
393 "mediatek,mt6577-uart";
394 reg = <0 0x11002000 0 0x400>;
395 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
396 clocks = <&topckgen CLK_TOP_UART_SEL>,
397 <&pericfg CLK_PERI_UART0_PD>;
398 clock-names = "baud", "bus";
402 uart1: serial@11003000 {
403 compatible = "mediatek,mt7622-uart",
404 "mediatek,mt6577-uart";
405 reg = <0 0x11003000 0 0x400>;
406 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
408 <&pericfg CLK_PERI_UART1_PD>;
409 clock-names = "baud", "bus";
413 uart2: serial@11004000 {
414 compatible = "mediatek,mt7622-uart",
415 "mediatek,mt6577-uart";
416 reg = <0 0x11004000 0 0x400>;
417 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
419 <&pericfg CLK_PERI_UART2_PD>;
420 clock-names = "baud", "bus";
424 uart3: serial@11005000 {
425 compatible = "mediatek,mt7622-uart",
426 "mediatek,mt6577-uart";
427 reg = <0 0x11005000 0 0x400>;
428 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
430 <&pericfg CLK_PERI_UART3_PD>;
431 clock-names = "baud", "bus";
436 compatible = "mediatek,mt7622-pwm";
437 reg = <0 0x11006000 0 0x1000>;
439 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
440 clocks = <&topckgen CLK_TOP_PWM_SEL>,
441 <&pericfg CLK_PERI_PWM_PD>,
442 <&pericfg CLK_PERI_PWM1_PD>,
443 <&pericfg CLK_PERI_PWM2_PD>,
444 <&pericfg CLK_PERI_PWM3_PD>,
445 <&pericfg CLK_PERI_PWM4_PD>,
446 <&pericfg CLK_PERI_PWM5_PD>,
447 <&pericfg CLK_PERI_PWM6_PD>;
448 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
454 compatible = "mediatek,mt7622-i2c";
455 reg = <0 0x11007000 0 0x90>,
456 <0 0x11000100 0 0x80>;
457 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
459 clocks = <&pericfg CLK_PERI_I2C0_PD>,
460 <&pericfg CLK_PERI_AP_DMA_PD>;
461 clock-names = "main", "dma";
462 #address-cells = <1>;
468 compatible = "mediatek,mt7622-i2c";
469 reg = <0 0x11008000 0 0x90>,
470 <0 0x11000180 0 0x80>;
471 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
473 clocks = <&pericfg CLK_PERI_I2C1_PD>,
474 <&pericfg CLK_PERI_AP_DMA_PD>;
475 clock-names = "main", "dma";
476 #address-cells = <1>;
482 compatible = "mediatek,mt7622-i2c";
483 reg = <0 0x11009000 0 0x90>,
484 <0 0x11000200 0 0x80>;
485 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
487 clocks = <&pericfg CLK_PERI_I2C2_PD>,
488 <&pericfg CLK_PERI_AP_DMA_PD>;
489 clock-names = "main", "dma";
490 #address-cells = <1>;
496 compatible = "mediatek,mt7622-spi";
497 reg = <0 0x1100a000 0 0x100>;
498 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
499 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
500 <&topckgen CLK_TOP_SPI0_SEL>,
501 <&pericfg CLK_PERI_SPI0_PD>;
502 clock-names = "parent-clk", "sel-clk", "spi-clk";
503 #address-cells = <1>;
508 thermal: thermal@1100b000 {
509 #thermal-sensor-cells = <1>;
510 compatible = "mediatek,mt7622-thermal";
511 reg = <0 0x1100b000 0 0x1000>;
512 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
513 clocks = <&pericfg CLK_PERI_THERM_PD>,
514 <&pericfg CLK_PERI_AUXADC_PD>;
515 clock-names = "therm", "auxadc";
516 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
517 reset-names = "therm";
518 mediatek,auxadc = <&auxadc>;
519 mediatek,apmixedsys = <&apmixedsys>;
520 nvmem-cells = <&thermal_calibration>;
521 nvmem-cell-names = "calibration-data";
524 btif: serial@1100c000 {
525 compatible = "mediatek,mt7622-btif",
527 reg = <0 0x1100c000 0 0x1000>;
528 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
529 clocks = <&pericfg CLK_PERI_BTIF_PD>;
530 clock-names = "main";
536 compatible = "mediatek,mt7622-bluetooth";
537 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
543 nandc: nfi@1100d000 {
544 compatible = "mediatek,mt7622-nfc";
545 reg = <0 0x1100D000 0 0x1000>;
546 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
547 clocks = <&pericfg CLK_PERI_NFI_PD>,
548 <&pericfg CLK_PERI_SNFI_PD>;
549 clock-names = "nfi_clk", "pad_clk";
551 #address-cells = <1>;
557 compatible = "mediatek,mt7622-snand";
558 reg = <0 0x1100d000 0 0x1000>;
559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
560 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
561 clock-names = "nfi_clk", "pad_clk";
562 nand-ecc-engine = <&bch>;
563 #address-cells = <1>;
569 compatible = "mediatek,mt7622-ecc";
570 reg = <0 0x1100e000 0 0x1000>;
571 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
572 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
573 clock-names = "nfiecc_clk";
577 nor_flash: spi@11014000 {
578 compatible = "mediatek,mt7622-nor",
579 "mediatek,mt8173-nor";
580 reg = <0 0x11014000 0 0xe0>;
581 clocks = <&pericfg CLK_PERI_FLASH_PD>,
582 <&topckgen CLK_TOP_FLASH_SEL>;
583 clock-names = "spi", "sf";
584 #address-cells = <1>;
590 compatible = "mediatek,mt7622-spi";
591 reg = <0 0x11016000 0 0x100>;
592 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
593 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
594 <&topckgen CLK_TOP_SPI1_SEL>,
595 <&pericfg CLK_PERI_SPI1_PD>;
596 clock-names = "parent-clk", "sel-clk", "spi-clk";
597 #address-cells = <1>;
602 uart4: serial@11019000 {
603 compatible = "mediatek,mt7622-uart",
604 "mediatek,mt6577-uart";
605 reg = <0 0x11019000 0 0x400>;
606 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
607 clocks = <&topckgen CLK_TOP_UART_SEL>,
608 <&pericfg CLK_PERI_UART4_PD>;
609 clock-names = "baud", "bus";
613 audsys: clock-controller@11220000 {
614 compatible = "mediatek,mt7622-audsys", "syscon";
615 reg = <0 0x11220000 0 0x2000>;
618 afe: audio-controller {
619 compatible = "mediatek,mt7622-audio";
620 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
621 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
622 interrupt-names = "afe", "asys";
624 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
625 <&topckgen CLK_TOP_AUD1_SEL>,
626 <&topckgen CLK_TOP_AUD2_SEL>,
627 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
628 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
629 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
630 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
631 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
632 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
633 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
634 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
635 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
636 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
637 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
638 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
639 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
640 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
641 <&audsys CLK_AUDIO_I2SO1>,
642 <&audsys CLK_AUDIO_I2SO2>,
643 <&audsys CLK_AUDIO_I2SO3>,
644 <&audsys CLK_AUDIO_I2SO4>,
645 <&audsys CLK_AUDIO_I2SIN1>,
646 <&audsys CLK_AUDIO_I2SIN2>,
647 <&audsys CLK_AUDIO_I2SIN3>,
648 <&audsys CLK_AUDIO_I2SIN4>,
649 <&audsys CLK_AUDIO_ASRCO1>,
650 <&audsys CLK_AUDIO_ASRCO2>,
651 <&audsys CLK_AUDIO_ASRCO3>,
652 <&audsys CLK_AUDIO_ASRCO4>,
653 <&audsys CLK_AUDIO_AFE>,
654 <&audsys CLK_AUDIO_AFE_CONN>,
655 <&audsys CLK_AUDIO_A1SYS>,
656 <&audsys CLK_AUDIO_A2SYS>;
658 clock-names = "infra_sys_audio_clk",
659 "top_audio_mux1_sel",
660 "top_audio_mux2_sel",
661 "top_audio_a1sys_hp",
662 "top_audio_a2sys_hp",
692 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
693 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
694 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
695 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
696 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
697 <&topckgen CLK_TOP_AUD2PLL>;
698 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
703 compatible = "mediatek,mt7622-mmc";
704 reg = <0 0x11230000 0 0x1000>;
705 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
706 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
707 <&topckgen CLK_TOP_MSDC50_0_SEL>;
708 clock-names = "source", "hclk";
709 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>;
710 reset-names = "hrst";
715 compatible = "mediatek,mt7622-mmc";
716 reg = <0 0x11240000 0 0x1000>;
717 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
718 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
719 <&topckgen CLK_TOP_AXI_SEL>;
720 clock-names = "source", "hclk";
721 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>;
722 reset-names = "hrst";
726 wmac: wmac@18000000 {
727 compatible = "mediatek,mt7622-wmac";
728 reg = <0 0x18000000 0 0x100000>;
729 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
731 mediatek,infracfg = <&infracfg>;
734 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
737 ssusbsys: ssusbsys@1a000000 {
738 compatible = "mediatek,mt7622-ssusbsys",
740 reg = <0 0x1a000000 0 0x1000>;
745 ssusb: usb@1a0c0000 {
746 compatible = "mediatek,mt7622-xhci",
748 reg = <0 0x1a0c0000 0 0x01000>,
749 <0 0x1a0c4700 0 0x0100>;
750 reg-names = "mac", "ippc";
751 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
752 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
753 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
754 <&ssusbsys CLK_SSUSB_REF_EN>,
755 <&ssusbsys CLK_SSUSB_MCU_EN>,
756 <&ssusbsys CLK_SSUSB_DMA_EN>;
757 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
758 phys = <&u2port0 PHY_TYPE_USB2>,
759 <&u3port0 PHY_TYPE_USB3>,
760 <&u2port1 PHY_TYPE_USB2>;
765 u3phy: t-phy@1a0c4000 {
766 compatible = "mediatek,mt7622-tphy",
767 "mediatek,generic-tphy-v1";
768 reg = <0 0x1a0c4000 0 0x700>;
769 #address-cells = <2>;
774 u2port0: usb-phy@1a0c4800 {
775 reg = <0 0x1a0c4800 0 0x0100>;
777 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
781 u3port0: usb-phy@1a0c4900 {
782 reg = <0 0x1a0c4900 0 0x0700>;
788 u2port1: usb-phy@1a0c5000 {
789 reg = <0 0x1a0c5000 0 0x0100>;
791 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
796 pciesys: pciesys@1a100800 {
797 compatible = "mediatek,mt7622-pciesys",
799 reg = <0 0x1a100800 0 0x1000>;
804 pciecfg: pciecfg@1a140000 {
805 compatible = "mediatek,generic-pciecfg", "syscon";
806 reg = <0 0x1a140000 0 0x1000>;
809 pcie0: pcie@1a143000 {
810 compatible = "mediatek,mt7622-pcie";
812 reg = <0 0x1a143000 0 0x1000>;
814 linux,pci-domain = <0>;
815 #address-cells = <3>;
817 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
818 interrupt-names = "pcie_irq";
819 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
820 <&pciesys CLK_PCIE_P0_AHB_EN>,
821 <&pciesys CLK_PCIE_P0_AUX_EN>,
822 <&pciesys CLK_PCIE_P0_AXI_EN>,
823 <&pciesys CLK_PCIE_P0_OBFF_EN>,
824 <&pciesys CLK_PCIE_P0_PIPE_EN>;
825 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
826 "axi_ck0", "obff_ck0", "pipe_ck0";
828 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
829 bus-range = <0x00 0xff>;
830 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
833 #interrupt-cells = <1>;
834 interrupt-map-mask = <0 0 0 7>;
835 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
836 <0 0 0 2 &pcie_intc0 1>,
837 <0 0 0 3 &pcie_intc0 2>,
838 <0 0 0 4 &pcie_intc0 3>;
839 pcie_intc0: interrupt-controller {
840 interrupt-controller;
841 #address-cells = <0>;
842 #interrupt-cells = <1>;
846 pcie1: pcie@1a145000 {
847 compatible = "mediatek,mt7622-pcie";
849 reg = <0 0x1a145000 0 0x1000>;
851 linux,pci-domain = <1>;
852 #address-cells = <3>;
854 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
855 interrupt-names = "pcie_irq";
856 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
857 /* designer has connect RC1 with p0_ahb clock */
858 <&pciesys CLK_PCIE_P0_AHB_EN>,
859 <&pciesys CLK_PCIE_P1_AUX_EN>,
860 <&pciesys CLK_PCIE_P1_AXI_EN>,
861 <&pciesys CLK_PCIE_P1_OBFF_EN>,
862 <&pciesys CLK_PCIE_P1_PIPE_EN>;
863 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
864 "axi_ck1", "obff_ck1", "pipe_ck1";
866 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
867 bus-range = <0x00 0xff>;
868 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
871 #interrupt-cells = <1>;
872 interrupt-map-mask = <0 0 0 7>;
873 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
874 <0 0 0 2 &pcie_intc1 1>,
875 <0 0 0 3 &pcie_intc1 2>,
876 <0 0 0 4 &pcie_intc1 3>;
877 pcie_intc1: interrupt-controller {
878 interrupt-controller;
879 #address-cells = <0>;
880 #interrupt-cells = <1>;
884 sata: sata@1a200000 {
885 compatible = "mediatek,mt7622-ahci",
887 reg = <0 0x1a200000 0 0x1100>;
888 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-names = "hostc";
890 clocks = <&pciesys CLK_SATA_AHB_EN>,
891 <&pciesys CLK_SATA_AXI_EN>,
892 <&pciesys CLK_SATA_ASIC_EN>,
893 <&pciesys CLK_SATA_RBC_EN>,
894 <&pciesys CLK_SATA_PM_EN>;
895 clock-names = "ahb", "axi", "asic", "rbc", "pm";
896 phys = <&sata_port PHY_TYPE_SATA>;
897 phy-names = "sata-phy";
898 ports-implemented = <0x1>;
899 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
900 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
901 <&pciesys MT7622_SATA_PHY_SW_RST>,
902 <&pciesys MT7622_SATA_PHY_REG_RST>;
903 reset-names = "axi", "sw", "reg";
904 mediatek,phy-mode = <&pciesys>;
908 sata_phy: t-phy@1a243000 {
909 compatible = "mediatek,mt7622-tphy",
910 "mediatek,generic-tphy-v1";
911 #address-cells = <2>;
916 sata_port: sata-phy@1a243000 {
917 reg = <0 0x1a243000 0 0x0100>;
918 clocks = <&topckgen CLK_TOP_ETH_500M>;
924 hifsys: syscon@1af00000 {
925 compatible = "mediatek,mt7622-hifsys", "syscon";
926 reg = <0 0x1af00000 0 0x70>;
929 ethsys: syscon@1b000000 {
930 compatible = "mediatek,mt7622-ethsys",
932 reg = <0 0x1b000000 0 0x1000>;
937 hsdma: dma-controller@1b007000 {
938 compatible = "mediatek,mt7622-hsdma";
939 reg = <0 0x1b007000 0 0x1000>;
940 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
941 clocks = <ðsys CLK_ETH_HSDMA_EN>;
942 clock-names = "hsdma";
943 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
948 pcie_mirror: pcie-mirror@10000400 {
949 compatible = "mediatek,mt7622-pcie-mirror",
951 reg = <0 0x10000400 0 0x10>;
955 compatible = "mediatek,mt7622-wed",
957 reg = <0 0x1020a000 0 0x1000>;
958 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>;
962 compatible = "mediatek,mt7622-wed",
964 reg = <0 0x1020b000 0 0x1000>;
965 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
968 eth: ethernet@1b100000 {
969 compatible = "mediatek,mt7622-eth",
970 "mediatek,mt2701-eth",
972 reg = <0 0x1b100000 0 0x20000>;
973 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
974 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
975 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
976 clocks = <&topckgen CLK_TOP_ETH_SEL>,
977 <ðsys CLK_ETH_ESW_EN>,
978 <ðsys CLK_ETH_GP0_EN>,
979 <ðsys CLK_ETH_GP1_EN>,
980 <ðsys CLK_ETH_GP2_EN>,
981 <&sgmiisys CLK_SGMII_TX250M_EN>,
982 <&sgmiisys CLK_SGMII_RX250M_EN>,
983 <&sgmiisys CLK_SGMII_CDR_REF>,
984 <&sgmiisys CLK_SGMII_CDR_FB>,
985 <&topckgen CLK_TOP_SGMIIPLL>,
986 <&apmixedsys CLK_APMIXED_ETH2PLL>;
987 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
988 "sgmii_tx250m", "sgmii_rx250m",
989 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
991 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
992 mediatek,ethsys = <ðsys>;
993 mediatek,sgmiisys = <&sgmiisys>;
994 cci-control-port = <&cci_control2>;
995 mediatek,wed = <&wed0>, <&wed1>;
996 mediatek,pcie-mirror = <&pcie_mirror>;
997 mediatek,hifsys = <&hifsys>;
999 #address-cells = <1>;
1001 status = "disabled";
1004 sgmiisys: sgmiisys@1b128000 {
1005 compatible = "mediatek,mt7622-sgmiisys",
1007 reg = <0 0x1b128000 0 0x3000>;