2 * Copyright (c) 2018 MediaTek Inc.
3 * Author: Ryder Lee <ryder.lee@mediatek.com>
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "Bananapi BPI-R64";
18 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
25 stdout-path = "serial0:115200n8";
26 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
36 proc-supply = <&mt6380_vcpu_reg>;
37 sram-supply = <&mt6380_vm_reg>;
42 compatible = "gpio-keys";
47 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
52 linux,code = <KEY_WPS_BUTTON>;
53 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
58 compatible = "gpio-leds";
61 label = "bpi-r64:pio:green";
62 color = <LED_COLOR_ID_GREEN>;
63 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
64 default-state = "off";
68 label = "bpi-r64:pio:red";
69 color = <LED_COLOR_ID_RED>;
70 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
71 default-state = "off";
76 reg = <0 0x40000000 0 0x40000000>;
79 reg_1p8v: regulator-1p8v {
80 compatible = "regulator-fixed";
81 regulator-name = "fixed-1.8V";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
87 reg_3p3v: regulator-3p3v {
88 compatible = "regulator-fixed";
89 regulator-name = "fixed-3.3V";
90 regulator-min-microvolt = <3300000>;
91 regulator-max-microvolt = <3300000>;
96 reg_5v: regulator-5v {
97 compatible = "regulator-fixed";
98 regulator-name = "fixed-5V";
99 regulator-min-microvolt = <5000000>;
100 regulator-max-microvolt = <5000000>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&irrx_pins>;
123 compatible = "mediatek,eth-mac";
125 phy-mode = "2500base-x";
135 compatible = "mediatek,eth-mac";
147 #address-cells = <1>;
151 compatible = "mediatek,mt7531";
153 reset-gpios = <&pio 54 0>;
156 #address-cells = <1>;
188 phy-mode = "2500base-x";
203 pinctrl-names = "default";
204 pinctrl-0 = <&i2c1_pins>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&i2c2_pins>;
215 pinctrl-names = "default", "state_uhs";
216 pinctrl-0 = <&emmc_pins_default>;
217 pinctrl-1 = <&emmc_pins_uhs>;
220 max-frequency = <50000000>;
223 vmmc-supply = <®_3p3v>;
224 vqmmc-supply = <®_1p8v>;
225 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
226 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
231 pinctrl-names = "default", "state_uhs";
232 pinctrl-0 = <&sd0_pins_default>;
233 pinctrl-1 = <&sd0_pins_uhs>;
236 max-frequency = <50000000>;
238 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
239 vmmc-supply = <®_3p3v>;
240 vqmmc-supply = <®_3p3v>;
241 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
242 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
246 pinctrl-names = "default";
247 pinctrl-0 = <¶llel_nand_pins>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&spi_nor_pins>;
257 compatible = "jedec,spi-nor";
263 pinctrl-names = "default";
264 pinctrl-0 = <&pcie0_pins>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pcie1_pins>;
275 /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
276 * SATA functions. i.e. output-high: PCIe, output-low: SATA
280 gpios = <90 GPIO_ACTIVE_HIGH>;
284 /* eMMC is shared pin with parallel NAND */
285 emmc_pins_default: emmc-pins-default {
287 function = "emmc", "emmc_rst";
291 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
292 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
293 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
296 pins = "NDL0", "NDL1", "NDL2",
297 "NDL3", "NDL4", "NDL5",
298 "NDL6", "NDL7", "NRB";
309 emmc_pins_uhs: emmc-pins-uhs {
316 pins = "NDL0", "NDL1", "NDL2",
317 "NDL3", "NDL4", "NDL5",
318 "NDL6", "NDL7", "NRB";
320 drive-strength = <4>;
326 drive-strength = <4>;
334 groups = "mdc_mdio", "rgmii_via_gmac2";
338 i2c1_pins: i2c1-pins {
345 i2c2_pins: i2c2-pins {
352 i2s1_pins: i2s1-pins {
355 groups = "i2s_out_mclk_bclk_ws",
361 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
362 "I2S_WS", "I2S_MCLK";
363 drive-strength = <12>;
368 irrx_pins: irrx-pins {
375 irtx_pins: irtx-pins {
382 /* Parallel nand is shared pin with eMMC */
383 parallel_nand_pins: parallel-nand-pins {
390 pcie0_pins: pcie0-pins {
393 groups = "pcie0_pad_perst",
399 pcie1_pins: pcie1-pins {
402 groups = "pcie1_pad_perst",
408 pmic_bus_pins: pmic-bus-pins {
418 groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
419 "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
420 "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
421 "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
422 "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
423 "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
427 wled_pins: wled-pins {
434 sd0_pins_default: sd0-pins-default {
440 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
441 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
442 * DAT2, DAT3, CMD, CLK for SD respectively.
445 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
446 "I2S2_IN","I2S4_OUT";
448 drive-strength = <8>;
453 drive-strength = <12>;
462 sd0_pins_uhs: sd0-pins-uhs {
469 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
470 "I2S2_IN","I2S4_OUT";
481 /* Serial NAND is shared pin with SPI-NOR */
482 serial_nand_pins: serial-nand-pins {
489 spic0_pins: spic0-pins {
496 spic1_pins: spic1-pins {
503 /* SPI-NOR is shared pin with serial NAND */
504 spi_nor_pins: spi-nor-pins {
511 /* serial NAND is shared pin with SPI-NOR */
512 serial_nand_pins: serial-nand-pins {
519 uart0_pins: uart0-pins {
522 groups = "uart0_0_tx_rx" ;
526 uart2_pins: uart2-pins {
529 groups = "uart2_1_tx_rx" ;
533 watchdog_pins: watchdog-pins {
535 function = "watchdog";
542 pinctrl-names = "default";
543 pinctrl-0 = <&pwm_pins>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&pmic_bus_pins>;
563 pinctrl-names = "default";
564 pinctrl-0 = <&spic0_pins>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&spic1_pins>;
574 vusb33-supply = <®_3p3v>;
575 vbus-supply = <®_5v>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&uart0_pins>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&uart2_pins>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&watchdog_pins>;