arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/leds/common.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "Bananapi BPI-R64";
  18         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  19
  20         aliases {
  21                 serial0 = &uart0;
  22         };
  23
  24         chosen {
  25                 stdout-path = "serial0:115200n8";
  26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  27         };
  28
  29         cpus {
  30                 cpu@0 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34
  35                 cpu@1 {
  36                         proc-supply = <&mt6380_vcpu_reg>;
  37                         sram-supply = <&mt6380_vm_reg>;
  38                 };
  39         };
  40
  41         gpio-keys {
  42                 compatible = "gpio-keys";
  43
  44                 factory-key {
  45                         label = "factory";
  46                         linux,code = <BTN_0>;
  47                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  48                 };
  49
  50                 wps-key {
  51                         label = "wps";
  52                         linux,code = <KEY_WPS_BUTTON>;
  53                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  54                 };
  55         };
  56
  57         leds {
  58                 compatible = "gpio-leds";
  59
  60                 led-0 {
  61                         label = "bpi-r64:pio:green";
  62                         color = <LED_COLOR_ID_GREEN>;
  63                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  64                         default-state = "off";
  65                 };
  66
  67                 led-1 {
  68                         label = "bpi-r64:pio:red";
  69                         color = <LED_COLOR_ID_RED>;
  70                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  71                         default-state = "off";
  72                 };
  73         };
  74
  75         memory {
  76                 reg = <0 0x40000000 0 0x40000000>;
  77         };
  78
  79         reg_1p8v: regulator-1p8v {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "fixed-1.8V";
  82                 regulator-min-microvolt = <1800000>;
  83                 regulator-max-microvolt = <1800000>;
  84                 regulator-always-on;
  85         };
  86
  87         reg_3p3v: regulator-3p3v {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "fixed-3.3V";
  90                 regulator-min-microvolt = <3300000>;
  91                 regulator-max-microvolt = <3300000>;
  92                 regulator-boot-on;
  93                 regulator-always-on;
  94         };
  95
  96         reg_5v: regulator-5v {
  97                 compatible = "regulator-fixed";
  98                 regulator-name = "fixed-5V";
  99                 regulator-min-microvolt = <5000000>;
 100                 regulator-max-microvolt = <5000000>;
 101                 regulator-boot-on;
 102                 regulator-always-on;
 103         };
 104 };
 105
 106 &bch {
 107         status = "disabled";
 108 };
 109
 110 &btif {
 111         status = "okay";
 112 };
 113
 114 &cir {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&irrx_pins>;
 117         status = "okay";
 118 };
 119
 120 &eth {
 121         status = "okay";
 122         gmac0: mac@0 {
 123                 compatible = "mediatek,eth-mac";
 124                 reg = <0>;
 125                 phy-mode = "2500base-x";
 126
 127                 fixed-link {
 128                         speed = <2500>;
 129                         full-duplex;
 130                         pause;
 131                 };
 132         };
 133
 134         gmac1: mac@1 {
 135                 compatible = "mediatek,eth-mac";
 136                 reg = <1>;
 137                 phy-mode = "rgmii";
 138
 139                 fixed-link {
 140                         speed = <1000>;
 141                         full-duplex;
 142                         pause;
 143                 };
 144         };
 145
 146         mdio: mdio-bus {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149
 150                 switch@0 {
 151                         compatible = "mediatek,mt7531";
 152                         reg = <0>;
 153                         reset-gpios = <&pio 54 0>;
 154
 155                         ports {
 156                                 #address-cells = <1>;
 157                                 #size-cells = <0>;
 158
 159                                 port@0 {
 160                                         reg = <0>;
 161                                         label = "wan";
 162                                 };
 163
 164                                 port@1 {
 165                                         reg = <1>;
 166                                         label = "lan0";
 167                                 };
 168
 169                                 port@2 {
 170                                         reg = <2>;
 171                                         label = "lan1";
 172                                 };
 173
 174                                 port@3 {
 175                                         reg = <3>;
 176                                         label = "lan2";
 177                                 };
 178
 179                                 port@4 {
 180                                         reg = <4>;
 181                                         label = "lan3";
 182                                 };
 183
 184                                 port@6 {
 185                                         reg = <6>;
 186                                         label = "cpu";
 187                                         ethernet = <&gmac0>;
 188                                         phy-mode = "2500base-x";
 189
 190                                         fixed-link {
 191                                                 speed = <2500>;
 192                                                 full-duplex;
 193                                                 pause;
 194                                         };
 195                                 };
 196                         };
 197                 };
 198
 199         };
 200 };
 201
 202 &i2c1 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&i2c1_pins>;
 205         status = "okay";
 206 };
 207
 208 &i2c2 {
 209         pinctrl-names = "default";
 210         pinctrl-0 = <&i2c2_pins>;
 211         status = "okay";
 212 };
 213
 214 &mmc0 {
 215         pinctrl-names = "default", "state_uhs";
 216         pinctrl-0 = <&emmc_pins_default>;
 217         pinctrl-1 = <&emmc_pins_uhs>;
 218         status = "okay";
 219         bus-width = <8>;
 220         max-frequency = <50000000>;
 221         cap-mmc-highspeed;
 222         mmc-hs200-1_8v;
 223         vmmc-supply = <&reg_3p3v>;
 224         vqmmc-supply = <&reg_1p8v>;
 225         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 226         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 227         non-removable;
 228 };
 229
 230 &mmc1 {
 231         pinctrl-names = "default", "state_uhs";
 232         pinctrl-0 = <&sd0_pins_default>;
 233         pinctrl-1 = <&sd0_pins_uhs>;
 234         status = "okay";
 235         bus-width = <4>;
 236         max-frequency = <50000000>;
 237         cap-sd-highspeed;
 238         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 239         vmmc-supply = <&reg_3p3v>;
 240         vqmmc-supply = <&reg_3p3v>;
 241         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 242         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 243 };
 244
 245 &nandc {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&parallel_nand_pins>;
 248         status = "disabled";
 249 };
 250
 251 &bch {
 252         status = "okay";
 253 };
 254
 255 &snfi {
 256         pinctrl-names = "default";
 257         pinctrl-0 = <&serial_nand_pins>;
 258         status = "okay";
 259         flash@0 {
 260                 compatible = "spi-nand";
 261                 reg = <0>;
 262                 spi-tx-bus-width = <4>;
 263                 spi-rx-bus-width = <4>;
 264                 nand-ecc-engine = <&snfi>;
 265                 partitions {
 266                         compatible = "fixed-partitions";
 267                         #address-cells = <1>;
 268                         #size-cells = <1>;
 269
 270                         partition@0 {
 271                                 label = "bl2";
 272                                 reg = <0x0 0x80000>;
 273                                 read-only;
 274                         };
 275
 276                         partition@80000 {
 277                                 label = "fip";
 278                                 reg = <0x80000 0x200000>;
 279                                 read-only;
 280                         };
 281
 282                         ubi: partition@280000 {
 283                                 label = "ubi";
 284                                 reg = <0x280000 0x7d80000>;
 285                         };
 286                 };
 287         };
 288 };
 289
 290 &pcie0 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pcie0_pins>;
 293         status = "okay";
 294 };
 295
 296 &pcie1 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pcie1_pins>;
 299         status = "okay";
 300 };
 301
 302 &pio {
 303         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 304          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 305          */
 306         asm_sel {
 307                 gpio-hog;
 308                 gpios = <90 GPIO_ACTIVE_HIGH>;
 309                 output-high;
 310         };
 311
 312         /* eMMC is shared pin with parallel NAND */
 313         emmc_pins_default: emmc-pins-default {
 314                 mux {
 315                         function = "emmc", "emmc_rst";
 316                         groups = "emmc";
 317                 };
 318
 319                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 320                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 321                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 322                  */
 323                 conf-cmd-dat {
 324                         pins = "NDL0", "NDL1", "NDL2",
 325                                "NDL3", "NDL4", "NDL5",
 326                                "NDL6", "NDL7", "NRB";
 327                         input-enable;
 328                         bias-pull-up;
 329                 };
 330
 331                 conf-clk {
 332                         pins = "NCLE";
 333                         bias-pull-down;
 334                 };
 335         };
 336
 337         emmc_pins_uhs: emmc-pins-uhs {
 338                 mux {
 339                         function = "emmc";
 340                         groups = "emmc";
 341                 };
 342
 343                 conf-cmd-dat {
 344                         pins = "NDL0", "NDL1", "NDL2",
 345                                "NDL3", "NDL4", "NDL5",
 346                                "NDL6", "NDL7", "NRB";
 347                         input-enable;
 348                         drive-strength = <4>;
 349                         bias-pull-up;
 350                 };
 351
 352                 conf-clk {
 353                         pins = "NCLE";
 354                         drive-strength = <4>;
 355                         bias-pull-down;
 356                 };
 357         };
 358
 359         eth_pins: eth-pins {
 360                 mux {
 361                         function = "eth";
 362                         groups = "mdc_mdio", "rgmii_via_gmac2";
 363                 };
 364         };
 365
 366         i2c1_pins: i2c1-pins {
 367                 mux {
 368                         function = "i2c";
 369                         groups = "i2c1_0";
 370                 };
 371         };
 372
 373         i2c2_pins: i2c2-pins {
 374                 mux {
 375                         function = "i2c";
 376                         groups = "i2c2_0";
 377                 };
 378         };
 379
 380         i2s1_pins: i2s1-pins {
 381                 mux {
 382                         function = "i2s";
 383                         groups =  "i2s_out_mclk_bclk_ws",
 384                                   "i2s1_in_data",
 385                                   "i2s1_out_data";
 386                 };
 387
 388                 conf {
 389                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 390                                "I2S_WS", "I2S_MCLK";
 391                         drive-strength = <12>;
 392                         bias-pull-down;
 393                 };
 394         };
 395
 396         irrx_pins: irrx-pins {
 397                 mux {
 398                         function = "ir";
 399                         groups = "ir_1_rx";
 400                 };
 401         };
 402
 403         irtx_pins: irtx-pins {
 404                 mux {
 405                         function = "ir";
 406                         groups = "ir_1_tx";
 407                 };
 408         };
 409
 410         /* Parallel nand is shared pin with eMMC */
 411         parallel_nand_pins: parallel-nand-pins {
 412                 mux {
 413                         function = "flash";
 414                         groups = "par_nand";
 415                 };
 416         };
 417
 418         pcie0_pins: pcie0-pins {
 419                 mux {
 420                         function = "pcie";
 421                         groups = "pcie0_pad_perst",
 422                                  "pcie0_1_waken",
 423                                  "pcie0_1_clkreq";
 424                 };
 425         };
 426
 427         pcie1_pins: pcie1-pins {
 428                 mux {
 429                         function = "pcie";
 430                         groups = "pcie1_pad_perst",
 431                                  "pcie1_0_waken",
 432                                  "pcie1_0_clkreq";
 433                 };
 434         };
 435
 436         pmic_bus_pins: pmic-bus-pins {
 437                 mux {
 438                         function = "pmic";
 439                         groups = "pmic_bus";
 440                 };
 441         };
 442
 443         pwm_pins: pwm-pins {
 444                 mux {
 445                         function = "pwm";
 446                         groups = "pwm_ch1_0", /* mt7622_pwm_ch1_0_pins[] = { 51, }; */
 447                                  "pwm_ch2_0", /* mt7622_pwm_ch2_0_pins[] = { 52, }; */
 448                                  "pwm_ch3_2", /* mt7622_pwm_ch3_2_pins[] = { 97, }; */
 449                                  "pwm_ch4_1", /* mt7622_pwm_ch4_1_pins[] = { 67, }; */
 450                                  "pwm_ch5_0", /* mt7622_pwm_ch5_0_pins[] = { 68, }; */
 451                                  "pwm_ch6_0"; /* mt7622_pwm_ch6_0_pins[] = { 69, }; */
 452                 };
 453         };
 454
 455         wled_pins: wled-pins {
 456                 mux {
 457                         function = "led";
 458                         groups = "wled";
 459                 };
 460         };
 461
 462         sd0_pins_default: sd0-pins-default {
 463                 mux {
 464                         function = "sd";
 465                         groups = "sd_0";
 466                 };
 467
 468                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 469                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 470                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 471                  */
 472                 conf-cmd-data {
 473                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 474                                "I2S2_IN","I2S4_OUT";
 475                         input-enable;
 476                         drive-strength = <8>;
 477                         bias-pull-up;
 478                 };
 479                 conf-clk {
 480                         pins = "I2S3_OUT";
 481                         drive-strength = <12>;
 482                         bias-pull-down;
 483                 };
 484                 conf-cd {
 485                         pins = "TXD3";
 486                         bias-pull-up;
 487                 };
 488         };
 489
 490         sd0_pins_uhs: sd0-pins-uhs {
 491                 mux {
 492                         function = "sd";
 493                         groups = "sd_0";
 494                 };
 495
 496                 conf-cmd-data {
 497                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 498                                "I2S2_IN","I2S4_OUT";
 499                         input-enable;
 500                         bias-pull-up;
 501                 };
 502
 503                 conf-clk {
 504                         pins = "I2S3_OUT";
 505                         bias-pull-down;
 506                 };
 507         };
 508
 509         /* Serial NAND is shared pin with SPI-NOR */
 510         serial_nand_pins: serial-nand-pins {
 511                 mux {
 512                         function = "flash";
 513                         groups = "snfi";
 514                 };
 515         };
 516
 517         spic0_pins: spic0-pins {
 518                 mux {
 519                         function = "spi";
 520                         groups = "spic0_0";
 521                 };
 522         };
 523
 524         spic1_pins: spic1-pins {
 525                 mux {
 526                         function = "spi";
 527                         groups = "spic1_0";
 528                 };
 529         };
 530
 531         /* SPI-NOR is shared pin with serial NAND */
 532         spi_nor_pins: spi-nor-pins {
 533                 mux {
 534                         function = "flash";
 535                         groups = "spi_nor";
 536                 };
 537         };
 538
 539         /* serial NAND is shared pin with SPI-NOR */
 540         serial_nand_pins: serial-nand-pins {
 541                 mux {
 542                         function = "flash";
 543                         groups = "snfi";
 544                 };
 545         };
 546
 547         uart0_pins: uart0-pins {
 548                 mux {
 549                         function = "uart";
 550                         groups = "uart0_0_tx_rx" ;
 551                 };
 552         };
 553
 554         uart2_pins: uart2-pins {
 555                 mux {
 556                         function = "uart";
 557                         groups = "uart2_1_tx_rx" ;
 558                 };
 559         };
 560
 561         watchdog_pins: watchdog-pins {
 562                 mux {
 563                         function = "watchdog";
 564                         groups = "watchdog";
 565                 };
 566         };
 567 };
 568
 569 &pwm {
 570         pinctrl-names = "default";
 571         pinctrl-0 = <&pwm_pins>;
 572         status = "okay";
 573 };
 574
 575 &pwrap {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&pmic_bus_pins>;
 578
 579         status = "okay";
 580 };
 581
 582 &sata {
 583         status = "disable";
 584 };
 585
 586 &sata_phy {
 587         status = "disable";
 588 };
 589
 590 &spi0 {
 591         pinctrl-names = "default";
 592         pinctrl-0 = <&spic0_pins>;
 593         status = "okay";
 594 };
 595
 596 &spi1 {
 597         pinctrl-names = "default";
 598         pinctrl-0 = <&spic1_pins>;
 599 };
 600
 601 &ssusb {
 602         vusb33-supply = <&reg_3p3v>;
 603         vbus-supply = <&reg_5v>;
 604         status = "okay";
 605 };
 606
 607 &u3phy {
 608         status = "okay";
 609 };
 610
 611 &uart0 {
 612         pinctrl-names = "default";
 613         pinctrl-0 = <&uart0_pins>;
 614         status = "okay";
 615 };
 616
 617 &uart2 {
 618         pinctrl-names = "default";
 619         pinctrl-0 = <&uart2_pins>;
 620 };
 621
 622 &watchdog {
 623         pinctrl-names = "default";
 624         pinctrl-0 = <&watchdog_pins>;
 625         status = "okay";
 626 };
 627
 628 &wmac {
 629         status = "okay";
 630 };