arch/arm64/boot/dts/mediatek/mt6795.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  * Author: Mars.C <mars.cheng@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "mediatek,mt6795";
  12         interrupt-parent = <&sysirq>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         psci {
  17                 compatible = "arm,psci-0.2";
  18                 method = "smc";
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a53";
  28                         enable-method = "psci";
  29                         reg = <0x000>;
  30                 };
  31
  32                 cpu1: cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53";
  35                         enable-method = "psci";
  36                         reg = <0x001>;
  37                 };
  38
  39                 cpu2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a53";
  42                         enable-method = "psci";
  43                         reg = <0x002>;
  44                 };
  45
  46                 cpu3: cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         enable-method = "psci";
  50                         reg = <0x003>;
  51                 };
  52
  53                 cpu4: cpu@100 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a53";
  56                         enable-method = "psci";
  57                         reg = <0x100>;
  58                 };
  59
  60                 cpu5: cpu@101 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         enable-method = "psci";
  64                         reg = <0x101>;
  65                 };
  66
  67                 cpu6: cpu@102 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a53";
  70                         enable-method = "psci";
  71                         reg = <0x102>;
  72                 };
  73
  74                 cpu7: cpu@103 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         enable-method = "psci";
  78                         reg = <0x103>;
  79                 };
  80         };
  81
  82         system_clk: dummy13m {
  83                 compatible = "fixed-clock";
  84                 clock-frequency = <13000000>;
  85                 #clock-cells = <0>;
  86         };
  87
  88         rtc_clk: dummy32k {
  89                 compatible = "fixed-clock";
  90                 clock-frequency = <32000>;
  91                 #clock-cells = <0>;
  92         };
  93
  94         uart_clk: dummy26m {
  95                 compatible = "fixed-clock";
  96                 clock-frequency = <26000000>;
  97                 #clock-cells = <0>;
  98         };
  99
 100         timer {
 101                 compatible = "arm,armv8-timer";
 102                 interrupt-parent = <&gic>;
 103                 interrupts = <GIC_PPI 13
 104                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 105                              <GIC_PPI 14
 106                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 107                              <GIC_PPI 11
 108                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 109                              <GIC_PPI 10
 110                              (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 111         };
 112
 113         sysirq: intpol-controller@10200620 {
 114                 compatible = "mediatek,mt6795-sysirq",
 115                              "mediatek,mt6577-sysirq";
 116                 interrupt-controller;
 117                 #interrupt-cells = <3>;
 118                 interrupt-parent = <&gic>;
 119                 reg = <0 0x10200620 0 0x20>;
 120         };
 121
 122         gic: interrupt-controller@10221000 {
 123                 compatible = "arm,gic-400";
 124                 #interrupt-cells = <3>;
 125                 interrupt-parent = <&gic>;
 126                 interrupt-controller;
 127                 reg = <0 0x10221000 0 0x1000>,
 128                       <0 0x10222000 0 0x2000>,
 129                       <0 0x10224000 0 0x2000>,
 130                       <0 0x10226000 0 0x2000>;
 131         };
 132
 133         uart0: serial@11002000 {
 134                 compatible = "mediatek,mt6795-uart",
 135                              "mediatek,mt6577-uart";
 136                 reg = <0 0x11002000 0 0x400>;
 137                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 138                 clocks = <&uart_clk>;
 139                 status = "disabled";
 140         };
 141
 142         uart1: serial@11003000 {
 143                 compatible = "mediatek,mt6795-uart",
 144                              "mediatek,mt6577-uart";
 145                 reg = <0 0x11003000 0 0x400>;
 146                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 147                 clocks = <&uart_clk>;
 148                 status = "disabled";
 149         };
 150
 151         uart2: serial@11004000 {
 152                 compatible = "mediatek,mt6795-uart",
 153                              "mediatek,mt6577-uart";
 154                 reg = <0 0x11004000 0 0x400>;
 155                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 156                 clocks = <&uart_clk>;
 157                 status = "disabled";
 158         };
 159
 160         uart3: serial@11005000 {
 161                 compatible = "mediatek,mt6795-uart",
 162                              "mediatek,mt6577-uart";
 163                 reg = <0 0x11005000 0 0x400>;
 164                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 165                 clocks = <&uart_clk>;
 166                 status = "disabled";
 167         };
 168 };