arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for CZ.NIC Turris Mox Board
   4  * 2019 by Marek Behún <kabel@kernel.org>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/bus/moxtet.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include "armada-372x.dtsi"
  13
  14 / {
  15         model = "CZ.NIC Turris Mox Board";
  16         compatible = "cznic,turris-mox", "marvell,armada3720",
  17                      "marvell,armada3710";
  18
  19         aliases {
  20                 spi0 = &spi0;
  21                 ethernet0 = &eth0;
  22                 ethernet1 = &eth1;
  23                 mmc0 = &sdhci0;
  24                 mmc1 = &sdhci1;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         memory@0 {
  32                 device_type = "memory";
  33                 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38                 red {
  39                         label = "mox:red:activity";
  40                         gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>;
  41                         linux,default-trigger = "default-on";
  42                 };
  43         };
  44
  45         gpio-keys {
  46                 compatible = "gpio-keys";
  47
  48                 reset {
  49                         label = "reset";
  50                         linux,code = <KEY_RESTART>;
  51                         gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>;
  52                         debounce-interval = <60>;
  53                 };
  54         };
  55
  56         exp_usb3_vbus: usb3-vbus {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "usb3-vbus";
  59                 regulator-min-microvolt = <5000000>;
  60                 regulator-max-microvolt = <5000000>;
  61                 enable-active-high;
  62                 regulator-always-on;
  63                 gpio = <&gpiosb 0 GPIO_ACTIVE_HIGH>;
  64         };
  65
  66         vsdc_reg: vsdc-reg {
  67                 compatible = "regulator-gpio";
  68                 regulator-name = "vsdc";
  69                 regulator-min-microvolt = <1800000>;
  70                 regulator-max-microvolt = <3300000>;
  71                 regulator-boot-on;
  72
  73                 gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>;
  74                 gpios-states = <0>;
  75                 states = <1800000 0x1
  76                           3300000 0x0>;
  77                 enable-active-high;
  78         };
  79
  80         vsdio_reg: vsdio-reg {
  81                 compatible = "regulator-gpio";
  82                 regulator-name = "vsdio";
  83                 regulator-min-microvolt = <1800000>;
  84                 regulator-max-microvolt = <3300000>;
  85                 regulator-boot-on;
  86
  87                 gpios = <&gpiosb 22 GPIO_ACTIVE_HIGH>;
  88                 gpios-states = <0>;
  89                 states = <1800000 0x1
  90                           3300000 0x0>;
  91                 enable-active-high;
  92         };
  93
  94         sdhci1_pwrseq: sdhci1-pwrseq {
  95                 compatible = "mmc-pwrseq-simple";
  96                 reset-gpios = <&gpionb 19 GPIO_ACTIVE_HIGH>;
  97                 status = "okay";
  98         };
  99
 100         sfp: sfp {
 101                 compatible = "sff,sfp";
 102                 i2c-bus = <&i2c0>;
 103                 los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
 104                 tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
 105                 mod-def0-gpio = <&moxtet_sfp 2 GPIO_ACTIVE_LOW>;
 106                 tx-disable-gpio = <&moxtet_sfp 4 GPIO_ACTIVE_HIGH>;
 107                 rate-select0-gpio = <&moxtet_sfp 5 GPIO_ACTIVE_HIGH>;
 108                 maximum-power-milliwatt = <3000>;
 109
 110                 /* enabled by U-Boot if SFP module is present */
 111                 status = "disabled";
 112         };
 113
 114         firmware {
 115                 armada-3700-rwtm {
 116                         compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
 117                 };
 118         };
 119 };
 120
 121 &i2c0 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&i2c1_pins>;
 124         clock-frequency = <100000>;
 125         /delete-property/ mrvl,i2c-fast-mode;
 126         status = "okay";
 127
 128         rtc@6f {
 129                 compatible = "microchip,mcp7940x";
 130                 reg = <0x6f>;
 131         };
 132 };
 133
 134 &pcie0 {
 135         pinctrl-names = "default";
 136         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
 137         status = "okay";
 138         reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
 139         /*
 140          * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
 141          * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
 142          * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
 143          * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
 144          * no remapping) and that this address is the lowest from all specified ranges. If these
 145          * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
 146          * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
 147          * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
 148          * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in
 149          * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):
 150          * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
 151          * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
 152          * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
 153          * Bug related to requirement of same child and parent addresses for first range is fixed
 154          * in U-Boot version 2022.04 by following commit:
 155          * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
 156          */
 157         #address-cells = <3>;
 158         #size-cells = <2>;
 159         ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */
 160                   0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */
 161
 162         /* enabled by U-Boot if PCIe module is present */
 163         status = "disabled";
 164 };
 165
 166 &uart0 {
 167         status = "okay";
 168 };
 169
 170 &eth0 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&rgmii_pins>;
 173         phy-mode = "rgmii-id";
 174         phy-handle = <&phy1>;
 175         status = "okay";
 176 };
 177
 178 &eth1 {
 179         phy-mode = "2500base-x";
 180         managed = "in-band-status";
 181         phys = <&comphy0 1>;
 182 };
 183
 184 &sdhci0 {
 185         wp-inverted;
 186         bus-width = <4>;
 187         cd-gpios = <&gpionb 10 GPIO_ACTIVE_HIGH>;
 188         vqmmc-supply = <&vsdc_reg>;
 189         marvell,pad-type = "sd";
 190         status = "okay";
 191 };
 192
 193 &sdhci1 {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&sdio_pins>;
 196         non-removable;
 197         bus-width = <4>;
 198         marvell,pad-type = "sd";
 199         vqmmc-supply = <&vsdio_reg>;
 200         mmc-pwrseq = <&sdhci1_pwrseq>;
 201         /* forbid SDR104 for FCC purposes */
 202         sdhci-caps-mask = <0x2 0x0>;
 203         status = "okay";
 204 };
 205
 206 &spi0 {
 207         status = "okay";
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&spi_quad_pins &spi_cs1_pins>;
 210         assigned-clocks = <&nb_periph_clk 7>;
 211         assigned-clock-parents = <&tbg 1>;
 212         assigned-clock-rates = <20000000>;
 213
 214         flash@0 {
 215                 #address-cells = <1>;
 216                 #size-cells = <1>;
 217                 compatible = "jedec,spi-nor";
 218                 reg = <0>;
 219                 spi-max-frequency = <20000000>;
 220
 221                 partitions {
 222                         compatible = "fixed-partitions";
 223                         #address-cells = <1>;
 224                         #size-cells = <1>;
 225
 226                         partition@0 {
 227                                 label = "secure-firmware";
 228                                 reg = <0x0 0x20000>;
 229                         };
 230
 231                         partition@20000 {
 232                                 label = "a53-firmware";
 233                                 reg = <0x20000 0x160000>;
 234                         };
 235
 236                         partition@180000 {
 237                                 label = "u-boot-env";
 238                                 reg = <0x180000 0x10000>;
 239                         };
 240
 241                         partition@190000 {
 242                                 label = "Rescue system";
 243                                 reg = <0x190000 0x660000>;
 244                         };
 245
 246                         partition@7f0000 {
 247                                 label = "dtb";
 248                                 reg = <0x7f0000 0x10000>;
 249                         };
 250                 };
 251         };
 252
 253         moxtet: moxtet@1 {
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 compatible = "cznic,moxtet";
 257                 reg = <1>;
 258                 reset-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>;
 259                 spi-max-frequency = <10000000>;
 260                 spi-cpol;
 261                 spi-cpha;
 262                 interrupt-controller;
 263                 #interrupt-cells = <1>;
 264                 interrupt-parent = <&gpiosb>;
 265                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 266                 status = "okay";
 267
 268                 moxtet_sfp: gpio@0 {
 269                         compatible = "cznic,moxtet-gpio";
 270                         gpio-controller;
 271                         #gpio-cells = <2>;
 272                         reg = <0>;
 273                         status = "disabled";
 274                 };
 275         };
 276 };
 277
 278 &usb2 {
 279         status = "okay";
 280 };
 281
 282 &comphy2 {
 283         connector {
 284                 compatible = "usb-a-connector";
 285                 phy-supply = <&exp_usb3_vbus>;
 286         };
 287 };
 288
 289 &usb3 {
 290         status = "okay";
 291         phys = <&comphy2 0>;
 292 };
 293
 294 &mdio {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&smi_pins>;
 297         status = "okay";
 298
 299         phy1: ethernet-phy@1 {
 300                 reg = <1>;
 301         };
 302
 303         /* switch nodes are enabled by U-Boot if modules are present */
 304         switch0@10 {
 305                 compatible = "marvell,mv88e6190";
 306                 reg = <0x10>;
 307                 dsa,member = <0 0>;
 308                 interrupt-parent = <&moxtet>;
 309                 interrupts = <MOXTET_IRQ_PERIDOT(0)>;
 310                 status = "disabled";
 311
 312                 mdio {
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315
 316                         switch0phy1: switch0phy1@1 {
 317                                 reg = <0x1>;
 318                         };
 319
 320                         switch0phy2: switch0phy2@2 {
 321                                 reg = <0x2>;
 322                         };
 323
 324                         switch0phy3: switch0phy3@3 {
 325                                 reg = <0x3>;
 326                         };
 327
 328                         switch0phy4: switch0phy4@4 {
 329                                 reg = <0x4>;
 330                         };
 331
 332                         switch0phy5: switch0phy5@5 {
 333                                 reg = <0x5>;
 334                         };
 335
 336                         switch0phy6: switch0phy6@6 {
 337                                 reg = <0x6>;
 338                         };
 339
 340                         switch0phy7: switch0phy7@7 {
 341                                 reg = <0x7>;
 342                         };
 343
 344                         switch0phy8: switch0phy8@8 {
 345                                 reg = <0x8>;
 346                         };
 347                 };
 348
 349                 ports {
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352
 353                         port@1 {
 354                                 reg = <0x1>;
 355                                 label = "lan1";
 356                                 phy-handle = <&switch0phy1>;
 357                         };
 358
 359                         port@2 {
 360                                 reg = <0x2>;
 361                                 label = "lan2";
 362                                 phy-handle = <&switch0phy2>;
 363                         };
 364
 365                         port@3 {
 366                                 reg = <0x3>;
 367                                 label = "lan3";
 368                                 phy-handle = <&switch0phy3>;
 369                         };
 370
 371                         port@4 {
 372                                 reg = <0x4>;
 373                                 label = "lan4";
 374                                 phy-handle = <&switch0phy4>;
 375                         };
 376
 377                         port@5 {
 378                                 reg = <0x5>;
 379                                 label = "lan5";
 380                                 phy-handle = <&switch0phy5>;
 381                         };
 382
 383                         port@6 {
 384                                 reg = <0x6>;
 385                                 label = "lan6";
 386                                 phy-handle = <&switch0phy6>;
 387                         };
 388
 389                         port@7 {
 390                                 reg = <0x7>;
 391                                 label = "lan7";
 392                                 phy-handle = <&switch0phy7>;
 393                         };
 394
 395                         port@8 {
 396                                 reg = <0x8>;
 397                                 label = "lan8";
 398                                 phy-handle = <&switch0phy8>;
 399                         };
 400
 401                         port@9 {
 402                                 reg = <0x9>;
 403                                 label = "cpu";
 404                                 ethernet = <&eth1>;
 405                                 phy-mode = "2500base-x";
 406                                 managed = "in-band-status";
 407                         };
 408
 409                         switch0port10: port@a {
 410                                 reg = <0xa>;
 411                                 label = "dsa";
 412                                 phy-mode = "2500base-x";
 413                                 managed = "in-band-status";
 414                                 link = <&switch1port9 &switch2port9>;
 415                                 status = "disabled";
 416                         };
 417
 418                         port-sfp@a {
 419                                 reg = <0xa>;
 420                                 label = "sfp";
 421                                 sfp = <&sfp>;
 422                                 phy-mode = "sgmii";
 423                                 managed = "in-band-status";
 424                                 status = "disabled";
 425                         };
 426                 };
 427         };
 428
 429         switch0@2 {
 430                 compatible = "marvell,mv88e6085";
 431                 reg = <0x2>;
 432                 dsa,member = <0 0>;
 433                 interrupt-parent = <&moxtet>;
 434                 interrupts = <MOXTET_IRQ_TOPAZ>;
 435                 status = "disabled";
 436
 437                 mdio {
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440
 441                         switch0phy1_topaz: switch0phy1@11 {
 442                                 reg = <0x11>;
 443                         };
 444
 445                         switch0phy2_topaz: switch0phy2@12 {
 446                                 reg = <0x12>;
 447                         };
 448
 449                         switch0phy3_topaz: switch0phy3@13 {
 450                                 reg = <0x13>;
 451                         };
 452
 453                         switch0phy4_topaz: switch0phy4@14 {
 454                                 reg = <0x14>;
 455                         };
 456                 };
 457
 458                 ports {
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461
 462                         port@1 {
 463                                 reg = <0x1>;
 464                                 label = "lan1";
 465                                 phy-handle = <&switch0phy1_topaz>;
 466                         };
 467
 468                         port@2 {
 469                                 reg = <0x2>;
 470                                 label = "lan2";
 471                                 phy-handle = <&switch0phy2_topaz>;
 472                         };
 473
 474                         port@3 {
 475                                 reg = <0x3>;
 476                                 label = "lan3";
 477                                 phy-handle = <&switch0phy3_topaz>;
 478                         };
 479
 480                         port@4 {
 481                                 reg = <0x4>;
 482                                 label = "lan4";
 483                                 phy-handle = <&switch0phy4_topaz>;
 484                         };
 485
 486                         port@5 {
 487                                 reg = <0x5>;
 488                                 label = "cpu";
 489                                 phy-mode = "2500base-x";
 490                                 managed = "in-band-status";
 491                                 ethernet = <&eth1>;
 492                         };
 493                 };
 494         };
 495
 496         switch1@11 {
 497                 compatible = "marvell,mv88e6190";
 498                 reg = <0x11>;
 499                 dsa,member = <0 1>;
 500                 interrupt-parent = <&moxtet>;
 501                 interrupts = <MOXTET_IRQ_PERIDOT(1)>;
 502                 status = "disabled";
 503
 504                 mdio {
 505                         #address-cells = <1>;
 506                         #size-cells = <0>;
 507
 508                         switch1phy1: switch1phy1@1 {
 509                                 reg = <0x1>;
 510                         };
 511
 512                         switch1phy2: switch1phy2@2 {
 513                                 reg = <0x2>;
 514                         };
 515
 516                         switch1phy3: switch1phy3@3 {
 517                                 reg = <0x3>;
 518                         };
 519
 520                         switch1phy4: switch1phy4@4 {
 521                                 reg = <0x4>;
 522                         };
 523
 524                         switch1phy5: switch1phy5@5 {
 525                                 reg = <0x5>;
 526                         };
 527
 528                         switch1phy6: switch1phy6@6 {
 529                                 reg = <0x6>;
 530                         };
 531
 532                         switch1phy7: switch1phy7@7 {
 533                                 reg = <0x7>;
 534                         };
 535
 536                         switch1phy8: switch1phy8@8 {
 537                                 reg = <0x8>;
 538                         };
 539                 };
 540
 541                 ports {
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544
 545                         port@1 {
 546                                 reg = <0x1>;
 547                                 label = "lan9";
 548                                 phy-handle = <&switch1phy1>;
 549                         };
 550
 551                         port@2 {
 552                                 reg = <0x2>;
 553                                 label = "lan10";
 554                                 phy-handle = <&switch1phy2>;
 555                         };
 556
 557                         port@3 {
 558                                 reg = <0x3>;
 559                                 label = "lan11";
 560                                 phy-handle = <&switch1phy3>;
 561                         };
 562
 563                         port@4 {
 564                                 reg = <0x4>;
 565                                 label = "lan12";
 566                                 phy-handle = <&switch1phy4>;
 567                         };
 568
 569                         port@5 {
 570                                 reg = <0x5>;
 571                                 label = "lan13";
 572                                 phy-handle = <&switch1phy5>;
 573                         };
 574
 575                         port@6 {
 576                                 reg = <0x6>;
 577                                 label = "lan14";
 578                                 phy-handle = <&switch1phy6>;
 579                         };
 580
 581                         port@7 {
 582                                 reg = <0x7>;
 583                                 label = "lan15";
 584                                 phy-handle = <&switch1phy7>;
 585                         };
 586
 587                         port@8 {
 588                                 reg = <0x8>;
 589                                 label = "lan16";
 590                                 phy-handle = <&switch1phy8>;
 591                         };
 592
 593                         switch1port9: port@9 {
 594                                 reg = <0x9>;
 595                                 label = "dsa";
 596                                 phy-mode = "2500base-x";
 597                                 managed = "in-band-status";
 598                                 link = <&switch0port10>;
 599                         };
 600
 601                         switch1port10: port@a {
 602                                 reg = <0xa>;
 603                                 label = "dsa";
 604                                 phy-mode = "2500base-x";
 605                                 managed = "in-band-status";
 606                                 link = <&switch2port9>;
 607                                 status = "disabled";
 608                         };
 609
 610                         port-sfp@a {
 611                                 reg = <0xa>;
 612                                 label = "sfp";
 613                                 sfp = <&sfp>;
 614                                 phy-mode = "sgmii";
 615                                 managed = "in-band-status";
 616                                 status = "disabled";
 617                         };
 618                 };
 619         };
 620
 621         switch1@2 {
 622                 compatible = "marvell,mv88e6085";
 623                 reg = <0x2>;
 624                 dsa,member = <0 1>;
 625                 interrupt-parent = <&moxtet>;
 626                 interrupts = <MOXTET_IRQ_TOPAZ>;
 627                 status = "disabled";
 628
 629                 mdio {
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632
 633                         switch1phy1_topaz: switch1phy1@11 {
 634                                 reg = <0x11>;
 635                         };
 636
 637                         switch1phy2_topaz: switch1phy2@12 {
 638                                 reg = <0x12>;
 639                         };
 640
 641                         switch1phy3_topaz: switch1phy3@13 {
 642                                 reg = <0x13>;
 643                         };
 644
 645                         switch1phy4_topaz: switch1phy4@14 {
 646                                 reg = <0x14>;
 647                         };
 648                 };
 649
 650                 ports {
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653
 654                         port@1 {
 655                                 reg = <0x1>;
 656                                 label = "lan9";
 657                                 phy-handle = <&switch1phy1_topaz>;
 658                         };
 659
 660                         port@2 {
 661                                 reg = <0x2>;
 662                                 label = "lan10";
 663                                 phy-handle = <&switch1phy2_topaz>;
 664                         };
 665
 666                         port@3 {
 667                                 reg = <0x3>;
 668                                 label = "lan11";
 669                                 phy-handle = <&switch1phy3_topaz>;
 670                         };
 671
 672                         port@4 {
 673                                 reg = <0x4>;
 674                                 label = "lan12";
 675                                 phy-handle = <&switch1phy4_topaz>;
 676                         };
 677
 678                         port@5 {
 679                                 reg = <0x5>;
 680                                 label = "dsa";
 681                                 phy-mode = "2500base-x";
 682                                 managed = "in-band-status";
 683                                 link = <&switch0port10>;
 684                         };
 685                 };
 686         };
 687
 688         switch2@12 {
 689                 compatible = "marvell,mv88e6190";
 690                 reg = <0x12>;
 691                 dsa,member = <0 2>;
 692                 interrupt-parent = <&moxtet>;
 693                 interrupts = <MOXTET_IRQ_PERIDOT(2)>;
 694                 status = "disabled";
 695
 696                 mdio {
 697                         #address-cells = <1>;
 698                         #size-cells = <0>;
 699
 700                         switch2phy1: switch2phy1@1 {
 701                                 reg = <0x1>;
 702                         };
 703
 704                         switch2phy2: switch2phy2@2 {
 705                                 reg = <0x2>;
 706                         };
 707
 708                         switch2phy3: switch2phy3@3 {
 709                                 reg = <0x3>;
 710                         };
 711
 712                         switch2phy4: switch2phy4@4 {
 713                                 reg = <0x4>;
 714                         };
 715
 716                         switch2phy5: switch2phy5@5 {
 717                                 reg = <0x5>;
 718                         };
 719
 720                         switch2phy6: switch2phy6@6 {
 721                                 reg = <0x6>;
 722                         };
 723
 724                         switch2phy7: switch2phy7@7 {
 725                                 reg = <0x7>;
 726                         };
 727
 728                         switch2phy8: switch2phy8@8 {
 729                                 reg = <0x8>;
 730                         };
 731                 };
 732
 733                 ports {
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736
 737                         port@1 {
 738                                 reg = <0x1>;
 739                                 label = "lan17";
 740                                 phy-handle = <&switch2phy1>;
 741                         };
 742
 743                         port@2 {
 744                                 reg = <0x2>;
 745                                 label = "lan18";
 746                                 phy-handle = <&switch2phy2>;
 747                         };
 748
 749                         port@3 {
 750                                 reg = <0x3>;
 751                                 label = "lan19";
 752                                 phy-handle = <&switch2phy3>;
 753                         };
 754
 755                         port@4 {
 756                                 reg = <0x4>;
 757                                 label = "lan20";
 758                                 phy-handle = <&switch2phy4>;
 759                         };
 760
 761                         port@5 {
 762                                 reg = <0x5>;
 763                                 label = "lan21";
 764                                 phy-handle = <&switch2phy5>;
 765                         };
 766
 767                         port@6 {
 768                                 reg = <0x6>;
 769                                 label = "lan22";
 770                                 phy-handle = <&switch2phy6>;
 771                         };
 772
 773                         port@7 {
 774                                 reg = <0x7>;
 775                                 label = "lan23";
 776                                 phy-handle = <&switch2phy7>;
 777                         };
 778
 779                         port@8 {
 780                                 reg = <0x8>;
 781                                 label = "lan24";
 782                                 phy-handle = <&switch2phy8>;
 783                         };
 784
 785                         switch2port9: port@9 {
 786                                 reg = <0x9>;
 787                                 label = "dsa";
 788                                 phy-mode = "2500base-x";
 789                                 managed = "in-band-status";
 790                                 link = <&switch1port10 &switch0port10>;
 791                         };
 792
 793                         port-sfp@a {
 794                                 reg = <0xa>;
 795                                 label = "sfp";
 796                                 sfp = <&sfp>;
 797                                 phy-mode = "sgmii";
 798                                 managed = "in-band-status";
 799                                 status = "disabled";
 800                         };
 801                 };
 802         };
 803
 804         switch2@2 {
 805                 compatible = "marvell,mv88e6085";
 806                 reg = <0x2>;
 807                 dsa,member = <0 2>;
 808                 interrupt-parent = <&moxtet>;
 809                 interrupts = <MOXTET_IRQ_TOPAZ>;
 810                 status = "disabled";
 811
 812                 mdio {
 813                         #address-cells = <1>;
 814                         #size-cells = <0>;
 815
 816                         switch2phy1_topaz: switch2phy1@11 {
 817                                 reg = <0x11>;
 818                         };
 819
 820                         switch2phy2_topaz: switch2phy2@12 {
 821                                 reg = <0x12>;
 822                         };
 823
 824                         switch2phy3_topaz: switch2phy3@13 {
 825                                 reg = <0x13>;
 826                         };
 827
 828                         switch2phy4_topaz: switch2phy4@14 {
 829                                 reg = <0x14>;
 830                         };
 831                 };
 832
 833                 ports {
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836
 837                         port@1 {
 838                                 reg = <0x1>;
 839                                 label = "lan17";
 840                                 phy-handle = <&switch2phy1_topaz>;
 841                         };
 842
 843                         port@2 {
 844                                 reg = <0x2>;
 845                                 label = "lan18";
 846                                 phy-handle = <&switch2phy2_topaz>;
 847                         };
 848
 849                         port@3 {
 850                                 reg = <0x3>;
 851                                 label = "lan19";
 852                                 phy-handle = <&switch2phy3_topaz>;
 853                         };
 854
 855                         port@4 {
 856                                 reg = <0x4>;
 857                                 label = "lan20";
 858                                 phy-handle = <&switch2phy4_topaz>;
 859                         };
 860
 861                         port@5 {
 862                                 reg = <0x5>;
 863                                 label = "dsa";
 864                                 phy-mode = "2500base-x";
 865                                 managed = "in-band-status";
 866                                 link = <&switch1port10 &switch0port10>;
 867                         };
 868                 };
 869         };
 870 };