arch/arm64/boot/dts/juno.dts

   1 /*
   2  * ARM Ltd. Juno Plaform
   3  *
   4  * Fast Models FVP v2 support
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10
  11 / {
  12         model = "Juno";
  13         compatible = "arm,juno", "arm,vexpress";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 serial0 = &soc_uart0;
  20         };
  21
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster1 {
  29                                 core0 {
  30                                         cpu = <&CPU0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&CPU1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&CPU2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&CPU3>;
  40                                 };
  41                         };
  42
  43                         cluster0 {
  44                                 core0 {
  45                                         cpu = <&CPU4>;
  46                                 };
  47                                 core1 {
  48                                         cpu = <&CPU5>;
  49                                 };
  50                         };
  51                 };
  52
  53                 idle-states {
  54                         entry-method = "arm,psci";
  55
  56                         CPU_SLEEP_0: cpu-sleep-0 {
  57                                 compatible = "arm,idle-state";
  58                                 entry-method-param = <0x0010000>;
  59                                 entry-latency-us = <40>;
  60                                 exit-latency-us = <100>;
  61                                 min-residency-us = <150>;
  62                         };
  63
  64                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  65                                 compatible = "arm,idle-state";
  66                                 entry-method-param = <0x1010000>;
  67                                 entry-latency-us = <500>;
  68                                 exit-latency-us = <1000>;
  69                                 min-residency-us = <2500>;
  70                         };
  71                 };
  72
  73                 CPU0:cpu@100 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53","arm,armv8";
  76                         reg = <0x0 0x100>;
  77                         enable-method = "psci";
  78                         clocks = <&scpi_dvfs 1>;
  79                         clock-names = "vlittle";
  80                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  81                 };
  82
  83                 CPU1:cpu@101 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53","arm,armv8";
  86                         reg = <0x0 0x101>;
  87                         enable-method = "psci";
  88                         clocks = <&scpi_dvfs 1>;
  89                         clock-names = "vlittle";
  90                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  91                 };
  92
  93                 CPU2:cpu@102 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53","arm,armv8";
  96                         reg = <0x0 0x102>;
  97                         enable-method = "psci";
  98                         clocks = <&scpi_dvfs 1>;
  99                         clock-names = "vlittle";
 100                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 101                 };
 102
 103                 CPU3:cpu@103 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a53","arm,armv8";
 106                         reg = <0x0 0x103>;
 107                         enable-method = "psci";
 108                         clocks = <&scpi_dvfs 1>;
 109                         clock-names = "vlittle";
 110                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 111                 };
 112
 113                 CPU4:cpu@0 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a57","arm,armv8";
 116                         reg = <0x0 0x0>;
 117                         enable-method = "psci";
 118                         clocks = <&scpi_dvfs 0>;
 119                         clock-names = "vbig";
 120                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 121                 };
 122
 123                 CPU5:cpu@1 {
 124                         device_type = "cpu";
 125                         compatible = "arm,cortex-a57","arm,armv8";
 126                         reg = <0x0 0x1>;
 127                         enable-method = "psci";
 128                         clocks = <&scpi_dvfs 0>;
 129                         clock-names = "vbig";
 130                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 131                 };
 132         };
 133
 134         memory@80000000 {
 135                 device_type = "memory";
 136                 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
 137                       <0x00000008 0x80000000 0x1 0x80000000>;
 138         };
 139
 140         /* memory@14000000 {
 141                 device_type = "memory";
 142                 reg = <0x00000000 0x14000000 0x0 0x02000000>;
 143         }; */
 144
 145         gic: interrupt-controller@2c001000 {
 146                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 147                 #interrupt-cells = <3>;
 148                 #address-cells = <0>;
 149                 interrupt-controller;
 150                 reg = <0x0 0x2c010000 0 0x1000>,
 151                       <0x0 0x2c02f000 0 0x2000>,
 152                       <0x0 0x2c04f000 0 0x2000>,
 153                       <0x0 0x2c06f000 0 0x2000>;
 154                 interrupts = <GIC_PPI 9 0xf04>;
 155         };
 156
 157         msi0: msi@2c1c0000 {
 158                 compatible = "arm,gic-msi";
 159                 reg = <0x0 0x2c1c0000 0 0x10000
 160                        0x0 0x2c1d0000 0 0x10000
 161                        0x0 0x2c1e0000 0 0x10000
 162                        0x0 0x2c1f0000 0 0x10000>;
 163         };
 164
 165         timer {
 166                 compatible = "arm,armv8-timer";
 167                 interrupts = <GIC_PPI 13 0xff01>,
 168                              <GIC_PPI 14 0xff01>,
 169                              <GIC_PPI 11 0xff01>,
 170                              <GIC_PPI 10 0xff01>;
 171         };
 172
 173         timer@2a810000 {
 174                 compatible = "arm,armv7-timer-mem";
 175                 reg = <0x0 0x2a810000 0x0 0x10000>;
 176                 clock-frequency = <100000000>;
 177                 #address-cells = <2>;
 178                 #size-cells = <2>;
 179                 ranges;
 180                 frame@2a830000 {
 181                         frame-number = <1>;
 182                         interrupts = <0 60 4>;
 183                         reg = <0x0 0x2a830000 0x0 0x10000>;
 184                 };
 185         };
 186
 187         pmu {
 188                 compatible = "arm,armv8-pmuv3";
 189                 interrupts = <0 18 4>,
 190                              <0 22 4>,
 191                              <0 26 4>,
 192                              <0 30 4>,
 193                              <0 02 4>,
 194                              <0 06 4>;
 195         };
 196
 197         psci {
 198                 compatible = "arm,psci";
 199                 method = "smc";
 200                 cpu_suspend = <0xc4000001>;
 201                 cpu_off = <0x84000002>;
 202                 cpu_on = <0xc4000003>;
 203                 migrate = <0xc4000005>;
 204                 sys_poweroff = <0x84000008>;
 205                 sys_reset = <0x84000009>;
 206         };
 207
 208         pci0: pci@30000000 {
 209                 compatible = "arm,pcie-xr3";
 210                 device_type = "pci";
 211                 reg = <0 0x7ff30000 0 0x1000
 212                        0 0x7ff20000 0 0x10000
 213                        0 0x40000000 0 0x10000000>;
 214                 bus-range = <0 255>;
 215                 #address-cells = <3>;
 216                 #size-cells = <2>;
 217                 ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000
 218                           0x02000000 0x0 0x00000000 0x00 0x40000000 0x0 0x1f000000>;
 219 /*                        0x42000000 0x0 0x20000000 0x40 0x00000000 0x0 0x80000000>;
 220                           0x02000000 0x0 0xA0000000 0x40 0x80000000 0x0 0x80000000>; */
 221                 #interrupt-cells = <1>;
 222                 interrupt-map-mask = <0 0 0 7>;
 223                 interrupt-map = <0 0 0 1 &gic 0 136 4
 224                                  0 0 0 2 &gic 0 137 4
 225                                  0 0 0 3 &gic 0 138 4
 226                                  0 0 0 4 &gic 0 139 4>;
 227         };
 228
 229         scpi: mhu@2b1f0000 {
 230                 compatible = "arm,mhu";
 231                 reg = <0x0 0x2b1f0000 0x0 0x10000>,   /* MHU registers */
 232                       <0x0 0x2e000000 0x0 0x10000>;   /* Payload area */
 233                 interrupts = <0 36 4>,   /* low priority interrupt */
 234                              <0 35 4>;   /* high priority interrupt */
 235         };
 236
 237         clocks {
 238                 compatible = "arm,scpi-clks";
 239
 240                 scpi_dvfs: scpi_clocks@0 {
 241                         compatible = "arm,scpi-clk-indexed";
 242                         #clock-cells = <1>;
 243                         clock-indices = <0>, <1>, <2>;
 244                         clock-output-names = "vbig", "vlittle", "vgpu";
 245                 };
 246
 247                 scpi_clk: scpi_clocks@3 {
 248                         compatible = "arm,scpi-clk-range";
 249                         #clock-cells = <1>;
 250                         clock-indices = <3>, <4>;
 251                         frequency-range = <23000000 210000000>;
 252                         clock-output-names = "pxlclk0", "pxlclk1";
 253                 };
 254
 255                 scpi_i2sclk: scpi_clocks@5 {
 256                         compatible = "arm,scpi-clk-range";
 257                         #clock-cells = <1>;
 258                         clock-indices = <5>;
 259                         frequency-range = <1536000 9216000>;
 260                         clock-output-names = "i2s_clock";
 261                 };
 262         };
 263
 264         cpufreq {
 265                 compatible = "arm,scpi-cpufreq";
 266         };
 267
 268         soc_uartclk: refclk72738khz {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <7273800>;
 272                 clock-output-names = "juno:uartclk";
 273         };
 274
 275         soc_refclk24mhz: clk24mhz {
 276                 compatible = "fixed-clock";
 277                 #clock-cells = <0>;
 278                 clock-frequency = <24000000>;
 279                 clock-output-names = "juno:clk24mhz";
 280         };
 281
 282         mb_eth25mhz: clk25mhz {
 283                 compatible = "fixed-clock";
 284                 #clock-cells = <0>;
 285                 clock-frequency = <25000000>;
 286                 clock-output-names = "ethclk25mhz";
 287         };
 288
 289         soc_usb48mhz: clk48mhz {
 290                 compatible = "fixed-clock";
 291                 #clock-cells = <0>;
 292                 clock-frequency = <48000000>;
 293                 clock-output-names = "clk48mhz";
 294         };
 295
 296         soc_smc50mhz: clk50mhz {
 297                 compatible = "fixed-clock";
 298                 #clock-cells = <0>;
 299                 clock-frequency = <50000000>;
 300                 clock-output-names = "smc_clk";
 301         };
 302
 303         soc_i2sclk: clki2s {
 304                 compatible = "fixed-clock";
 305                 #clock-cells = <0>;
 306                 clock-frequency = <2116800>;
 307                 clock-output-names = "i2sclk";
 308         };
 309
 310         soc_refclk100mhz: refclk100mhz {
 311                 compatible = "fixed-clock";
 312                 #clock-cells = <0>;
 313                 clock-frequency = <100000000>;
 314                 clock-output-names = "apb_pclk";
 315         };
 316
 317         soc_faxiclk: refclk533mhz {
 318                 compatible = "fixed-clock";
 319                 #clock-cells = <0>;
 320                 clock-frequency = <533000000>;
 321                 clock-output-names = "faxi_clk";
 322         };
 323
 324         soc_fixed_3v3: fixedregulator@0 {
 325                 compatible = "regulator-fixed";
 326                 regulator-name = "3V3";
 327                 regulator-min-microvolt = <3300000>;
 328                 regulator-max-microvolt = <3300000>;
 329                 regulator-always-on;
 330         };
 331
 332         memory-controller@7ffd0000 {
 333                 compatible = "arm,pl354", "arm,primecell";
 334                 reg = <0 0x7ffd0000 0 0x1000>;
 335                 interrupts = <0 86 4>,
 336                              <0 87 4>;
 337                 clocks = <&soc_smc50mhz>;
 338                 clock-names = "apb_pclk";
 339                 chip5-memwidth = <16>;
 340         };
 341
 342         dma0: dma@0x7ff00000 {
 343                 compatible = "arm,pl330", "arm,primecell";
 344                 reg = <0x0 0x7ff00000 0 0x1000>;
 345                 interrupts = <0 95 4>,
 346                              <0 88 4>,
 347                              <0 89 4>,
 348                              <0 90 4>,
 349                              <0 91 4>,
 350                              <0 108 4>,
 351                              <0 109 4>,
 352                              <0 110 4>,
 353                              <0 111 4>;
 354                 #dma-cells = <1>;
 355                 #dma-channels = <8>;
 356                 #dma-requests = <32>;
 357                 clocks = <&soc_faxiclk>;
 358                 clock-names = "apb_pclk";
 359         };
 360
 361         soc_uart0: uart@7ff80000 {
 362                 compatible = "arm,pl011", "arm,primecell";
 363                 reg = <0x0 0x7ff80000 0x0 0x1000>;
 364                 interrupts = <0 83 4>;
 365                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 366                 clock-names = "uartclk", "apb_pclk";
 367                 dmas = <&dma0 1
 368                         &dma0 2>;
 369                 dma-names = "rx", "tx";
 370         };
 371
 372         /* this UART is reserved for secure software.
 373         soc_uart1: uart@7ff70000 {
 374                 compatible = "arm,pl011", "arm,primecell";
 375                 reg = <0x0 0x7ff70000 0x0 0x1000>;
 376                 interrupts = <0 84 4>;
 377                 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
 378                 clock-names = "uartclk", "apb_pclk";
 379         }; */
 380
 381         ulpi_phy: phy@0 {
 382                 compatible = "phy-ulpi-generic";
 383                 reg = <0x0 0x94 0x0 0x4>;
 384                 phy-id = <0>;
 385         };
 386
 387         ehci@7ffc0000 {
 388                 compatible = "snps,ehci-h20ahb";
 389                 /* compatible = "arm,h20ahb-ehci"; */
 390                 reg = <0x0 0x7ffc0000 0x0 0x10000>;
 391                 interrupts = <0 117 4>;
 392                 clocks = <&soc_usb48mhz>;
 393                 clock-names = "otg";
 394                 phys = <&ulpi_phy>;
 395         };
 396
 397         ohci@0x7ffb0000 {
 398                 compatible = "generic-ohci";
 399                 reg = <0x0 0x7ffb0000 0x0 0x10000>;
 400                 interrupts = <0 116 4>;
 401                 clocks = <&soc_usb48mhz>;
 402                 clock-names = "otg";
 403         };
 404
 405         i2c@0x7ffa0000 {
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 compatible = "snps,designware-i2c";
 409                 reg = <0x0 0x7ffa0000 0x0 0x1000>;
 410                 interrupts = <0 104 4>;
 411                 clock-frequency = <400000>;
 412                 i2c-sda-hold-time-ns = <500>;
 413                 clocks = <&soc_smc50mhz>;
 414
 415                 dvi0: dvi-transmitter@70 {
 416                         compatible = "nxp,tda998x";
 417                         reg = <0x70>;
 418                         audio-ports = <0x03>, <0x04>;
 419                         audio-port-names = "i2s", "spdif";
 420                         #sound-dai-cells = <1>;
 421                 };
 422
 423                 dvi1: dvi-transmitter@71 {
 424                         compatible = "nxp,tda998x";
 425                         reg = <0x71>;
 426                         audio-ports = <0x03>, <0x04>;
 427                         audio-port-names = "i2s", "spdif";
 428                         #sound-dai-cells = <1>;
 429                 };
 430         };
 431
 432         /* mmci@1c050000 {
 433                 compatible = "arm,pl180", "arm,primecell";
 434                 reg = <0x0 0x1c050000 0x0 0x1000>;
 435                 interrupts = <0 73 4>,
 436                              <0 74 4>;
 437                 max-frequency = <12000000>;
 438                 vmmc-supply = <&soc_fixed_3v3>;
 439                 clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>;
 440                 clock-names = "mclk", "apb_pclk";
 441         }; */
 442
 443         hdlcd@7ff60000 {
 444                 compatible = "arm,hdlcd";
 445                 reg = <0 0x7ff60000 0 0x1000>;
 446                 interrupts = <0 85 4>;
 447                 clocks = <&scpi_clk 0>;
 448                 clock-names = "pxlclk";
 449                 i2c-slave = <&dvi0>;
 450
 451                 /* display-timings {
 452                         native-mode = <&timing0>;
 453                         timing0: timing@0 {
 454                                 /* 1024 x 768 framebufer, standard VGA timings * /
 455                                 clock-frequency = <65000>;
 456                                 hactive = <1024>;
 457                                 vactive = <768>;
 458                                 hfront-porch = <24>;
 459                                 hback-porch = <160>;
 460                                 hsync-len = <136>;
 461                                 vfront-porch = <3>;
 462                                 vback-porch = <29>;
 463                                 vsync-len = <6>;
 464                         };
 465                 }; */
 466         };
 467
 468         /* hdlcd@7ff50000 {
 469                 compatible = "arm,hdlcd";
 470                 reg = <0 0x7ff50000 0 0x1000>;
 471                 interrupts = <0 93 4>;
 472                 clocks = <&scpi_clk 1>;
 473                 clock-names = "pxlclk";
 474                 i2c-slave = <&dvi1>;
 475
 476                 display-timings {
 477                         native-mode = <&timing1>;
 478                         timing1: timing@1 {
 479                                 /* 1024 x 768 framebufer, standard VGA timings * /
 480                                 clock-frequency = <65000>;
 481                                 hactive = <1024>;
 482                                 vactive = <768>;
 483                                 hfront-porch = <24>;
 484                                 hback-porch = <160>;
 485                                 hsync-len = <136>;
 486                                 vfront-porch = <3>;
 487                                 vback-porch = <29>;
 488                                 vsync-len = <6>;
 489                         };
 490                 };
 491         }; */
 492
 493         gpu@0x2d000000 {
 494                 compatible = "arm,malit6xx", "arm,mali";
 495                 reg = <0x0 0x2d000000 0x0 0x4000>;
 496                 interrupts = <0 33 4>, <0 34 4>, <0 32 4>;
 497                 interrupt-names = "JOB", "MMU", "GPU";
 498                 clocks = <&scpi_dvfs 2>;
 499                 clock-names = "clk_mali";
 500         };
 501
 502         soc_i2s: i2s@7ff90000 {
 503                 compatible = "snps,i2s";
 504                 reg = <0x0 0x7ff90000 0x0 0x1000>;
 505                 clocks = <&scpi_i2sclk 0>, <&soc_refclk100mhz>;
 506                 clock-names = "i2sclk", "apb_pclk";
 507                 #sound-dai-cells = <0>;
 508                 dmas = <&dma0 5>;
 509                 dma-names = "tx";
 510         };
 511
 512         hdmi_audio: hdmi_audio@0 {
 513                 compatible = "linux,hdmi-audio";
 514                 #sound-dai-cells = <0>;
 515                 status = "okay";
 516         };
 517
 518         sound {
 519                 compatible = "simple-audio-card";
 520
 521                 simple-audio-card,format = "i2s";
 522
 523                 simple-audio-card,cpu {
 524                         sound-dai = <&soc_i2s>;
 525                 };
 526
 527                 simple-audio-card,codec {
 528                         sound-dai = <&dvi0 0>;
 529                 };
 530
 531         };
 532
 533         smb {
 534                 compatible = "simple-bus";
 535                 #address-cells = <2>;
 536                 #size-cells = <1>;
 537                 ranges = <0 0 0 0x08000000 0x04000000>,
 538                          <1 0 0 0x14000000 0x04000000>,
 539                          <2 0 0 0x18000000 0x04000000>,
 540                          <3 0 0 0x1c000000 0x04000000>,
 541                          <4 0 0 0x0c000000 0x04000000>,
 542                          <5 0 0 0x10000000 0x04000000>;
 543
 544                 #interrupt-cells = <1>;
 545                 interrupt-map-mask = <0 0 15>;
 546                 interrupt-map = <0 0  0 &gic 0  68 4>,
 547                                 <0 0  1 &gic 0  69 4>,
 548                                 <0 0  2 &gic 0  70 4>,
 549                                 <0 0  3 &gic 0 160 4>,
 550                                 <0 0  4 &gic 0 161 4>,
 551                                 <0 0  5 &gic 0 162 4>,
 552                                 <0 0  6 &gic 0 163 4>,
 553                                 <0 0  7 &gic 0 164 4>,
 554                                 <0 0  8 &gic 0 165 4>,
 555                                 <0 0  9 &gic 0 166 4>,
 556                                 <0 0 10 &gic 0 167 4>,
 557                                 <0 0 11 &gic 0 168 4>,
 558                                 <0 0 12 &gic 0 169 4>;
 559
 560                 motherboard {
 561                         model = "V2M-Juno";
 562                         arm,hbi = <0x252>;
 563                         arm,vexpress,site = <0>;
 564                         arm,v2m-memory-map = "rs1";
 565                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
 566                         #address-cells = <2>;  /* SMB chipselect number and offset */
 567                         #size-cells = <1>;
 568                         #interrupt-cells = <1>;
 569                         ranges;
 570
 571                         usb@5,00000000 {
 572                                 compatible = "nxp,usb-isp1763";
 573                                 reg = <5 0x00000000 0x20000>;
 574                                 bus-width = <16>;
 575                                 interrupts = <4>;
 576                         };
 577
 578                         ethernet@2,00000000 {
 579                                 compatible = "smsc,lan9118", "smsc,lan9115";
 580                                 reg = <2 0x00000000 0x10000>;
 581                                 interrupts = <3>;
 582                                 phy-mode = "mii";
 583                                 reg-io-width = <4>;
 584                                 smsc,irq-active-high;
 585                                 smsc,irq-push-pull;
 586                                 clocks = <&mb_eth25mhz>;
 587                                 vdd33a-supply = <&soc_fixed_3v3>; /* change this */
 588                                 vddvario-supply = <&soc_fixed_3v3>; /* and this */
 589                         };
 590
 591                         iofpga@3,00000000 {
 592                                 compatible = "arm,amba-bus", "simple-bus";
 593                                 #address-cells = <1>;
 594                                 #size-cells = <1>;
 595                                 ranges = <0 3 0 0x200000>;
 596
 597                                 kmi@060000 {
 598                                         compatible = "arm,pl050", "arm,primecell";
 599                                         reg = <0x060000 0x1000>;
 600                                         interrupts = <8>;
 601                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 602                                         clock-names = "KMIREFCLK", "apb_pclk";
 603                                 };
 604
 605                                 kmi@070000 {
 606                                         compatible = "arm,pl050", "arm,primecell";
 607                                         reg = <0x070000 0x1000>;
 608                                         interrupts = <8>;
 609                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 610                                         clock-names = "KMIREFCLK", "apb_pclk";
 611                                 };
 612
 613                                 wdt@0f0000 {
 614                                         compatible = "arm,sp805", "arm,primecell";
 615                                         reg = <0x0f0000 0x10000>;
 616                                         interrupts = <7>;
 617                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 618                                         clock-names = "wdogclk", "apb_pclk";
 619                                 };
 620
 621                                 v2m_timer01: timer@110000 {
 622                                         compatible = "arm,sp804", "arm,primecell";
 623                                         reg = <0x110000 0x10000>;
 624                                         interrupts = <9>;
 625                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 626                                         clock-names = "timclken1", "apb_pclk";
 627                                 };
 628
 629                                 v2m_timer23: timer@120000 {
 630                                         compatible = "arm,sp804", "arm,primecell";
 631                                         reg = <0x120000 0x10000>;
 632                                         interrupts = <9>;
 633                                         clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>;
 634                                         clock-names = "timclken1", "apb_pclk";
 635                                 };
 636
 637                                 rtc@170000 {
 638                                         compatible = "arm,pl031", "arm,primecell";
 639                                         reg = <0x170000 0x10000>;
 640                                         interrupts = <0>;
 641                                         clocks = <&soc_smc50mhz>;
 642                                         clock-names = "apb_pclk";
 643                                 };
 644                         };
 645                 };
 646         };
 647 };