1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
15 #include "imx8mq-pinfunc.h"
18 interrupt-parent = <&gpc>;
46 compatible = "fixed-clock";
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
66 hdmi_phy_27m: clock-hdmi-phy-27m {
67 compatible = "fixed-clock";
69 clock-frequency = <27000000>;
70 clock-output-names = "hdmi_phy_27m";
73 clk_ext1: clock-ext1 {
74 compatible = "fixed-clock";
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext1";
80 clk_ext2: clock-ext2 {
81 compatible = "fixed-clock";
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext2";
87 clk_ext3: clock-ext3 {
88 compatible = "fixed-clock";
90 clock-frequency = <133000000>;
91 clock-output-names = "clk_ext3";
94 clk_ext4: clock-ext4 {
95 compatible = "fixed-clock";
97 clock-frequency = <133000000>;
98 clock-output-names = "clk_ext4";
102 #address-cells = <1>;
107 compatible = "arm,cortex-a53";
109 clock-latency = <61036>; /* two CLK32 periods */
110 clocks = <&clk IMX8MQ_CLK_ARM>;
111 enable-method = "psci";
112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
118 next-level-cache = <&A53_L2>;
119 operating-points-v2 = <&a53_opp_table>;
120 #cooling-cells = <2>;
121 nvmem-cells = <&cpu_speed_grade>;
122 nvmem-cell-names = "speed_grade";
127 compatible = "arm,cortex-a53";
129 clock-latency = <61036>; /* two CLK32 periods */
130 clocks = <&clk IMX8MQ_CLK_ARM>;
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <128>;
138 next-level-cache = <&A53_L2>;
139 operating-points-v2 = <&a53_opp_table>;
140 #cooling-cells = <2>;
145 compatible = "arm,cortex-a53";
147 clock-latency = <61036>; /* two CLK32 periods */
148 clocks = <&clk IMX8MQ_CLK_ARM>;
149 enable-method = "psci";
150 i-cache-size = <0x8000>;
151 i-cache-line-size = <64>;
152 i-cache-sets = <256>;
153 d-cache-size = <0x8000>;
154 d-cache-line-size = <64>;
155 d-cache-sets = <128>;
156 next-level-cache = <&A53_L2>;
157 operating-points-v2 = <&a53_opp_table>;
158 #cooling-cells = <2>;
163 compatible = "arm,cortex-a53";
165 clock-latency = <61036>; /* two CLK32 periods */
166 clocks = <&clk IMX8MQ_CLK_ARM>;
167 enable-method = "psci";
168 i-cache-size = <0x8000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 next-level-cache = <&A53_L2>;
175 operating-points-v2 = <&a53_opp_table>;
176 #cooling-cells = <2>;
180 compatible = "cache";
183 cache-size = <0x100000>;
184 cache-line-size = <64>;
189 a53_opp_table: opp-table {
190 compatible = "operating-points-v2";
194 opp-hz = /bits/ 64 <800000000>;
195 opp-microvolt = <900000>;
196 /* Industrial only */
197 opp-supported-hw = <0xf>, <0x4>;
198 clock-latency-ns = <150000>;
203 opp-hz = /bits/ 64 <1000000000>;
204 opp-microvolt = <900000>;
206 opp-supported-hw = <0xe>, <0x3>;
207 clock-latency-ns = <150000>;
212 opp-hz = /bits/ 64 <1300000000>;
213 opp-microvolt = <1000000>;
214 opp-supported-hw = <0xc>, <0x4>;
215 clock-latency-ns = <150000>;
220 opp-hz = /bits/ 64 <1500000000>;
221 opp-microvolt = <1000000>;
222 opp-supported-hw = <0x8>, <0x3>;
223 clock-latency-ns = <150000>;
229 compatible = "arm,cortex-a53-pmu";
230 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-parent = <&gic>;
235 compatible = "arm,psci-1.0";
240 cpu_thermal: cpu-thermal {
241 polling-delay-passive = <250>;
242 polling-delay = <2000>;
243 thermal-sensors = <&tmu 0>;
246 cpu_alert: cpu-alert {
247 temperature = <80000>;
253 temperature = <90000>;
263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
272 polling-delay-passive = <250>;
273 polling-delay = <2000>;
274 thermal-sensors = <&tmu 1>;
277 gpu_alert: gpu-alert {
278 temperature = <80000>;
284 temperature = <90000>;
294 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
300 polling-delay-passive = <250>;
301 polling-delay = <2000>;
302 thermal-sensors = <&tmu 2>;
306 temperature = <90000>;
315 compatible = "arm,armv8-timer";
316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
317 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
318 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
319 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
320 interrupt-parent = <&gic>;
321 arm,no-tick-in-suspend;
325 compatible = "fsl,imx8mq-soc", "simple-bus";
326 #address-cells = <1>;
328 ranges = <0x0 0x0 0x0 0x3e000000>;
329 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
330 nvmem-cells = <&imx8mq_uid>;
331 nvmem-cell-names = "soc_unique_id";
334 compatible = "arm,coresight-etm4x", "arm,primecell";
335 reg = <0x28440000 0x1000>;
337 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
338 clock-names = "apb_pclk";
342 etm0_out_port: endpoint {
343 remote-endpoint = <&ca_funnel_in_port0>;
350 compatible = "arm,coresight-etm4x", "arm,primecell";
351 reg = <0x28540000 0x1000>;
353 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
354 clock-names = "apb_pclk";
358 etm1_out_port: endpoint {
359 remote-endpoint = <&ca_funnel_in_port1>;
366 compatible = "arm,coresight-etm4x", "arm,primecell";
367 reg = <0x28640000 0x1000>;
369 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
370 clock-names = "apb_pclk";
374 etm2_out_port: endpoint {
375 remote-endpoint = <&ca_funnel_in_port2>;
382 compatible = "arm,coresight-etm4x", "arm,primecell";
383 reg = <0x28740000 0x1000>;
385 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
386 clock-names = "apb_pclk";
390 etm3_out_port: endpoint {
391 remote-endpoint = <&ca_funnel_in_port3>;
399 * non-configurable funnel don't show up on the AMBA
400 * bus. As such no need to add "arm,primecell".
402 compatible = "arm,coresight-static-funnel";
405 #address-cells = <1>;
411 ca_funnel_in_port0: endpoint {
412 remote-endpoint = <&etm0_out_port>;
419 ca_funnel_in_port1: endpoint {
420 remote-endpoint = <&etm1_out_port>;
427 ca_funnel_in_port2: endpoint {
428 remote-endpoint = <&etm2_out_port>;
435 ca_funnel_in_port3: endpoint {
436 remote-endpoint = <&etm3_out_port>;
443 ca_funnel_out_port0: endpoint {
444 remote-endpoint = <&hugo_funnel_in_port0>;
451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
452 reg = <0x28c03000 0x1000>;
453 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
454 clock-names = "apb_pclk";
457 #address-cells = <1>;
463 hugo_funnel_in_port0: endpoint {
464 remote-endpoint = <&ca_funnel_out_port0>;
471 hugo_funnel_in_port1: endpoint {
475 /* the other input ports are not connect to anything */
480 hugo_funnel_out_port0: endpoint {
481 remote-endpoint = <&etf_in_port>;
488 compatible = "arm,coresight-tmc", "arm,primecell";
489 reg = <0x28c04000 0x1000>;
490 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
491 clock-names = "apb_pclk";
495 etf_in_port: endpoint {
496 remote-endpoint = <&hugo_funnel_out_port0>;
503 etf_out_port: endpoint {
504 remote-endpoint = <&etr_in_port>;
511 compatible = "arm,coresight-tmc", "arm,primecell";
512 reg = <0x28c06000 0x1000>;
513 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>;
514 clock-names = "apb_pclk";
518 etr_in_port: endpoint {
519 remote-endpoint = <&etf_out_port>;
525 aips1: bus@30000000 { /* AIPS1 */
526 compatible = "fsl,aips-bus", "simple-bus";
527 reg = <0x30000000 0x400000>;
528 #address-cells = <1>;
530 ranges = <0x30000000 0x30000000 0x400000>;
533 #sound-dai-cells = <0>;
534 compatible = "fsl,imx8mq-sai";
535 reg = <0x30010000 0x10000>;
536 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
538 <&clk IMX8MQ_CLK_SAI1_ROOT>,
539 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
541 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
542 dma-names = "rx", "tx";
547 #sound-dai-cells = <0>;
548 compatible = "fsl,imx8mq-sai";
549 reg = <0x30030000 0x10000>;
550 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
552 <&clk IMX8MQ_CLK_SAI6_ROOT>,
553 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
554 clock-names = "bus", "mclk1", "mclk2", "mclk3";
555 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
556 dma-names = "rx", "tx";
561 #sound-dai-cells = <0>;
562 compatible = "fsl,imx8mq-sai";
563 reg = <0x30040000 0x10000>;
564 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
566 <&clk IMX8MQ_CLK_SAI5_ROOT>,
567 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
568 clock-names = "bus", "mclk1", "mclk2", "mclk3";
569 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
570 dma-names = "rx", "tx";
575 #sound-dai-cells = <0>;
576 compatible = "fsl,imx8mq-sai";
577 reg = <0x30050000 0x10000>;
578 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
580 <&clk IMX8MQ_CLK_SAI4_ROOT>,
581 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
582 clock-names = "bus", "mclk1", "mclk2", "mclk3";
583 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
584 dma-names = "rx", "tx";
588 gpio1: gpio@30200000 {
589 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
590 reg = <0x30200000 0x10000>;
591 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
593 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 gpio-ranges = <&iomuxc 0 10 30>;
601 gpio2: gpio@30210000 {
602 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
603 reg = <0x30210000 0x10000>;
604 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 gpio-ranges = <&iomuxc 0 40 21>;
614 gpio3: gpio@30220000 {
615 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
616 reg = <0x30220000 0x10000>;
617 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 gpio-ranges = <&iomuxc 0 61 26>;
627 gpio4: gpio@30230000 {
628 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
629 reg = <0x30230000 0x10000>;
630 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 gpio-ranges = <&iomuxc 0 87 32>;
640 gpio5: gpio@30240000 {
641 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
642 reg = <0x30240000 0x10000>;
643 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 gpio-ranges = <&iomuxc 0 119 30>;
654 compatible = "fsl,imx8mq-tmu";
655 reg = <0x30260000 0x10000>;
656 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
657 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
659 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
660 fsl,tmu-calibration = <0x00000000 0x00000023>,
661 <0x00000001 0x00000029>,
662 <0x00000002 0x0000002f>,
663 <0x00000003 0x00000035>,
664 <0x00000004 0x0000003d>,
665 <0x00000005 0x00000043>,
666 <0x00000006 0x0000004b>,
667 <0x00000007 0x00000051>,
668 <0x00000008 0x00000057>,
669 <0x00000009 0x0000005f>,
670 <0x0000000a 0x00000067>,
671 <0x0000000b 0x0000006f>,
673 <0x00010000 0x0000001b>,
674 <0x00010001 0x00000023>,
675 <0x00010002 0x0000002b>,
676 <0x00010003 0x00000033>,
677 <0x00010004 0x0000003b>,
678 <0x00010005 0x00000043>,
679 <0x00010006 0x0000004b>,
680 <0x00010007 0x00000055>,
681 <0x00010008 0x0000005d>,
682 <0x00010009 0x00000067>,
683 <0x0001000a 0x00000070>,
685 <0x00020000 0x00000017>,
686 <0x00020001 0x00000023>,
687 <0x00020002 0x0000002d>,
688 <0x00020003 0x00000037>,
689 <0x00020004 0x00000041>,
690 <0x00020005 0x0000004b>,
691 <0x00020006 0x00000057>,
692 <0x00020007 0x00000063>,
693 <0x00020008 0x0000006f>,
695 <0x00030000 0x00000015>,
696 <0x00030001 0x00000021>,
697 <0x00030002 0x0000002d>,
698 <0x00030003 0x00000039>,
699 <0x00030004 0x00000045>,
700 <0x00030005 0x00000053>,
701 <0x00030006 0x0000005f>,
702 <0x00030007 0x00000071>;
703 #thermal-sensor-cells = <1>;
706 wdog1: watchdog@30280000 {
707 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
708 reg = <0x30280000 0x10000>;
709 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
714 wdog2: watchdog@30290000 {
715 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
716 reg = <0x30290000 0x10000>;
717 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
722 wdog3: watchdog@302a0000 {
723 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
724 reg = <0x302a0000 0x10000>;
725 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
730 sdma2: dma-controller@302c0000 {
731 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
732 reg = <0x302c0000 0x10000>;
733 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
735 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
736 clock-names = "ipg", "ahb";
738 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
741 lcdif: lcd-controller@30320000 {
742 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
743 reg = <0x30320000 0x10000>;
744 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
746 <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
747 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>;
748 clock-names = "pix", "axi", "disp_axi";
749 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
750 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
751 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
752 <&clk IMX8MQ_VIDEO_PLL1>;
753 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
754 <&clk IMX8MQ_VIDEO_PLL1>,
755 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
756 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
760 lcdif_mipi_dsi: endpoint {
761 remote-endpoint = <&mipi_dsi_lcdif_in>;
766 iomuxc: pinctrl@30330000 {
767 compatible = "fsl,imx8mq-iomuxc";
768 reg = <0x30330000 0x10000>;
771 iomuxc_gpr: syscon@30340000 {
772 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
773 reg = <0x30340000 0x10000>;
775 mux: mux-controller {
776 compatible = "mmio-mux";
777 #mux-control-cells = <1>;
778 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
782 ocotp: efuse@30350000 {
783 compatible = "fsl,imx8mq-ocotp", "syscon";
784 reg = <0x30350000 0x10000>;
785 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
786 #address-cells = <1>;
790 * The register address below maps to the MX8M
791 * Fusemap Description Table entries this way.
795 * Fuse Address = (ADDR * 4) + 0x400
796 * Note that if SIZE is greater than 4, then
797 * each subsequent fuse is located at offset
798 * +0x10 in Fusemap Description Table (e.g.
799 * reg = <0x4 0x8> describes fuses 0x410 and
802 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
806 cpu_speed_grade: speed-grade@10 { /* 0x440 */
810 fec_mac_address: mac-address@90 { /* 0x640 */
815 anatop: clock-controller@30360000 {
816 compatible = "fsl,imx8mq-anatop";
817 reg = <0x30360000 0x10000>;
818 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
822 snvs: snvs@30370000 {
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
824 reg = <0x30370000 0x10000>;
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
830 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
833 clock-names = "snvs-rtc";
836 snvs_pwrkey: snvs-powerkey {
837 compatible = "fsl,sec-v4.0-pwrkey";
839 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
841 clock-names = "snvs-pwrkey";
842 linux,keycode = <KEY_POWER>;
848 clk: clock-controller@30380000 {
849 compatible = "fsl,imx8mq-ccm";
850 reg = <0x30380000 0x10000>;
851 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
855 <&clk_ext1>, <&clk_ext2>,
856 <&clk_ext3>, <&clk_ext4>;
857 clock-names = "ckil", "osc_25m", "osc_27m",
858 "clk_ext1", "clk_ext2",
859 "clk_ext3", "clk_ext4";
860 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
861 <&clk IMX8MQ_CLK_A53_CORE>,
862 <&clk IMX8MQ_CLK_NOC>,
863 <&clk IMX8MQ_CLK_AUDIO_AHB>,
864 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
865 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
866 <&clk IMX8MQ_AUDIO_PLL1>,
867 <&clk IMX8MQ_AUDIO_PLL2>;
868 assigned-clock-rates = <0>, <0>,
875 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
876 <&clk IMX8MQ_ARM_PLL_OUT>,
878 <&clk IMX8MQ_SYS2_PLL_500M>,
879 <&clk IMX8MQ_AUDIO_PLL1>,
880 <&clk IMX8MQ_AUDIO_PLL2>;
883 src: reset-controller@30390000 {
884 compatible = "fsl,imx8mq-src", "syscon";
885 reg = <0x30390000 0x10000>;
886 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
891 compatible = "fsl,imx8mq-gpc";
892 reg = <0x303a0000 0x10000>;
893 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
894 interrupt-parent = <&gic>;
895 interrupt-controller;
896 #interrupt-cells = <3>;
899 #address-cells = <1>;
902 pgc_mipi: power-domain@0 {
903 #power-domain-cells = <0>;
904 reg = <IMX8M_POWER_DOMAIN_MIPI>;
908 * As per comment in ATF source code:
910 * PCIE1 and PCIE2 share the
911 * same reset signal, if we
912 * power down PCIE2, PCIE1
913 * will be held in reset too.
915 * So instead of creating two
916 * separate power domains for
917 * PCIE1 and PCIE2 we create a
918 * link between both and use
919 * it as a shared PCIE power
922 pgc_pcie: power-domain@1 {
923 #power-domain-cells = <0>;
924 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
925 power-domains = <&pgc_pcie2>;
928 pgc_otg1: power-domain@2 {
929 #power-domain-cells = <0>;
930 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
933 pgc_otg2: power-domain@3 {
934 #power-domain-cells = <0>;
935 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
938 pgc_ddr1: power-domain@4 {
939 #power-domain-cells = <0>;
940 reg = <IMX8M_POWER_DOMAIN_DDR1>;
943 pgc_gpu: power-domain@5 {
944 #power-domain-cells = <0>;
945 reg = <IMX8M_POWER_DOMAIN_GPU>;
946 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
947 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
948 <&clk IMX8MQ_CLK_GPU_AXI>,
949 <&clk IMX8MQ_CLK_GPU_AHB>;
952 pgc_vpu: power-domain@6 {
953 #power-domain-cells = <0>;
954 reg = <IMX8M_POWER_DOMAIN_VPU>;
955 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
956 <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
957 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
958 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
959 <&clk IMX8MQ_CLK_VPU_G2>,
960 <&clk IMX8MQ_CLK_VPU_BUS>,
961 <&clk IMX8MQ_VPU_PLL_BYPASS>;
962 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
963 <&clk IMX8MQ_VPU_PLL_OUT>,
964 <&clk IMX8MQ_SYS1_PLL_800M>,
965 <&clk IMX8MQ_VPU_PLL>;
966 assigned-clock-rates = <600000000>,
972 pgc_disp: power-domain@7 {
973 #power-domain-cells = <0>;
974 reg = <IMX8M_POWER_DOMAIN_DISP>;
977 pgc_mipi_csi1: power-domain@8 {
978 #power-domain-cells = <0>;
979 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
982 pgc_mipi_csi2: power-domain@9 {
983 #power-domain-cells = <0>;
984 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
987 pgc_pcie2: power-domain@a {
988 #power-domain-cells = <0>;
989 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
995 aips2: bus@30400000 { /* AIPS2 */
996 compatible = "fsl,aips-bus", "simple-bus";
997 reg = <0x30400000 0x400000>;
998 #address-cells = <1>;
1000 ranges = <0x30400000 0x30400000 0x400000>;
1002 pwm1: pwm@30660000 {
1003 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1004 reg = <0x30660000 0x10000>;
1005 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
1007 <&clk IMX8MQ_CLK_PWM1_ROOT>;
1008 clock-names = "ipg", "per";
1010 status = "disabled";
1013 pwm2: pwm@30670000 {
1014 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1015 reg = <0x30670000 0x10000>;
1016 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
1018 <&clk IMX8MQ_CLK_PWM2_ROOT>;
1019 clock-names = "ipg", "per";
1021 status = "disabled";
1024 pwm3: pwm@30680000 {
1025 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1026 reg = <0x30680000 0x10000>;
1027 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1028 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
1029 <&clk IMX8MQ_CLK_PWM3_ROOT>;
1030 clock-names = "ipg", "per";
1032 status = "disabled";
1035 pwm4: pwm@30690000 {
1036 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1037 reg = <0x30690000 0x10000>;
1038 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
1040 <&clk IMX8MQ_CLK_PWM4_ROOT>;
1041 clock-names = "ipg", "per";
1043 status = "disabled";
1046 system_counter: timer@306a0000 {
1047 compatible = "nxp,sysctr-timer";
1048 reg = <0x306a0000 0x20000>;
1049 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&osc_25m>;
1051 clock-names = "per";
1055 aips3: bus@30800000 { /* AIPS3 */
1056 compatible = "fsl,aips-bus", "simple-bus";
1057 reg = <0x30800000 0x400000>;
1058 #address-cells = <1>;
1060 ranges = <0x30800000 0x30800000 0x400000>,
1061 <0x08000000 0x08000000 0x10000000>;
1063 spdif1: spdif@30810000 {
1064 compatible = "fsl,imx35-spdif";
1065 reg = <0x30810000 0x10000>;
1066 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
1068 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
1069 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */
1070 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
1071 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
1072 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
1073 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
1074 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
1075 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
1076 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
1077 clock-names = "core", "rxtx0",
1082 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
1083 dma-names = "rx", "tx";
1084 status = "disabled";
1087 ecspi1: spi@30820000 {
1088 #address-cells = <1>;
1090 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1091 reg = <0x30820000 0x10000>;
1092 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
1094 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
1095 clock-names = "ipg", "per";
1096 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1097 dma-names = "rx", "tx";
1098 status = "disabled";
1101 ecspi2: spi@30830000 {
1102 #address-cells = <1>;
1104 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1105 reg = <0x30830000 0x10000>;
1106 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
1108 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
1109 clock-names = "ipg", "per";
1110 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1111 dma-names = "rx", "tx";
1112 status = "disabled";
1115 ecspi3: spi@30840000 {
1116 #address-cells = <1>;
1118 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1119 reg = <0x30840000 0x10000>;
1120 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
1122 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
1123 clock-names = "ipg", "per";
1124 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1125 dma-names = "rx", "tx";
1126 status = "disabled";
1129 uart1: serial@30860000 {
1130 compatible = "fsl,imx8mq-uart",
1132 reg = <0x30860000 0x10000>;
1133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1134 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
1135 <&clk IMX8MQ_CLK_UART1_ROOT>;
1136 clock-names = "ipg", "per";
1137 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1138 dma-names = "rx", "tx";
1139 status = "disabled";
1142 uart3: serial@30880000 {
1143 compatible = "fsl,imx8mq-uart",
1145 reg = <0x30880000 0x10000>;
1146 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
1148 <&clk IMX8MQ_CLK_UART3_ROOT>;
1149 clock-names = "ipg", "per";
1150 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1151 dma-names = "rx", "tx";
1152 status = "disabled";
1155 uart2: serial@30890000 {
1156 compatible = "fsl,imx8mq-uart",
1158 reg = <0x30890000 0x10000>;
1159 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
1161 <&clk IMX8MQ_CLK_UART2_ROOT>;
1162 clock-names = "ipg", "per";
1163 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1164 dma-names = "rx", "tx";
1165 status = "disabled";
1168 spdif2: spdif@308a0000 {
1169 compatible = "fsl,imx35-spdif";
1170 reg = <0x308a0000 0x10000>;
1171 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */
1173 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */
1174 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */
1175 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */
1176 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */
1177 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */
1178 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */
1179 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */
1180 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */
1181 <&clk IMX8MQ_CLK_DUMMY>; /* spba */
1182 clock-names = "core", "rxtx0",
1187 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
1188 dma-names = "rx", "tx";
1189 status = "disabled";
1192 sai2: sai@308b0000 {
1193 #sound-dai-cells = <0>;
1194 compatible = "fsl,imx8mq-sai";
1195 reg = <0x308b0000 0x10000>;
1196 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
1198 <&clk IMX8MQ_CLK_SAI2_ROOT>,
1199 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
1200 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1201 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
1202 dma-names = "rx", "tx";
1203 status = "disabled";
1206 sai3: sai@308c0000 {
1207 #sound-dai-cells = <0>;
1208 compatible = "fsl,imx8mq-sai";
1209 reg = <0x308c0000 0x10000>;
1210 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1211 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
1212 <&clk IMX8MQ_CLK_SAI3_ROOT>,
1213 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
1214 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1215 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1216 dma-names = "rx", "tx";
1217 status = "disabled";
1220 crypto: crypto@30900000 {
1221 compatible = "fsl,sec-v4.0";
1222 #address-cells = <1>;
1224 reg = <0x30900000 0x40000>;
1225 ranges = <0 0x30900000 0x40000>;
1226 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1227 clocks = <&clk IMX8MQ_CLK_AHB>,
1228 <&clk IMX8MQ_CLK_IPG_ROOT>;
1229 clock-names = "aclk", "ipg";
1232 compatible = "fsl,sec-v4.0-job-ring";
1233 reg = <0x1000 0x1000>;
1234 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1235 status = "disabled";
1239 compatible = "fsl,sec-v4.0-job-ring";
1240 reg = <0x2000 0x1000>;
1241 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1245 compatible = "fsl,sec-v4.0-job-ring";
1246 reg = <0x3000 0x1000>;
1247 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1251 mipi_dsi: dsi@30a00000 {
1252 compatible = "fsl,imx8mq-nwl-dsi";
1253 reg = <0x30a00000 0x300>;
1254 #address-cells = <1>;
1256 clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
1257 <&clk IMX8MQ_CLK_DSI_AHB>,
1258 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
1259 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1260 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
1261 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1262 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1263 <&clk IMX8MQ_CLK_DSI_CORE>,
1264 <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
1265 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1266 <&clk IMX8MQ_SYS1_PLL_266M>;
1267 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1269 mux-controls = <&mux 0>;
1270 power-domains = <&pgc_mipi>;
1273 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
1274 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
1275 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
1276 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
1277 reset-names = "byte", "dpi", "esc", "pclk";
1278 status = "disabled";
1281 #address-cells = <1>;
1286 #address-cells = <1>;
1288 mipi_dsi_lcdif_in: endpoint@0 {
1290 remote-endpoint = <&lcdif_mipi_dsi>;
1296 dphy: dphy@30a00300 {
1297 compatible = "fsl,imx8mq-mipi-dphy";
1298 reg = <0x30a00300 0x100>;
1299 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
1300 clock-names = "phy_ref";
1301 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1302 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
1303 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
1304 <&clk IMX8MQ_VIDEO_PLL1>;
1305 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1306 <&clk IMX8MQ_VIDEO_PLL1>,
1307 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
1308 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1310 power-domains = <&pgc_mipi>;
1311 status = "disabled";
1314 i2c1: i2c@30a20000 {
1315 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1316 reg = <0x30a20000 0x10000>;
1317 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
1319 #address-cells = <1>;
1321 status = "disabled";
1324 i2c2: i2c@30a30000 {
1325 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1326 reg = <0x30a30000 0x10000>;
1327 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1328 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
1329 #address-cells = <1>;
1331 status = "disabled";
1334 i2c3: i2c@30a40000 {
1335 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1336 reg = <0x30a40000 0x10000>;
1337 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1338 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
1339 #address-cells = <1>;
1341 status = "disabled";
1344 i2c4: i2c@30a50000 {
1345 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1346 reg = <0x30a50000 0x10000>;
1347 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1348 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
1349 #address-cells = <1>;
1351 status = "disabled";
1354 uart4: serial@30a60000 {
1355 compatible = "fsl,imx8mq-uart",
1357 reg = <0x30a60000 0x10000>;
1358 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
1360 <&clk IMX8MQ_CLK_UART4_ROOT>;
1361 clock-names = "ipg", "per";
1362 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1363 dma-names = "rx", "tx";
1364 status = "disabled";
1367 mipi_csi1: csi@30a70000 {
1368 compatible = "fsl,imx8mq-mipi-csi2";
1369 reg = <0x30a70000 0x1000>;
1370 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1371 <&clk IMX8MQ_CLK_CSI1_ESC>,
1372 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
1373 clock-names = "core", "esc", "ui";
1374 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1375 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
1376 <&clk IMX8MQ_CLK_CSI1_ESC>;
1377 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1378 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1379 <&clk IMX8MQ_SYS2_PLL_1000M>,
1380 <&clk IMX8MQ_SYS1_PLL_800M>;
1381 power-domains = <&pgc_mipi_csi1>;
1382 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
1383 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
1384 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
1385 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1386 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1387 interconnect-names = "dram";
1388 status = "disabled";
1391 #address-cells = <1>;
1397 csi1_mipi_ep: endpoint {
1398 remote-endpoint = <&csi1_ep>;
1404 csi1: csi@30a90000 {
1405 compatible = "fsl,imx8mq-csi";
1406 reg = <0x30a90000 0x10000>;
1407 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1408 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>;
1409 clock-names = "mclk";
1410 status = "disabled";
1414 remote-endpoint = <&csi1_mipi_ep>;
1419 mipi_csi2: csi@30b60000 {
1420 compatible = "fsl,imx8mq-mipi-csi2";
1421 reg = <0x30b60000 0x1000>;
1422 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1423 <&clk IMX8MQ_CLK_CSI2_ESC>,
1424 <&clk IMX8MQ_CLK_CSI2_PHY_REF>;
1425 clock-names = "core", "esc", "ui";
1426 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1427 <&clk IMX8MQ_CLK_CSI2_PHY_REF>,
1428 <&clk IMX8MQ_CLK_CSI2_ESC>;
1429 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1430 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1431 <&clk IMX8MQ_SYS2_PLL_1000M>,
1432 <&clk IMX8MQ_SYS1_PLL_800M>;
1433 power-domains = <&pgc_mipi_csi2>;
1434 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>,
1435 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>,
1436 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>;
1437 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1438 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1439 interconnect-names = "dram";
1440 status = "disabled";
1443 #address-cells = <1>;
1449 csi2_mipi_ep: endpoint {
1450 remote-endpoint = <&csi2_ep>;
1456 csi2: csi@30b80000 {
1457 compatible = "fsl,imx8mq-csi";
1458 reg = <0x30b80000 0x10000>;
1459 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1460 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>;
1461 clock-names = "mclk";
1462 status = "disabled";
1466 remote-endpoint = <&csi2_mipi_ep>;
1471 mu: mailbox@30aa0000 {
1472 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1473 reg = <0x30aa0000 0x10000>;
1474 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1475 clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
1479 usdhc1: mmc@30b40000 {
1480 compatible = "fsl,imx8mq-usdhc",
1482 reg = <0x30b40000 0x10000>;
1483 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1485 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1486 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
1487 clock-names = "ipg", "ahb", "per";
1488 fsl,tuning-start-tap = <20>;
1489 fsl,tuning-step = <2>;
1491 status = "disabled";
1494 usdhc2: mmc@30b50000 {
1495 compatible = "fsl,imx8mq-usdhc",
1497 reg = <0x30b50000 0x10000>;
1498 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1499 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
1500 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
1501 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
1502 clock-names = "ipg", "ahb", "per";
1503 fsl,tuning-start-tap = <20>;
1504 fsl,tuning-step = <2>;
1506 status = "disabled";
1509 qspi0: spi@30bb0000 {
1510 #address-cells = <1>;
1512 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1513 reg = <0x30bb0000 0x10000>,
1514 <0x08000000 0x10000000>;
1515 reg-names = "QuadSPI", "QuadSPI-memory";
1516 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1517 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
1518 <&clk IMX8MQ_CLK_QSPI_ROOT>;
1519 clock-names = "qspi_en", "qspi";
1520 status = "disabled";
1523 sdma1: dma-controller@30bd0000 {
1524 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1525 reg = <0x30bd0000 0x10000>;
1526 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1527 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1528 <&clk IMX8MQ_CLK_AHB>;
1529 clock-names = "ipg", "ahb";
1531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1534 fec1: ethernet@30be0000 {
1535 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1536 reg = <0x30be0000 0x10000>;
1537 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1541 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1542 <&clk IMX8MQ_CLK_ENET1_ROOT>,
1543 <&clk IMX8MQ_CLK_ENET_TIMER>,
1544 <&clk IMX8MQ_CLK_ENET_REF>,
1545 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1546 clock-names = "ipg", "ahb", "ptp",
1547 "enet_clk_ref", "enet_out";
1548 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1549 <&clk IMX8MQ_CLK_ENET_TIMER>,
1550 <&clk IMX8MQ_CLK_ENET_REF>,
1551 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1552 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1553 <&clk IMX8MQ_SYS2_PLL_100M>,
1554 <&clk IMX8MQ_SYS2_PLL_125M>,
1555 <&clk IMX8MQ_SYS2_PLL_50M>;
1556 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1557 fsl,num-tx-queues = <3>;
1558 fsl,num-rx-queues = <3>;
1559 nvmem-cells = <&fec_mac_address>;
1560 nvmem-cell-names = "mac-address";
1561 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1562 status = "disabled";
1566 noc: interconnect@32700000 {
1567 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1568 reg = <0x32700000 0x100000>;
1569 clocks = <&clk IMX8MQ_CLK_NOC>;
1571 #interconnect-cells = <1>;
1572 operating-points-v2 = <&noc_opp_table>;
1574 noc_opp_table: opp-table {
1575 compatible = "operating-points-v2";
1578 opp-hz = /bits/ 64 <133333333>;
1582 opp-hz = /bits/ 64 <400000000>;
1586 opp-hz = /bits/ 64 <800000000>;
1591 aips4: bus@32c00000 { /* AIPS4 */
1592 compatible = "fsl,aips-bus", "simple-bus";
1593 reg = <0x32c00000 0x400000>;
1594 #address-cells = <1>;
1596 ranges = <0x32c00000 0x32c00000 0x400000>;
1598 irqsteer: interrupt-controller@32e2d000 {
1599 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1600 reg = <0x32e2d000 0x1000>;
1601 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1602 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1603 clock-names = "ipg";
1605 fsl,num-irqs = <64>;
1606 interrupt-controller;
1607 #interrupt-cells = <1>;
1612 compatible = "vivante,gc";
1613 reg = <0x38000000 0x40000>;
1614 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1615 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1616 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1617 <&clk IMX8MQ_CLK_GPU_AXI>,
1618 <&clk IMX8MQ_CLK_GPU_AHB>;
1619 clock-names = "core", "shader", "bus", "reg";
1620 #cooling-cells = <2>;
1621 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1622 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1623 <&clk IMX8MQ_CLK_GPU_AXI>,
1624 <&clk IMX8MQ_CLK_GPU_AHB>,
1625 <&clk IMX8MQ_GPU_PLL_BYPASS>;
1626 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1627 <&clk IMX8MQ_GPU_PLL_OUT>,
1628 <&clk IMX8MQ_GPU_PLL_OUT>,
1629 <&clk IMX8MQ_GPU_PLL_OUT>,
1630 <&clk IMX8MQ_GPU_PLL>;
1631 assigned-clock-rates = <800000000>, <800000000>,
1632 <800000000>, <800000000>, <0>;
1633 power-domains = <&pgc_gpu>;
1636 usb_dwc3_0: usb@38100000 {
1637 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1638 reg = <0x38100000 0x10000>;
1639 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1640 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1641 <&clk IMX8MQ_CLK_32K>;
1642 clock-names = "bus_early", "ref", "suspend";
1643 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1644 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1645 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1646 <&clk IMX8MQ_SYS1_PLL_100M>;
1647 assigned-clock-rates = <500000000>, <100000000>;
1648 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1649 phys = <&usb3_phy0>, <&usb3_phy0>;
1650 phy-names = "usb2-phy", "usb3-phy";
1651 power-domains = <&pgc_otg1>;
1652 status = "disabled";
1655 usb3_phy0: usb-phy@381f0040 {
1656 compatible = "fsl,imx8mq-usb-phy";
1657 reg = <0x381f0040 0x40>;
1658 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1659 clock-names = "phy";
1660 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1661 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1662 assigned-clock-rates = <100000000>;
1664 status = "disabled";
1667 usb_dwc3_1: usb@38200000 {
1668 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1669 reg = <0x38200000 0x10000>;
1670 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1671 <&clk IMX8MQ_CLK_USB_CORE_REF>,
1672 <&clk IMX8MQ_CLK_32K>;
1673 clock-names = "bus_early", "ref", "suspend";
1674 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1675 <&clk IMX8MQ_CLK_USB_CORE_REF>;
1676 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1677 <&clk IMX8MQ_SYS1_PLL_100M>;
1678 assigned-clock-rates = <500000000>, <100000000>;
1679 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1680 phys = <&usb3_phy1>, <&usb3_phy1>;
1681 phy-names = "usb2-phy", "usb3-phy";
1682 power-domains = <&pgc_otg2>;
1683 status = "disabled";
1686 usb3_phy1: usb-phy@382f0040 {
1687 compatible = "fsl,imx8mq-usb-phy";
1688 reg = <0x382f0040 0x40>;
1689 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1690 clock-names = "phy";
1691 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1692 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1693 assigned-clock-rates = <100000000>;
1695 status = "disabled";
1698 vpu_g1: video-codec@38300000 {
1699 compatible = "nxp,imx8mq-vpu-g1";
1700 reg = <0x38300000 0x10000>;
1701 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1702 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
1703 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1706 vpu_g2: video-codec@38310000 {
1707 compatible = "nxp,imx8mq-vpu-g2";
1708 reg = <0x38310000 0x10000>;
1709 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1710 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1711 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1714 vpu_blk_ctrl: blk-ctrl@38320000 {
1715 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1716 reg = <0x38320000 0x100>;
1717 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1718 power-domain-names = "bus", "g1", "g2";
1719 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
1720 <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
1721 clock-names = "g1", "g2";
1722 #power-domain-cells = <1>;
1725 pcie0: pcie@33800000 {
1726 compatible = "fsl,imx8mq-pcie";
1727 reg = <0x33800000 0x400000>,
1728 <0x1ff00000 0x80000>;
1729 reg-names = "dbi", "config";
1730 #address-cells = <3>;
1732 device_type = "pci";
1733 bus-range = <0x00 0xff>;
1734 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1735 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1737 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1738 interrupt-names = "msi";
1739 #interrupt-cells = <1>;
1740 interrupt-map-mask = <0 0 0 0x7>;
1741 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1742 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1743 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1744 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1745 fsl,max-link-speed = <2>;
1746 linux,pci-domain = <0>;
1747 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
1748 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1749 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1750 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1751 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1752 power-domains = <&pgc_pcie>;
1753 resets = <&src IMX8MQ_RESET_PCIEPHY>,
1754 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1755 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1756 reset-names = "pciephy", "apps", "turnoff";
1757 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1758 <&clk IMX8MQ_CLK_PCIE1_PHY>,
1759 <&clk IMX8MQ_CLK_PCIE1_AUX>;
1760 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1761 <&clk IMX8MQ_SYS2_PLL_100M>,
1762 <&clk IMX8MQ_SYS1_PLL_80M>;
1763 assigned-clock-rates = <250000000>, <100000000>,
1765 status = "disabled";
1768 pcie1: pcie@33c00000 {
1769 compatible = "fsl,imx8mq-pcie";
1770 reg = <0x33c00000 0x400000>,
1771 <0x27f00000 0x80000>;
1772 reg-names = "dbi", "config";
1773 #address-cells = <3>;
1775 device_type = "pci";
1776 bus-range = <0x00 0xff>;
1777 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1778 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1780 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1781 interrupt-names = "msi";
1782 #interrupt-cells = <1>;
1783 interrupt-map-mask = <0 0 0 0x7>;
1784 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1785 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1786 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1787 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1788 fsl,max-link-speed = <2>;
1789 linux,pci-domain = <1>;
1790 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
1791 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1792 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1793 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1794 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1795 power-domains = <&pgc_pcie>;
1796 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1797 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1798 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1799 reset-names = "pciephy", "apps", "turnoff";
1800 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1801 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1802 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1803 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1804 <&clk IMX8MQ_SYS2_PLL_100M>,
1805 <&clk IMX8MQ_SYS1_PLL_80M>;
1806 assigned-clock-rates = <250000000>, <100000000>,
1808 status = "disabled";
1811 pcie1_ep: pcie-ep@33c00000 {
1812 compatible = "fsl,imx8mq-pcie-ep";
1813 reg = <0x33c00000 0x000400000>,
1814 <0x20000000 0x08000000>;
1815 reg-names = "dbi", "addr_space";
1817 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1818 interrupt-names = "dma";
1819 fsl,max-link-speed = <2>;
1820 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
1821 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1822 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1823 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1824 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1825 power-domains = <&pgc_pcie>;
1826 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1827 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1828 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1829 reset-names = "pciephy", "apps", "turnoff";
1830 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1831 <&clk IMX8MQ_CLK_PCIE2_PHY>,
1832 <&clk IMX8MQ_CLK_PCIE2_AUX>;
1833 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1834 <&clk IMX8MQ_SYS2_PLL_100M>,
1835 <&clk IMX8MQ_SYS1_PLL_80M>;
1836 assigned-clock-rates = <250000000>, <100000000>,
1838 num-ib-windows = <4>;
1839 num-ob-windows = <4>;
1840 status = "disabled";
1843 gic: interrupt-controller@38800000 {
1844 compatible = "arm,gic-v3";
1845 reg = <0x38800000 0x10000>, /* GIC Dist */
1846 <0x38880000 0xc0000>, /* GICR */
1847 <0x31000000 0x2000>, /* GICC */
1848 <0x31010000 0x2000>, /* GICV */
1849 <0x31020000 0x2000>; /* GICH */
1850 #interrupt-cells = <3>;
1851 interrupt-controller;
1852 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1853 interrupt-parent = <&gic>;
1856 ddrc: memory-controller@3d400000 {
1857 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1858 reg = <0x3d400000 0x400000>;
1859 clock-names = "core", "pll", "alt", "apb";
1860 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1861 <&clk IMX8MQ_DRAM_PLL_OUT>,
1862 <&clk IMX8MQ_CLK_DRAM_ALT>,
1863 <&clk IMX8MQ_CLK_DRAM_APB>;
1864 status = "disabled";
1868 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1869 reg = <0x3d800000 0x400000>;
1870 interrupt-parent = <&gic>;
1871 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;