1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
125 compatible = "cache";
128 cache-size = <0x80000>;
129 cache-line-size = <64>;
134 a53_opp_table: opp-table {
135 compatible = "operating-points-v2";
139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <150000>;
147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <950000>;
149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <150000>;
155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <150000>;
163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock";
166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k";
170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m";
177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock";
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1";
184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock";
187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2";
191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock";
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3";
198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock";
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4";
206 #address-cells = <2>;
210 dsp_reserved: dsp@92400000 {
211 reg = <0 0x92400000 0 0x2000000>;
217 compatible = "arm,cortex-a53-pmu";
218 interrupts = <GIC_PPI 7
219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223 compatible = "arm,psci-1.0";
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tmu 0>;
234 temperature = <85000>;
240 temperature = <95000>;
248 trip = <&cpu_alert0>;
250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
259 polling-delay-passive = <250>;
260 polling-delay = <2000>;
261 thermal-sensors = <&tmu 1>;
264 temperature = <85000>;
270 temperature = <95000>;
278 trip = <&soc_alert0>;
280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
290 compatible = "arm,armv8-timer";
291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
295 clock-frequency = <8000000>;
296 arm,no-tick-in-suspend;
300 compatible = "fsl,imx8mp-soc", "simple-bus";
301 #address-cells = <1>;
303 ranges = <0x0 0x0 0x0 0x3e000000>;
304 nvmem-cells = <&imx8mp_uid>;
305 nvmem-cell-names = "soc_unique_id";
308 compatible = "arm,coresight-etm4x", "arm,primecell";
309 reg = <0x28440000 0x10000>;
310 arm,primecell-periphid = <0xbb95d>;
312 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
313 clock-names = "apb_pclk";
317 etm0_out_port: endpoint {
318 remote-endpoint = <&ca_funnel_in_port0>;
325 compatible = "arm,coresight-etm4x", "arm,primecell";
326 reg = <0x28540000 0x10000>;
327 arm,primecell-periphid = <0xbb95d>;
329 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
330 clock-names = "apb_pclk";
334 etm1_out_port: endpoint {
335 remote-endpoint = <&ca_funnel_in_port1>;
342 compatible = "arm,coresight-etm4x", "arm,primecell";
343 reg = <0x28640000 0x10000>;
344 arm,primecell-periphid = <0xbb95d>;
346 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
347 clock-names = "apb_pclk";
351 etm2_out_port: endpoint {
352 remote-endpoint = <&ca_funnel_in_port2>;
359 compatible = "arm,coresight-etm4x", "arm,primecell";
360 reg = <0x28740000 0x10000>;
361 arm,primecell-periphid = <0xbb95d>;
363 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
364 clock-names = "apb_pclk";
368 etm3_out_port: endpoint {
369 remote-endpoint = <&ca_funnel_in_port3>;
377 * non-configurable funnel don't show up on the AMBA
378 * bus. As such no need to add "arm,primecell".
380 compatible = "arm,coresight-static-funnel";
383 #address-cells = <1>;
389 ca_funnel_in_port0: endpoint {
390 remote-endpoint = <&etm0_out_port>;
397 ca_funnel_in_port1: endpoint {
398 remote-endpoint = <&etm1_out_port>;
405 ca_funnel_in_port2: endpoint {
406 remote-endpoint = <&etm2_out_port>;
413 ca_funnel_in_port3: endpoint {
414 remote-endpoint = <&etm3_out_port>;
421 ca_funnel_out_port0: endpoint {
422 remote-endpoint = <&hugo_funnel_in_port0>;
429 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
430 reg = <0x28c03000 0x1000>;
431 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
432 clock-names = "apb_pclk";
435 #address-cells = <1>;
441 hugo_funnel_in_port0: endpoint {
442 remote-endpoint = <&ca_funnel_out_port0>;
449 hugo_funnel_in_port1: endpoint {
457 hugo_funnel_in_port2: endpoint {
461 /* the other input ports are not connect to anything */
466 hugo_funnel_out_port0: endpoint {
467 remote-endpoint = <&etf_in_port>;
474 compatible = "arm,coresight-tmc", "arm,primecell";
475 reg = <0x28c04000 0x1000>;
476 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
477 clock-names = "apb_pclk";
481 etf_in_port: endpoint {
482 remote-endpoint = <&hugo_funnel_out_port0>;
489 etf_out_port: endpoint {
490 remote-endpoint = <&etr_in_port>;
497 compatible = "arm,coresight-tmc", "arm,primecell";
498 reg = <0x28c06000 0x1000>;
499 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
500 clock-names = "apb_pclk";
504 etr_in_port: endpoint {
505 remote-endpoint = <&etf_out_port>;
511 aips1: bus@30000000 {
512 compatible = "fsl,aips-bus", "simple-bus";
513 reg = <0x30000000 0x400000>;
514 #address-cells = <1>;
518 gpio1: gpio@30200000 {
519 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
520 reg = <0x30200000 0x10000>;
521 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 gpio-ranges = <&iomuxc 0 5 30>;
531 gpio2: gpio@30210000 {
532 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
533 reg = <0x30210000 0x10000>;
534 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 gpio-ranges = <&iomuxc 0 35 21>;
544 gpio3: gpio@30220000 {
545 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
546 reg = <0x30220000 0x10000>;
547 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
557 gpio4: gpio@30230000 {
558 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
559 reg = <0x30230000 0x10000>;
560 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 gpio-ranges = <&iomuxc 0 82 32>;
570 gpio5: gpio@30240000 {
571 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
572 reg = <0x30240000 0x10000>;
573 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 gpio-ranges = <&iomuxc 0 114 30>;
584 compatible = "fsl,imx8mp-tmu";
585 reg = <0x30260000 0x10000>;
586 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
587 nvmem-cells = <&tmu_calib>;
588 nvmem-cell-names = "calib";
589 #thermal-sensor-cells = <1>;
592 wdog1: watchdog@30280000 {
593 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
594 reg = <0x30280000 0x10000>;
595 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
600 wdog2: watchdog@30290000 {
601 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
602 reg = <0x30290000 0x10000>;
603 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
608 wdog3: watchdog@302a0000 {
609 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
610 reg = <0x302a0000 0x10000>;
611 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
616 gpt1: timer@302d0000 {
617 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
618 reg = <0x302d0000 0x10000>;
619 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
621 clock-names = "ipg", "per";
624 gpt2: timer@302e0000 {
625 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
626 reg = <0x302e0000 0x10000>;
627 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
629 clock-names = "ipg", "per";
632 gpt3: timer@302f0000 {
633 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
634 reg = <0x302f0000 0x10000>;
635 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
637 clock-names = "ipg", "per";
640 iomuxc: pinctrl@30330000 {
641 compatible = "fsl,imx8mp-iomuxc";
642 reg = <0x30330000 0x10000>;
645 gpr: syscon@30340000 {
646 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
647 reg = <0x30340000 0x10000>;
650 ocotp: efuse@30350000 {
651 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
652 reg = <0x30350000 0x10000>;
653 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
654 /* For nvmem subnodes */
655 #address-cells = <1>;
659 * The register address below maps to the MX8M
660 * Fusemap Description Table entries this way.
664 * Fuse Address = (ADDR * 4) + 0x400
665 * Note that if SIZE is greater than 4, then
666 * each subsequent fuse is located at offset
667 * +0x10 in Fusemap Description Table (e.g.
668 * reg = <0x8 0x8> describes fuses 0x420 and
671 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
675 cpu_speed_grade: speed-grade@10 { /* 0x440 */
679 eth_mac1: mac-address@90 { /* 0x640 */
683 eth_mac2: mac-address@96 { /* 0x658 */
687 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
692 anatop: clock-controller@30360000 {
693 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
694 reg = <0x30360000 0x10000>;
698 snvs: snvs@30370000 {
699 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
700 reg = <0x30370000 0x10000>;
702 snvs_rtc: snvs-rtc-lp {
703 compatible = "fsl,sec-v4.0-mon-rtc-lp";
706 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
709 clock-names = "snvs-rtc";
712 snvs_pwrkey: snvs-powerkey {
713 compatible = "fsl,sec-v4.0-pwrkey";
715 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
717 clock-names = "snvs-pwrkey";
718 linux,keycode = <KEY_POWER>;
723 snvs_lpgpr: snvs-lpgpr {
724 compatible = "fsl,imx8mp-snvs-lpgpr",
725 "fsl,imx7d-snvs-lpgpr";
729 clk: clock-controller@30380000 {
730 compatible = "fsl,imx8mp-ccm";
731 reg = <0x30380000 0x10000>;
733 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk_ext3>, <&clk_ext4>;
735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 "clk_ext3", "clk_ext4";
737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 <&clk IMX8MP_CLK_A53_CORE>,
739 <&clk IMX8MP_CLK_NOC>,
740 <&clk IMX8MP_CLK_NOC_IO>,
741 <&clk IMX8MP_CLK_GIC>;
742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 <&clk IMX8MP_ARM_PLL_OUT>,
744 <&clk IMX8MP_SYS_PLL2_1000M>,
745 <&clk IMX8MP_SYS_PLL1_800M>,
746 <&clk IMX8MP_SYS_PLL2_500M>;
747 assigned-clock-rates = <0>, <0>,
753 src: reset-controller@30390000 {
754 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390000 0x10000>;
756 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
761 compatible = "fsl,imx8mp-gpc";
762 reg = <0x303a0000 0x1000>;
763 interrupt-parent = <&gic>;
764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-controller;
766 #interrupt-cells = <3>;
769 #address-cells = <1>;
772 pgc_mipi_phy1: power-domain@0 {
773 #power-domain-cells = <0>;
774 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
777 pgc_pcie_phy: power-domain@1 {
778 #power-domain-cells = <0>;
779 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
782 pgc_usb1_phy: power-domain@2 {
783 #power-domain-cells = <0>;
784 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
787 pgc_usb2_phy: power-domain@3 {
788 #power-domain-cells = <0>;
789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
792 pgc_audio: power-domain@5 {
793 #power-domain-cells = <0>;
794 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
795 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
796 <&clk IMX8MP_CLK_AUDIO_AXI>;
799 pgc_gpu2d: power-domain@6 {
800 #power-domain-cells = <0>;
801 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
802 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
803 power-domains = <&pgc_gpumix>;
806 pgc_gpumix: power-domain@7 {
807 #power-domain-cells = <0>;
808 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
809 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
810 <&clk IMX8MP_CLK_GPU_AHB>;
811 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
812 <&clk IMX8MP_CLK_GPU_AHB>;
813 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
814 <&clk IMX8MP_SYS_PLL1_800M>;
815 assigned-clock-rates = <800000000>, <400000000>;
818 pgc_gpu3d: power-domain@9 {
819 #power-domain-cells = <0>;
820 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
821 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
822 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
823 power-domains = <&pgc_gpumix>;
826 pgc_mediamix: power-domain@10 {
827 #power-domain-cells = <0>;
828 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
829 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
830 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
833 pgc_mipi_phy2: power-domain@16 {
834 #power-domain-cells = <0>;
835 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
838 pgc_hsiomix: power-domain@17 {
839 #power-domain-cells = <0>;
840 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
841 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
842 <&clk IMX8MP_CLK_HSIO_ROOT>;
843 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
844 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
845 assigned-clock-rates = <500000000>;
848 pgc_ispdwp: power-domain@18 {
849 #power-domain-cells = <0>;
850 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
851 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
854 pgc_vpumix: power-domain@19 {
855 #power-domain-cells = <0>;
856 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
857 clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
860 pgc_vpu_g1: power-domain@20 {
861 #power-domain-cells = <0>;
862 power-domains = <&pgc_vpumix>;
863 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
864 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
867 pgc_vpu_g2: power-domain@21 {
868 #power-domain-cells = <0>;
869 power-domains = <&pgc_vpumix>;
870 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
871 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
874 pgc_vpu_vc8000e: power-domain@22 {
875 #power-domain-cells = <0>;
876 power-domains = <&pgc_vpumix>;
877 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
878 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
881 pgc_mlmix: power-domain@24 {
882 #power-domain-cells = <0>;
883 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
884 clocks = <&clk IMX8MP_CLK_ML_AXI>,
885 <&clk IMX8MP_CLK_ML_AHB>,
886 <&clk IMX8MP_CLK_NPU_ROOT>;
892 aips2: bus@30400000 {
893 compatible = "fsl,aips-bus", "simple-bus";
894 reg = <0x30400000 0x400000>;
895 #address-cells = <1>;
900 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
901 reg = <0x30660000 0x10000>;
902 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
904 <&clk IMX8MP_CLK_PWM1_ROOT>;
905 clock-names = "ipg", "per";
911 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
912 reg = <0x30670000 0x10000>;
913 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
914 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
915 <&clk IMX8MP_CLK_PWM2_ROOT>;
916 clock-names = "ipg", "per";
922 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
923 reg = <0x30680000 0x10000>;
924 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
926 <&clk IMX8MP_CLK_PWM3_ROOT>;
927 clock-names = "ipg", "per";
933 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30690000 0x10000>;
935 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
937 <&clk IMX8MP_CLK_PWM4_ROOT>;
938 clock-names = "ipg", "per";
943 system_counter: timer@306a0000 {
944 compatible = "nxp,sysctr-timer";
945 reg = <0x306a0000 0x20000>;
946 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
951 gpt6: timer@306e0000 {
952 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
953 reg = <0x306e0000 0x10000>;
954 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
956 clock-names = "ipg", "per";
959 gpt5: timer@306f0000 {
960 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
961 reg = <0x306f0000 0x10000>;
962 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
964 clock-names = "ipg", "per";
967 gpt4: timer@30700000 {
968 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
969 reg = <0x30700000 0x10000>;
970 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
972 clock-names = "ipg", "per";
976 aips3: bus@30800000 {
977 compatible = "fsl,aips-bus", "simple-bus";
978 reg = <0x30800000 0x400000>;
979 #address-cells = <1>;
984 compatible = "fsl,spba-bus", "simple-bus";
985 reg = <0x30800000 0x100000>;
986 #address-cells = <1>;
990 ecspi1: spi@30820000 {
991 #address-cells = <1>;
993 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
994 reg = <0x30820000 0x10000>;
995 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
997 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
998 clock-names = "ipg", "per";
999 assigned-clock-rates = <80000000>;
1000 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1001 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1002 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1003 dma-names = "rx", "tx";
1004 status = "disabled";
1007 ecspi2: spi@30830000 {
1008 #address-cells = <1>;
1010 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1011 reg = <0x30830000 0x10000>;
1012 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1014 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1015 clock-names = "ipg", "per";
1016 assigned-clock-rates = <80000000>;
1017 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1018 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1019 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1020 dma-names = "rx", "tx";
1021 status = "disabled";
1024 ecspi3: spi@30840000 {
1025 #address-cells = <1>;
1027 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1028 reg = <0x30840000 0x10000>;
1029 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1031 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1032 clock-names = "ipg", "per";
1033 assigned-clock-rates = <80000000>;
1034 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1035 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1036 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1037 dma-names = "rx", "tx";
1038 status = "disabled";
1041 uart1: serial@30860000 {
1042 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1043 reg = <0x30860000 0x10000>;
1044 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1045 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1046 <&clk IMX8MP_CLK_UART1_ROOT>;
1047 clock-names = "ipg", "per";
1048 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1049 dma-names = "rx", "tx";
1050 status = "disabled";
1053 uart3: serial@30880000 {
1054 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1055 reg = <0x30880000 0x10000>;
1056 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1058 <&clk IMX8MP_CLK_UART3_ROOT>;
1059 clock-names = "ipg", "per";
1060 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1061 dma-names = "rx", "tx";
1062 status = "disabled";
1065 uart2: serial@30890000 {
1066 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1067 reg = <0x30890000 0x10000>;
1068 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1070 <&clk IMX8MP_CLK_UART2_ROOT>;
1071 clock-names = "ipg", "per";
1072 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1073 dma-names = "rx", "tx";
1074 status = "disabled";
1077 flexcan1: can@308c0000 {
1078 compatible = "fsl,imx8mp-flexcan";
1079 reg = <0x308c0000 0x10000>;
1080 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1082 <&clk IMX8MP_CLK_CAN1_ROOT>;
1083 clock-names = "ipg", "per";
1084 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1085 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1086 assigned-clock-rates = <40000000>;
1087 fsl,clk-source = /bits/ 8 <0>;
1088 fsl,stop-mode = <&gpr 0x10 4>;
1089 status = "disabled";
1092 flexcan2: can@308d0000 {
1093 compatible = "fsl,imx8mp-flexcan";
1094 reg = <0x308d0000 0x10000>;
1095 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1096 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1097 <&clk IMX8MP_CLK_CAN2_ROOT>;
1098 clock-names = "ipg", "per";
1099 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1100 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1101 assigned-clock-rates = <40000000>;
1102 fsl,clk-source = /bits/ 8 <0>;
1103 fsl,stop-mode = <&gpr 0x10 5>;
1104 status = "disabled";
1108 crypto: crypto@30900000 {
1109 compatible = "fsl,sec-v4.0";
1110 #address-cells = <1>;
1112 reg = <0x30900000 0x40000>;
1113 ranges = <0 0x30900000 0x40000>;
1114 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1115 clocks = <&clk IMX8MP_CLK_AHB>,
1116 <&clk IMX8MP_CLK_IPG_ROOT>;
1117 clock-names = "aclk", "ipg";
1120 compatible = "fsl,sec-v4.0-job-ring";
1121 reg = <0x1000 0x1000>;
1122 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1123 status = "disabled";
1127 compatible = "fsl,sec-v4.0-job-ring";
1128 reg = <0x2000 0x1000>;
1129 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1133 compatible = "fsl,sec-v4.0-job-ring";
1134 reg = <0x3000 0x1000>;
1135 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1139 i2c1: i2c@30a20000 {
1140 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1141 #address-cells = <1>;
1143 reg = <0x30a20000 0x10000>;
1144 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1146 status = "disabled";
1149 i2c2: i2c@30a30000 {
1150 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1151 #address-cells = <1>;
1153 reg = <0x30a30000 0x10000>;
1154 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1155 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1156 status = "disabled";
1159 i2c3: i2c@30a40000 {
1160 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1161 #address-cells = <1>;
1163 reg = <0x30a40000 0x10000>;
1164 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1166 status = "disabled";
1169 i2c4: i2c@30a50000 {
1170 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1171 #address-cells = <1>;
1173 reg = <0x30a50000 0x10000>;
1174 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1175 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1176 status = "disabled";
1179 uart4: serial@30a60000 {
1180 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1181 reg = <0x30a60000 0x10000>;
1182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1184 <&clk IMX8MP_CLK_UART4_ROOT>;
1185 clock-names = "ipg", "per";
1186 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1187 dma-names = "rx", "tx";
1188 status = "disabled";
1191 mu: mailbox@30aa0000 {
1192 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1193 reg = <0x30aa0000 0x10000>;
1194 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1195 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1199 mu2: mailbox@30e60000 {
1200 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1201 reg = <0x30e60000 0x10000>;
1202 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1204 status = "disabled";
1207 i2c5: i2c@30ad0000 {
1208 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1209 #address-cells = <1>;
1211 reg = <0x30ad0000 0x10000>;
1212 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1213 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1214 status = "disabled";
1217 i2c6: i2c@30ae0000 {
1218 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1219 #address-cells = <1>;
1221 reg = <0x30ae0000 0x10000>;
1222 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1224 status = "disabled";
1227 usdhc1: mmc@30b40000 {
1228 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1229 reg = <0x30b40000 0x10000>;
1230 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clk IMX8MP_CLK_DUMMY>,
1232 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1233 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1234 clock-names = "ipg", "ahb", "per";
1235 fsl,tuning-start-tap = <20>;
1236 fsl,tuning-step = <2>;
1238 status = "disabled";
1241 usdhc2: mmc@30b50000 {
1242 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1243 reg = <0x30b50000 0x10000>;
1244 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&clk IMX8MP_CLK_DUMMY>,
1246 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1247 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1248 clock-names = "ipg", "ahb", "per";
1249 fsl,tuning-start-tap = <20>;
1250 fsl,tuning-step = <2>;
1252 status = "disabled";
1255 usdhc3: mmc@30b60000 {
1256 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1257 reg = <0x30b60000 0x10000>;
1258 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1259 clocks = <&clk IMX8MP_CLK_DUMMY>,
1260 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1261 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1262 clock-names = "ipg", "ahb", "per";
1263 fsl,tuning-start-tap = <20>;
1264 fsl,tuning-step = <2>;
1266 status = "disabled";
1269 flexspi: spi@30bb0000 {
1270 compatible = "nxp,imx8mp-fspi";
1271 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1272 reg-names = "fspi_base", "fspi_mmap";
1273 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1274 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1275 <&clk IMX8MP_CLK_QSPI_ROOT>;
1276 clock-names = "fspi_en", "fspi";
1277 assigned-clock-rates = <80000000>;
1278 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1279 #address-cells = <1>;
1281 status = "disabled";
1284 sdma1: dma-controller@30bd0000 {
1285 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1286 reg = <0x30bd0000 0x10000>;
1287 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1289 <&clk IMX8MP_CLK_AHB>;
1290 clock-names = "ipg", "ahb";
1292 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1295 fec: ethernet@30be0000 {
1296 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1297 reg = <0x30be0000 0x10000>;
1298 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1303 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1304 <&clk IMX8MP_CLK_ENET_TIMER>,
1305 <&clk IMX8MP_CLK_ENET_REF>,
1306 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1307 clock-names = "ipg", "ahb", "ptp",
1308 "enet_clk_ref", "enet_out";
1309 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1310 <&clk IMX8MP_CLK_ENET_TIMER>,
1311 <&clk IMX8MP_CLK_ENET_REF>,
1312 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1313 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1314 <&clk IMX8MP_SYS_PLL2_100M>,
1315 <&clk IMX8MP_SYS_PLL2_125M>,
1316 <&clk IMX8MP_SYS_PLL2_50M>;
1317 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1318 fsl,num-tx-queues = <3>;
1319 fsl,num-rx-queues = <3>;
1320 nvmem-cells = <ð_mac1>;
1321 nvmem-cell-names = "mac-address";
1322 fsl,stop-mode = <&gpr 0x10 3>;
1323 status = "disabled";
1326 eqos: ethernet@30bf0000 {
1327 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1328 reg = <0x30bf0000 0x10000>;
1329 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1330 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1331 interrupt-names = "macirq", "eth_wake_irq";
1332 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1333 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1334 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1335 <&clk IMX8MP_CLK_ENET_QOS>;
1336 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1337 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1338 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1339 <&clk IMX8MP_CLK_ENET_QOS>;
1340 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1341 <&clk IMX8MP_SYS_PLL2_100M>,
1342 <&clk IMX8MP_SYS_PLL2_125M>;
1343 assigned-clock-rates = <0>, <100000000>, <125000000>;
1344 nvmem-cells = <ð_mac2>;
1345 nvmem-cell-names = "mac-address";
1346 intf_mode = <&gpr 0x4>;
1347 status = "disabled";
1351 aips5: bus@30c00000 {
1352 compatible = "fsl,aips-bus", "simple-bus";
1353 reg = <0x30c00000 0x400000>;
1354 #address-cells = <1>;
1359 compatible = "fsl,spba-bus", "simple-bus";
1360 reg = <0x30c00000 0x100000>;
1361 #address-cells = <1>;
1365 sai1: sai@30c10000 {
1366 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1367 reg = <0x30c10000 0x10000>;
1368 #sound-dai-cells = <0>;
1369 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
1370 <&clk IMX8MP_CLK_DUMMY>,
1371 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
1372 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
1373 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
1374 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1375 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1376 dma-names = "rx", "tx";
1377 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1378 status = "disabled";
1381 sai2: sai@30c20000 {
1382 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1383 reg = <0x30c20000 0x10000>;
1384 #sound-dai-cells = <0>;
1385 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
1386 <&clk IMX8MP_CLK_DUMMY>,
1387 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
1388 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
1389 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
1390 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1391 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1392 dma-names = "rx", "tx";
1393 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1394 status = "disabled";
1397 sai3: sai@30c30000 {
1398 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1399 reg = <0x30c30000 0x10000>;
1400 #sound-dai-cells = <0>;
1401 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
1402 <&clk IMX8MP_CLK_DUMMY>,
1403 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
1404 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
1405 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
1406 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1407 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1408 dma-names = "rx", "tx";
1409 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1410 status = "disabled";
1413 sai5: sai@30c50000 {
1414 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1415 reg = <0x30c50000 0x10000>;
1416 #sound-dai-cells = <0>;
1417 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
1418 <&clk IMX8MP_CLK_DUMMY>,
1419 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
1422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1423 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1424 dma-names = "rx", "tx";
1425 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1426 status = "disabled";
1429 sai6: sai@30c60000 {
1430 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1431 reg = <0x30c60000 0x10000>;
1432 #sound-dai-cells = <0>;
1433 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
1434 <&clk IMX8MP_CLK_DUMMY>,
1435 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
1438 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1439 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1440 dma-names = "rx", "tx";
1441 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1442 status = "disabled";
1445 sai7: sai@30c80000 {
1446 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1447 reg = <0x30c80000 0x10000>;
1448 #sound-dai-cells = <0>;
1449 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
1450 <&clk IMX8MP_CLK_DUMMY>,
1451 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
1454 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1455 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1456 dma-names = "rx", "tx";
1457 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1458 status = "disabled";
1462 sdma3: dma-controller@30e00000 {
1463 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1464 reg = <0x30e00000 0x10000>;
1466 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
1467 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1468 clock-names = "ipg", "ahb";
1469 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1470 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1473 sdma2: dma-controller@30e10000 {
1474 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1475 reg = <0x30e10000 0x10000>;
1477 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
1478 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1479 clock-names = "ipg", "ahb";
1480 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1481 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1484 audio_blk_ctrl: clock-controller@30e20000 {
1485 compatible = "fsl,imx8mp-audio-blk-ctrl";
1486 reg = <0x30e20000 0x10000>;
1488 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
1489 <&clk IMX8MP_CLK_SAI1>,
1490 <&clk IMX8MP_CLK_SAI2>,
1491 <&clk IMX8MP_CLK_SAI3>,
1492 <&clk IMX8MP_CLK_SAI5>,
1493 <&clk IMX8MP_CLK_SAI6>,
1494 <&clk IMX8MP_CLK_SAI7>;
1495 clock-names = "ahb",
1496 "sai1", "sai2", "sai3",
1497 "sai5", "sai6", "sai7";
1498 power-domains = <&pgc_audio>;
1502 noc: interconnect@32700000 {
1503 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1504 reg = <0x32700000 0x100000>;
1505 clocks = <&clk IMX8MP_CLK_NOC>;
1506 #interconnect-cells = <1>;
1507 operating-points-v2 = <&noc_opp_table>;
1509 noc_opp_table: opp-table {
1510 compatible = "operating-points-v2";
1513 opp-hz = /bits/ 64 <200000000>;
1517 opp-hz = /bits/ 64 <1000000000>;
1522 aips4: bus@32c00000 {
1523 compatible = "fsl,aips-bus", "simple-bus";
1524 reg = <0x32c00000 0x400000>;
1525 #address-cells = <1>;
1529 isi_0: isi@32e00000 {
1530 compatible = "fsl,imx8mp-isi";
1531 reg = <0x32e00000 0x4000>;
1532 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1534 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1535 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1536 clock-names = "axi", "apb";
1537 fsl,blk-ctrl = <&media_blk_ctrl>;
1538 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1539 status = "disabled";
1542 #address-cells = <1>;
1548 isi_in_0: endpoint {
1549 remote-endpoint = <&mipi_csi_0_out>;
1556 isi_in_1: endpoint {
1557 remote-endpoint = <&mipi_csi_1_out>;
1563 dewarp: dwe@32e30000 {
1564 compatible = "nxp,imx8mp-dw100";
1565 reg = <0x32e30000 0x10000>;
1566 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1567 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1568 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1569 clock-names = "axi", "ahb";
1570 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1573 mipi_csi_0: csi@32e40000 {
1574 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1575 reg = <0x32e40000 0x10000>;
1576 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1577 clock-frequency = <500000000>;
1578 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1579 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1580 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1581 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1582 clock-names = "pclk", "wrap", "phy", "axi";
1583 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1584 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1585 assigned-clock-rates = <500000000>;
1586 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1587 status = "disabled";
1590 #address-cells = <1>;
1600 mipi_csi_0_out: endpoint {
1601 remote-endpoint = <&isi_in_0>;
1607 mipi_csi_1: csi@32e50000 {
1608 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1609 reg = <0x32e50000 0x10000>;
1610 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1611 clock-frequency = <266000000>;
1612 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1613 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1614 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1615 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1616 clock-names = "pclk", "wrap", "phy", "axi";
1617 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1618 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1619 assigned-clock-rates = <266000000>;
1620 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1621 status = "disabled";
1624 #address-cells = <1>;
1634 mipi_csi_1_out: endpoint {
1635 remote-endpoint = <&isi_in_1>;
1641 mipi_dsi: dsi@32e60000 {
1642 compatible = "fsl,imx8mp-mipi-dsim";
1643 reg = <0x32e60000 0x400>;
1644 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1645 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1646 clock-names = "bus_clk", "sclk_mipi";
1647 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1648 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1649 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1650 <&clk IMX8MP_CLK_24M>;
1651 assigned-clock-rates = <200000000>, <24000000>;
1652 samsung,pll-clock-frequency = <24000000>;
1653 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1654 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1655 status = "disabled";
1658 #address-cells = <1>;
1664 dsim_from_lcdif1: endpoint {
1665 remote-endpoint = <&lcdif1_to_dsim>;
1671 lcdif1: display-controller@32e80000 {
1672 compatible = "fsl,imx8mp-lcdif";
1673 reg = <0x32e80000 0x10000>;
1674 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1675 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1676 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1677 clock-names = "pix", "axi", "disp_axi";
1678 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1679 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1680 status = "disabled";
1683 lcdif1_to_dsim: endpoint {
1684 remote-endpoint = <&dsim_from_lcdif1>;
1689 lcdif2: display-controller@32e90000 {
1690 compatible = "fsl,imx8mp-lcdif";
1691 reg = <0x32e90000 0x10000>;
1692 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1693 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1694 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1695 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1696 clock-names = "pix", "axi", "disp_axi";
1697 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1698 status = "disabled";
1701 lcdif2_to_ldb: endpoint {
1702 remote-endpoint = <&ldb_from_lcdif2>;
1707 media_blk_ctrl: blk-ctrl@32ec0000 {
1708 compatible = "fsl,imx8mp-media-blk-ctrl",
1710 reg = <0x32ec0000 0x10000>;
1711 #address-cells = <1>;
1713 power-domains = <&pgc_mediamix>,
1723 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1724 "lcdif1", "isi", "mipi-csi2",
1725 "lcdif2", "isp", "dwe",
1728 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1729 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1730 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1731 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1732 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1733 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1734 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1735 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1736 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1737 "isi1", "isi2", "isp0", "isp1",
1739 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1740 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1741 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1742 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1743 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1744 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1745 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1746 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1747 clock-names = "apb", "axi", "cam1", "cam2",
1748 "disp1", "disp2", "isp", "phy";
1750 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1751 <&clk IMX8MP_CLK_MEDIA_APB>,
1752 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1753 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1754 <&clk IMX8MP_VIDEO_PLL1>;
1755 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1756 <&clk IMX8MP_SYS_PLL1_800M>,
1757 <&clk IMX8MP_VIDEO_PLL1_OUT>,
1758 <&clk IMX8MP_VIDEO_PLL1_OUT>;
1759 assigned-clock-rates = <500000000>, <200000000>,
1760 <0>, <0>, <1039500000>;
1761 #power-domain-cells = <1>;
1763 lvds_bridge: bridge@5c {
1764 compatible = "fsl,imx8mp-ldb";
1765 reg = <0x5c 0x4>, <0x128 0x4>;
1766 reg-names = "ldb", "lvds";
1767 clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1768 clock-names = "ldb";
1769 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1770 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1771 status = "disabled";
1774 #address-cells = <1>;
1780 ldb_from_lcdif2: endpoint {
1781 remote-endpoint = <&lcdif2_to_ldb>;
1788 ldb_lvds_ch0: endpoint {
1795 ldb_lvds_ch1: endpoint {
1802 pcie_phy: pcie-phy@32f00000 {
1803 compatible = "fsl,imx8mp-pcie-phy";
1804 reg = <0x32f00000 0x10000>;
1805 resets = <&src IMX8MP_RESET_PCIEPHY>,
1806 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1807 reset-names = "pciephy", "perst";
1808 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1810 status = "disabled";
1813 hsio_blk_ctrl: blk-ctrl@32f10000 {
1814 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1815 reg = <0x32f10000 0x24>;
1816 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1817 <&clk IMX8MP_CLK_PCIE_ROOT>;
1818 clock-names = "usb", "pcie";
1819 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1820 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1821 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1822 power-domain-names = "bus", "usb", "usb-phy1",
1823 "usb-phy2", "pcie", "pcie-phy";
1824 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
1825 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
1826 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
1827 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
1828 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1829 #power-domain-cells = <1>;
1834 pcie: pcie@33800000 {
1835 compatible = "fsl,imx8mp-pcie";
1836 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1837 reg-names = "dbi", "config";
1838 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1839 <&clk IMX8MP_CLK_HSIO_AXI>,
1840 <&clk IMX8MP_CLK_PCIE_ROOT>;
1841 clock-names = "pcie", "pcie_bus", "pcie_aux";
1842 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1843 assigned-clock-rates = <10000000>;
1844 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1845 #address-cells = <3>;
1847 device_type = "pci";
1848 bus-range = <0x00 0xff>;
1849 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1850 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1853 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1854 interrupt-names = "msi";
1855 #interrupt-cells = <1>;
1856 interrupt-map-mask = <0 0 0 0x7>;
1857 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1858 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1859 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1860 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1861 fsl,max-link-speed = <3>;
1862 linux,pci-domain = <0>;
1863 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1864 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1865 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1866 reset-names = "apps", "turnoff";
1868 phy-names = "pcie-phy";
1869 status = "disabled";
1872 pcie_ep: pcie-ep@33800000 {
1873 compatible = "fsl,imx8mp-pcie-ep";
1874 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
1875 reg-names = "dbi", "addr_space";
1876 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
1877 <&clk IMX8MP_CLK_HSIO_AXI>,
1878 <&clk IMX8MP_CLK_PCIE_ROOT>;
1879 clock-names = "pcie", "pcie_bus", "pcie_aux";
1880 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1881 assigned-clock-rates = <10000000>;
1882 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1884 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
1885 interrupt-names = "dma";
1886 fsl,max-link-speed = <3>;
1887 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1888 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
1889 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
1890 reset-names = "apps", "turnoff";
1892 phy-names = "pcie-phy";
1893 num-ib-windows = <4>;
1894 num-ob-windows = <4>;
1895 status = "disabled";
1898 gpu3d: gpu@38000000 {
1899 compatible = "vivante,gc";
1900 reg = <0x38000000 0x8000>;
1901 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1902 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
1903 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
1904 <&clk IMX8MP_CLK_GPU_ROOT>,
1905 <&clk IMX8MP_CLK_GPU_AHB>;
1906 clock-names = "core", "shader", "bus", "reg";
1907 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1908 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
1909 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1910 <&clk IMX8MP_SYS_PLL1_800M>;
1911 assigned-clock-rates = <800000000>, <800000000>;
1912 power-domains = <&pgc_gpu3d>;
1915 gpu2d: gpu@38008000 {
1916 compatible = "vivante,gc";
1917 reg = <0x38008000 0x8000>;
1918 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1919 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
1920 <&clk IMX8MP_CLK_GPU_ROOT>,
1921 <&clk IMX8MP_CLK_GPU_AHB>;
1922 clock-names = "core", "bus", "reg";
1923 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1924 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1925 assigned-clock-rates = <800000000>;
1926 power-domains = <&pgc_gpu2d>;
1929 vpu_g1: video-codec@38300000 {
1930 compatible = "nxp,imx8mm-vpu-g1";
1931 reg = <0x38300000 0x10000>;
1932 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1933 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
1934 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
1935 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1936 assigned-clock-rates = <600000000>;
1937 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
1940 vpu_g2: video-codec@38310000 {
1941 compatible = "nxp,imx8mq-vpu-g2";
1942 reg = <0x38310000 0x10000>;
1943 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1944 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
1945 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
1946 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1947 assigned-clock-rates = <500000000>;
1948 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
1951 vpumix_blk_ctrl: blk-ctrl@38330000 {
1952 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1953 reg = <0x38330000 0x100>;
1954 #power-domain-cells = <1>;
1955 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1956 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
1957 power-domain-names = "bus", "g1", "g2", "vc8000e";
1958 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
1959 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
1960 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
1961 clock-names = "g1", "g2", "vc8000e";
1962 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
1963 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1964 assigned-clock-rates = <600000000>, <600000000>;
1965 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
1966 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
1967 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
1968 interconnect-names = "g1", "g2", "vc8000e";
1971 gic: interrupt-controller@38800000 {
1972 compatible = "arm,gic-v3";
1973 reg = <0x38800000 0x10000>,
1974 <0x38880000 0xc0000>;
1975 #interrupt-cells = <3>;
1976 interrupt-controller;
1977 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1978 interrupt-parent = <&gic>;
1981 edacmc: memory-controller@3d400000 {
1982 compatible = "snps,ddrc-3.80a";
1983 reg = <0x3d400000 0x400000>;
1984 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1988 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1989 reg = <0x3d800000 0x400000>;
1990 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1993 usb3_phy0: usb-phy@381f0040 {
1994 compatible = "fsl,imx8mp-usb-phy";
1995 reg = <0x381f0040 0x40>;
1996 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
1997 clock-names = "phy";
1998 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
1999 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2000 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2002 status = "disabled";
2005 usb3_0: usb@32f10100 {
2006 compatible = "fsl,imx8mp-dwc3";
2007 reg = <0x32f10100 0x8>,
2009 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2010 <&clk IMX8MP_CLK_USB_SUSP>;
2011 clock-names = "hsio", "suspend";
2012 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2013 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2014 #address-cells = <1>;
2016 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2018 status = "disabled";
2020 usb_dwc3_0: usb@38100000 {
2021 compatible = "snps,dwc3";
2022 reg = <0x38100000 0x10000>;
2023 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2024 <&clk IMX8MP_CLK_USB_CORE_REF>,
2025 <&clk IMX8MP_CLK_USB_SUSP>;
2026 clock-names = "bus_early", "ref", "suspend";
2027 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2028 phys = <&usb3_phy0>, <&usb3_phy0>;
2029 phy-names = "usb2-phy", "usb3-phy";
2030 snps,gfladj-refclk-lpm-sel-quirk;
2035 usb3_phy1: usb-phy@382f0040 {
2036 compatible = "fsl,imx8mp-usb-phy";
2037 reg = <0x382f0040 0x40>;
2038 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2039 clock-names = "phy";
2040 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2041 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2042 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2044 status = "disabled";
2047 usb3_1: usb@32f10108 {
2048 compatible = "fsl,imx8mp-dwc3";
2049 reg = <0x32f10108 0x8>,
2051 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2052 <&clk IMX8MP_CLK_USB_SUSP>;
2053 clock-names = "hsio", "suspend";
2054 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2055 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2056 #address-cells = <1>;
2058 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2060 status = "disabled";
2062 usb_dwc3_1: usb@38200000 {
2063 compatible = "snps,dwc3";
2064 reg = <0x38200000 0x10000>;
2065 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2066 <&clk IMX8MP_CLK_USB_CORE_REF>,
2067 <&clk IMX8MP_CLK_USB_SUSP>;
2068 clock-names = "bus_early", "ref", "suspend";
2069 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2070 phys = <&usb3_phy1>, <&usb3_phy1>;
2071 phy-names = "usb2-phy", "usb3-phy";
2072 snps,gfladj-refclk-lpm-sel-quirk;
2077 compatible = "fsl,imx8mp-dsp";
2078 reg = <0x3b6e8000 0x88000>;
2079 mbox-names = "txdb0", "txdb1",
2081 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2082 <&mu2 3 0>, <&mu2 3 1>;
2083 memory-region = <&dsp_reserved>;
2084 status = "disabled";