arch/arm64/boot/dts/freescale/imx8mp-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         model = "NXP i.MX8MPlus EVK board";
  12         compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         gpio-leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_gpio_led>;
  22
  23                 status {
  24                         label = "yellow:status";
  25                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  26                         default-state = "on";
  27                 };
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000 0 0xc0000000>,
  33                       <0x1 0x00000000 0 0xc0000000>;
  34         };
  35
  36         reg_can1_stby: regulator-can1-stby {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "can1-stby";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_flexcan1_reg>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         reg_can2_stby: regulator-can2-stby {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "can2-stby";
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57
  58         reg_usdhc2_vmmc: regulator-usdhc2 {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  62                 regulator-name = "VSD_3V3";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67         };
  68 };
  69
  70 &A53_0 {
  71         cpu-supply = <&reg_arm>;
  72 };
  73
  74 &A53_1 {
  75         cpu-supply = <&reg_arm>;
  76 };
  77
  78 &A53_2 {
  79         cpu-supply = <&reg_arm>;
  80 };
  81
  82 &A53_3 {
  83         cpu-supply = <&reg_arm>;
  84 };
  85
  86 &eqos {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_eqos>;
  89         phy-mode = "rgmii-id";
  90         phy-handle = <&ethphy0>;
  91         snps,force_thresh_dma_mode;
  92         snps,mtl-tx-config = <&mtl_tx_setup>;
  93         snps,mtl-rx-config = <&mtl_rx_setup>;
  94         status = "okay";
  95
  96         mdio {
  97                 compatible = "snps,dwmac-mdio";
  98                 #address-cells = <1>;
  99                 #size-cells = <0>;
 100
 101                 ethphy0: ethernet-phy@1 {
 102                         compatible = "ethernet-phy-ieee802.3-c22";
 103                         reg = <1>;
 104                         eee-broken-1000t;
 105                         reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 106                         reset-assert-us = <10000>;
 107                         reset-deassert-us = <80000>;
 108                         realtek,clkout-disable;
 109                 };
 110         };
 111
 112         mtl_tx_setup: tx-queues-config {
 113                 snps,tx-queues-to-use = <5>;
 114                 snps,tx-sched-sp;
 115
 116                 queue0 {
 117                         snps,dcb-algorithm;
 118                         snps,priority = <0x1>;
 119                 };
 120
 121                 queue1 {
 122                         snps,dcb-algorithm;
 123                         snps,priority = <0x2>;
 124                 };
 125
 126                 queue2 {
 127                         snps,dcb-algorithm;
 128                         snps,priority = <0x4>;
 129                 };
 130
 131                 queue3 {
 132                         snps,dcb-algorithm;
 133                         snps,priority = <0x8>;
 134                 };
 135
 136                 queue4 {
 137                         snps,dcb-algorithm;
 138                         snps,priority = <0xf0>;
 139                 };
 140         };
 141
 142         mtl_rx_setup: rx-queues-config {
 143                 snps,rx-queues-to-use = <5>;
 144                 snps,rx-sched-sp;
 145
 146                 queue0 {
 147                         snps,dcb-algorithm;
 148                         snps,priority = <0x1>;
 149                         snps,map-to-dma-channel = <0>;
 150                 };
 151
 152                 queue1 {
 153                         snps,dcb-algorithm;
 154                         snps,priority = <0x2>;
 155                         snps,map-to-dma-channel = <1>;
 156                 };
 157
 158                 queue2 {
 159                         snps,dcb-algorithm;
 160                         snps,priority = <0x4>;
 161                         snps,map-to-dma-channel = <2>;
 162                 };
 163
 164                 queue3 {
 165                         snps,dcb-algorithm;
 166                         snps,priority = <0x8>;
 167                         snps,map-to-dma-channel = <3>;
 168                 };
 169
 170                 queue4 {
 171                         snps,dcb-algorithm;
 172                         snps,priority = <0xf0>;
 173                         snps,map-to-dma-channel = <4>;
 174                 };
 175         };
 176 };
 177
 178 &fec {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_fec>;
 181         phy-mode = "rgmii-id";
 182         phy-handle = <&ethphy1>;
 183         fsl,magic-packet;
 184         status = "okay";
 185
 186         mdio {
 187                 #address-cells = <1>;
 188                 #size-cells = <0>;
 189
 190                 ethphy1: ethernet-phy@1 {
 191                         compatible = "ethernet-phy-ieee802.3-c22";
 192                         reg = <1>;
 193                         eee-broken-1000t;
 194                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 195                         reset-assert-us = <10000>;
 196                         reset-deassert-us = <80000>;
 197                         realtek,clkout-disable;
 198                 };
 199         };
 200 };
 201
 202 &flexcan1 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_flexcan1>;
 205         xceiver-supply = <&reg_can1_stby>;
 206         status = "okay";
 207 };
 208
 209 &flexcan2 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_flexcan2>;
 212         xceiver-supply = <&reg_can2_stby>;
 213         status = "disabled";/* can2 pin conflict with pdm */
 214 };
 215
 216 &i2c1 {
 217         clock-frequency = <400000>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_i2c1>;
 220         status = "okay";
 221
 222         pmic@25 {
 223                 compatible = "nxp,pca9450c";
 224                 reg = <0x25>;
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&pinctrl_pmic>;
 227                 interrupt-parent = <&gpio1>;
 228                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 229
 230                 regulators {
 231                         BUCK1 {
 232                                 regulator-name = "BUCK1";
 233                                 regulator-min-microvolt = <720000>;
 234                                 regulator-max-microvolt = <1000000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                                 regulator-ramp-delay = <3125>;
 238                         };
 239
 240                         reg_arm: BUCK2 {
 241                                 regulator-name = "BUCK2";
 242                                 regulator-min-microvolt = <720000>;
 243                                 regulator-max-microvolt = <1025000>;
 244                                 regulator-boot-on;
 245                                 regulator-always-on;
 246                                 regulator-ramp-delay = <3125>;
 247                                 nxp,dvs-run-voltage = <950000>;
 248                                 nxp,dvs-standby-voltage = <850000>;
 249                         };
 250
 251                         BUCK4 {
 252                                 regulator-name = "BUCK4";
 253                                 regulator-min-microvolt = <3000000>;
 254                                 regulator-max-microvolt = <3600000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                         };
 258
 259                         BUCK5 {
 260                                 regulator-name = "BUCK5";
 261                                 regulator-min-microvolt = <1650000>;
 262                                 regulator-max-microvolt = <1950000>;
 263                                 regulator-boot-on;
 264                                 regulator-always-on;
 265                         };
 266
 267                         BUCK6 {
 268                                 regulator-name = "BUCK6";
 269                                 regulator-min-microvolt = <1045000>;
 270                                 regulator-max-microvolt = <1155000>;
 271                                 regulator-boot-on;
 272                                 regulator-always-on;
 273                         };
 274
 275                         LDO1 {
 276                                 regulator-name = "LDO1";
 277                                 regulator-min-microvolt = <1650000>;
 278                                 regulator-max-microvolt = <1950000>;
 279                                 regulator-boot-on;
 280                                 regulator-always-on;
 281                         };
 282
 283                         LDO3 {
 284                                 regulator-name = "LDO3";
 285                                 regulator-min-microvolt = <1710000>;
 286                                 regulator-max-microvolt = <1890000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         LDO5 {
 292                                 regulator-name = "LDO5";
 293                                 regulator-min-microvolt = <1800000>;
 294                                 regulator-max-microvolt = <3300000>;
 295                                 regulator-boot-on;
 296                                 regulator-always-on;
 297                         };
 298                 };
 299         };
 300 };
 301
 302 &i2c3 {
 303         clock-frequency = <400000>;
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_i2c3>;
 306         status = "okay";
 307
 308         pca6416: gpio@20 {
 309                 compatible = "ti,tca6416";
 310                 reg = <0x20>;
 311                 gpio-controller;
 312                 #gpio-cells = <2>;
 313                 interrupt-controller;
 314                 #interrupt-cells = <2>;
 315                 pinctrl-names = "default";
 316                 pinctrl-0 = <&pinctrl_pca6416_int>;
 317                 interrupt-parent = <&gpio1>;
 318                 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
 319                 gpio-line-names = "EXT_PWREN1",
 320                         "EXT_PWREN2",
 321                         "CAN1/I2C5_SEL",
 322                         "PDM/CAN2_SEL",
 323                         "FAN_EN",
 324                         "PWR_MEAS_IO1",
 325                         "PWR_MEAS_IO2",
 326                         "EXP_P0_7",
 327                         "EXP_P1_0",
 328                         "EXP_P1_1",
 329                         "EXP_P1_2",
 330                         "EXP_P1_3",
 331                         "EXP_P1_4",
 332                         "EXP_P1_5",
 333                         "EXP_P1_6",
 334                         "EXP_P1_7";
 335         };
 336 };
 337
 338 /* I2C on expansion connector J22. */
 339 &i2c5 {
 340         clock-frequency = <100000>; /* Lower clock speed for external bus. */
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pinctrl_i2c5>;
 343         status = "disabled"; /* can1 pins conflict with i2c5 */
 344
 345         /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
 346          *     LOW:  CAN1 (default, pull-down)
 347          *     HIGH: I2C5
 348          * You need to set it to high to enable I2C5 (for example, add gpio-hog
 349          * in pca6416 node).
 350          */
 351 };
 352
 353 &snvs_pwrkey {
 354         status = "okay";
 355 };
 356
 357 &uart2 {
 358         /* console */
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&pinctrl_uart2>;
 361         status = "okay";
 362 };
 363
 364 &usb3_phy1 {
 365         status = "okay";
 366 };
 367
 368 &usb3_1 {
 369         status = "okay";
 370 };
 371
 372 &usb_dwc3_1 {
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_usb1_vbus>;
 375         dr_mode = "host";
 376         status = "okay";
 377 };
 378
 379 &usdhc2 {
 380         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 381         assigned-clock-rates = <400000000>;
 382         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 383         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 384         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 385         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 386         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 387         vmmc-supply = <&reg_usdhc2_vmmc>;
 388         bus-width = <4>;
 389         status = "okay";
 390 };
 391
 392 &usdhc3 {
 393         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 394         assigned-clock-rates = <400000000>;
 395         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 396         pinctrl-0 = <&pinctrl_usdhc3>;
 397         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 398         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 399         bus-width = <8>;
 400         non-removable;
 401         status = "okay";
 402 };
 403
 404 &wdog1 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_wdog>;
 407         fsl,ext-reset-output;
 408         status = "okay";
 409 };
 410
 411 &iomuxc {
 412         pinctrl_eqos: eqosgrp {
 413                 fsl,pins = <
 414                         MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x2
 415                         MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x2
 416                         MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x90
 417                         MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x90
 418                         MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x90
 419                         MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x90
 420                         MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
 421                         MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x90
 422                         MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x16
 423                         MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x16
 424                         MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x16
 425                         MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x16
 426                         MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x16
 427                         MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
 428                         MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22                               0x10
 429                 >;
 430         };
 431
 432         pinctrl_fec: fecgrp {
 433                 fsl,pins = <
 434                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x2
 435                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x2
 436                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x90
 437                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x90
 438                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x90
 439                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x90
 440                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x90
 441                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x90
 442                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x16
 443                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x16
 444                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x16
 445                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x16
 446                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x16
 447                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x16
 448                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x10
 449                 >;
 450         };
 451
 452         pinctrl_flexcan1: flexcan1grp {
 453                 fsl,pins = <
 454                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
 455                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
 456                 >;
 457         };
 458
 459         pinctrl_flexcan2: flexcan2grp {
 460                 fsl,pins = <
 461                         MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 462                         MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 463                 >;
 464         };
 465
 466         pinctrl_flexcan1_reg: flexcan1reggrp {
 467                 fsl,pins = <
 468                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
 469                 >;
 470         };
 471
 472         pinctrl_flexcan2_reg: flexcan2reggrp {
 473                 fsl,pins = <
 474                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
 475                 >;
 476         };
 477
 478         pinctrl_gpio_led: gpioledgrp {
 479                 fsl,pins = <
 480                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16   0x140
 481                 >;
 482         };
 483
 484         pinctrl_i2c1: i2c1grp {
 485                 fsl,pins = <
 486                         MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL         0x400001c2
 487                         MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA         0x400001c2
 488                 >;
 489         };
 490
 491         pinctrl_i2c3: i2c3grp {
 492                 fsl,pins = <
 493                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c2
 494                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c2
 495                 >;
 496         };
 497
 498         pinctrl_i2c5: i2c5grp {
 499                 fsl,pins = <
 500                         MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA         0x400001c2
 501                         MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL         0x400001c2
 502                 >;
 503         };
 504
 505         pinctrl_pmic: pmicgrp {
 506                 fsl,pins = <
 507                         MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03     0x000001c0
 508                 >;
 509         };
 510
 511         pinctrl_pca6416_int: pca6416_int_grp {
 512                 fsl,pins = <
 513                         MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x146 /* Input pull-up. */
 514                 >;
 515         };
 516
 517         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 518                 fsl,pins = <
 519                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x40
 520                 >;
 521         };
 522
 523         pinctrl_uart2: uart2grp {
 524                 fsl,pins = <
 525                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x140
 526                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x140
 527                 >;
 528         };
 529
 530         pinctrl_usb1_vbus: usb1grp {
 531                 fsl,pins = <
 532                         MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR   0x10
 533                 >;
 534         };
 535
 536         pinctrl_usdhc2: usdhc2grp {
 537                 fsl,pins = <
 538                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 539                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 540                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 541                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 542                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 543                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 544                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 545                 >;
 546         };
 547
 548         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 549                 fsl,pins = <
 550                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 551                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 552                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 553                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 554                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 555                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 556                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 557                 >;
 558         };
 559
 560         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 561                 fsl,pins = <
 562                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 563                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 564                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 565                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 566                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 567                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 568                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
 569                 >;
 570         };
 571
 572         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 573                 fsl,pins = <
 574                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 575                 >;
 576         };
 577
 578         pinctrl_usdhc3: usdhc3grp {
 579                 fsl,pins = <
 580                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 581                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 582                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 583                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 584                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 585                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 586                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 587                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 588                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 589                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 590                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 591                 >;
 592         };
 593
 594         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 595                 fsl,pins = <
 596                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 597                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 598                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 599                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 600                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 601                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 602                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 603                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 604                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 605                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 606                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 607                 >;
 608         };
 609
 610         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 611                 fsl,pins = <
 612                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 613                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 614                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 615                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 616                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 617                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 618                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 619                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 620                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 621                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 622                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 623                 >;
 624         };
 625
 626         pinctrl_wdog: wdoggrp {
 627                 fsl,pins = <
 628                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
 629                 >;
 630         };
 631 };