1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2021 Gateworks Corporation
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
13 #include "imx8mn.dtsi"
16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x80000000>;
33 compatible = "fixed-clock";
35 clock-frequency = <20000000>;
36 clock-output-names = "can20m";
40 compatible = "gpio-keys";
44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
51 interrupt-parent = <&gsc>;
58 interrupt-parent = <&gsc>;
65 interrupt-parent = <&gsc>;
72 interrupt-parent = <&gsc>;
77 label = "switch_hold";
79 interrupt-parent = <&gsc>;
85 compatible = "gpio-leds";
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_leds>;
90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_GREEN>;
93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off";
98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_GREEN>;
101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off";
106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_GREEN>;
109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off";
114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_GREEN>;
117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off";
122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_GREEN>;
125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off";
131 compatible = "pps-gpio";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed";
140 regulator-name = "3P3V";
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed";
148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed";
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
164 startup-delay-us = <100>;
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
171 cpu-supply = <&buck2>;
175 cpu-supply = <&buck2>;
179 cpu-supply = <&buck2>;
183 cpu-supply = <&buck2>;
187 operating-points-v2 = <&ddrc_opp_table>;
189 ddrc_opp_table: opp-table {
190 compatible = "operating-points-v2";
193 opp-hz = /bits/ 64 <25000000>;
197 opp-hz = /bits/ 64 <100000000>;
201 opp-hz = /bits/ 64 <750000000>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
213 compatible = "microchip,mcp2515";
216 oscillator-frequency = <20000000>;
217 interrupt-parent = <&gpio2>;
218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
219 spi-max-frequency = <10000000>;
223 /* off-board header */
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_spi2>;
227 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_fec1>;
234 phy-mode = "rgmii-id";
235 phy-handle = <ðphy0>;
236 local-mac-address = [00 00 00 00 00 00];
240 #address-cells = <1>;
243 ethphy0: ethernet-phy@0 {
244 compatible = "ethernet-phy-ieee802.3-c22";
246 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
247 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
249 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
255 clock-frequency = <100000>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c1>;
261 compatible = "gw,gsc";
263 pinctrl-0 = <&pinctrl_gsc>;
264 interrupt-parent = <&gpio2>;
265 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
270 compatible = "gw,gsc-adc";
271 #address-cells = <1>;
290 gw,voltage-divider-ohms = <22100 1000>;
291 gw,voltage-offset-microvolt = <700000>;
298 gw,voltage-divider-ohms = <10000 10000>;
305 gw,voltage-divider-ohms = <10000 10000>;
348 gw,voltage-divider-ohms = <10000 10000>;
355 gw,voltage-divider-ohms = <10000 10000>;
361 compatible = "nxp,pca9555";
365 interrupt-parent = <&gsc>;
370 compatible = "rohm,bd71847";
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_pmic>;
374 interrupt-parent = <&gpio3>;
375 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
376 rohm,reset-snvs-powered;
378 clocks = <&osc_32k 0>;
379 clock-output-names = "clk-32k-out";
382 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
384 regulator-name = "buck1";
385 regulator-min-microvolt = <700000>;
386 regulator-max-microvolt = <1300000>;
389 regulator-ramp-delay = <1250>;
392 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
394 regulator-name = "buck2";
395 regulator-min-microvolt = <700000>;
396 regulator-max-microvolt = <1300000>;
399 regulator-ramp-delay = <1250>;
400 rohm,dvs-run-voltage = <1000000>;
401 rohm,dvs-idle-voltage = <900000>;
404 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
406 regulator-name = "buck3";
407 regulator-min-microvolt = <700000>;
408 regulator-max-microvolt = <1350000>;
415 regulator-name = "buck4";
416 regulator-min-microvolt = <3000000>;
417 regulator-max-microvolt = <3300000>;
424 regulator-name = "buck5";
425 regulator-min-microvolt = <1605000>;
426 regulator-max-microvolt = <1995000>;
433 regulator-name = "buck6";
434 regulator-min-microvolt = <800000>;
435 regulator-max-microvolt = <1400000>;
442 regulator-name = "ldo1";
443 regulator-min-microvolt = <1600000>;
444 regulator-max-microvolt = <1900000>;
451 regulator-name = "ldo2";
452 regulator-min-microvolt = <800000>;
453 regulator-max-microvolt = <900000>;
460 regulator-name = "ldo3";
461 regulator-min-microvolt = <1800000>;
462 regulator-max-microvolt = <3300000>;
468 regulator-name = "ldo4";
469 regulator-min-microvolt = <900000>;
470 regulator-max-microvolt = <1800000>;
476 regulator-name = "ldo6";
477 regulator-min-microvolt = <900000>;
478 regulator-max-microvolt = <1800000>;
486 compatible = "atmel,24c02";
492 compatible = "atmel,24c02";
498 compatible = "atmel,24c02";
504 compatible = "atmel,24c02";
510 compatible = "dallas,ds1672";
516 clock-frequency = <400000>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_i2c2>;
522 compatible = "st,lis2de12";
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_accel>;
526 st,drdy-int-pin = <1>;
527 interrupt-parent = <&gpio1>;
528 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
529 interrupt-names = "INT1";
533 /* off-board header */
535 clock-frequency = <400000>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_i2c3>;
541 /* off-board header */
543 clock-frequency = <400000>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&pinctrl_i2c4>;
549 /* off-board header */
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_sai3>;
553 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
554 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
555 assigned-clock-rates = <24576000>;
559 /* RS232/RS485/RS422 selectable */
561 pinctrl-names = "default";
562 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_uart2>;
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
577 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
578 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
582 compatible = "brcm,bcm4330-bt";
583 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
587 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart4>;
596 vbus-supply = <®_usb1_vbus>;
597 disable-over-current;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_usdhc2>;
607 vmmc-supply = <®_wifi>;
613 pinctrl-names = "default", "state_100mhz", "state_200mhz";
614 pinctrl-0 = <&pinctrl_usdhc3>;
615 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
616 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&pinctrl_wdog>;
625 fsl,ext-reset-output;
630 pinctrl-names = "default";
631 pinctrl-0 = <&pinctrl_hog>;
633 pinctrl_hog: hoggrp {
635 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
636 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
637 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
638 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
639 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
640 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
641 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
642 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
643 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
644 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
645 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
649 pinctrl_accel: accelgrp {
651 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
655 pinctrl_fec1: fec1grp {
657 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
658 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
659 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
660 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
661 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
662 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
663 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
664 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
665 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
666 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
667 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
668 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
669 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
670 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
671 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
672 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
673 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
674 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
678 pinctrl_gsc: gscgrp {
680 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
684 pinctrl_i2c1: i2c1grp {
686 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
687 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
691 pinctrl_i2c2: i2c2grp {
693 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
694 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
698 pinctrl_i2c3: i2c3grp {
700 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
701 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
705 pinctrl_i2c4: i2c4grp {
707 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
708 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
712 pinctrl_gpio_leds: gpioledgrp {
714 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
715 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
716 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
717 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
718 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
722 pinctrl_pmic: pmicgrp {
724 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
728 pinctrl_pps: ppsgrp {
730 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
734 pinctrl_reg_wl: regwlgrp {
736 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
740 pinctrl_reg_usb1: regusb1grp {
742 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
746 pinctrl_sai3: sai3grp {
748 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
749 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
750 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
751 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
752 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
756 pinctrl_spi1: spi1grp {
758 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
759 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
760 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
761 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
762 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
766 pinctrl_spi2: spi2grp {
768 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
769 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
770 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
771 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
775 pinctrl_uart1: uart1grp {
777 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
778 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
782 pinctrl_uart1_gpio: uart1gpiogrp {
784 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
785 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
786 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
790 pinctrl_uart2: uart2grp {
792 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
793 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
797 pinctrl_uart3_gpio: uart3_gpiogrp {
799 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
803 pinctrl_uart3: uart3grp {
805 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
806 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
807 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
808 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
812 pinctrl_uart4: uart4grp {
814 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
815 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
816 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
820 pinctrl_usdhc2: usdhc2grp {
822 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
823 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
824 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
825 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
826 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
827 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
831 pinctrl_usdhc3: usdhc3grp {
833 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
834 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
835 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
836 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
837 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
838 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
839 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
840 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
841 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
842 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
843 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
847 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
849 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
850 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
851 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
852 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
853 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
854 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
855 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
856 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
857 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
858 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
859 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
863 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
865 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
866 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
867 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
868 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
869 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
870 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
871 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
872 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
873 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
874 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
875 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
879 pinctrl_wdog: wdoggrp {
881 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6