arch/arm64/boot/dts/freescale/imx8mm.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mm-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/imx8mm-power.h>
  11 #include <dt-bindings/reset/imx8mq-reset.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 #include "imx8mm-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &fec1;
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 mmc0 = &usdhc1;
  33                 mmc1 = &usdhc2;
  34                 mmc2 = &usdhc3;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42         };
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 idle-states {
  49                         entry-method = "psci";
  50
  51                         cpu_pd_wait: cpu-pd-wait {
  52                                 compatible = "arm,idle-state";
  53                                 arm,psci-suspend-param = <0x0010033>;
  54                                 local-timer-stop;
  55                                 entry-latency-us = <1000>;
  56                                 exit-latency-us = <700>;
  57                                 min-residency-us = <2700>;
  58                         };
  59                 };
  60
  61                 A53_0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x0>;
  65                         clock-latency = <61036>; /* two CLK32 periods */
  66                         clocks = <&clk IMX8MM_CLK_ARM>;
  67                         enable-method = "psci";
  68                         i-cache-size = <0x8000>;
  69                         i-cache-line-size = <64>;
  70                         i-cache-sets = <256>;
  71                         d-cache-size = <0x8000>;
  72                         d-cache-line-size = <64>;
  73                         d-cache-sets = <128>;
  74                         next-level-cache = <&A53_L2>;
  75                         operating-points-v2 = <&a53_opp_table>;
  76                         nvmem-cells = <&cpu_speed_grade>;
  77                         nvmem-cell-names = "speed_grade";
  78                         cpu-idle-states = <&cpu_pd_wait>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 A53_1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x1>;
  86                         clock-latency = <61036>; /* two CLK32 periods */
  87                         clocks = <&clk IMX8MM_CLK_ARM>;
  88                         enable-method = "psci";
  89                         i-cache-size = <0x8000>;
  90                         i-cache-line-size = <64>;
  91                         i-cache-sets = <256>;
  92                         d-cache-size = <0x8000>;
  93                         d-cache-line-size = <64>;
  94                         d-cache-sets = <128>;
  95                         next-level-cache = <&A53_L2>;
  96                         operating-points-v2 = <&a53_opp_table>;
  97                         cpu-idle-states = <&cpu_pd_wait>;
  98                         #cooling-cells = <2>;
  99                 };
 100
 101                 A53_2: cpu@2 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53";
 104                         reg = <0x2>;
 105                         clock-latency = <61036>; /* two CLK32 periods */
 106                         clocks = <&clk IMX8MM_CLK_ARM>;
 107                         enable-method = "psci";
 108                         i-cache-size = <0x8000>;
 109                         i-cache-line-size = <64>;
 110                         i-cache-sets = <256>;
 111                         d-cache-size = <0x8000>;
 112                         d-cache-line-size = <64>;
 113                         d-cache-sets = <128>;
 114                         next-level-cache = <&A53_L2>;
 115                         operating-points-v2 = <&a53_opp_table>;
 116                         cpu-idle-states = <&cpu_pd_wait>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_3: cpu@3 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x3>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MM_CLK_ARM>;
 126                         enable-method = "psci";
 127                         i-cache-size = <0x8000>;
 128                         i-cache-line-size = <64>;
 129                         i-cache-sets = <256>;
 130                         d-cache-size = <0x8000>;
 131                         d-cache-line-size = <64>;
 132                         d-cache-sets = <128>;
 133                         next-level-cache = <&A53_L2>;
 134                         operating-points-v2 = <&a53_opp_table>;
 135                         cpu-idle-states = <&cpu_pd_wait>;
 136                         #cooling-cells = <2>;
 137                 };
 138
 139                 A53_L2: l2-cache0 {
 140                         compatible = "cache";
 141                         cache-level = <2>;
 142                         cache-unified;
 143                         cache-size = <0x80000>;
 144                         cache-line-size = <64>;
 145                         cache-sets = <512>;
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-1200000000 {
 154                         opp-hz = /bits/ 64 <1200000000>;
 155                         opp-microvolt = <850000>;
 156                         opp-supported-hw = <0xe>, <0x7>;
 157                         clock-latency-ns = <150000>;
 158                         opp-suspend;
 159                 };
 160
 161                 opp-1600000000 {
 162                         opp-hz = /bits/ 64 <1600000000>;
 163                         opp-microvolt = <950000>;
 164                         opp-supported-hw = <0xc>, <0x7>;
 165                         clock-latency-ns = <150000>;
 166                         opp-suspend;
 167                 };
 168
 169                 opp-1800000000 {
 170                         opp-hz = /bits/ 64 <1800000000>;
 171                         opp-microvolt = <1000000>;
 172                         opp-supported-hw = <0x8>, <0x3>;
 173                         clock-latency-ns = <150000>;
 174                         opp-suspend;
 175                 };
 176         };
 177
 178         osc_32k: clock-osc-32k {
 179                 compatible = "fixed-clock";
 180                 #clock-cells = <0>;
 181                 clock-frequency = <32768>;
 182                 clock-output-names = "osc_32k";
 183         };
 184
 185         osc_24m: clock-osc-24m {
 186                 compatible = "fixed-clock";
 187                 #clock-cells = <0>;
 188                 clock-frequency = <24000000>;
 189                 clock-output-names = "osc_24m";
 190         };
 191
 192         clk_ext1: clock-ext1 {
 193                 compatible = "fixed-clock";
 194                 #clock-cells = <0>;
 195                 clock-frequency = <133000000>;
 196                 clock-output-names = "clk_ext1";
 197         };
 198
 199         clk_ext2: clock-ext2 {
 200                 compatible = "fixed-clock";
 201                 #clock-cells = <0>;
 202                 clock-frequency = <133000000>;
 203                 clock-output-names = "clk_ext2";
 204         };
 205
 206         clk_ext3: clock-ext3 {
 207                 compatible = "fixed-clock";
 208                 #clock-cells = <0>;
 209                 clock-frequency = <133000000>;
 210                 clock-output-names = "clk_ext3";
 211         };
 212
 213         clk_ext4: clock-ext4 {
 214                 compatible = "fixed-clock";
 215                 #clock-cells = <0>;
 216                 clock-frequency = <133000000>;
 217                 clock-output-names = "clk_ext4";
 218         };
 219
 220         psci {
 221                 compatible = "arm,psci-1.0";
 222                 method = "smc";
 223         };
 224
 225         pmu {
 226                 compatible = "arm,cortex-a53-pmu";
 227                 interrupts = <GIC_PPI 7
 228                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 229         };
 230
 231         timer {
 232                 compatible = "arm,armv8-timer";
 233                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
 234                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
 235                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
 236                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
 237                 clock-frequency = <8000000>;
 238                 arm,no-tick-in-suspend;
 239         };
 240
 241         thermal-zones {
 242                 cpu-thermal {
 243                         polling-delay-passive = <250>;
 244                         polling-delay = <2000>;
 245                         thermal-sensors = <&tmu>;
 246                         trips {
 247                                 cpu_alert0: trip0 {
 248                                         temperature = <85000>;
 249                                         hysteresis = <2000>;
 250                                         type = "passive";
 251                                 };
 252
 253                                 cpu_crit0: trip1 {
 254                                         temperature = <95000>;
 255                                         hysteresis = <2000>;
 256                                         type = "critical";
 257                                 };
 258                         };
 259
 260                         cooling-maps {
 261                                 map0 {
 262                                         trip = <&cpu_alert0>;
 263                                         cooling-device =
 264                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 265                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 266                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 267                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 268                                 };
 269                         };
 270                 };
 271         };
 272
 273         usbphynop1: usbphynop1 {
 274                 #phy-cells = <0>;
 275                 compatible = "usb-nop-xceiv";
 276                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 277                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 278                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 279                 clock-names = "main_clk";
 280                 power-domains = <&pgc_otg1>;
 281         };
 282
 283         usbphynop2: usbphynop2 {
 284                 #phy-cells = <0>;
 285                 compatible = "usb-nop-xceiv";
 286                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 287                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 288                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 289                 clock-names = "main_clk";
 290                 power-domains = <&pgc_otg2>;
 291         };
 292
 293         soc: soc@0 {
 294                 compatible = "fsl,imx8mm-soc", "simple-bus";
 295                 #address-cells = <1>;
 296                 #size-cells = <1>;
 297                 ranges = <0x0 0x0 0x0 0x3e000000>;
 298                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 299                 nvmem-cells = <&imx8mm_uid>;
 300                 nvmem-cell-names = "soc_unique_id";
 301
 302                 aips1: bus@30000000 {
 303                         compatible = "fsl,aips-bus", "simple-bus";
 304                         reg = <0x30000000 0x400000>;
 305                         #address-cells = <1>;
 306                         #size-cells = <1>;
 307                         ranges = <0x30000000 0x30000000 0x400000>;
 308
 309                         spba2: spba-bus@30000000 {
 310                                 compatible = "fsl,spba-bus", "simple-bus";
 311                                 #address-cells = <1>;
 312                                 #size-cells = <1>;
 313                                 reg = <0x30000000 0x100000>;
 314                                 ranges;
 315
 316                                 sai1: sai@30010000 {
 317                                         #sound-dai-cells = <0>;
 318                                         compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 319                                         reg = <0x30010000 0x10000>;
 320                                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 321                                         clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
 322                                                  <&clk IMX8MM_CLK_SAI1_ROOT>,
 323                                                  <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 324                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 325                                         dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
 326                                         dma-names = "rx", "tx";
 327                                         status = "disabled";
 328                                 };
 329
 330                                 sai2: sai@30020000 {
 331                                         #sound-dai-cells = <0>;
 332                                         compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 333                                         reg = <0x30020000 0x10000>;
 334                                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 335                                         clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
 336                                                 <&clk IMX8MM_CLK_SAI2_ROOT>,
 337                                                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 338                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 339                                         dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 340                                         dma-names = "rx", "tx";
 341                                         status = "disabled";
 342                                 };
 343
 344                                 sai3: sai@30030000 {
 345                                         #sound-dai-cells = <0>;
 346                                         compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 347                                         reg = <0x30030000 0x10000>;
 348                                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 349                                         clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
 350                                                  <&clk IMX8MM_CLK_SAI3_ROOT>,
 351                                                  <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 352                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 353                                         dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 354                                         dma-names = "rx", "tx";
 355                                         status = "disabled";
 356                                 };
 357
 358                                 sai5: sai@30050000 {
 359                                         #sound-dai-cells = <0>;
 360                                         compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 361                                         reg = <0x30050000 0x10000>;
 362                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 363                                         clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
 364                                                  <&clk IMX8MM_CLK_SAI5_ROOT>,
 365                                                  <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 366                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 367                                         dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 368                                         dma-names = "rx", "tx";
 369                                         status = "disabled";
 370                                 };
 371
 372                                 sai6: sai@30060000 {
 373                                         #sound-dai-cells = <0>;
 374                                         compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 375                                         reg = <0x30060000 0x10000>;
 376                                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 377                                         clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
 378                                                  <&clk IMX8MM_CLK_SAI6_ROOT>,
 379                                                  <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 380                                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 381                                         dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 382                                         dma-names = "rx", "tx";
 383                                         status = "disabled";
 384                                 };
 385
 386                                 micfil: audio-controller@30080000 {
 387                                         compatible = "fsl,imx8mm-micfil";
 388                                         reg = <0x30080000 0x10000>;
 389                                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 390                                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 391                                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 392                                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 393                                         clocks = <&clk IMX8MM_CLK_PDM_IPG>,
 394                                                  <&clk IMX8MM_CLK_PDM_ROOT>,
 395                                                  <&clk IMX8MM_AUDIO_PLL1_OUT>,
 396                                                  <&clk IMX8MM_AUDIO_PLL2_OUT>,
 397                                                  <&clk IMX8MM_CLK_EXT3>;
 398                                         clock-names = "ipg_clk", "ipg_clk_app",
 399                                                       "pll8k", "pll11k", "clkext3";
 400                                         dmas = <&sdma2 24 25 0x80000000>;
 401                                         dma-names = "rx";
 402                                         status = "disabled";
 403                                 };
 404
 405                                 spdif1: spdif@30090000 {
 406                                         compatible = "fsl,imx35-spdif";
 407                                         reg = <0x30090000 0x10000>;
 408                                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 409                                         clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
 410                                                  <&clk IMX8MM_CLK_24M>, /* rxtx0 */
 411                                                  <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
 412                                                  <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
 413                                                  <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
 414                                                  <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
 415                                                  <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
 416                                                  <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
 417                                                  <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
 418                                                  <&clk IMX8MM_CLK_DUMMY>; /* spba */
 419                                         clock-names = "core", "rxtx0",
 420                                                       "rxtx1", "rxtx2",
 421                                                       "rxtx3", "rxtx4",
 422                                                       "rxtx5", "rxtx6",
 423                                                       "rxtx7", "spba";
 424                                         dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
 425                                         dma-names = "rx", "tx";
 426                                         status = "disabled";
 427                                 };
 428                         };
 429
 430                         gpio1: gpio@30200000 {
 431                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 432                                 reg = <0x30200000 0x10000>;
 433                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 434                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 435                                 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
 436                                 gpio-controller;
 437                                 #gpio-cells = <2>;
 438                                 interrupt-controller;
 439                                 #interrupt-cells = <2>;
 440                                 gpio-ranges = <&iomuxc 0 10 30>;
 441                         };
 442
 443                         gpio2: gpio@30210000 {
 444                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 445                                 reg = <0x30210000 0x10000>;
 446                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 447                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 448                                 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
 449                                 gpio-controller;
 450                                 #gpio-cells = <2>;
 451                                 interrupt-controller;
 452                                 #interrupt-cells = <2>;
 453                                 gpio-ranges = <&iomuxc 0 40 21>;
 454                         };
 455
 456                         gpio3: gpio@30220000 {
 457                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 458                                 reg = <0x30220000 0x10000>;
 459                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 460                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 461                                 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
 462                                 gpio-controller;
 463                                 #gpio-cells = <2>;
 464                                 interrupt-controller;
 465                                 #interrupt-cells = <2>;
 466                                 gpio-ranges = <&iomuxc 0 61 26>;
 467                         };
 468
 469                         gpio4: gpio@30230000 {
 470                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 471                                 reg = <0x30230000 0x10000>;
 472                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 473                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 474                                 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
 475                                 gpio-controller;
 476                                 #gpio-cells = <2>;
 477                                 interrupt-controller;
 478                                 #interrupt-cells = <2>;
 479                                 gpio-ranges = <&iomuxc 0 87 32>;
 480                         };
 481
 482                         gpio5: gpio@30240000 {
 483                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 484                                 reg = <0x30240000 0x10000>;
 485                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 486                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 487                                 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
 488                                 gpio-controller;
 489                                 #gpio-cells = <2>;
 490                                 interrupt-controller;
 491                                 #interrupt-cells = <2>;
 492                                 gpio-ranges = <&iomuxc 0 119 30>;
 493                         };
 494
 495                         tmu: tmu@30260000 {
 496                                 compatible = "fsl,imx8mm-tmu";
 497                                 reg = <0x30260000 0x10000>;
 498                                 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
 499                                 nvmem-cells = <&tmu_calib>;
 500                                 nvmem-cell-names = "calib";
 501                                 #thermal-sensor-cells = <0>;
 502                         };
 503
 504                         wdog1: watchdog@30280000 {
 505                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 506                                 reg = <0x30280000 0x10000>;
 507                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 508                                 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
 509                                 status = "disabled";
 510                         };
 511
 512                         wdog2: watchdog@30290000 {
 513                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 514                                 reg = <0x30290000 0x10000>;
 515                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 516                                 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
 517                                 status = "disabled";
 518                         };
 519
 520                         wdog3: watchdog@302a0000 {
 521                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 522                                 reg = <0x302a0000 0x10000>;
 523                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 524                                 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
 525                                 status = "disabled";
 526                         };
 527
 528                         sdma2: dma-controller@302c0000 {
 529                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 530                                 reg = <0x302c0000 0x10000>;
 531                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 532                                 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
 533                                          <&clk IMX8MM_CLK_SDMA2_ROOT>;
 534                                 clock-names = "ipg", "ahb";
 535                                 #dma-cells = <3>;
 536                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 537                         };
 538
 539                         sdma3: dma-controller@302b0000 {
 540                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 541                                 reg = <0x302b0000 0x10000>;
 542                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 543                                 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
 544                                  <&clk IMX8MM_CLK_SDMA3_ROOT>;
 545                                 clock-names = "ipg", "ahb";
 546                                 #dma-cells = <3>;
 547                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 548                         };
 549
 550                         iomuxc: pinctrl@30330000 {
 551                                 compatible = "fsl,imx8mm-iomuxc";
 552                                 reg = <0x30330000 0x10000>;
 553                         };
 554
 555                         gpr: syscon@30340000 {
 556                                 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
 557                                 reg = <0x30340000 0x10000>;
 558                         };
 559
 560                         ocotp: efuse@30350000 {
 561                                 compatible = "fsl,imx8mm-ocotp", "syscon";
 562                                 reg = <0x30350000 0x10000>;
 563                                 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
 564                                 /* For nvmem subnodes */
 565                                 #address-cells = <1>;
 566                                 #size-cells = <1>;
 567
 568                                 /*
 569                                  * The register address below maps to the MX8M
 570                                  * Fusemap Description Table entries this way.
 571                                  * Assuming
 572                                  *   reg = <ADDR SIZE>;
 573                                  * then
 574                                  *   Fuse Address = (ADDR * 4) + 0x400
 575                                  * Note that if SIZE is greater than 4, then
 576                                  * each subsequent fuse is located at offset
 577                                  * +0x10 in Fusemap Description Table (e.g.
 578                                  * reg = <0x4 0x8> describes fuses 0x410 and
 579                                  * 0x420).
 580                                  */
 581                                 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
 582                                         reg = <0x4 0x8>;
 583                                 };
 584
 585                                 cpu_speed_grade: speed-grade@10 { /* 0x440 */
 586                                         reg = <0x10 4>;
 587                                 };
 588
 589                                 tmu_calib: calib@3c { /* 0x4f0 */
 590                                         reg = <0x3c 4>;
 591                                 };
 592
 593                                 fec_mac_address: mac-address@90 { /* 0x640 */
 594                                         reg = <0x90 6>;
 595                                 };
 596                         };
 597
 598                         anatop: clock-controller@30360000 {
 599                                 compatible = "fsl,imx8mm-anatop";
 600                                 reg = <0x30360000 0x10000>;
 601                                 #clock-cells = <1>;
 602                         };
 603
 604                         snvs: snvs@30370000 {
 605                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 606                                 reg = <0x30370000 0x10000>;
 607
 608                                 snvs_rtc: snvs-rtc-lp {
 609                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 610                                         regmap = <&snvs>;
 611                                         offset = <0x34>;
 612                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 613                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 614                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 615                                         clock-names = "snvs-rtc";
 616                                 };
 617
 618                                 snvs_pwrkey: snvs-powerkey {
 619                                         compatible = "fsl,sec-v4.0-pwrkey";
 620                                         regmap = <&snvs>;
 621                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 622                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 623                                         clock-names = "snvs-pwrkey";
 624                                         linux,keycode = <KEY_POWER>;
 625                                         wakeup-source;
 626                                         status = "disabled";
 627                                 };
 628
 629                                 snvs_lpgpr: snvs-lpgpr {
 630                                         compatible = "fsl,imx8mm-snvs-lpgpr",
 631                                                      "fsl,imx7d-snvs-lpgpr";
 632                                 };
 633                         };
 634
 635                         clk: clock-controller@30380000 {
 636                                 compatible = "fsl,imx8mm-ccm";
 637                                 reg = <0x30380000 0x10000>;
 638                                 #clock-cells = <1>;
 639                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 640                                          <&clk_ext3>, <&clk_ext4>;
 641                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 642                                               "clk_ext3", "clk_ext4";
 643                                 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
 644                                                 <&clk IMX8MM_CLK_A53_CORE>,
 645                                                 <&clk IMX8MM_CLK_NOC>,
 646                                                 <&clk IMX8MM_CLK_AUDIO_AHB>,
 647                                                 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 648                                                 <&clk IMX8MM_SYS_PLL3>,
 649                                                 <&clk IMX8MM_VIDEO_PLL1>,
 650                                                 <&clk IMX8MM_AUDIO_PLL1>;
 651                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
 652                                                          <&clk IMX8MM_ARM_PLL_OUT>,
 653                                                          <&clk IMX8MM_SYS_PLL3_OUT>,
 654                                                          <&clk IMX8MM_SYS_PLL1_800M>;
 655                                 assigned-clock-rates = <0>, <0>, <0>,
 656                                                         <400000000>,
 657                                                         <400000000>,
 658                                                         <750000000>,
 659                                                         <594000000>,
 660                                                         <393216000>;
 661                         };
 662
 663                         src: reset-controller@30390000 {
 664                                 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
 665                                 reg = <0x30390000 0x10000>;
 666                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 667                                 #reset-cells = <1>;
 668                         };
 669
 670                         gpc: gpc@303a0000 {
 671                                 compatible = "fsl,imx8mm-gpc";
 672                                 reg = <0x303a0000 0x10000>;
 673                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 674                                 interrupt-parent = <&gic>;
 675                                 interrupt-controller;
 676                                 #interrupt-cells = <3>;
 677
 678                                 pgc {
 679                                         #address-cells = <1>;
 680                                         #size-cells = <0>;
 681
 682                                         pgc_hsiomix: power-domain@0 {
 683                                                 #power-domain-cells = <0>;
 684                                                 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
 685                                                 clocks = <&clk IMX8MM_CLK_USB_BUS>;
 686                                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
 687                                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 688                                         };
 689
 690                                         pgc_pcie: power-domain@1 {
 691                                                 #power-domain-cells = <0>;
 692                                                 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
 693                                                 power-domains = <&pgc_hsiomix>;
 694                                                 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
 695                                         };
 696
 697                                         pgc_otg1: power-domain@2 {
 698                                                 #power-domain-cells = <0>;
 699                                                 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
 700                                         };
 701
 702                                         pgc_otg2: power-domain@3 {
 703                                                 #power-domain-cells = <0>;
 704                                                 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
 705                                         };
 706
 707                                         pgc_gpumix: power-domain@4 {
 708                                                 #power-domain-cells = <0>;
 709                                                 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
 710                                                 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
 711                                                          <&clk IMX8MM_CLK_GPU_AHB>;
 712                                                 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
 713                                                                   <&clk IMX8MM_CLK_GPU_AHB>;
 714                                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
 715                                                                          <&clk IMX8MM_SYS_PLL1_800M>;
 716                                                 assigned-clock-rates = <800000000>, <400000000>;
 717                                         };
 718
 719                                         pgc_gpu: power-domain@5 {
 720                                                 #power-domain-cells = <0>;
 721                                                 reg = <IMX8MM_POWER_DOMAIN_GPU>;
 722                                                 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
 723                                                          <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
 724                                                          <&clk IMX8MM_CLK_GPU2D_ROOT>,
 725                                                          <&clk IMX8MM_CLK_GPU3D_ROOT>;
 726                                                 resets = <&src IMX8MQ_RESET_GPU_RESET>;
 727                                                 power-domains = <&pgc_gpumix>;
 728                                         };
 729
 730                                         pgc_vpumix: power-domain@6 {
 731                                                 #power-domain-cells = <0>;
 732                                                 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
 733                                                 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
 734                                                 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
 735                                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
 736                                         };
 737
 738                                         pgc_vpu_g1: power-domain@7 {
 739                                                 #power-domain-cells = <0>;
 740                                                 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
 741                                         };
 742
 743                                         pgc_vpu_g2: power-domain@8 {
 744                                                 #power-domain-cells = <0>;
 745                                                 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
 746                                         };
 747
 748                                         pgc_vpu_h1: power-domain@9 {
 749                                                 #power-domain-cells = <0>;
 750                                                 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
 751                                         };
 752
 753                                         pgc_dispmix: power-domain@10 {
 754                                                 #power-domain-cells = <0>;
 755                                                 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
 756                                                 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
 757                                                          <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
 758                                                 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
 759                                                                   <&clk IMX8MM_CLK_DISP_APB>;
 760                                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
 761                                                                          <&clk IMX8MM_SYS_PLL1_800M>;
 762                                                 assigned-clock-rates = <500000000>, <200000000>;
 763                                         };
 764
 765                                         pgc_mipi: power-domain@11 {
 766                                                 #power-domain-cells = <0>;
 767                                                 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
 768                                         };
 769                                 };
 770                         };
 771                 };
 772
 773                 aips2: bus@30400000 {
 774                         compatible = "fsl,aips-bus", "simple-bus";
 775                         reg = <0x30400000 0x400000>;
 776                         #address-cells = <1>;
 777                         #size-cells = <1>;
 778                         ranges = <0x30400000 0x30400000 0x400000>;
 779
 780                         pwm1: pwm@30660000 {
 781                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 782                                 reg = <0x30660000 0x10000>;
 783                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 784                                 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
 785                                         <&clk IMX8MM_CLK_PWM1_ROOT>;
 786                                 clock-names = "ipg", "per";
 787                                 #pwm-cells = <3>;
 788                                 status = "disabled";
 789                         };
 790
 791                         pwm2: pwm@30670000 {
 792                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 793                                 reg = <0x30670000 0x10000>;
 794                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
 796                                          <&clk IMX8MM_CLK_PWM2_ROOT>;
 797                                 clock-names = "ipg", "per";
 798                                 #pwm-cells = <3>;
 799                                 status = "disabled";
 800                         };
 801
 802                         pwm3: pwm@30680000 {
 803                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 804                                 reg = <0x30680000 0x10000>;
 805                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
 807                                          <&clk IMX8MM_CLK_PWM3_ROOT>;
 808                                 clock-names = "ipg", "per";
 809                                 #pwm-cells = <3>;
 810                                 status = "disabled";
 811                         };
 812
 813                         pwm4: pwm@30690000 {
 814                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 815                                 reg = <0x30690000 0x10000>;
 816                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
 818                                          <&clk IMX8MM_CLK_PWM4_ROOT>;
 819                                 clock-names = "ipg", "per";
 820                                 #pwm-cells = <3>;
 821                                 status = "disabled";
 822                         };
 823
 824                         system_counter: timer@306a0000 {
 825                                 compatible = "nxp,sysctr-timer";
 826                                 reg = <0x306a0000 0x20000>;
 827                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&osc_24m>;
 829                                 clock-names = "per";
 830                         };
 831                 };
 832
 833                 aips3: bus@30800000 {
 834                         compatible = "fsl,aips-bus", "simple-bus";
 835                         reg = <0x30800000 0x400000>;
 836                         #address-cells = <1>;
 837                         #size-cells = <1>;
 838                         ranges = <0x30800000 0x30800000 0x400000>,
 839                                  <0x8000000 0x8000000 0x10000000>;
 840
 841                         spba1: spba-bus@30800000 {
 842                                 compatible = "fsl,spba-bus", "simple-bus";
 843                                 #address-cells = <1>;
 844                                 #size-cells = <1>;
 845                                 reg = <0x30800000 0x100000>;
 846                                 ranges;
 847
 848                                 ecspi1: spi@30820000 {
 849                                         compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 850                                         #address-cells = <1>;
 851                                         #size-cells = <0>;
 852                                         reg = <0x30820000 0x10000>;
 853                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 854                                         clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
 855                                                  <&clk IMX8MM_CLK_ECSPI1_ROOT>;
 856                                         clock-names = "ipg", "per";
 857                                         dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 858                                         dma-names = "rx", "tx";
 859                                         status = "disabled";
 860                                 };
 861
 862                                 ecspi2: spi@30830000 {
 863                                         compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 864                                         #address-cells = <1>;
 865                                         #size-cells = <0>;
 866                                         reg = <0x30830000 0x10000>;
 867                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 868                                         clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
 869                                                  <&clk IMX8MM_CLK_ECSPI2_ROOT>;
 870                                         clock-names = "ipg", "per";
 871                                         dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 872                                         dma-names = "rx", "tx";
 873                                         status = "disabled";
 874                                 };
 875
 876                                 ecspi3: spi@30840000 {
 877                                         compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 878                                         #address-cells = <1>;
 879                                         #size-cells = <0>;
 880                                         reg = <0x30840000 0x10000>;
 881                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 882                                         clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
 883                                                  <&clk IMX8MM_CLK_ECSPI3_ROOT>;
 884                                         clock-names = "ipg", "per";
 885                                         dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 886                                         dma-names = "rx", "tx";
 887                                         status = "disabled";
 888                                 };
 889
 890                                 uart1: serial@30860000 {
 891                                         compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 892                                         reg = <0x30860000 0x10000>;
 893                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 894                                         clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
 895                                                  <&clk IMX8MM_CLK_UART1_ROOT>;
 896                                         clock-names = "ipg", "per";
 897                                         dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 898                                         dma-names = "rx", "tx";
 899                                         status = "disabled";
 900                                 };
 901
 902                                 uart3: serial@30880000 {
 903                                         compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 904                                         reg = <0x30880000 0x10000>;
 905                                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 906                                         clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
 907                                                  <&clk IMX8MM_CLK_UART3_ROOT>;
 908                                         clock-names = "ipg", "per";
 909                                         dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 910                                         dma-names = "rx", "tx";
 911                                         status = "disabled";
 912                                 };
 913
 914                                 uart2: serial@30890000 {
 915                                         compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 916                                         reg = <0x30890000 0x10000>;
 917                                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 918                                         clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
 919                                                  <&clk IMX8MM_CLK_UART2_ROOT>;
 920                                         clock-names = "ipg", "per";
 921                                         status = "disabled";
 922                                 };
 923                         };
 924
 925                         crypto: crypto@30900000 {
 926                                 compatible = "fsl,sec-v4.0";
 927                                 #address-cells = <1>;
 928                                 #size-cells = <1>;
 929                                 reg = <0x30900000 0x40000>;
 930                                 ranges = <0 0x30900000 0x40000>;
 931                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 932                                 clocks = <&clk IMX8MM_CLK_AHB>,
 933                                          <&clk IMX8MM_CLK_IPG_ROOT>;
 934                                 clock-names = "aclk", "ipg";
 935
 936                                 sec_jr0: jr@1000 {
 937                                         compatible = "fsl,sec-v4.0-job-ring";
 938                                         reg = <0x1000 0x1000>;
 939                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 940                                         status = "disabled";
 941                                 };
 942
 943                                 sec_jr1: jr@2000 {
 944                                         compatible = "fsl,sec-v4.0-job-ring";
 945                                         reg = <0x2000 0x1000>;
 946                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 947                                 };
 948
 949                                 sec_jr2: jr@3000 {
 950                                         compatible = "fsl,sec-v4.0-job-ring";
 951                                         reg = <0x3000 0x1000>;
 952                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 953                                 };
 954                         };
 955
 956                         i2c1: i2c@30a20000 {
 957                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 958                                 #address-cells = <1>;
 959                                 #size-cells = <0>;
 960                                 reg = <0x30a20000 0x10000>;
 961                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 962                                 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
 963                                 status = "disabled";
 964                         };
 965
 966                         i2c2: i2c@30a30000 {
 967                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 968                                 #address-cells = <1>;
 969                                 #size-cells = <0>;
 970                                 reg = <0x30a30000 0x10000>;
 971                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 972                                 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
 973                                 status = "disabled";
 974                         };
 975
 976                         i2c3: i2c@30a40000 {
 977                                 #address-cells = <1>;
 978                                 #size-cells = <0>;
 979                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 980                                 reg = <0x30a40000 0x10000>;
 981                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 982                                 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
 983                                 status = "disabled";
 984                         };
 985
 986                         i2c4: i2c@30a50000 {
 987                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 988                                 #address-cells = <1>;
 989                                 #size-cells = <0>;
 990                                 reg = <0x30a50000 0x10000>;
 991                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 992                                 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
 993                                 status = "disabled";
 994                         };
 995
 996                         uart4: serial@30a60000 {
 997                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 998                                 reg = <0x30a60000 0x10000>;
 999                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1000                                 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
1001                                          <&clk IMX8MM_CLK_UART4_ROOT>;
1002                                 clock-names = "ipg", "per";
1003                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1004                                 dma-names = "rx", "tx";
1005                                 status = "disabled";
1006                         };
1007
1008                         mu: mailbox@30aa0000 {
1009                                 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1010                                 reg = <0x30aa0000 0x10000>;
1011                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1012                                 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
1013                                 #mbox-cells = <2>;
1014                         };
1015
1016                         usdhc1: mmc@30b40000 {
1017                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1018                                 reg = <0x30b40000 0x10000>;
1019                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1020                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1021                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1022                                          <&clk IMX8MM_CLK_USDHC1_ROOT>;
1023                                 clock-names = "ipg", "ahb", "per";
1024                                 fsl,tuning-start-tap = <20>;
1025                                 fsl,tuning-step = <2>;
1026                                 bus-width = <4>;
1027                                 status = "disabled";
1028                         };
1029
1030                         usdhc2: mmc@30b50000 {
1031                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1032                                 reg = <0x30b50000 0x10000>;
1033                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1034                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1035                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1036                                          <&clk IMX8MM_CLK_USDHC2_ROOT>;
1037                                 clock-names = "ipg", "ahb", "per";
1038                                 fsl,tuning-start-tap = <20>;
1039                                 fsl,tuning-step = <2>;
1040                                 bus-width = <4>;
1041                                 status = "disabled";
1042                         };
1043
1044                         usdhc3: mmc@30b60000 {
1045                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1046                                 reg = <0x30b60000 0x10000>;
1047                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1049                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1050                                          <&clk IMX8MM_CLK_USDHC3_ROOT>;
1051                                 clock-names = "ipg", "ahb", "per";
1052                                 fsl,tuning-start-tap = <20>;
1053                                 fsl,tuning-step = <2>;
1054                                 bus-width = <4>;
1055                                 status = "disabled";
1056                         };
1057
1058                         flexspi: spi@30bb0000 {
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 compatible = "nxp,imx8mm-fspi";
1062                                 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1063                                 reg-names = "fspi_base", "fspi_mmap";
1064                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1065                                 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1066                                          <&clk IMX8MM_CLK_QSPI_ROOT>;
1067                                 clock-names = "fspi_en", "fspi";
1068                                 status = "disabled";
1069                         };
1070
1071                         sdma1: dma-controller@30bd0000 {
1072                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1073                                 reg = <0x30bd0000 0x10000>;
1074                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1075                                 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1076                                          <&clk IMX8MM_CLK_AHB>;
1077                                 clock-names = "ipg", "ahb";
1078                                 #dma-cells = <3>;
1079                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1080                         };
1081
1082                         fec1: ethernet@30be0000 {
1083                                 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1084                                 reg = <0x30be0000 0x10000>;
1085                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1086                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1087                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1088                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1089                                 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1090                                          <&clk IMX8MM_CLK_ENET1_ROOT>,
1091                                          <&clk IMX8MM_CLK_ENET_TIMER>,
1092                                          <&clk IMX8MM_CLK_ENET_REF>,
1093                                          <&clk IMX8MM_CLK_ENET_PHY_REF>;
1094                                 clock-names = "ipg", "ahb", "ptp",
1095                                               "enet_clk_ref", "enet_out";
1096                                 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1097                                                   <&clk IMX8MM_CLK_ENET_TIMER>,
1098                                                   <&clk IMX8MM_CLK_ENET_REF>,
1099                                                   <&clk IMX8MM_CLK_ENET_PHY_REF>;
1100                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1101                                                          <&clk IMX8MM_SYS_PLL2_100M>,
1102                                                          <&clk IMX8MM_SYS_PLL2_125M>,
1103                                                          <&clk IMX8MM_SYS_PLL2_50M>;
1104                                 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1105                                 fsl,num-tx-queues = <3>;
1106                                 fsl,num-rx-queues = <3>;
1107                                 nvmem-cells = <&fec_mac_address>;
1108                                 nvmem-cell-names = "mac-address";
1109                                 fsl,stop-mode = <&gpr 0x10 3>;
1110                                 status = "disabled";
1111                         };
1112
1113                 };
1114
1115                 aips4: bus@32c00000 {
1116                         compatible = "fsl,aips-bus", "simple-bus";
1117                         reg = <0x32c00000 0x400000>;
1118                         #address-cells = <1>;
1119                         #size-cells = <1>;
1120                         ranges = <0x32c00000 0x32c00000 0x400000>;
1121
1122                         lcdif: lcdif@32e00000 {
1123                                 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1124                                 reg = <0x32e00000 0x10000>;
1125                                 clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1126                                          <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1127                                          <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1128                                 clock-names = "pix", "axi", "disp_axi";
1129                                 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1130                                                   <&clk IMX8MM_CLK_DISP_AXI>,
1131                                                   <&clk IMX8MM_CLK_DISP_APB>;
1132                                 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1133                                                          <&clk IMX8MM_SYS_PLL2_1000M>,
1134                                                          <&clk IMX8MM_SYS_PLL1_800M>;
1135                                 assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1136                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1137                                 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1138                                 status = "disabled";
1139
1140                                 port {
1141                                         lcdif_to_dsim: endpoint {
1142                                                 remote-endpoint = <&dsim_from_lcdif>;
1143                                         };
1144                                 };
1145                         };
1146
1147                         mipi_dsi: dsi@32e10000 {
1148                                 compatible = "fsl,imx8mm-mipi-dsim";
1149                                 reg = <0x32e10000 0x400>;
1150                                 clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1151                                          <&clk IMX8MM_CLK_DSI_PHY_REF>;
1152                                 clock-names = "bus_clk", "sclk_mipi";
1153                                 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1154                                                   <&clk IMX8MM_CLK_DSI_PHY_REF>;
1155                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1156                                                          <&clk IMX8MM_CLK_24M>;
1157                                 assigned-clock-rates = <266000000>, <24000000>;
1158                                 samsung,pll-clock-frequency = <24000000>;
1159                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1160                                 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1161                                 status = "disabled";
1162
1163                                 ports {
1164                                         #address-cells = <1>;
1165                                         #size-cells = <0>;
1166
1167                                         port@0 {
1168                                                 reg = <0>;
1169
1170                                                 dsim_from_lcdif: endpoint {
1171                                                         remote-endpoint = <&lcdif_to_dsim>;
1172                                                 };
1173                                         };
1174                                 };
1175                         };
1176
1177                         csi: csi@32e20000 {
1178                                 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1179                                 reg = <0x32e20000 0x1000>;
1180                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1181                                 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1182                                 clock-names = "mclk";
1183                                 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1184                                 status = "disabled";
1185
1186                                 port {
1187                                         csi_in: endpoint {
1188                                                 remote-endpoint = <&imx8mm_mipi_csi_out>;
1189                                         };
1190                                 };
1191                         };
1192
1193                         disp_blk_ctrl: blk-ctrl@32e28000 {
1194                                 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1195                                 reg = <0x32e28000 0x100>;
1196                                 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1197                                                 <&pgc_dispmix>, <&pgc_mipi>,
1198                                                 <&pgc_mipi>;
1199                                 power-domain-names = "bus", "csi-bridge",
1200                                                      "lcdif", "mipi-dsi",
1201                                                      "mipi-csi";
1202                                 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1203                                          <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1204                                          <&clk IMX8MM_CLK_CSI1_ROOT>,
1205                                          <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1206                                          <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1207                                          <&clk IMX8MM_CLK_DISP_ROOT>,
1208                                          <&clk IMX8MM_CLK_DSI_CORE>,
1209                                          <&clk IMX8MM_CLK_DSI_PHY_REF>,
1210                                          <&clk IMX8MM_CLK_CSI1_CORE>,
1211                                          <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1212                                 clock-names = "csi-bridge-axi","csi-bridge-apb",
1213                                               "csi-bridge-core", "lcdif-axi",
1214                                               "lcdif-apb", "lcdif-pix",
1215                                               "dsi-pclk", "dsi-ref",
1216                                               "csi-aclk", "csi-pclk";
1217                                 #power-domain-cells = <1>;
1218                         };
1219
1220                         mipi_csi: mipi-csi@32e30000 {
1221                                 compatible = "fsl,imx8mm-mipi-csi2";
1222                                 reg = <0x32e30000 0x1000>;
1223                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1224                                 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1225                                                   <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1226                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
1227                                                           <&clk IMX8MM_SYS_PLL2_1000M>;
1228                                 clock-frequency = <333000000>;
1229                                 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1230                                          <&clk IMX8MM_CLK_CSI1_ROOT>,
1231                                          <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1232                                          <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1233                                 clock-names = "pclk", "wrap", "phy", "axi";
1234                                 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1235                                 status = "disabled";
1236
1237                                 ports {
1238                                         #address-cells = <1>;
1239                                         #size-cells = <0>;
1240
1241                                         port@0 {
1242                                                 reg = <0>;
1243                                         };
1244
1245                                         port@1 {
1246                                                 reg = <1>;
1247
1248                                                 imx8mm_mipi_csi_out: endpoint {
1249                                                         remote-endpoint = <&csi_in>;
1250                                                 };
1251                                         };
1252                                 };
1253                         };
1254
1255                         usbotg1: usb@32e40000 {
1256                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1257                                 reg = <0x32e40000 0x200>;
1258                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1259                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1260                                 clock-names = "usb1_ctrl_root_clk";
1261                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1262                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1263                                 phys = <&usbphynop1>;
1264                                 fsl,usbmisc = <&usbmisc1 0>;
1265                                 power-domains = <&pgc_hsiomix>;
1266                                 status = "disabled";
1267                         };
1268
1269                         usbmisc1: usbmisc@32e40200 {
1270                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1271                                              "fsl,imx6q-usbmisc";
1272                                 #index-cells = <1>;
1273                                 reg = <0x32e40200 0x200>;
1274                         };
1275
1276                         usbotg2: usb@32e50000 {
1277                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1278                                 reg = <0x32e50000 0x200>;
1279                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1280                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
1281                                 clock-names = "usb1_ctrl_root_clk";
1282                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1283                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1284                                 phys = <&usbphynop2>;
1285                                 fsl,usbmisc = <&usbmisc2 0>;
1286                                 power-domains = <&pgc_hsiomix>;
1287                                 status = "disabled";
1288                         };
1289
1290                         usbmisc2: usbmisc@32e50200 {
1291                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1292                                              "fsl,imx6q-usbmisc";
1293                                 #index-cells = <1>;
1294                                 reg = <0x32e50200 0x200>;
1295                         };
1296
1297                         pcie_phy: pcie-phy@32f00000 {
1298                                 compatible = "fsl,imx8mm-pcie-phy";
1299                                 reg = <0x32f00000 0x10000>;
1300                                 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1301                                 clock-names = "ref";
1302                                 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1303                                 assigned-clock-rates = <100000000>;
1304                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1305                                 resets = <&src IMX8MQ_RESET_PCIEPHY>;
1306                                 reset-names = "pciephy";
1307                                 #phy-cells = <0>;
1308                                 status = "disabled";
1309                         };
1310                 };
1311
1312                 dma_apbh: dma-controller@33000000 {
1313                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1314                         reg = <0x33000000 0x2000>;
1315                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1316                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1317                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1319                         #dma-cells = <1>;
1320                         dma-channels = <4>;
1321                         clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1322                 };
1323
1324                 gpmi: nand-controller@33002000 {
1325                         compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1326                         #address-cells = <1>;
1327                         #size-cells = <0>;
1328                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1329                         reg-names = "gpmi-nand", "bch";
1330                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1331                         interrupt-names = "bch";
1332                         clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1333                                  <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1334                         clock-names = "gpmi_io", "gpmi_bch_apb";
1335                         dmas = <&dma_apbh 0>;
1336                         dma-names = "rx-tx";
1337                         status = "disabled";
1338                 };
1339
1340                 pcie0: pcie@33800000 {
1341                         compatible = "fsl,imx8mm-pcie";
1342                         reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1343                         reg-names = "dbi", "config";
1344                         #address-cells = <3>;
1345                         #size-cells = <2>;
1346                         device_type = "pci";
1347                         bus-range = <0x00 0xff>;
1348                         ranges =  <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1349                                    0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1350                         num-lanes = <1>;
1351                         num-viewport = <4>;
1352                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1353                         interrupt-names = "msi";
1354                         #interrupt-cells = <1>;
1355                         interrupt-map-mask = <0 0 0 0x7>;
1356                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1357                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1358                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1359                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1360                         fsl,max-link-speed = <2>;
1361                         linux,pci-domain = <0>;
1362                         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1363                                  <&clk IMX8MM_CLK_PCIE1_PHY>,
1364                                  <&clk IMX8MM_CLK_PCIE1_AUX>;
1365                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1366                         power-domains = <&pgc_pcie>;
1367                         resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1368                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1369                         reset-names = "apps", "turnoff";
1370                         phys = <&pcie_phy>;
1371                         phy-names = "pcie-phy";
1372                         status = "disabled";
1373                 };
1374
1375                 pcie0_ep: pcie-ep@33800000 {
1376                         compatible = "fsl,imx8mm-pcie-ep";
1377                         reg = <0x33800000 0x400000>,
1378                               <0x18000000 0x8000000>;
1379                         reg-names = "dbi", "addr_space";
1380                         num-lanes = <1>;
1381                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1382                         interrupt-names = "dma";
1383                         fsl,max-link-speed = <2>;
1384                         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1385                                  <&clk IMX8MM_CLK_PCIE1_PHY>,
1386                                  <&clk IMX8MM_CLK_PCIE1_AUX>;
1387                         clock-names = "pcie", "pcie_bus", "pcie_aux";
1388                         power-domains = <&pgc_pcie>;
1389                         resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1390                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1391                         reset-names = "apps", "turnoff";
1392                         phys = <&pcie_phy>;
1393                         phy-names = "pcie-phy";
1394                         num-ib-windows = <4>;
1395                         num-ob-windows = <4>;
1396                         status = "disabled";
1397                 };
1398
1399                 gpu_3d: gpu@38000000 {
1400                         compatible = "vivante,gc";
1401                         reg = <0x38000000 0x8000>;
1402                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1403                         clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1404                                  <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1405                                  <&clk IMX8MM_CLK_GPU3D_ROOT>,
1406                                  <&clk IMX8MM_CLK_GPU3D_ROOT>;
1407                         clock-names = "reg", "bus", "core", "shader";
1408                         assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1409                                           <&clk IMX8MM_GPU_PLL_OUT>;
1410                         assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1411                         assigned-clock-rates = <0>, <1000000000>;
1412                         power-domains = <&pgc_gpu>;
1413                 };
1414
1415                 gpu_2d: gpu@38008000 {
1416                         compatible = "vivante,gc";
1417                         reg = <0x38008000 0x8000>;
1418                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1419                         clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1420                                  <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1421                                  <&clk IMX8MM_CLK_GPU2D_ROOT>;
1422                         clock-names = "reg", "bus", "core";
1423                         assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1424                                           <&clk IMX8MM_GPU_PLL_OUT>;
1425                         assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1426                         assigned-clock-rates = <0>, <1000000000>;
1427                         power-domains = <&pgc_gpu>;
1428                 };
1429
1430                 vpu_g1: video-codec@38300000 {
1431                         compatible = "nxp,imx8mm-vpu-g1";
1432                         reg = <0x38300000 0x10000>;
1433                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1434                         clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1435                         power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1436                 };
1437
1438                 vpu_g2: video-codec@38310000 {
1439                         compatible = "nxp,imx8mq-vpu-g2";
1440                         reg = <0x38310000 0x10000>;
1441                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1442                         clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1443                         power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1444                 };
1445
1446                 vpu_blk_ctrl: blk-ctrl@38330000 {
1447                         compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1448                         reg = <0x38330000 0x100>;
1449                         power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1450                                         <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1451                         power-domain-names = "bus", "g1", "g2", "h1";
1452                         clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1453                                  <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1454                                  <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1455                         clock-names = "g1", "g2", "h1";
1456                         assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1457                                           <&clk IMX8MM_CLK_VPU_G2>;
1458                         assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1459                                                  <&clk IMX8MM_VPU_PLL_OUT>;
1460                         assigned-clock-rates = <600000000>,
1461                                                <600000000>;
1462                         #power-domain-cells = <1>;
1463                 };
1464
1465                 gic: interrupt-controller@38800000 {
1466                         compatible = "arm,gic-v3";
1467                         reg = <0x38800000 0x10000>, /* GIC Dist */
1468                               <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1469                         #interrupt-cells = <3>;
1470                         interrupt-controller;
1471                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1472                 };
1473
1474                 ddrc: memory-controller@3d400000 {
1475                         compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1476                         reg = <0x3d400000 0x400000>;
1477                         clock-names = "core", "pll", "alt", "apb";
1478                         clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1479                                  <&clk IMX8MM_DRAM_PLL>,
1480                                  <&clk IMX8MM_CLK_DRAM_ALT>,
1481                                  <&clk IMX8MM_CLK_DRAM_APB>;
1482                 };
1483
1484                 ddr-pmu@3d800000 {
1485                         compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1486                         reg = <0x3d800000 0x400000>;
1487                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1488                 };
1489         };
1490 };