Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[platform/kernel/linux-starfive.git] / arch / arm64 / boot / dts / freescale / imx8mm-venice-gw71xx.dtsi
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright 2020 Gateworks Corporation
4  */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9
10 / {
11         aliases {
12                 usb0 = &usbotg1;
13                 usb1 = &usbotg2;
14         };
15
16         led-controller {
17                 compatible = "gpio-leds";
18                 pinctrl-names = "default";
19                 pinctrl-0 = <&pinctrl_gpio_leds>;
20
21                 led-0 {
22                         function = LED_FUNCTION_STATUS;
23                         color = <LED_COLOR_ID_GREEN>;
24                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
25                         default-state = "on";
26                         linux,default-trigger = "heartbeat";
27                 };
28
29                 led-1 {
30                         function = LED_FUNCTION_STATUS;
31                         color = <LED_COLOR_ID_RED>;
32                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
33                         default-state = "off";
34                 };
35         };
36
37         pcie0_refclk: pcie0-refclk {
38                 compatible = "fixed-clock";
39                 #clock-cells = <0>;
40                 clock-frequency = <100000000>;
41         };
42
43         pps {
44                 compatible = "pps-gpio";
45                 pinctrl-names = "default";
46                 pinctrl-0 = <&pinctrl_pps>;
47                 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
48                 status = "okay";
49         };
50
51         reg_usb_otg1_vbus: regulator-usb-otg1 {
52                 pinctrl-names = "default";
53                 pinctrl-0 = <&pinctrl_reg_usb1_en>;
54                 compatible = "regulator-fixed";
55                 regulator-name = "usb_otg1_vbus";
56                 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
57                 enable-active-high;
58                 regulator-min-microvolt = <5000000>;
59                 regulator-max-microvolt = <5000000>;
60         };
61 };
62
63 /* off-board header */
64 &ecspi2 {
65         pinctrl-names = "default";
66         pinctrl-0 = <&pinctrl_spi2>;
67         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
68         status = "okay";
69 };
70
71 &gpio1 {
72         gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
73                 "", "dio1", "", "", "", "", "", "",
74                 "", "", "", "", "", "", "", "",
75                 "", "", "", "", "", "", "", "";
76 };
77
78 &gpio4 {
79         gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
80                 "", "", "", "", "", "", "", "",
81                 "", "", "", "", "", "", "", "",
82                 "", "", "", "", "", "", "", "";
83 };
84
85 &i2c2 {
86         clock-frequency = <400000>;
87         pinctrl-names = "default";
88         pinctrl-0 = <&pinctrl_i2c2>;
89         status = "okay";
90
91         accelerometer@19 {
92                 pinctrl-names = "default";
93                 pinctrl-0 = <&pinctrl_accel>;
94                 compatible = "st,lis2de12";
95                 reg = <0x19>;
96                 st,drdy-int-pin = <1>;
97                 interrupt-parent = <&gpio4>;
98                 interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
99                 interrupt-names = "INT1";
100         };
101 };
102
103 /* off-board header */
104 &i2c3 {
105         clock-frequency = <400000>;
106         pinctrl-names = "default";
107         pinctrl-0 = <&pinctrl_i2c3>;
108         status = "okay";
109 };
110
111 &pcie_phy {
112         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
113         fsl,clkreq-unsupported;
114         clocks = <&pcie0_refclk>;
115         clock-names = "ref";
116         status = "okay";
117 };
118
119 &pcie0 {
120         pinctrl-names = "default";
121         pinctrl-0 = <&pinctrl_pcie0>;
122         reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
123         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
124                  <&pcie0_refclk>;
125         clock-names = "pcie", "pcie_aux", "pcie_bus";
126         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
127                           <&clk IMX8MM_CLK_PCIE1_CTRL>;
128         assigned-clock-rates = <10000000>, <250000000>;
129         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
130                                  <&clk IMX8MM_SYS_PLL2_250M>;
131         status = "okay";
132 };
133
134 /* GPS */
135 &uart1 {
136         pinctrl-names = "default";
137         pinctrl-0 = <&pinctrl_uart1>;
138         status = "okay";
139 };
140
141 /* off-board header */
142 &uart3 {
143         pinctrl-names = "default";
144         pinctrl-0 = <&pinctrl_uart3>;
145         status = "okay";
146 };
147
148 &usbotg1 {
149         dr_mode = "otg";
150         over-current-active-low;
151         vbus-supply = <&reg_usb_otg1_vbus>;
152         status = "okay";
153 };
154
155 &usbotg2 {
156         dr_mode = "host";
157         disable-over-current;
158         status = "okay";
159 };
160
161 &iomuxc {
162         pinctrl-names = "default";
163         pinctrl-0 = <&pinctrl_hog>;
164
165         pinctrl_hog: hoggrp {
166                 fsl,pins = <
167                         MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3         0x40000041 /* PLUG_TEST */
168                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6       0x40000041 /* PCI_USBSEL */
169                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7        0x40000041 /* PCIE_WDIS# */
170                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x40000041 /* DIO0 */
171                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9       0x40000041 /* DIO1 */
172                         MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3        0x40000041 /* DIO2 */
173                         MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4        0x40000041 /* DIO2 */
174                 >;
175         };
176
177         pinctrl_accel: accelgrp {
178                 fsl,pins = <
179                         MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5        0x159
180                 >;
181         };
182
183         pinctrl_gpio_leds: gpioledgrp {
184                 fsl,pins = <
185                         MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5    0x19
186                         MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4         0x19
187                 >;
188         };
189
190         pinctrl_i2c3: i2c3grp {
191                 fsl,pins = <
192                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
193                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
194                 >;
195         };
196
197         pinctrl_pcie0: pcie0grp {
198                 fsl,pins = <
199                         MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6        0x41
200                 >;
201         };
202
203         pinctrl_pps: ppsgrp {
204                 fsl,pins = <
205                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x41
206                 >;
207         };
208
209         pinctrl_reg_usb1_en: regusb1grp {
210                 fsl,pins = <
211                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x41
212                         MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12      0x141
213                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x41
214                 >;
215         };
216
217         pinctrl_spi2: spi2grp {
218                 fsl,pins = <
219                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0xd6
220                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0xd6
221                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0xd6
222                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0xd6
223                 >;
224         };
225
226         pinctrl_uart1: uart1grp {
227                 fsl,pins = <
228                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
229                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
230                 >;
231         };
232
233         pinctrl_uart3: uart3grp {
234                 fsl,pins = <
235                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
236                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
237                 >;
238         };
239 };