arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright 2020-2021 TQ-Systems GmbH
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mm-tqma8mqml.dtsi"
   9 #include "mba8mx.dtsi"
  10
  11 / {
  12         model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
  13         compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
  14
  15         aliases {
  16                 eeprom0 = &eeprom3;
  17                 mmc0 = &usdhc3;
  18                 mmc1 = &usdhc2;
  19                 mmc2 = &usdhc1;
  20                 rtc0 = &pcf85063;
  21                 rtc1 = &snvs_rtc;
  22         };
  23
  24         reg_usdhc2_vmmc: regulator-vmmc {
  25                 compatible = "regulator-fixed";
  26                 pinctrl-names = "default";
  27                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  28                 regulator-name = "VSD_3V3";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  32                 enable-active-high;
  33                 startup-delay-us = <100>;
  34                 off-on-delay-us = <12000>;
  35         };
  36
  37         extcon_usbotg1: extcon-usbotg1 {
  38                 compatible = "linux,extcon-usb-gpio";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_usb1_extcon>;
  41                 id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  42         };
  43 };
  44
  45 &i2c1 {
  46         expander2: gpio@27 {
  47                 compatible = "nxp,pca9555";
  48                 reg = <0x27>;
  49                 gpio-controller;
  50                 #gpio-cells = <2>;
  51                 vcc-supply = <&reg_vcc_3v3>;
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_expander>;
  54                 interrupt-parent = <&gpio1>;
  55                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
  56                 interrupt-controller;
  57                 #interrupt-cells = <2>;
  58         };
  59 };
  60
  61 &pcie_phy {
  62         clocks = <&pcie0_refclk>;
  63         status = "okay";
  64 };
  65
  66 &pcie0 {
  67         reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
  68         clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
  69                 <&pcie0_refclk>;
  70         clock-names = "pcie", "pcie_aux", "pcie_bus";
  71         assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
  72                                 <&clk IMX8MM_CLK_PCIE1_CTRL>;
  73         assigned-clock-rates = <10000000>, <250000000>;
  74         assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
  75                                 <&clk IMX8MM_SYS_PLL2_250M>;
  76         status = "okay";
  77 };
  78
  79 &sai3 {
  80         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
  81         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
  82         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
  83         clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
  84                 <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
  85                 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
  86                 <&clk IMX8MM_AUDIO_PLL2_OUT>;
  87 };
  88
  89 &tlv320aic3x04 {
  90         clock-names = "mclk";
  91         clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  92 };
  93
  94 &uart1 {
  95         assigned-clocks = <&clk IMX8MM_CLK_UART1>;
  96         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
  97 };
  98
  99 &uart2 {
 100         assigned-clocks = <&clk IMX8MM_CLK_UART2>;
 101         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 102 };
 103
 104 &usbotg1 {
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_usbotg1>;
 107         dr_mode = "otg";
 108         extcon = <&extcon_usbotg1>;
 109         srp-disable;
 110         hnp-disable;
 111         adp-disable;
 112         power-active-high;
 113         over-current-active-low;
 114         status = "okay";
 115 };
 116
 117 &usbotg2 {
 118         dr_mode = "host";
 119         disable-over-current;
 120         vbus-supply = <&reg_hub_vbus>;
 121         status = "okay";
 122 };
 123
 124 &iomuxc {
 125         pinctrl_ecspi1: ecspi1grp {
 126                 fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x00000006>,
 127                            <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x00000006>,
 128                            <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x00000006>,
 129                            <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9           0x00000006>;
 130         };
 131
 132         pinctrl_ecspi2: ecspi2grp {
 133                 fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK        0x00000006>,
 134                            <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI        0x00000006>,
 135                            <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO        0x00000006>,
 136                            <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13          0x00000006>;
 137         };
 138
 139         pinctrl_expander: expandergrp {
 140                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9           0x94>;
 141         };
 142
 143         pinctrl_fec1: fec1grp {
 144                 fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC             0x40000002>,
 145                            <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO           0x40000002>,
 146                            <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3       0x14>,
 147                            <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2       0x14>,
 148                            <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1       0x14>,
 149                            <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0       0x14>,
 150                            <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3       0x90>,
 151                            <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2       0x90>,
 152                            <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1       0x90>,
 153                            <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0       0x90>,
 154                            <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC       0x14>,
 155                            <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC       0x90>,
 156                            <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>,
 157                            <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>;
 158         };
 159
 160         pinctrl_gpiobutton: gpiobuttongrp {
 161                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5           0x84>,
 162                            <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7           0x84>,
 163                            <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0              0x84>;
 164         };
 165
 166         pinctrl_gpioled: gpioledgrp {
 167                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0           0x84>,
 168                            <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14            0x84>;
 169         };
 170
 171         pinctrl_i2c2: i2c2grp {
 172                 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL              0x40000004>,
 173                            <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA              0x40000004>;
 174         };
 175
 176         pinctrl_i2c2_gpio: i2c2gpiogrp {
 177                 fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16            0x40000004>,
 178                            <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17            0x40000004>;
 179         };
 180
 181         pinctrl_i2c3: i2c3grp {
 182                 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL              0x40000004>,
 183                            <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA              0x40000004>;
 184         };
 185
 186         pinctrl_i2c3_gpio: i2c3gpiogrp {
 187                 fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18            0x40000004>,
 188                            <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19            0x40000004>;
 189         };
 190
 191         pinctrl_pwm3: pwm3grp {
 192                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT            0x14>;
 193         };
 194
 195         pinctrl_pwm4: pwm4grp {
 196                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT            0x14>;
 197         };
 198
 199         pinctrl_sai3: sai3grp {
 200                 fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK            0x94>,
 201                            <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK          0x94>,
 202                            <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC         0x94>,
 203                            <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0         0x94>,
 204                            <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC         0x94>,
 205                            <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0         0x94>,
 206                            <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK          0x94>;
 207         };
 208
 209         pinctrl_uart1: uart1grp {
 210                 fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX         0x16>,
 211                            <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX         0x16>;
 212         };
 213
 214         pinctrl_uart2: uart2grp {
 215                 fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX         0x16>,
 216                            <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX         0x16>;
 217         };
 218
 219         pinctrl_uart3: uart3grp {
 220                 fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX         0x16>,
 221                            <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX         0x16>;
 222         };
 223
 224         pinctrl_uart4: uart4grp {
 225                 fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX         0x16>,
 226                            <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX         0x16>;
 227         };
 228
 229         pinctrl_usbotg1: usbotg1grp {
 230                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR        0x84>,
 231                            <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC         0x84>;
 232         };
 233
 234         pinctrl_usb1_extcon: usb1-extcongrp {
 235                 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10          0x1c0>;
 236         };
 237
 238         pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
 239                 fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12            0x84>;
 240         };
 241
 242         pinctrl_usdhc2: usdhc2grp {
 243                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 244                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 245                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 246                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 247                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 248                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 249                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 250         };
 251
 252         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 253                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 254                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 255                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 256                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 257                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 258                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 259                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 260         };
 261
 262         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 263                 fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
 264                            <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
 265                            <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
 266                            <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
 267                            <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
 268                            <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
 269                            <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
 270         };
 271 };