arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Boundary Devices i.MX8MMini Nitrogen8MM Rev2 board.
   4  * Adrien Grassein <adrien.grassein@gmail.com.com>
   5  */
   6 /dts-v1/;
   7 #include "imx8mm.dtsi"
   8
   9 / {
  10         model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
  11         compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
  12
  13         reg_vref_1v8: regulator-vref-1v8 {
  14                 compatible = "regulator-fixed";
  15                 regulator-name = "vref-1v8";
  16                 regulator-min-microvolt = <1800000>;
  17                 regulator-max-microvolt = <1800000>;
  18         };
  19
  20         reg_vref_3v3: regulator-vref-3v3 {
  21                 compatible = "regulator-fixed";
  22                 regulator-name = "vref-3v3";
  23                 regulator-min-microvolt = <3300000>;
  24                 regulator-max-microvolt = <3300000>;
  25         };
  26
  27         reg_wlan_vmmc: regulator-wlan-vmmc {
  28                 compatible = "regulator-fixed";
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
  31                 regulator-name = "reg_wlan_vmmc";
  32                 regulator-min-microvolt = <3300000>;
  33                 regulator-max-microvolt = <3300000>;
  34                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  35                 enable-active-high;
  36         };
  37
  38         sound-wm8960 {
  39                 audio-cpu = <&sai1>;
  40                 audio-codec = <&wm8960>;
  41                 audio-routing =
  42                         "Headphone Jack", "HP_L",
  43                         "Headphone Jack", "HP_R",
  44                         "Ext Spk", "SPK_LP",
  45                         "Ext Spk", "SPK_LN",
  46                         "Ext Spk", "SPK_RP",
  47                         "Ext Spk", "SPK_RN",
  48                         "RINPUT1", "Mic Jack",
  49                         "Mic Jack", "MICB";
  50                 compatible = "fsl,imx-audio-wm8960";
  51                 /* JD2: hp detect high for headphone*/
  52                 hp-det-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
  53                 /* Jack is not stuffed */
  54                 mic-det-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
  55                 model = "wm8960-audio";
  56                 pinctrl-names = "default";
  57                 pinctrl-0 = <&pinctrl_sound_wm8960>;
  58         };
  59 };
  60
  61 &A53_0 {
  62         cpu-supply = <&reg_buck3>;
  63 };
  64
  65 &A53_1 {
  66         cpu-supply = <&reg_buck3>;
  67 };
  68
  69 &A53_2 {
  70         cpu-supply = <&reg_buck3>;
  71 };
  72
  73 &A53_3 {
  74         cpu-supply = <&reg_buck3>;
  75 };
  76
  77 /* J15 */
  78 &ecspi2 {
  79         assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;
  80         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
  81         assigned-clock-rates = <40000000>;
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_ecspi2>;
  84         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  85         status = "okay";
  86 };
  87
  88 &fec1 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_fec1>;
  91         phy-mode = "rgmii-id";
  92         phy-handle = <&ethphy0>;
  93         fsl,magic-packet;
  94         status = "okay";
  95
  96         mdio {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 ethphy0: ethernet-phy@4 {
 101                         compatible = "ethernet-phy-ieee802.3-c22";
 102                         reg = <4>;
 103                         interrupts-extended = <&gpio3 16 IRQ_TYPE_LEVEL_LOW>;
 104                 };
 105         };
 106 };
 107
 108 &flexspi {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_flexspi>;
 111         status = "okay";
 112 };
 113
 114 &i2c1 {
 115         clock-frequency = <100000>;
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_i2c1>;
 118         status = "okay";
 119
 120         pmic@8 {
 121                 compatible = "nxp,pf8121a";
 122                 reg = <0x8>;
 123
 124                 regulators {
 125                         reg_ldo1: ldo1 {
 126                                 regulator-min-microvolt = <1500000>;
 127                                 regulator-max-microvolt = <5000000>;
 128                                 regulator-boot-on;
 129                                 regulator-always-on;
 130                         };
 131
 132                         reg_ldo2: ldo2 {
 133                                 regulator-min-microvolt = <1500000>;
 134                                 regulator-max-microvolt = <5000000>;
 135                                 regulator-boot-on;
 136                                 regulator-always-on;
 137                         };
 138
 139                         reg_ldo3: ldo3 {
 140                                 regulator-min-microvolt = <1500000>;
 141                                 regulator-max-microvolt = <5000000>;
 142                                 regulator-boot-on;
 143                                 regulator-always-on;
 144                         };
 145
 146                         reg_ldo4: ldo4 {
 147                                 regulator-min-microvolt = <1500000>;
 148                                 regulator-max-microvolt = <5000000>;
 149                                 regulator-boot-on;
 150                                 regulator-always-on;
 151                         };
 152
 153                         reg_buck1: buck1 {
 154                                 regulator-min-microvolt = <400000>;
 155                                 regulator-max-microvolt = <1800000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                         };
 159
 160                         reg_buck2: buck2 {
 161                                 regulator-min-microvolt = <400000>;
 162                                 regulator-max-microvolt = <1800000>;
 163                                 regulator-boot-on;
 164                                 regulator-always-on;
 165                         };
 166
 167                         reg_buck3: buck3 {
 168                                 regulator-min-microvolt = <400000>;
 169                                 regulator-max-microvolt = <1800000>;
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                         };
 173
 174                         reg_buck4: buck4 {
 175                                 regulator-min-microvolt = <400000>;
 176                                 regulator-max-microvolt = <1800000>;
 177                                 regulator-boot-on;
 178                                 regulator-always-on;
 179                         };
 180
 181                         reg_buck5: buck5 {
 182                                 regulator-min-microvolt = <400000>;
 183                                 regulator-max-microvolt = <1800000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                         };
 187
 188                         reg_buck6: buck6 {
 189                                 regulator-min-microvolt = <400000>;
 190                                 regulator-max-microvolt = <1800000>;
 191                                 regulator-boot-on;
 192                                 regulator-always-on;
 193                         };
 194
 195                         reg_buck7: buck7 {
 196                                 regulator-min-microvolt = <3300000>;
 197                                 regulator-max-microvolt = <3300000>;
 198                                 regulator-boot-on;
 199                                 regulator-always-on;
 200                         };
 201
 202                         reg_vsnvs: vsnvs {
 203                                 regulator-min-microvolt = <1800000>;
 204                                 regulator-max-microvolt = <3300000>;
 205                                 regulator-boot-on;
 206                         };
 207                 };
 208         };
 209 };
 210
 211 &i2c3 {
 212         clock-frequency = <100000>;
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_i2c3>;
 215         status = "okay";
 216
 217         i2cmux@70 {
 218                 compatible = "nxp,pca9540";
 219                 reg = <0x70>;
 220                 #address-cells = <1>;
 221                 #size-cells = <0>;
 222
 223                 i2c3@0 {
 224                         reg = <0>;
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227
 228                         rtc@68 {
 229                                 compatible = "microcrystal,rv4162";
 230                                 reg = <0x68>;
 231                                 pinctrl-names = "default";
 232                                 pinctrl-0 = <&pinctrl_i2c3a_rv4162>;
 233                                 interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>;
 234                                 wakeup-source;
 235                         };
 236                 };
 237         };
 238 };
 239
 240 &i2c4 {
 241         clock-frequency = <100000>;
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_i2c4>;
 244         status = "okay";
 245
 246         wm8960: codec@1a {
 247                 compatible = "wlf,wm8960";
 248                 reg = <0x1a>;
 249                 clocks = <&clk IMX8MM_CLK_SAI1_ROOT>;
 250                 clock-names = "mclk1";
 251                 wlf,shared-lrclk;
 252                 #sound-dai-cells = <0>;
 253         };
 254 };
 255
 256 &pwm1 {
 257         pinctrl-names = "default";
 258         pinctrl-0 = <&pinctrl_pwm1>;
 259         status = "okay";
 260 };
 261
 262 &pwm2 {
 263         assigned-clocks = <&clk IMX8MM_CLK_PWM2>;
 264         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;
 265         assigned-clock-rates = <40000000>;
 266         pinctrl-names = "default";
 267         pinctrl-0 = <&pinctrl_pwm2>;
 268         status = "okay";
 269 };
 270
 271 &pwm3 {
 272         pinctrl-names = "default";
 273         pinctrl-0 = <&pinctrl_pwm3>;
 274         status = "okay";
 275 };
 276
 277 &pwm4 {
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_pwm4>;
 280         status = "okay";
 281 };
 282
 283 &sai1 {
 284         pinctrl-names = "default";
 285         pinctrl-0 = <&pinctrl_sai1>;
 286         status = "okay";
 287 };
 288
 289 &sai2 {
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&pinctrl_sai2>;
 292         status = "okay";
 293 };
 294
 295 /* BT */
 296 &uart1 {
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&pinctrl_uart1>;
 299         uart-has-rtscts;
 300         status = "okay";
 301 };
 302
 303 /* console */
 304 &uart2 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&pinctrl_uart2>;
 307         status = "okay";
 308 };
 309
 310 /* J15 */
 311 &uart3 {
 312         pinctrl-names = "default";
 313         pinctrl-0 = <&pinctrl_uart3>;
 314         uart-has-rtscts;
 315         status = "okay";
 316 };
 317
 318 /* J9 */
 319 &uart4 {
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&pinctrl_uart4>;
 322         status = "okay";
 323 };
 324
 325 /* eMMC */
 326 &usdhc1 {
 327         bus-width = <8>;
 328         sdhci-caps-mask = <0x80000000 0x0>;
 329         non-removable;
 330         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 331         pinctrl-0 = <&pinctrl_usdhc1>;
 332         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 333         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 334         vmmc-supply = <&reg_vref_3v3>;
 335         vqmmc-supply = <&reg_vref_1v8>;
 336         status = "okay";
 337 };
 338
 339 /* sdcard */
 340 &usdhc2 {
 341         bus-width = <4>;
 342         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 343         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 344         pinctrl-0 = <&pinctrl_usdhc2>;
 345         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 346         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 347         vqmmc-supply = <&reg_ldo2>;
 348         status = "okay";
 349 };
 350
 351 /* wlan */
 352 &usdhc3 {
 353         bus-width = <4>;
 354         sdhci-caps-mask = <0x2 0x0>;
 355         non-removable;
 356         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 357         pinctrl-0 = <&pinctrl_usdhc3>;
 358         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 359         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 360         vmmc-supply = <&reg_wlan_vmmc>;
 361         vqmmc-supply = <&reg_vref_1v8>;
 362         status = "okay";
 363 };
 364
 365 /* USB OTG port */
 366 &usbotg1 {
 367         dr_mode = "otg";
 368         over-current-active-low;
 369         pinctrl-names = "default";
 370         pinctrl-0 = <&pinctrl_usbotg1>;
 371         power-active-high;
 372         status = "okay";
 373 };
 374
 375 /* USB Host port */
 376 &usbotg2 {
 377         dr_mode = "host";
 378         over-current-active-low;
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_usbotg2>;
 381         power-active-high;
 382         /*
 383          * FIXME: having USB2 enabled hangs the boot just after:
 384          *[    1.655941] ci_hdrc ci_hdrc.1: EHCI Host Controller
 385          *[    1.660880] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 2
 386          *[    1.681505] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
 387          *[    1.687730] hub 2-0:1.0: USB hub found
 388          *[    1.691528] hub 2-0:1.0: 1 port detected
 389          */
 390         status = "disabled";
 391 };
 392
 393 &wdog1 {
 394         pinctrl-names = "default";
 395         pinctrl-0 = <&pinctrl_wdog>;
 396         fsl,ext-reset-output;
 397         status = "okay";
 398 };
 399
 400 &iomuxc {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_hog>;
 403
 404         pinctrl_ecspi2: ecspi2grp {
 405                 fsl,pins = <
 406                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x140
 407                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x19
 408                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x19
 409                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x19
 410                 >;
 411         };
 412
 413         pinctrl_fec1: fec1grp {
 414                 fsl,pins = <
 415                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 416                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 417                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 418                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 419                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 420                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 421                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 422                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 423                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 424                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 425                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 426                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 427                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 428                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 429                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16            0x159
 430                 >;
 431         };
 432
 433         pinctrl_flexspi: flexspigrp {
 434                 fsl,pins = <
 435                         MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x1c2
 436                         MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
 437                         MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
 438                         MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
 439                         MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
 440                         MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
 441                 >;
 442         };
 443
 444         pinctrl_hog: hoggrp {
 445                 fsl,pins = <
 446                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x09
 447                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x09
 448                 >;
 449         };
 450
 451         pinctrl_i2c1: i2c1grp {
 452                 fsl,pins = <
 453                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
 454                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
 455                 >;
 456         };
 457
 458         pinctrl_i2c3: i2c3grp {
 459                 fsl,pins = <
 460                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
 461                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
 462                 >;
 463         };
 464
 465         pinctrl_i2c4: i2c4grp {
 466                 fsl,pins = <
 467                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
 468                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
 469                 >;
 470         };
 471
 472         pinctrl_i2c3a_rv4162: i2c3a-rv4162grp {
 473                 fsl,pins = <
 474                         MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
 475                 >;
 476         };
 477
 478         pinctrl_pwm1: pwm1grp {
 479                 fsl,pins = <
 480                         MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
 481                 >;
 482         };
 483
 484         pinctrl_pwm2: pwm2grp {
 485                 fsl,pins = <
 486                         MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
 487                 >;
 488         };
 489
 490         pinctrl_pwm3: pwm3grp {
 491                 fsl,pins = <
 492                         MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
 493                 >;
 494         };
 495
 496         pinctrl_pwm4: pwm4grp {
 497                 fsl,pins = <
 498                         MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
 499                 >;
 500         };
 501
 502         pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
 503                 fsl,pins = <
 504                         MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
 505                 >;
 506         };
 507
 508         pinctrl_sai1: sai1grp {
 509                 fsl,pins = <
 510                         /* wm8960 */
 511                         MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK        0xd6
 512                         MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC     0xd6
 513                         MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK      0xd6
 514                         MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0    0xd6
 515                         MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0    0xd6
 516                 >;
 517         };
 518
 519         pinctrl_sai2: sai2grp {
 520                 fsl,pins = <
 521                         /* Bluetooth PCM */
 522                         MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC     0xd6
 523                         MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK      0xd6
 524                         MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0    0xd6
 525                         MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0    0xd6
 526                 >;
 527         };
 528
 529         pinctrl_sound_wm8960: sound-wm8960grp {
 530                 fsl,pins = <
 531                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x80
 532                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28       0x80
 533                 >;
 534         };
 535
 536         pinctrl_uart1: uart1grp {
 537                 fsl,pins = <
 538                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
 539                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
 540                         MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
 541                         MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
 542                 >;
 543         };
 544
 545         pinctrl_uart2: uart2grp {
 546                 fsl,pins = <
 547                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
 548                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
 549                 >;
 550         };
 551
 552         pinctrl_uart3: uart3grp {
 553                 fsl,pins = <
 554                         MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
 555                         MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
 556                         MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
 557                         MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
 558                 >;
 559         };
 560
 561         pinctrl_uart4: uart4grp {
 562                 fsl,pins = <
 563                         MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
 564                         MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
 565                 >;
 566         };
 567
 568         pinctrl_usbotg1: usbotg1grp {
 569                 fsl,pins = <
 570                         MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR    0x16
 571                         MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC     0x156
 572                 >;
 573         };
 574
 575         pinctrl_usbotg2: usbotg2grp {
 576                 fsl,pins = <
 577                         MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR    0x16
 578                         MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC     0x15
 579                 >;
 580         };
 581
 582         pinctrl_usdhc1: usdhc1grp {
 583                 fsl,pins = <
 584                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 585                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 586                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 587                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 588                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 589                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 590                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d0
 591                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d0
 592                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d0
 593                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d0
 594                         MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x141
 595                 >;
 596         };
 597
 598         pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
 599                 fsl,pins = <
 600                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 601                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 602                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 603                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 604                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 605                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 606                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d4
 607                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d4
 608                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d4
 609                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d4
 610                 >;
 611         };
 612
 613         pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
 614                 fsl,pins = <
 615                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 616                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 617                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 618                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 619                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 620                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 621                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4     0x1d6
 622                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5     0x1d6
 623                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6     0x1d6
 624                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7     0x1d6
 625                 >;
 626         };
 627
 628         pinctrl_usdhc2: usdhc2grp {
 629                 fsl,pins = <
 630                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 631                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 632                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 633                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 634                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 635                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 636                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12        0x1c4
 637                 >;
 638         };
 639
 640         pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
 641                 fsl,pins = <
 642                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 643                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 644                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 645                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 646                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 647                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 648                 >;
 649         };
 650
 651         pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
 652                 fsl,pins = <
 653                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 654                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 655                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 656                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 657                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 658                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 659                 >;
 660         };
 661
 662         pinctrl_usdhc3: usdhc3grp {
 663                 fsl,pins = <
 664                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 665                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 666                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 667                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 668                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 669                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 670                         MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x03
 671                 >;
 672         };
 673
 674         pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
 675                 fsl,pins = <
 676                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x194
 677                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d4
 678                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d4
 679                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d4
 680                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d4
 681                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d4
 682                 >;
 683         };
 684
 685         pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
 686                 fsl,pins = <
 687                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK       0x196
 688                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD       0x1d6
 689                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0   0x1d6
 690                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1   0x1d6
 691                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2   0x1d6
 692                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3   0x1d6
 693                 >;
 694         };
 695
 696         pinctrl_wdog: wdoggrp {
 697                 fsl,pins = <
 698                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x140
 699                 >;
 700         };
 701 };