arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright (C) 2019 Kontron Electronics GmbH
   4  */
   5
   6 #include "imx8mm.dtsi"
   7
   8 / {
   9         model = "Kontron i.MX8MM N801X SoM";
  10         compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
  11
  12         memory@40000000 {
  13                 device_type = "memory";
  14                 /*
  15                  * There are multiple SoM flavors with different DDR sizes.
  16                  * The smallest is 1GB. For larger sizes the bootloader will
  17                  * update the reg property.
  18                  */
  19                 reg = <0x0 0x40000000 0 0x80000000>;
  20         };
  21
  22         chosen {
  23                 stdout-path = &uart3;
  24         };
  25 };
  26
  27 &A53_0 {
  28         cpu-supply = <&reg_vdd_arm>;
  29 };
  30
  31 &A53_1 {
  32         cpu-supply = <&reg_vdd_arm>;
  33 };
  34
  35 &A53_2 {
  36         cpu-supply = <&reg_vdd_arm>;
  37 };
  38
  39 &A53_3 {
  40         cpu-supply = <&reg_vdd_arm>;
  41 };
  42
  43 &ddrc {
  44         operating-points-v2 = <&ddrc_opp_table>;
  45
  46         ddrc_opp_table: opp-table {
  47                 compatible = "operating-points-v2";
  48
  49                 opp-25M {
  50                         opp-hz = /bits/ 64 <25000000>;
  51                 };
  52
  53                 opp-100M {
  54                         opp-hz = /bits/ 64 <100000000>;
  55                 };
  56
  57                 opp-750M {
  58                         opp-hz = /bits/ 64 <750000000>;
  59                 };
  60         };
  61 };
  62
  63 &ecspi1 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_ecspi1>;
  66         cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  67         status = "okay";
  68
  69         spi-flash@0 {
  70                 compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
  71                 spi-max-frequency = <80000000>;
  72                 reg = <0>;
  73         };
  74 };
  75
  76 &i2c1 {
  77         clock-frequency = <400000>;
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_i2c1>;
  80         status = "okay";
  81
  82         pca9450: pmic@25 {
  83                 compatible = "nxp,pca9450a";
  84                 reg = <0x25>;
  85                 pinctrl-names = "default";
  86                 pinctrl-0 = <&pinctrl_pmic>;
  87                 interrupt-parent = <&gpio1>;
  88                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  89
  90                 regulators {
  91                         reg_vdd_soc: BUCK1 {
  92                                 regulator-name = "buck1";
  93                                 regulator-min-microvolt = <800000>;
  94                                 regulator-max-microvolt = <900000>;
  95                                 regulator-boot-on;
  96                                 regulator-always-on;
  97                                 regulator-ramp-delay = <3125>;
  98                         };
  99
 100                         reg_vdd_arm: BUCK2 {
 101                                 regulator-name = "buck2";
 102                                 regulator-min-microvolt = <850000>;
 103                                 regulator-max-microvolt = <950000>;
 104                                 regulator-boot-on;
 105                                 regulator-always-on;
 106                                 regulator-ramp-delay = <3125>;
 107                                 nxp,dvs-run-voltage = <950000>;
 108                                 nxp,dvs-standby-voltage = <850000>;
 109                         };
 110
 111                         reg_vdd_dram: BUCK3 {
 112                                 regulator-name = "buck3";
 113                                 regulator-min-microvolt = <850000>;
 114                                 regulator-max-microvolt = <900000>;
 115                                 regulator-boot-on;
 116                                 regulator-always-on;
 117                         };
 118
 119                         reg_vdd_3v3: BUCK4 {
 120                                 regulator-name = "buck4";
 121                                 regulator-min-microvolt = <3300000>;
 122                                 regulator-max-microvolt = <3300000>;
 123                                 regulator-boot-on;
 124                                 regulator-always-on;
 125                         };
 126
 127                         reg_vdd_1v8: BUCK5 {
 128                                 regulator-name = "buck5";
 129                                 regulator-min-microvolt = <1800000>;
 130                                 regulator-max-microvolt = <1800000>;
 131                                 regulator-boot-on;
 132                                 regulator-always-on;
 133                         };
 134
 135                         reg_nvcc_dram: BUCK6 {
 136                                 regulator-name = "buck6";
 137                                 regulator-min-microvolt = <1100000>;
 138                                 regulator-max-microvolt = <1100000>;
 139                                 regulator-boot-on;
 140                                 regulator-always-on;
 141                         };
 142
 143                         reg_nvcc_snvs: LDO1 {
 144                                 regulator-name = "ldo1";
 145                                 regulator-min-microvolt = <1800000>;
 146                                 regulator-max-microvolt = <1800000>;
 147                                 regulator-boot-on;
 148                                 regulator-always-on;
 149                         };
 150
 151                         reg_vdd_snvs: LDO2 {
 152                                 regulator-name = "ldo2";
 153                                 regulator-min-microvolt = <850000>;
 154                                 regulator-max-microvolt = <900000>;
 155                                 regulator-boot-on;
 156                                 regulator-always-on;
 157                         };
 158
 159                         reg_vdda: LDO3 {
 160                                 regulator-name = "ldo3";
 161                                 regulator-min-microvolt = <1800000>;
 162                                 regulator-max-microvolt = <1800000>;
 163                                 regulator-boot-on;
 164                                 regulator-always-on;
 165                         };
 166
 167                         reg_vdd_phy: LDO4 {
 168                                 regulator-name = "ldo4";
 169                                 regulator-min-microvolt = <900000>;
 170                                 regulator-max-microvolt = <900000>;
 171                                 regulator-boot-on;
 172                                 regulator-always-on;
 173                         };
 174
 175                         reg_nvcc_sd: LDO5 {
 176                                 regulator-name = "ldo5";
 177                                 regulator-min-microvolt = <1800000>;
 178                                 regulator-max-microvolt = <3300000>;
 179                         };
 180                 };
 181         };
 182 };
 183
 184 &uart3 { /* console */
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart3>;
 187         status = "okay";
 188 };
 189
 190 &usdhc1 {
 191         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 192         pinctrl-0 = <&pinctrl_usdhc1>;
 193         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 194         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 195         vmmc-supply = <&reg_vdd_3v3>;
 196         vqmmc-supply = <&reg_vdd_1v8>;
 197         bus-width = <8>;
 198         non-removable;
 199         status = "okay";
 200 };
 201
 202 &wdog1 {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_wdog>;
 205         fsl,ext-reset-output;
 206         status = "okay";
 207 };
 208
 209 &iomuxc {
 210         pinctrl_ecspi1: ecspi1grp {
 211                 fsl,pins = <
 212                         MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO            0x82
 213                         MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI            0x82
 214                         MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK            0x82
 215                         MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9               0x19
 216                 >;
 217         };
 218
 219         pinctrl_i2c1: i2c1grp {
 220                 fsl,pins = <
 221                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                  0x400001c3
 222                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                  0x400001c3
 223                 >;
 224         };
 225
 226         pinctrl_pmic: pmicgrp {
 227                 fsl,pins = <
 228                         MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0               0x141
 229                 >;
 230         };
 231
 232         pinctrl_uart3: uart3grp {
 233                 fsl,pins = <
 234                         MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX             0x140
 235                         MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX             0x140
 236                 >;
 237         };
 238
 239         pinctrl_usdhc1: usdhc1grp {
 240                 fsl,pins = <
 241                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x190
 242                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d0
 243                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d0
 244                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d0
 245                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d0
 246                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d0
 247                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x1d0
 248                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x1d0
 249                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x1d0
 250                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x1d0
 251                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0x019
 252                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x190
 253                 >;
 254         };
 255
 256         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
 257                 fsl,pins = <
 258                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x194
 259                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d4
 260                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d4
 261                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d4
 262                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d4
 263                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d4
 264                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x1d4
 265                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x1d4
 266                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x1d4
 267                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x1d4
 268                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0x019
 269                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x194
 270                 >;
 271         };
 272
 273         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
 274                 fsl,pins = <
 275                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                 0x196
 276                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                 0x1d6
 277                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0             0x1d6
 278                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1             0x1d6
 279                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2             0x1d6
 280                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3             0x1d6
 281                         MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4             0x1d6
 282                         MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5             0x1d6
 283                         MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6             0x1d6
 284                         MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7             0x1d6
 285                         MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B         0x019
 286                         MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE           0x196
 287                 >;
 288         };
 289
 290         pinctrl_wdog: wdoggrp {
 291                 fsl,pins = <
 292                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 293                 >;
 294         };
 295 };