1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 dma_subsys: bus@5a000000 {
11 compatible = "simple-bus";
14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
16 dma_ipg_clk: clock-dma-ipg {
17 compatible = "fixed-clock";
19 clock-frequency = <120000000>;
20 clock-output-names = "dma_ipg_clk";
23 lpuart0: serial@5a060000 {
24 reg = <0x5a060000 0x1000>;
25 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
26 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>,
27 <&uart0_lpcg IMX_LPCG_CLK_0>;
28 clock-names = "ipg", "baud";
29 power-domains = <&pd IMX_SC_R_UART_0>;
33 lpuart1: serial@5a070000 {
34 reg = <0x5a070000 0x1000>;
35 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
36 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>,
37 <&uart1_lpcg IMX_LPCG_CLK_0>;
38 clock-names = "ipg", "baud";
39 power-domains = <&pd IMX_SC_R_UART_1>;
43 lpuart2: serial@5a080000 {
44 reg = <0x5a080000 0x1000>;
45 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
46 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>,
47 <&uart2_lpcg IMX_LPCG_CLK_0>;
48 clock-names = "ipg", "baud";
49 power-domains = <&pd IMX_SC_R_UART_2>;
53 lpuart3: serial@5a090000 {
54 reg = <0x5a090000 0x1000>;
55 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>,
57 <&uart3_lpcg IMX_LPCG_CLK_0>;
58 clock-names = "ipg", "baud";
59 power-domains = <&pd IMX_SC_R_UART_3>;
63 uart0_lpcg: clock-controller@5a460000 {
64 compatible = "fsl,imx8qxp-lpcg";
65 reg = <0x5a460000 0x10000>;
67 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>,
69 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
70 clock-output-names = "uart0_lpcg_baud_clk",
72 power-domains = <&pd IMX_SC_R_UART_0>;
75 uart1_lpcg: clock-controller@5a470000 {
76 compatible = "fsl,imx8qxp-lpcg";
77 reg = <0x5a470000 0x10000>;
79 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>,
81 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
82 clock-output-names = "uart1_lpcg_baud_clk",
84 power-domains = <&pd IMX_SC_R_UART_1>;
87 uart2_lpcg: clock-controller@5a480000 {
88 compatible = "fsl,imx8qxp-lpcg";
89 reg = <0x5a480000 0x10000>;
91 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>,
93 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
94 clock-output-names = "uart2_lpcg_baud_clk",
96 power-domains = <&pd IMX_SC_R_UART_2>;
99 uart3_lpcg: clock-controller@5a490000 {
100 compatible = "fsl,imx8qxp-lpcg";
101 reg = <0x5a490000 0x10000>;
103 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>,
105 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
106 clock-output-names = "uart3_lpcg_baud_clk",
107 "uart3_lpcg_ipg_clk";
108 power-domains = <&pd IMX_SC_R_UART_3>;
112 reg = <0x5a800000 0x4000>;
113 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>,
115 <&i2c0_lpcg IMX_LPCG_CLK_4>;
116 clock-names = "per", "ipg";
117 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>;
118 assigned-clock-rates = <24000000>;
119 power-domains = <&pd IMX_SC_R_I2C_0>;
124 reg = <0x5a810000 0x4000>;
125 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>,
127 <&i2c1_lpcg IMX_LPCG_CLK_4>;
128 clock-names = "per", "ipg";
129 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>;
130 assigned-clock-rates = <24000000>;
131 power-domains = <&pd IMX_SC_R_I2C_1>;
136 reg = <0x5a820000 0x4000>;
137 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>,
139 <&i2c2_lpcg IMX_LPCG_CLK_4>;
140 clock-names = "per", "ipg";
141 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>;
142 assigned-clock-rates = <24000000>;
143 power-domains = <&pd IMX_SC_R_I2C_2>;
148 reg = <0x5a830000 0x4000>;
149 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>,
151 <&i2c3_lpcg IMX_LPCG_CLK_4>;
152 clock-names = "per", "ipg";
153 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>;
154 assigned-clock-rates = <24000000>;
155 power-domains = <&pd IMX_SC_R_I2C_3>;
160 compatible = "nxp,imx8qxp-adc";
161 reg = <0x5a880000 0x10000>;
162 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-parent = <&gic>;
164 clocks = <&adc0_lpcg 0>,
166 clock-names = "per", "ipg";
167 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>;
168 assigned-clock-rates = <24000000>;
169 power-domains = <&pd IMX_SC_R_ADC_0>;
174 compatible = "nxp,imx8qxp-adc";
175 reg = <0x5a890000 0x10000>;
176 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-parent = <&gic>;
178 clocks = <&adc1_lpcg 0>,
180 clock-names = "per", "ipg";
181 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>;
182 assigned-clock-rates = <24000000>;
183 power-domains = <&pd IMX_SC_R_ADC_1>;
187 i2c0_lpcg: clock-controller@5ac00000 {
188 compatible = "fsl,imx8qxp-lpcg";
189 reg = <0x5ac00000 0x10000>;
191 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>,
193 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
194 clock-output-names = "i2c0_lpcg_clk",
196 power-domains = <&pd IMX_SC_R_I2C_0>;
199 i2c1_lpcg: clock-controller@5ac10000 {
200 compatible = "fsl,imx8qxp-lpcg";
201 reg = <0x5ac10000 0x10000>;
203 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>,
205 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
206 clock-output-names = "i2c1_lpcg_clk",
208 power-domains = <&pd IMX_SC_R_I2C_1>;
211 i2c2_lpcg: clock-controller@5ac20000 {
212 compatible = "fsl,imx8qxp-lpcg";
213 reg = <0x5ac20000 0x10000>;
215 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>,
217 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
218 clock-output-names = "i2c2_lpcg_clk",
220 power-domains = <&pd IMX_SC_R_I2C_2>;
223 i2c3_lpcg: clock-controller@5ac30000 {
224 compatible = "fsl,imx8qxp-lpcg";
225 reg = <0x5ac30000 0x10000>;
227 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>,
229 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
230 clock-output-names = "i2c3_lpcg_clk",
232 power-domains = <&pd IMX_SC_R_I2C_3>;
235 adc0_lpcg: clock-controller@5ac80000 {
236 compatible = "fsl,imx8qxp-lpcg";
237 reg = <0x5ac80000 0x10000>;
239 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>,
241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
242 clock-output-names = "adc0_lpcg_clk",
244 power-domains = <&pd IMX_SC_R_ADC_0>;
247 adc1_lpcg: clock-controller@5ac90000 {
248 compatible = "fsl,imx8qxp-lpcg";
249 reg = <0x5ac90000 0x10000>;
251 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>,
253 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
254 clock-output-names = "adc1_lpcg_clk",
256 power-domains = <&pd IMX_SC_R_ADC_1>;