arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include <dt-bindings/pwm/pwm.h>
   7
   8 / {
   9         chosen {
  10                 stdout-path = &lpuart1;
  11         };
  12
  13         /* Apalis BKL1 */
  14         backlight: backlight {
  15                 compatible = "pwm-backlight";
  16                 pinctrl-names = "default";
  17                 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
  18                 brightness-levels = <0 45 63 88 119 158 203 255>;
  19                 default-brightness-level = <4>;
  20                 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
  21                 /* TODO: hook-up to Apalis BKL1_PWM */
  22                 status = "disabled";
  23         };
  24
  25         gpio_fan: gpio-fan {
  26                 compatible = "gpio-fan";
  27                 pinctrl-names = "default";
  28                 pinctrl-0 = <&pinctrl_gpio8>;
  29                 gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
  30                 gpio-fan,speed-map = <   0 0
  31                                       3000 1>;
  32         };
  33
  34         /* TODO: LVDS Panel */
  35
  36         /* TODO: Shared PCIe/SATA Reference Clock */
  37
  38         /* TODO: PCIe Wi-Fi Reference Clock */
  39
  40         /*
  41          * Power management bus used to control LDO1OUT of the
  42          * second PMIC PF8100. This is used for controlling voltage levels of
  43          * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
  44          *
  45          * IMX_SC_R_BOARD_R1 for 3.3V
  46          * IMX_SC_R_BOARD_R2 for 1.8V
  47          * IMX_SC_R_BOARD_R3 for 2.5V
  48          * Note that for 2.5V operation the pad muxing needs to be changed,
  49          * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
  50          *
  51          * those power domains are mutually exclusive.
  52          */
  53         reg_ext_rgmii: regulator-ext-rgmii {
  54                 compatible = "regulator-fixed";
  55                 power-domains = <&pd IMX_SC_R_BOARD_R1>;
  56                 regulator-max-microvolt = <3300000>;
  57                 regulator-min-microvolt = <3300000>;
  58                 regulator-name = "VDD_EXT_RGMII (LDO1)";
  59
  60                 regulator-state-mem {
  61                         regulator-off-in-suspend;
  62                 };
  63         };
  64
  65         reg_module_3v3: regulator-module-3v3 {
  66                 compatible = "regulator-fixed";
  67                 regulator-max-microvolt = <3300000>;
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-name = "+V3.3";
  70         };
  71
  72         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  73                 compatible = "regulator-fixed";
  74                 regulator-max-microvolt = <3300000>;
  75                 regulator-min-microvolt = <3300000>;
  76                 regulator-name = "+V3.3_AUDIO";
  77         };
  78
  79         reg_module_wifi: regulator-module-wifi {
  80                 compatible = "regulator-fixed";
  81                 pinctrl-names = "default";
  82                 pinctrl-0 = <&pinctrl_wifi_pdn>;
  83                 gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
  84                 enable-active-high;
  85                 regulator-name = "wifi_pwrdn_fake_regulator";
  86                 regulator-settling-time-us = <100>;
  87
  88                 regulator-state-mem {
  89                         regulator-off-in-suspend;
  90                 };
  91         };
  92
  93         reg_pcie_switch: regulator-pcie-switch {
  94                 compatible = "regulator-fixed";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_gpio7>;
  97                 gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
  98                 enable-active-high;
  99                 regulator-max-microvolt = <1800000>;
 100                 regulator-min-microvolt = <1800000>;
 101                 regulator-name = "pcie_switch";
 102                 startup-delay-us = <100000>;
 103         };
 104
 105         reg_usb_host_vbus: regulator-usb-host-vbus {
 106                 compatible = "regulator-fixed";
 107                 pinctrl-names = "default";
 108                 pinctrl-0 = <&pinctrl_usbh_en>;
 109                 /* Apalis USBH_EN */
 110                 gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
 111                 enable-active-high;
 112                 regulator-always-on;
 113                 regulator-max-microvolt = <5000000>;
 114                 regulator-min-microvolt = <5000000>;
 115                 regulator-name = "usb-host-vbus";
 116         };
 117
 118         reg_usb_hsic: regulator-usb-hsic {
 119                 compatible = "regulator-fixed";
 120                 regulator-max-microvolt = <3000000>;
 121                 regulator-min-microvolt = <3000000>;
 122                 regulator-name = "usb-hsic-dummy";
 123         };
 124
 125         reg_usb_phy: regulator-usb-hsic1 {
 126                 compatible = "regulator-fixed";
 127                 regulator-max-microvolt = <3000000>;
 128                 regulator-min-microvolt = <3000000>;
 129                 regulator-name = "usb-phy-dummy";
 130         };
 131
 132         reserved-memory {
 133                 #address-cells = <2>;
 134                 #size-cells = <2>;
 135                 ranges;
 136
 137                 decoder_boot: decoder-boot@84000000 {
 138                         reg = <0 0x84000000 0 0x2000000>;
 139                         no-map;
 140                 };
 141
 142                 encoder1_boot: encoder1-boot@86000000 {
 143                         reg = <0 0x86000000 0 0x200000>;
 144                         no-map;
 145                 };
 146
 147                 encoder2_boot: encoder2-boot@86200000 {
 148                         reg = <0 0x86200000 0 0x200000>;
 149                         no-map;
 150                 };
 151
 152                 /*
 153                  * reserved-memory layout
 154                  * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
 155                  * Shouldn't be used at A core and Linux side.
 156                  *
 157                  */
 158                 m4_reserved: m4@88000000 {
 159                         reg = <0 0x88000000 0 0x8000000>;
 160                         no-map;
 161                 };
 162
 163                 rpmsg_reserved: rpmsg@90200000 {
 164                         reg = <0 0x90200000 0 0x200000>;
 165                         no-map;
 166                 };
 167
 168                 vdevbuffer: vdevbuffer@90400000 {
 169                         compatible = "shared-dma-pool";
 170                         reg = <0 0x90400000 0 0x100000>;
 171                         no-map;
 172                 };
 173
 174                 decoder_rpc: decoder-rpc@92000000 {
 175                         reg = <0 0x92000000 0 0x200000>;
 176                         no-map;
 177                 };
 178
 179                 dsp_reserved: dsp@92400000 {
 180                         reg = <0 0x92400000 0 0x2000000>;
 181                         no-map;
 182                 };
 183
 184                 encoder1_rpc: encoder1-rpc@94400000 {
 185                         reg = <0 0x94400000 0 0x700000>;
 186                         no-map;
 187                 };
 188
 189                 encoder2_rpc: encoder2-rpc@94b00000 {
 190                         reg = <0 0x94b00000 0 0x700000>;
 191                         no-map;
 192                 };
 193
 194                 /* global autoconfigured region for contiguous allocations */
 195                 linux,cma {
 196                         compatible = "shared-dma-pool";
 197                         alloc-ranges = <0 0xc0000000 0 0x3c000000>;
 198                         linux,cma-default;
 199                         reusable;
 200                         size = <0 0x3c000000>;
 201                 };
 202         };
 203
 204         /* TODO: Apalis Analogue Audio */
 205
 206         /* TODO: HDMI Audio */
 207
 208         /* TODO: Apalis SPDIF1 */
 209
 210         touchscreen: touchscreen {
 211                 compatible = "toradex,vf50-touchscreen";
 212                 interrupt-parent = <&lsio_gpio3>;
 213                 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
 214                 pinctrl-names = "idle", "default";
 215                 pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
 216                 pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
 217                 io-channels = <&adc1 2>, <&adc1 1>,
 218                               <&adc1 0>, <&adc1 3>;
 219                 vf50-ts-min-pressure = <200>;
 220                 xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
 221                 xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
 222                 yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
 223                 ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
 224                 /*
 225                  * NOTE: you must remove the pinctrl-adc1 from the adc1
 226                  * node below to use the touchscreen
 227                  */
 228                 status = "disabled";
 229         };
 230
 231 };
 232
 233 &adc0 {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&pinctrl_adc0>;
 236 };
 237
 238 &adc1 {
 239         pinctrl-names = "default";
 240         pinctrl-0 = <&pinctrl_adc1>;
 241 };
 242
 243 /* TODO: Asynchronous Sample Rate Converter (ASRC) */
 244
 245 /* Apalis ETH1 */
 246 &fec1 {
 247         pinctrl-names = "default", "sleep";
 248         pinctrl-0 = <&pinctrl_fec1>;
 249         pinctrl-1 = <&pinctrl_fec1_sleep>;
 250         fsl,magic-packet;
 251         phy-handle = <&ethphy0>;
 252         phy-mode = "rgmii-id";
 253
 254         mdio {
 255                 #address-cells = <1>;
 256                 #size-cells = <0>;
 257
 258                 ethphy0: ethernet-phy@7 {
 259                         compatible = "ethernet-phy-ieee802.3-c22";
 260                         reg = <7>;
 261                         interrupt-parent = <&lsio_gpio1>;
 262                         interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
 263                         micrel,led-mode = <0>;
 264                         reset-assert-us = <2>;
 265                         reset-deassert-us = <2>;
 266                         reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
 267                         reset-names = "phy-reset";
 268                 };
 269         };
 270 };
 271
 272 /* Apalis CAN1 */
 273 &flexcan1 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_flexcan1>;
 276 };
 277
 278 /* Apalis CAN2 */
 279 &flexcan2 {
 280         pinctrl-names = "default";
 281         pinctrl-0 = <&pinctrl_flexcan2>;
 282 };
 283
 284 /* Apalis CAN3 (optional) */
 285 &flexcan3 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_flexcan3>;
 288 };
 289
 290 /* TODO: Apalis HDMI1 */
 291
 292 /* On-module I2C */
 293 &i2c1 {
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_lpi2c1>;
 296         #address-cells = <1>;
 297         #size-cells = <0>;
 298         clock-frequency = <100000>;
 299         status = "okay";
 300
 301         /* TODO: Audio Codec */
 302
 303         /* USB3503A */
 304         usb-hub@8 {
 305                 compatible = "smsc,usb3503a";
 306                 reg = <0x08>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&pinctrl_usb3503a>;
 309                 connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
 310                 initial-mode = <1>;
 311                 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
 312                 refclk-frequency = <25000000>;
 313                 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
 314         };
 315 };
 316
 317 /* Apalis I2C1 */
 318 &i2c2 {
 319         pinctrl-names = "default";
 320         pinctrl-0 = <&pinctrl_lpi2c2>;
 321         #address-cells = <1>;
 322         #size-cells = <0>;
 323         clock-frequency = <100000>;
 324
 325         atmel_mxt_ts: touch@4a {
 326                 compatible = "atmel,maxtouch";
 327                 reg = <0x4a>;
 328                 interrupt-parent = <&lsio_gpio4>;
 329                 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;         /* Apalis GPIO5 */
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
 332                 reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>;  /* Apalis GPIO6 */
 333                 status = "disabled";
 334         };
 335
 336         /* M41T0M6 real time clock on carrier board */
 337         rtc_i2c: rtc@68 {
 338                 compatible = "st,m41t0";
 339                 reg = <0x68>;
 340                 status = "disabled";
 341         };
 342 };
 343
 344 /* Apalis I2C3 (CAM) */
 345 &i2c3 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_lpi2c3>;
 348         #address-cells = <1>;
 349         #size-cells = <0>;
 350         clock-frequency = <100000>;
 351 };
 352
 353 &jpegdec {
 354         status = "okay";
 355 };
 356
 357 &jpegenc {
 358         status = "okay";
 359 };
 360
 361 /* TODO: Apalis LVDS1 */
 362
 363 /* Apalis SPI1 */
 364 &lpspi0 {
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&pinctrl_lpspi0>;
 367         #address-cells = <1>;
 368         #size-cells = <0>;
 369         cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
 370 };
 371
 372 /* Apalis SPI2 */
 373 &lpspi2 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_lpspi2>;
 376         #address-cells = <1>;
 377         #size-cells = <0>;
 378         cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
 379 };
 380
 381 /* Apalis UART3 */
 382 &lpuart0 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_lpuart0>;
 385 };
 386
 387 /* Apalis UART1 */
 388 &lpuart1 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_lpuart1>;
 391 };
 392
 393 /* Apalis UART4 */
 394 &lpuart2 {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_lpuart2>;
 397 };
 398
 399 /* Apalis UART2 */
 400 &lpuart3 {
 401         pinctrl-names = "default";
 402         pinctrl-0 = <&pinctrl_lpuart3>;
 403 };
 404
 405 &lsio_gpio0 {
 406         gpio-line-names = "MXM3_279",
 407                           "MXM3_277",
 408                           "MXM3_135",
 409                           "MXM3_203",
 410                           "MXM3_201",
 411                           "MXM3_275",
 412                           "MXM3_110",
 413                           "MXM3_120",
 414                           "MXM3_1/GPIO1",
 415                           "MXM3_3/GPIO2",
 416                           "MXM3_124",
 417                           "MXM3_122",
 418                           "MXM3_5/GPIO3",
 419                           "MXM3_7/GPIO4",
 420                           "",
 421                           "",
 422                           "MXM3_4",
 423                           "MXM3_211",
 424                           "MXM3_209",
 425                           "MXM3_2",
 426                           "MXM3_136",
 427                           "MXM3_134",
 428                           "MXM3_6",
 429                           "MXM3_8",
 430                           "MXM3_112",
 431                           "MXM3_118",
 432                           "MXM3_114",
 433                           "MXM3_116";
 434 };
 435
 436 &lsio_gpio1 {
 437         gpio-line-names = "",
 438                           "",
 439                           "",
 440                           "",
 441                           "MXM3_286",
 442                           "",
 443                           "MXM3_87",
 444                           "MXM3_99",
 445                           "MXM3_138",
 446                           "MXM3_140",
 447                           "MXM3_239",
 448                           "",
 449                           "MXM3_281",
 450                           "MXM3_283",
 451                           "MXM3_126",
 452                           "MXM3_132",
 453                           "",
 454                           "",
 455                           "",
 456                           "",
 457                           "MXM3_173",
 458                           "MXM3_175",
 459                           "MXM3_123";
 460
 461         hdmi-ctrl-hog {
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&pinctrl_hdmi_ctrl>;
 464                 gpio-hog;
 465                 gpios = <30 GPIO_ACTIVE_HIGH>;
 466                 line-name = "CONNECTOR_IS_HDMI";
 467                 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */
 468                 output-high;
 469         };
 470 };
 471
 472 &lsio_gpio2 {
 473         gpio-line-names = "",
 474                           "",
 475                           "",
 476                           "",
 477                           "",
 478                           "",
 479                           "",
 480                           "MXM3_198",
 481                           "MXM3_35",
 482                           "MXM3_164",
 483                           "",
 484                           "",
 485                           "",
 486                           "",
 487                           "MXM3_217",
 488                           "MXM3_215",
 489                           "",
 490                           "",
 491                           "MXM3_193",
 492                           "MXM3_194",
 493                           "MXM3_37",
 494                           "",
 495                           "MXM3_271",
 496                           "MXM3_273",
 497                           "MXM3_195",
 498                           "MXM3_197",
 499                           "MXM3_177",
 500                           "MXM3_179",
 501                           "MXM3_181",
 502                           "MXM3_183",
 503                           "MXM3_185",
 504                           "MXM3_187";
 505
 506         /*
 507          * Add GPIO2_20 as a wakeup source:
 508          * Pin:  101    SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
 509          * Type: 5      SC_PAD_WAKEUP_FALL_EDGE
 510          * Line: 20
 511          */
 512         pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
 513         pad-wakeup-num = <1>;
 514
 515         pcie-wifi-hog {
 516                 pinctrl-names = "default";
 517                 pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
 518                 gpio-hog;
 519                 gpios = <11 GPIO_ACTIVE_HIGH>;
 520                 line-name = "PCIE_WIFI_CLK";
 521                 output-high;
 522         };
 523 };
 524
 525 &lsio_gpio3 {
 526         gpio-line-names = "MXM3_191",
 527                           "",
 528                           "MXM3_221",
 529                           "MXM3_225",
 530                           "MXM3_223",
 531                           "MXM3_227",
 532                           "MXM3_200",
 533                           "MXM3_235",
 534                           "MXM3_231",
 535                           "MXM3_229",
 536                           "MXM3_233",
 537                           "MXM3_204",
 538                           "MXM3_196",
 539                           "",
 540                           "MXM3_202",
 541                           "",
 542                           "",
 543                           "",
 544                           "MXM3_305",
 545                           "MXM3_307",
 546                           "MXM3_309",
 547                           "MXM3_311",
 548                           "MXM3_315",
 549                           "MXM3_317",
 550                           "MXM3_319",
 551                           "MXM3_321",
 552                           "MXM3_15/GPIO7",
 553                           "MXM3_63",
 554                           "MXM3_17/GPIO8",
 555                           "MXM3_12",
 556                           "MXM3_14",
 557                           "MXM3_16";
 558 };
 559
 560 &lsio_gpio4 {
 561         gpio-line-names = "MXM3_18",
 562                           "MXM3_11/GPIO5",
 563                           "MXM3_13/GPIO6",
 564                           "MXM3_274",
 565                           "MXM3_84",
 566                           "MXM3_262",
 567                           "MXM3_96",
 568                           "",
 569                           "",
 570                           "",
 571                           "",
 572                           "",
 573                           "MXM3_190",
 574                           "",
 575                           "",
 576                           "",
 577                           "MXM3_269",
 578                           "MXM3_251",
 579                           "MXM3_253",
 580                           "MXM3_295",
 581                           "MXM3_299",
 582                           "MXM3_301",
 583                           "MXM3_297",
 584                           "MXM3_293",
 585                           "MXM3_291",
 586                           "MXM3_289",
 587                           "MXM3_287";
 588
 589         /* Enable pcie root / sata ref clock unconditionally */
 590         pcie-sata-hog {
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
 593                 gpio-hog;
 594                 gpios = <11 GPIO_ACTIVE_HIGH>;
 595                 line-name = "PCIE_SATA_CLK";
 596                 output-high;
 597         };
 598 };
 599
 600 &lsio_gpio5 {
 601         gpio-line-names = "",
 602                           "",
 603                           "",
 604                           "",
 605                           "",
 606                           "",
 607                           "",
 608                           "",
 609                           "",
 610                           "",
 611                           "",
 612                           "",
 613                           "",
 614                           "",
 615                           "MXM3_150",
 616                           "MXM3_160",
 617                           "MXM3_162",
 618                           "MXM3_144",
 619                           "MXM3_146",
 620                           "MXM3_148",
 621                           "MXM3_152",
 622                           "MXM3_156",
 623                           "MXM3_158",
 624                           "MXM3_159",
 625                           "MXM3_184",
 626                           "MXM3_180",
 627                           "MXM3_186",
 628                           "MXM3_188",
 629                           "MXM3_176",
 630                           "MXM3_178";
 631 };
 632
 633 &lsio_gpio6 {
 634         gpio-line-names = "",
 635                           "",
 636                           "",
 637                           "",
 638                           "",
 639                           "",
 640                           "",
 641                           "",
 642                           "",
 643                           "",
 644                           "MXM3_261",
 645                           "MXM3_263",
 646                           "MXM3_259",
 647                           "MXM3_257",
 648                           "MXM3_255",
 649                           "MXM3_128",
 650                           "MXM3_130",
 651                           "MXM3_265",
 652                           "MXM3_249",
 653                           "MXM3_247",
 654                           "MXM3_245",
 655                           "MXM3_243";
 656 };
 657
 658 /* Apalis PWM3, MXM3 pin 6 */
 659 &lsio_pwm0 {
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pinctrl_pwm0>;
 662         #pwm-cells = <3>;
 663 };
 664
 665 /* Apalis PWM4, MXM3 pin 8 */
 666 &lsio_pwm1 {
 667         pinctrl-names = "default";
 668         pinctrl-0 = <&pinctrl_pwm1>;
 669         #pwm-cells = <3>;
 670 };
 671
 672 /* Apalis PWM1, MXM3 pin 2 */
 673 &lsio_pwm2 {
 674         pinctrl-names = "default";
 675         pinctrl-0 = <&pinctrl_pwm2>;
 676         #pwm-cells = <3>;
 677 };
 678
 679 /* Apalis PWM2, MXM3 pin 4 */
 680 &lsio_pwm3 {
 681         pinctrl-names = "default";
 682         pinctrl-0 = <&pinctrl_pwm3>;
 683         #pwm-cells = <3>;
 684 };
 685
 686 /* Messaging Units */
 687 &mu_m0 {
 688         status = "okay";
 689 };
 690
 691 &mu1_m0 {
 692         status = "okay";
 693 };
 694
 695 &mu2_m0 {
 696         status = "okay";
 697 };
 698
 699 /* TODO: Apalis PCIE1 */
 700
 701 /* TODO: On-module Wi-Fi */
 702
 703 /* TODO: Apalis BKL1_PWM */
 704
 705 /* TODO: Apalis DAP1 */
 706
 707 /* TODO: Analogue Audio */
 708
 709 /* TODO: Apalis SATA1 */
 710
 711 /* TODO: Apalis SPDIF1 */
 712
 713 /* TODO: Thermal Zones */
 714
 715 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
 716
 717 /* TODO: Apalis USBH4 */
 718
 719 /* Apalis USBO1 */
 720 &usbphy1 {
 721         phy-3p0-supply = <&reg_usb_phy>;
 722         status = "okay";
 723 };
 724
 725 &usbotg1 {
 726         pinctrl-names = "default";
 727         pinctrl-0 = <&pinctrl_usbotg1>;
 728         adp-disable;
 729         hnp-disable;
 730         over-current-active-low;
 731         power-active-high;
 732         srp-disable;
 733 };
 734
 735 /* On-module eMMC */
 736 &usdhc1 {
 737         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 738         pinctrl-0 = <&pinctrl_usdhc1>;
 739         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 740         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 741         bus-width = <8>;
 742         non-removable;
 743         status = "okay";
 744 };
 745
 746 /* Apalis MMC1 */
 747 &usdhc2 {
 748         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 749         pinctrl-0 = <&pinctrl_usdhc2_4bit>,
 750                     <&pinctrl_usdhc2_8bit>,
 751                     <&pinctrl_mmc1_cd>;
 752         pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
 753                     <&pinctrl_usdhc2_8bit_100mhz>,
 754                     <&pinctrl_mmc1_cd>;
 755         pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
 756                     <&pinctrl_usdhc2_8bit_200mhz>,
 757                     <&pinctrl_mmc1_cd>;
 758         pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
 759                     <&pinctrl_usdhc2_8bit_sleep>,
 760                     <&pinctrl_mmc1_cd_sleep>;
 761         bus-width = <8>;
 762         cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
 763         no-1-8-v;
 764 };
 765
 766 /* Apalis SD1 */
 767 &usdhc3 {
 768         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 769         pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
 770         pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
 771         pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
 772         bus-width = <4>;
 773         cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
 774         no-1-8-v;
 775 };
 776
 777 /* Video Processing Unit */
 778 &vpu {
 779         compatible = "nxp,imx8qm-vpu";
 780         status = "okay";
 781 };
 782
 783 &vpu_core0 {
 784         reg = <0x2d080000 0x10000>;
 785         memory-region = <&decoder_boot>, <&decoder_rpc>;
 786         status = "okay";
 787 };
 788
 789 &vpu_core1 {
 790         reg = <0x2d090000 0x10000>;
 791         memory-region = <&encoder1_boot>, <&encoder1_rpc>;
 792         status = "okay";
 793 };
 794
 795 &vpu_core2 {
 796         reg = <0x2d0a0000 0x10000>;
 797         memory-region = <&encoder2_boot>, <&encoder2_rpc>;
 798         status = "okay";
 799 };
 800
 801 &iomuxc {
 802         pinctrl-names = "default";
 803         pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
 804                     <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
 805                     <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
 806                     <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
 807                     <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
 808                     <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
 809                     <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
 810                     <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
 811                     <&pinctrl_usdhc1_gpios>;
 812
 813         /* Apalis AN1_ADC */
 814         pinctrl_adc0: adc0grp {
 815                 fsl,pins = /* Apalis AN1_ADC0 */
 816                            <IMX8QM_ADC_IN0_DMA_ADC0_IN0                         0xc0000060>,
 817                            /* Apalis AN1_ADC1 */
 818                            <IMX8QM_ADC_IN1_DMA_ADC0_IN1                         0xc0000060>,
 819                            /* Apalis AN1_ADC2 */
 820                            <IMX8QM_ADC_IN2_DMA_ADC0_IN2                         0xc0000060>,
 821                            /* Apalis AN1_TSWIP_ADC3 */
 822                            <IMX8QM_ADC_IN3_DMA_ADC0_IN3                         0xc0000060>;
 823         };
 824
 825         /* Apalis AN1_TS */
 826         pinctrl_adc1: adc1grp {
 827                 fsl,pins = /* Apalis AN1_TSPX */
 828                            <IMX8QM_ADC_IN4_DMA_ADC1_IN0                         0xc0000060>,
 829                            /* Apalis AN1_TSMX */
 830                            <IMX8QM_ADC_IN5_DMA_ADC1_IN1                         0xc0000060>,
 831                            /* Apalis AN1_TSPY */
 832                            <IMX8QM_ADC_IN6_DMA_ADC1_IN2                         0xc0000060>,
 833                            /* Apalis AN1_TSMY */
 834                            <IMX8QM_ADC_IN7_DMA_ADC1_IN3                         0xc0000060>;
 835         };
 836
 837         /* Apalis CAM1 */
 838         pinctrl_cam1_gpios: cam1gpiosgrp {
 839                 fsl,pins = /* Apalis CAM1_D7 */
 840                            <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20           0x00000021>,
 841                            /* Apalis CAM1_D6 */
 842                            <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21           0x00000021>,
 843                            /* Apalis CAM1_D5 */
 844                            <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26                    0x00000021>,
 845                            /* Apalis CAM1_D4 */
 846                            <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27                    0x00000021>,
 847                            /* Apalis CAM1_D3 */
 848                            <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28                0x00000021>,
 849                            /* Apalis CAM1_D2 */
 850                            <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29                0x00000021>,
 851                            /* Apalis CAM1_D1 */
 852                            <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30                0x00000021>,
 853                            /* Apalis CAM1_D0 */
 854                            <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31                0x00000021>,
 855                            /* Apalis CAM1_PCLK */
 856                            <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00                     0x00000021>,
 857                            /* Apalis CAM1_MCLK */
 858                            <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18                     0x00000021>,
 859                            /* Apalis CAM1_VSYNC */
 860                            <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24                   0x00000021>,
 861                            /* Apalis CAM1_HSYNC */
 862                            <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25                   0x00000021>;
 863         };
 864
 865         /* Apalis DAP1 */
 866         pinctrl_dap1_gpios: dap1gpiosgrp {
 867                 fsl,pins = /* Apalis DAP1_MCLK */
 868                            <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19                     0x00000021>,
 869                            /* Apalis DAP1_D_OUT */
 870                            <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12                     0x00000021>,
 871                            /* Apalis DAP1_RESET */
 872                            <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07                   0x00000021>,
 873                            /* Apalis DAP1_BIT_CLK */
 874                            <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06                     0x00000021>,
 875                            /* Apalis DAP1_D_IN */
 876                            <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14                    0x00000021>,
 877                            /* Apalis DAP1_SYNC */
 878                            <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11                     0x00000021>,
 879                            /* On-module Wi-Fi_I2S_EN# */
 880                            <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13                0x00000021>;
 881         };
 882
 883         /* Apalis LCD1_G1+2 */
 884         pinctrl_esai0_gpios: esai0gpiosgrp {
 885                 fsl,pins = /* Apalis LCD1_G1 */
 886                            <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22                    0x00000021>,
 887                            /* Apalis LCD1_G2 */
 888                            <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23                    0x00000021>;
 889         };
 890
 891         /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
 892         pinctrl_fec1: fec1grp {
 893                 fsl,pins = /* Use pads in 3.3V mode */
 894                            <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD                 0x000014a0>,
 895                            <IMX8QM_ENET0_MDC_CONN_ENET0_MDC                             0x06000020>,
 896                            <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO                           0x06000020>,
 897                            <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL           0x06000020>,
 898                            <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC                 0x06000020>,
 899                            <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0               0x06000020>,
 900                            <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1               0x06000020>,
 901                            <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2               0x06000020>,
 902                            <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3               0x06000020>,
 903                            <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC                 0x06000020>,
 904                            <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL           0x06000020>,
 905                            <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0               0x06000020>,
 906                            <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1               0x06000020>,
 907                            <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2               0x06000020>,
 908                            <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3               0x06000020>,
 909                            <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M     0x06000020>,
 910                            /* On-module ETH_RESET# */
 911                            <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11                         0x06000020>,
 912                            /* On-module ETH_INT# */
 913                            <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29                   0x04000060>;
 914         };
 915
 916         pinctrl_fec1_sleep: fec1-sleepgrp {
 917                 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD         0x000014a0>,
 918                            <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14                    0x04000040>,
 919                            <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13                   0x04000040>,
 920                            <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31           0x04000040>,
 921                            <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30              0x04000040>,
 922                            <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00             0x04000040>,
 923                            <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01             0x04000040>,
 924                            <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02             0x04000040>,
 925                            <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03             0x04000040>,
 926                            <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04              0x04000040>,
 927                            <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05           0x04000040>,
 928                            <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06             0x04000040>,
 929                            <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07             0x04000040>,
 930                            <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08             0x04000040>,
 931                            <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09             0x04000040>,
 932                            <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15        0x04000040>,
 933                            <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11                 0x06000020>,
 934                            <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29           0x04000040>;
 935         };
 936
 937         /* Apalis LCD1_ */
 938         pinctrl_fec2_gpios: fec2gpiosgrp {
 939                 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD         0x000014a0>,
 940                            /* Apalis LCD1_R1 */
 941                            <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18                    0x00000021>,
 942                            /* Apalis LCD1_R0 */
 943                            <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17                   0x00000021>,
 944                            /* Apalis LCD1_G0 */
 945                            <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16        0x00000021>,
 946                            /* Apalis LCD1_R7 */
 947                            <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17           0x00000021>,
 948                            /* Apalis LCD1_DE */
 949                            <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18             0x00000021>,
 950                            /* Apalis LCD1_HSYNC */
 951                            <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19             0x00000021>,
 952                            /* Apalis LCD1_VSYNC */
 953                            <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20             0x00000021>,
 954                            /* Apalis LCD1_PCLK */
 955                            <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21             0x00000021>,
 956                            /* Apalis LCD1_R6 */
 957                            <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11           0x00000021>,
 958                            /* Apalis LCD1_R5 */
 959                            <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10              0x00000021>,
 960                            /* Apalis LCD1_R4 */
 961                            <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12             0x00000021>,
 962                            /* Apalis LCD1_R3 */
 963                            <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13             0x00000021>,
 964                            /* Apalis LCD1_R2 */
 965                            <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14             0x00000021>;
 966         };
 967
 968         /* Apalis CAN1 */
 969         pinctrl_flexcan1: flexcan0grp {
 970                 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX                  0x00000021>,
 971                            <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX                  0x00000021>;
 972         };
 973
 974         /* Apalis CAN2 */
 975         pinctrl_flexcan2: flexcan1grp {
 976                 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX                  0x00000021>,
 977                            <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX                  0x00000021>;
 978         };
 979
 980         /* Apalis CAN3 (optional) */
 981         pinctrl_flexcan3: flexcan2grp {
 982                 fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX                  0x00000021>,
 983                            <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX                  0x00000021>;
 984         };
 985
 986         /* Apalis GPIO1 */
 987         pinctrl_gpio1: gpio1grp {
 988                 fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08                 0x06000021>;
 989         };
 990
 991         /* Apalis GPIO2 */
 992         pinctrl_gpio2: gpio2grp {
 993                 fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09                 0x06000021>;
 994         };
 995
 996         /* Apalis GPIO3 */
 997         pinctrl_gpio3: gpio3grp {
 998                 fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12                 0x06000021>;
 999         };
1000
1001         /* Apalis GPIO4 */
1002         pinctrl_gpio4: gpio4grp {
1003                 fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13                 0x06000021>;
1004         };
1005
1006         /* Apalis GPIO5 */
1007         pinctrl_gpio5: gpio5grp {
1008                 fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01                  0x06000021>;
1009         };
1010
1011         /* Apalis GPIO6 */
1012         pinctrl_gpio6: gpio6grp {
1013                 fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02                  0x00000021>;
1014         };
1015
1016         /* Apalis GPIO7 */
1017         pinctrl_gpio7: gpio7grp {
1018                 fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26                      0x00000021>;
1019         };
1020
1021         /* Apalis GPIO8 */
1022         pinctrl_gpio8: gpio8grp {
1023                 fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28                     0x00000021>;
1024         };
1025
1026         /* Apalis BKL1_ON */
1027         pinctrl_gpio_bkl_on: gpiobklongrp {
1028                 fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04                 0x00000021>;
1029         };
1030
1031         /* Apalis WAKE1_MICO */
1032         pinctrl_gpio_keys: gpiokeysgrp {
1033                 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20                     0x06700021>;
1034         };
1035
1036         /* Apalis USBH_OC# */
1037         pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1038                 fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06                  0x04000021>;
1039         };
1040
1041         /* On-module HDMI_CTRL */
1042         pinctrl_hdmi_ctrl: hdmictrlgrp {
1043                 fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30           0x00000061>;
1044         };
1045
1046         /* On-module I2C */
1047         pinctrl_lpi2c1: lpi2c1grp {
1048                 fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL                        0x04000020>,
1049                            <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA                    0x04000020>;
1050         };
1051
1052         /* Apalis I2C1 */
1053         pinctrl_lpi2c2: lpi2c2grp {
1054                 fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL                        0x04000020>,
1055                            <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA                    0x04000020>;
1056         };
1057
1058         /* Apalis I2C3 (CAM) */
1059         pinctrl_lpi2c3: lpi2c3grp {
1060                 fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL                         0x04000020>,
1061                            <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA                   0x04000020>;
1062         };
1063
1064         /* Apalis SPI1 */
1065         pinctrl_lpspi0: lpspi0grp {
1066                 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK                        0x0600004c>,
1067                            <IMX8QM_SPI0_SDO_DMA_SPI0_SDO                        0x0600004c>,
1068                            <IMX8QM_SPI0_SDI_DMA_SPI0_SDI                        0x0600004c>,
1069                            <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05                     0x0600004c>;
1070         };
1071
1072         /* Apalis SPI2 */
1073         pinctrl_lpspi2: lpspi2grp {
1074                 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK                        0x0600004c>,
1075                            <IMX8QM_SPI2_SDO_DMA_SPI2_SDO                        0x0600004c>,
1076                            <IMX8QM_SPI2_SDI_DMA_SPI2_SDI                        0x0600004c>,
1077                            <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10                     0x0600004c>;
1078         };
1079
1080         /* Apalis UART3 */
1081         pinctrl_lpuart0: lpuart0grp {
1082                 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX                        0x06000020>,
1083                            <IMX8QM_UART0_TX_DMA_UART0_TX                        0x06000020>;
1084         };
1085
1086         /* Apalis UART1 */
1087         pinctrl_lpuart1: lpuart1grp {
1088                 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX                        0x06000020>,
1089                            <IMX8QM_UART1_TX_DMA_UART1_TX                        0x06000020>,
1090                            <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B                  0x06000020>,
1091                            <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B                  0x06000020>;
1092         };
1093
1094         /* Apalis UART1 */
1095         pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1096                 fsl,pins = /* Apalis UART1_DTR */
1097                            <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06                 0x00000021>,
1098                            /* Apalis UART1_DSR */
1099                            <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07                 0x00000021>,
1100                            /* Apalis UART1_DCD */
1101                            <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10                 0x00000021>,
1102                            /* Apalis UART1_RI */
1103                            <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11                 0x00000021>;
1104         };
1105
1106         /* Apalis UART4 */
1107         pinctrl_lpuart2: lpuart2grp {
1108                 fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX                  0x06000020>,
1109                            <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX                  0x06000020>;
1110         };
1111
1112         /* Apalis UART2 */
1113         pinctrl_lpuart3: lpuart3grp {
1114                 fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX                  0x06000020>,
1115                            <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX                  0x06000020>,
1116                            <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B             0x06000020>,
1117                            <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B              0x06000020>;
1118         };
1119
1120         /* Apalis TS_2 */
1121         pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1122                 fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06               0x00000021>;
1123         };
1124
1125         /* Apalis LCD1_G6+7 */
1126         pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1127                 fsl,pins = /* Apalis LCD1_G6 */
1128                            <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12               0x00000021>,
1129                            /* Apalis LCD1_G7 */
1130                            <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13               0x00000021>;
1131         };
1132
1133         /* Apalis TS_3 */
1134         pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1135                 fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07               0x00000021>;
1136         };
1137
1138         /* Apalis TS_4 */
1139         pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1140                 fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22           0x00000021>;
1141         };
1142
1143         /* Apalis TS_1 */
1144         pinctrl_mlb_gpios: mlbgpiosgrp {
1145                 fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27                      0x00000021>;
1146         };
1147
1148         /* Apalis MMC1_CD# */
1149         pinctrl_mmc1_cd: mmc1cdgrp {
1150                 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09                    0x00000021>;
1151         };
1152
1153         pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1154                 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09                    0x04000021>;
1155         };
1156
1157         /* On-module PCIe_Wi-Fi */
1158         pinctrl_pcieb: pciebgrp {
1159                 fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30          0x00000021>,
1160                            <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31            0x00000021>,
1161                            <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00           0x00000021>;
1162         };
1163
1164         /* On-module PCIe_CLK_EN1 */
1165         pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1166                 fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11                    0x00000021>;
1167         };
1168
1169         /* On-module PCIe_CLK_EN2 */
1170         pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1171                 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11                0x00000021>;
1172         };
1173
1174         /* Apalis PWM3 */
1175         pinctrl_pwm0: pwm0grp {
1176                 fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT                    0x00000020>;
1177         };
1178
1179         /* Apalis PWM4 */
1180         pinctrl_pwm1: pwm1grp {
1181                 fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT                    0x00000020>;
1182         };
1183
1184         /* Apalis PWM1 */
1185         pinctrl_pwm2: pwm2grp {
1186                 fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT                   0x00000020>;
1187         };
1188
1189         /* Apalis PWM2 */
1190         pinctrl_pwm3: pwm3grp {
1191                 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT                   0x00000020>;
1192         };
1193
1194         /* Apalis BKL1_PWM */
1195         pinctrl_pwm_bkl: pwmbklgrp {
1196                 fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT                  0x00000020>;
1197         };
1198
1199         /* Apalis LCD1_ */
1200         pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1201                 fsl,pins = /* Apalis LCD1_B0 */
1202                            <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26                 0x00000021>,
1203                            /* Apalis LCD1_B1 */
1204                            <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25                 0x00000021>,
1205                            /* Apalis LCD1_B2 */
1206                            <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24                 0x00000021>,
1207                            /* Apalis LCD1_B3 */
1208                            <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23                 0x00000021>,
1209                            /* Apalis LCD1_B5 */
1210                            <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22                   0x00000021>,
1211                            /* Apalis LCD1_B7 */
1212                            <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21                  0x00000021>,
1213                            /* Apalis LCD1_B4 */
1214                            <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19                 0x00000021>,
1215                            /* Apalis LCD1_B6 */
1216                            <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20                 0x00000021>;
1217         };
1218
1219         /* On-module RESET_MOCI#_DRV */
1220         pinctrl_reset_moci: resetmocigrp {
1221                 fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30                 0x00000021>;
1222         };
1223
1224         /* On-module I2S SGTL5000 for Apalis Analogue Audio */
1225         pinctrl_sai1: sai1grp {
1226                 fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD                        0xc600006c>,
1227                            <IMX8QM_SAI1_RXD_AUD_SAI1_RXD                        0xc600004c>,
1228                            <IMX8QM_SAI1_TXC_AUD_SAI1_TXC                        0xc600004c>,
1229                            <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS                      0xc600004c>;
1230         };
1231
1232         /* Apalis SATA1_ACT# */
1233         pinctrl_sata1_act: sata1actgrp {
1234                 fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08                    0x00000021>;
1235         };
1236
1237         /* Apalis SD1_CD# */
1238         pinctrl_sd1_cd: sd1cdgrp {
1239                 fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12                  0x00000021>;
1240         };
1241
1242         /* On-module I2S SGTL5000 SYS_MCLK */
1243         pinctrl_sgtl5000: sgtl5000grp {
1244                 fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0                  0xc600004c>;
1245         };
1246
1247         /* Apalis LCD1_ */
1248         pinctrl_sim0_gpios: sim0gpiosgrp {
1249                 fsl,pins = /* Apalis LCD1_G5 */
1250                            <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00                     0x00000021>,
1251                            /* Apalis LCD1_G3 */
1252                            <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05                0x00000021>,
1253                            /* Apalis TS_5 */
1254                            <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02                      0x00000021>,
1255                            /* Apalis LCD1_G4 */
1256                            <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01                     0x00000021>;
1257         };
1258
1259         /* Apalis SPDIF */
1260         pinctrl_spdif0: spdif0grp {
1261                 fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX                      0xc6000040>,
1262                            <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX                      0xc6000040>;
1263         };
1264
1265         pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1266                 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04                    0x00000021>,
1267                            <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05                    0x00000041>,
1268                            <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17                     0x00000021>,
1269                            <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21                     0x00000041>;
1270         };
1271
1272         pinctrl_touchctrl_idle: touchctrlidlegrp {
1273                 fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22                      0x00000021>,
1274                            <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23                      0x00000021>,
1275                            <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24                      0x00000021>,
1276                            <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25                      0x00000021>;
1277         };
1278
1279         /* On-module USB HSIC HUB (active) */
1280         pinctrl_usb_hsic_active: usbh1activegrp {
1281                 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA           0x000000cf>,
1282                            <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE       0x000000ff>;
1283         };
1284
1285         /* On-module USB HSIC HUB (idle) */
1286         pinctrl_usb_hsic_idle: usbh1idlegrp {
1287                 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA           0x000000cf>,
1288                            <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE       0x000000cf>;
1289         };
1290
1291         /* On-module USB HSIC HUB */
1292         pinctrl_usb3503a: usb3503agrp {
1293                 fsl,pins = /* On-module HSIC_HUB_CONNECT */
1294                            <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31                 0x00000041>,
1295                            /* On-module HSIC_INT_N */
1296                            <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01                 0x00000021>,
1297                            /* On-module HSIC_RESET_N */
1298                            <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02                 0x00000041>;
1299         };
1300
1301         /* Apalis USBH_EN */
1302         pinctrl_usbh_en: usbhengrp {
1303                 fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04                  0x00000021>;
1304         };
1305
1306         /* Apalis USBO1 */
1307         pinctrl_usbotg1: usbotg1grp {
1308                 fsl,pins = /* Apalis USBO1_EN */
1309                            <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR                0x00000021>,
1310                            /* Apalis USBO1_OC# */
1311                            <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC                 0x04000021>;
1312         };
1313
1314         /* On-module eMMC */
1315         pinctrl_usdhc1: usdhc1grp {
1316                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000041>,
1317                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000021>,
1318                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000021>,
1319                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000021>,
1320                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000021>,
1321                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000021>,
1322                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000021>,
1323                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000021>,
1324                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000021>,
1325                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000021>,
1326                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000041>,
1327                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000021>;
1328         };
1329
1330         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1331                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000040>,
1332                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000020>,
1333                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000020>,
1334                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000020>,
1335                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000020>,
1336                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000020>,
1337                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000020>,
1338                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000020>,
1339                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000020>,
1340                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000020>,
1341                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000040>,
1342                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000020>;
1343         };
1344
1345         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1346                 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK                     0x06000040>,
1347                            <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD                     0x00000020>,
1348                            <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0                 0x00000020>,
1349                            <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1                 0x00000020>,
1350                            <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2                 0x00000020>,
1351                            <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3                 0x00000020>,
1352                            <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4                 0x00000020>,
1353                            <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5                 0x00000020>,
1354                            <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6                 0x00000020>,
1355                            <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7                 0x00000020>,
1356                            <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE               0x06000040>,
1357                            <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B             0x00000020>;
1358         };
1359
1360         /* Apalis TS_6 */
1361         pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1362                 fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23                0x00000021>;
1363         };
1364
1365         /* Apalis MMC1 */
1366         pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1367                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000041>,
1368                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000021>,
1369                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000021>,
1370                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000021>,
1371                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000021>,
1372                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000021>,
1373                            /* On-module PMIC use */
1374                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1375         };
1376
1377         pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1378                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000040>,
1379                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000020>,
1380                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000020>,
1381                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000020>,
1382                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000020>,
1383                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000020>,
1384                            /* On-module PMIC use */
1385                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1386         };
1387
1388         pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1389                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x06000040>,
1390                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x00000020>,
1391                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x00000020>,
1392                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x00000020>,
1393                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x00000020>,
1394                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x00000020>,
1395                            /* On-module PMIC use */
1396                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1397         };
1398
1399         pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1400                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000021>,
1401                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000021>,
1402                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000021>,
1403                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000021>;
1404         };
1405
1406         pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1407                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000020>,
1408                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000020>,
1409                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000020>,
1410                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000020>;
1411         };
1412
1413         pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1414                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x00000020>,
1415                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x00000020>,
1416                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x00000020>,
1417                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x00000020>;
1418         };
1419
1420         pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1421                 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK                   0x04000061>,
1422                            <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD                   0x04000061>,
1423                            <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0               0x04000061>,
1424                            <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1               0x04000061>,
1425                            <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2               0x04000061>,
1426                            <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3               0x04000061>,
1427                            /* On-module PMIC use */
1428                            <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT           0x00000021>;
1429         };
1430
1431         pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1432                 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4               0x04000061>,
1433                            <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5               0x04000061>,
1434                            <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6               0x04000061>,
1435                            <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7               0x04000061>;
1436         };
1437
1438         /* Apalis SD1 */
1439         pinctrl_usdhc3: usdhc3grp {
1440                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1441                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1442                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1443                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1444                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1445                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1446                            /* On-module PMIC use */
1447                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1448         };
1449
1450         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1451                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1452                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1453                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1454                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1455                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1456                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1457                            /* On-module PMIC use */
1458                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1459         };
1460
1461         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1462                 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK                   0x06000041>,
1463                            <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD                   0x00000021>,
1464                            <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0               0x00000021>,
1465                            <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1               0x00000021>,
1466                            <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2               0x00000021>,
1467                            <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3               0x00000021>,
1468                            /* On-module PMIC use */
1469                            <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT           0x00000021>;
1470         };
1471
1472         /* On-module Wi-Fi */
1473         pinctrl_wifi: wifigrp {
1474                 fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1475                            <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K    0x06000021>,
1476                            /* On-module Wi-Fi_PCIE_W_DISABLE */
1477                            <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24           0x06000021>;
1478         };
1479
1480         pinctrl_wifi_pdn: wifipdngrp {
1481                 fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1482                            <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28           0x06000021>;
1483         };
1484 };