arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2017-2020 NXP
   7  *
   8  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
   9  *
  10  */
  11
  12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15
  16 / {
  17         compatible = "fsl,ls2080a";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 crypto = &crypto;
  24                 rtc1 = &ftm_alarm0;
  25                 serial0 = &serial0;
  26                 serial1 = &serial1;
  27                 serial2 = &serial2;
  28                 serial3 = &serial3;
  29         };
  30
  31         cpu: cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34         };
  35
  36         memory@80000000 {
  37                 device_type = "memory";
  38                 reg = <0x00000000 0x80000000 0 0x80000000>;
  39                       /* DRAM space - 1, size : 2 GB DRAM */
  40         };
  41
  42         sysclk: sysclk {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <100000000>;
  46                 clock-output-names = "sysclk";
  47         };
  48
  49         gic: interrupt-controller@6000000 {
  50                 compatible = "arm,gic-v3";
  51                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  52                         <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
  53                         <0x0 0x0c0c0000 0 0x2000>, /* GICC */
  54                         <0x0 0x0c0d0000 0 0x1000>, /* GICH */
  55                         <0x0 0x0c0e0000 0 0x20000>; /* GICV */
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <2>;
  58                 #size-cells = <2>;
  59                 ranges;
  60                 interrupt-controller;
  61                 interrupts = <1 9 0x4>;
  62
  63                 its: gic-its@6020000 {
  64                         compatible = "arm,gic-v3-its";
  65                         msi-controller;
  66                         reg = <0x0 0x6020000 0 0x20000>;
  67                 };
  68         };
  69
  70         rstcr: syscon@1e60000 {
  71                 compatible = "fsl,ls2080a-rstcr", "syscon";
  72                 reg = <0x0 0x1e60000 0x0 0x4>;
  73         };
  74
  75         reboot {
  76                 compatible = "syscon-reboot";
  77                 regmap = <&rstcr>;
  78                 offset = <0x0>;
  79                 mask = <0x2>;
  80         };
  81
  82         thermal-zones {
  83                 ddr-controller1 {
  84                         polling-delay-passive = <1000>;
  85                         polling-delay = <5000>;
  86                         thermal-sensors = <&tmu 1>;
  87
  88                         trips {
  89                                 ddr-ctrler1-crit {
  90                                         temperature = <95000>;
  91                                         hysteresis = <2000>;
  92                                         type = "critical";
  93                                 };
  94                         };
  95                 };
  96
  97                 ddr-controller2 {
  98                         polling-delay-passive = <1000>;
  99                         polling-delay = <5000>;
 100                         thermal-sensors = <&tmu 2>;
 101
 102                         trips {
 103                                 ddr-ctrler2-crit {
 104                                         temperature = <95000>;
 105                                         hysteresis = <2000>;
 106                                         type = "critical";
 107                                 };
 108                         };
 109                 };
 110
 111                 ddr-controller3 {
 112                         polling-delay-passive = <1000>;
 113                         polling-delay = <5000>;
 114                         thermal-sensors = <&tmu 3>;
 115
 116                         trips {
 117                                 ddr-ctrler3-crit {
 118                                         temperature = <95000>;
 119                                         hysteresis = <2000>;
 120                                         type = "critical";
 121                                 };
 122                         };
 123                 };
 124
 125                 core-cluster1 {
 126                         polling-delay-passive = <1000>;
 127                         polling-delay = <5000>;
 128                         thermal-sensors = <&tmu 4>;
 129
 130                         trips {
 131                                 core_cluster1_alert: core-cluster1-alert {
 132                                         temperature = <85000>;
 133                                         hysteresis = <2000>;
 134                                         type = "passive";
 135                                 };
 136
 137                                 core-cluster1-crit {
 138                                         temperature = <95000>;
 139                                         hysteresis = <2000>;
 140                                         type = "critical";
 141                                 };
 142                         };
 143
 144                         cooling-maps {
 145                                 map0 {
 146                                         trip = <&core_cluster1_alert>;
 147                                         cooling-device =
 148                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 149                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 150                                 };
 151                         };
 152                 };
 153
 154                 core-cluster2 {
 155                         polling-delay-passive = <1000>;
 156                         polling-delay = <5000>;
 157                         thermal-sensors = <&tmu 5>;
 158
 159                         trips {
 160                                 core_cluster2_alert: core-cluster2-alert {
 161                                         temperature = <85000>;
 162                                         hysteresis = <2000>;
 163                                         type = "passive";
 164                                 };
 165
 166                                 core-cluster2-crit {
 167                                         temperature = <95000>;
 168                                         hysteresis = <2000>;
 169                                         type = "critical";
 170                                 };
 171                         };
 172
 173                         cooling-maps {
 174                                 map0 {
 175                                         trip = <&core_cluster2_alert>;
 176                                         cooling-device =
 177                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 178                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 179                                 };
 180                         };
 181                 };
 182
 183                 core-cluster3 {
 184                         polling-delay-passive = <1000>;
 185                         polling-delay = <5000>;
 186                         thermal-sensors = <&tmu 6>;
 187
 188                         trips {
 189                                 core_cluster3_alert: core-cluster3-alert {
 190                                         temperature = <85000>;
 191                                         hysteresis = <2000>;
 192                                         type = "passive";
 193                                 };
 194
 195                                 core-cluster3-crit {
 196                                         temperature = <95000>;
 197                                         hysteresis = <2000>;
 198                                         type = "critical";
 199                                 };
 200                         };
 201
 202                         cooling-maps {
 203                                 map0 {
 204                                         trip = <&core_cluster3_alert>;
 205                                         cooling-device =
 206                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 207                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 208                                 };
 209                         };
 210                 };
 211
 212                 core-cluster4 {
 213                         polling-delay-passive = <1000>;
 214                         polling-delay = <5000>;
 215                         thermal-sensors = <&tmu 7>;
 216
 217                         trips {
 218                                 core_cluster4_alert: core-cluster4-alert {
 219                                         temperature = <85000>;
 220                                         hysteresis = <2000>;
 221                                         type = "passive";
 222                                 };
 223
 224                                 core-cluster4-crit {
 225                                         temperature = <95000>;
 226                                         hysteresis = <2000>;
 227                                         type = "critical";
 228                                 };
 229                         };
 230
 231                         cooling-maps {
 232                                 map0 {
 233                                         trip = <&core_cluster4_alert>;
 234                                         cooling-device =
 235                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 236                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         timer: timer {
 243                 compatible = "arm,armv8-timer";
 244                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
 245                              <1 14 4>, /* Physical Non-Secure PPI, active-low */
 246                              <1 11 4>, /* Virtual PPI, active-low */
 247                              <1 10 4>; /* Hypervisor PPI, active-low */
 248         };
 249
 250         pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
 253         };
 254
 255         psci {
 256                 compatible = "arm,psci-0.2";
 257                 method = "smc";
 258         };
 259
 260         soc {
 261                 compatible = "simple-bus";
 262                 #address-cells = <2>;
 263                 #size-cells = <2>;
 264                 ranges;
 265                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 266
 267                 clockgen: clocking@1300000 {
 268                         compatible = "fsl,ls2080a-clockgen";
 269                         reg = <0 0x1300000 0 0xa0000>;
 270                         #clock-cells = <2>;
 271                         clocks = <&sysclk>;
 272                 };
 273
 274                 dcfg: dcfg@1e00000 {
 275                         compatible = "fsl,ls2080a-dcfg", "syscon";
 276                         reg = <0x0 0x1e00000 0x0 0x10000>;
 277                         little-endian;
 278                 };
 279
 280                 sfp: efuse@1e80000 {
 281                         compatible = "fsl,ls1028a-sfp";
 282                         reg = <0x0 0x1e80000 0x0 0x10000>;
 283                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 284                                             QORIQ_CLK_PLL_DIV(4)>;
 285                         clock-names = "sfp";
 286                 };
 287
 288                 isc: syscon@1f70000 {
 289                         compatible = "fsl,ls2080a-isc", "syscon";
 290                         reg = <0x0 0x1f70000 0x0 0x10000>;
 291                         little-endian;
 292                         #address-cells = <1>;
 293                         #size-cells = <1>;
 294                         ranges = <0x0 0x0 0x1f70000 0x10000>;
 295
 296                         extirq: interrupt-controller@14 {
 297                                 compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
 298                                 #interrupt-cells = <2>;
 299                                 #address-cells = <0>;
 300                                 interrupt-controller;
 301                                 reg = <0x14 4>;
 302                                 interrupt-map =
 303                                         <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 304                                         <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 305                                         <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 306                                         <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 307                                         <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 308                                         <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 309                                         <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 310                                         <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 311                                         <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 312                                         <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 313                                         <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 314                                         <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 315                                 interrupt-map-mask = <0xf 0x0>;
 316                         };
 317                 };
 318
 319                 tmu: tmu@1f80000 {
 320                         compatible = "fsl,qoriq-tmu";
 321                         reg = <0x0 0x1f80000 0x0 0x10000>;
 322                         interrupts = <0 23 0x4>;
 323                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 324                         fsl,tmu-calibration = <0x00000000 0x00000026
 325                                                0x00000001 0x0000002d
 326                                                0x00000002 0x00000032
 327                                                0x00000003 0x00000039
 328                                                0x00000004 0x0000003f
 329                                                0x00000005 0x00000046
 330                                                0x00000006 0x0000004d
 331                                                0x00000007 0x00000054
 332                                                0x00000008 0x0000005a
 333                                                0x00000009 0x00000061
 334                                                0x0000000a 0x0000006a
 335                                                0x0000000b 0x00000071
 336
 337                                                0x00010000 0x00000025
 338                                                0x00010001 0x0000002c
 339                                                0x00010002 0x00000035
 340                                                0x00010003 0x0000003d
 341                                                0x00010004 0x00000045
 342                                                0x00010005 0x0000004e
 343                                                0x00010006 0x00000057
 344                                                0x00010007 0x00000061
 345                                                0x00010008 0x0000006b
 346                                                0x00010009 0x00000076
 347
 348                                                0x00020000 0x00000029
 349                                                0x00020001 0x00000033
 350                                                0x00020002 0x0000003d
 351                                                0x00020003 0x00000049
 352                                                0x00020004 0x00000056
 353                                                0x00020005 0x00000061
 354                                                0x00020006 0x0000006d
 355
 356                                                0x00030000 0x00000021
 357                                                0x00030001 0x0000002a
 358                                                0x00030002 0x0000003c
 359                                                0x00030003 0x0000004e>;
 360                         little-endian;
 361                         #thermal-sensor-cells = <1>;
 362                 };
 363
 364                 serial0: serial@21c0500 {
 365                         compatible = "fsl,ns16550", "ns16550a";
 366                         reg = <0x0 0x21c0500 0x0 0x100>;
 367                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 368                                             QORIQ_CLK_PLL_DIV(4)>;
 369                         interrupts = <0 32 0x4>; /* Level high type */
 370                 };
 371
 372                 serial1: serial@21c0600 {
 373                         compatible = "fsl,ns16550", "ns16550a";
 374                         reg = <0x0 0x21c0600 0x0 0x100>;
 375                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 376                                             QORIQ_CLK_PLL_DIV(4)>;
 377                         interrupts = <0 32 0x4>; /* Level high type */
 378                 };
 379
 380                 serial2: serial@21d0500 {
 381                         compatible = "fsl,ns16550", "ns16550a";
 382                         reg = <0x0 0x21d0500 0x0 0x100>;
 383                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 384                                             QORIQ_CLK_PLL_DIV(4)>;
 385                         interrupts = <0 33 0x4>; /* Level high type */
 386                 };
 387
 388                 serial3: serial@21d0600 {
 389                         compatible = "fsl,ns16550", "ns16550a";
 390                         reg = <0x0 0x21d0600 0x0 0x100>;
 391                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 392                                             QORIQ_CLK_PLL_DIV(4)>;
 393                         interrupts = <0 33 0x4>; /* Level high type */
 394                 };
 395
 396                 cluster1_core0_watchdog: wdt@c000000 {
 397                         compatible = "arm,sp805", "arm,primecell";
 398                         reg = <0x0 0xc000000 0x0 0x1000>;
 399                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 400                                             QORIQ_CLK_PLL_DIV(4)>,
 401                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 402                                             QORIQ_CLK_PLL_DIV(4)>;
 403                         clock-names = "wdog_clk", "apb_pclk";
 404                 };
 405
 406                 cluster1_core1_watchdog: wdt@c010000 {
 407                         compatible = "arm,sp805", "arm,primecell";
 408                         reg = <0x0 0xc010000 0x0 0x1000>;
 409                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 410                                             QORIQ_CLK_PLL_DIV(4)>,
 411                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 412                                             QORIQ_CLK_PLL_DIV(4)>;
 413                         clock-names = "wdog_clk", "apb_pclk";
 414                 };
 415
 416                 cluster2_core0_watchdog: wdt@c100000 {
 417                         compatible = "arm,sp805", "arm,primecell";
 418                         reg = <0x0 0xc100000 0x0 0x1000>;
 419                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 420                                             QORIQ_CLK_PLL_DIV(4)>,
 421                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 422                                             QORIQ_CLK_PLL_DIV(4)>;
 423                         clock-names = "wdog_clk", "apb_pclk";
 424                 };
 425
 426                 cluster2_core1_watchdog: wdt@c110000 {
 427                         compatible = "arm,sp805", "arm,primecell";
 428                         reg = <0x0 0xc110000 0x0 0x1000>;
 429                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 430                                             QORIQ_CLK_PLL_DIV(4)>,
 431                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 432                                             QORIQ_CLK_PLL_DIV(4)>;
 433                         clock-names = "wdog_clk", "apb_pclk";
 434                 };
 435
 436                 cluster3_core0_watchdog: wdt@c200000 {
 437                         compatible = "arm,sp805", "arm,primecell";
 438                         reg = <0x0 0xc200000 0x0 0x1000>;
 439                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 440                                             QORIQ_CLK_PLL_DIV(4)>,
 441                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 442                                             QORIQ_CLK_PLL_DIV(4)>;
 443                         clock-names = "wdog_clk", "apb_pclk";
 444                 };
 445
 446                 cluster3_core1_watchdog: wdt@c210000 {
 447                         compatible = "arm,sp805", "arm,primecell";
 448                         reg = <0x0 0xc210000 0x0 0x1000>;
 449                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 450                                             QORIQ_CLK_PLL_DIV(4)>,
 451                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 452                                             QORIQ_CLK_PLL_DIV(4)>;
 453                         clock-names = "wdog_clk", "apb_pclk";
 454                 };
 455
 456                 cluster4_core0_watchdog: wdt@c300000 {
 457                         compatible = "arm,sp805", "arm,primecell";
 458                         reg = <0x0 0xc300000 0x0 0x1000>;
 459                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 460                                             QORIQ_CLK_PLL_DIV(4)>,
 461                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 462                                             QORIQ_CLK_PLL_DIV(4)>;
 463                         clock-names = "wdog_clk", "apb_pclk";
 464                 };
 465
 466                 cluster4_core1_watchdog: wdt@c310000 {
 467                         compatible = "arm,sp805", "arm,primecell";
 468                         reg = <0x0 0xc310000 0x0 0x1000>;
 469                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 470                                             QORIQ_CLK_PLL_DIV(4)>,
 471                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
 472                                             QORIQ_CLK_PLL_DIV(4)>;
 473                         clock-names = "wdog_clk", "apb_pclk";
 474                 };
 475
 476                 crypto: crypto@8000000 {
 477                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 478                         fsl,sec-era = <8>;
 479                         #address-cells = <1>;
 480                         #size-cells = <1>;
 481                         ranges = <0x0 0x00 0x8000000 0x100000>;
 482                         reg = <0x00 0x8000000 0x0 0x100000>;
 483                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 484                         dma-coherent;
 485
 486                         sec_jr0: jr@10000 {
 487                                 compatible = "fsl,sec-v5.0-job-ring",
 488                                              "fsl,sec-v4.0-job-ring";
 489                                 reg = <0x10000 0x10000>;
 490                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 491                         };
 492
 493                         sec_jr1: jr@20000 {
 494                                 compatible = "fsl,sec-v5.0-job-ring",
 495                                              "fsl,sec-v4.0-job-ring";
 496                                 reg = <0x20000 0x10000>;
 497                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 498                         };
 499
 500                         sec_jr2: jr@30000 {
 501                                 compatible = "fsl,sec-v5.0-job-ring",
 502                                              "fsl,sec-v4.0-job-ring";
 503                                 reg = <0x30000 0x10000>;
 504                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 505                         };
 506
 507                         sec_jr3: jr@40000 {
 508                                 compatible = "fsl,sec-v5.0-job-ring",
 509                                              "fsl,sec-v4.0-job-ring";
 510                                 reg = <0x40000 0x10000>;
 511                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 512                         };
 513                 };
 514
 515                 console@8340020 {
 516                         compatible = "fsl,dpaa2-console";
 517                         reg = <0x00000000 0x08340020 0 0x2>;
 518                 };
 519
 520                 ptp-timer@8b95000 {
 521                         compatible = "fsl,dpaa2-ptp";
 522                         reg = <0x0 0x8b95000 0x0 0x100>;
 523                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 524                                             QORIQ_CLK_PLL_DIV(2)>;
 525                         little-endian;
 526                         fsl,extts-fifo;
 527                 };
 528
 529                 emdio1: mdio@8b96000 {
 530                         compatible = "fsl,fman-memac-mdio";
 531                         reg = <0x0 0x8b96000 0x0 0x1000>;
 532                         little-endian;
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         status = "disabled";
 536                 };
 537
 538                 emdio2: mdio@8b97000 {
 539                         compatible = "fsl,fman-memac-mdio";
 540                         reg = <0x0 0x8b97000 0x0 0x1000>;
 541                         little-endian;
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         status = "disabled";
 545                 };
 546
 547                 pcs_mdio1: mdio@8c07000 {
 548                         compatible = "fsl,fman-memac-mdio";
 549                         reg = <0x0 0x8c07000 0x0 0x1000>;
 550                         little-endian;
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         status = "disabled";
 554
 555                         pcs1: ethernet-phy@0 {
 556                                 reg = <0>;
 557                         };
 558                 };
 559
 560                 pcs_mdio2: mdio@8c0b000 {
 561                         compatible = "fsl,fman-memac-mdio";
 562                         reg = <0x0 0x8c0b000 0x0 0x1000>;
 563                         little-endian;
 564                         #address-cells = <1>;
 565                         #size-cells = <0>;
 566                         status = "disabled";
 567
 568                         pcs2: ethernet-phy@0 {
 569                                 reg = <0>;
 570                         };
 571                 };
 572
 573                 pcs_mdio3: mdio@8c0f000 {
 574                         compatible = "fsl,fman-memac-mdio";
 575                         reg = <0x0 0x8c0f000 0x0 0x1000>;
 576                         little-endian;
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         status = "disabled";
 580
 581                         pcs3: ethernet-phy@0 {
 582                                 reg = <0>;
 583                         };
 584                 };
 585
 586                 pcs_mdio4: mdio@8c13000 {
 587                         compatible = "fsl,fman-memac-mdio";
 588                         reg = <0x0 0x8c13000 0x0 0x1000>;
 589                         little-endian;
 590                         #address-cells = <1>;
 591                         #size-cells = <0>;
 592                         status = "disabled";
 593
 594                         pcs4: ethernet-phy@0 {
 595                                 reg = <0>;
 596                         };
 597                 };
 598
 599                 pcs_mdio5: mdio@8c17000 {
 600                         compatible = "fsl,fman-memac-mdio";
 601                         reg = <0x0 0x8c17000 0x0 0x1000>;
 602                         little-endian;
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                         status = "disabled";
 606
 607                         pcs5: ethernet-phy@0 {
 608                                 reg = <0>;
 609                         };
 610                 };
 611
 612                 pcs_mdio6: mdio@8c1b000 {
 613                         compatible = "fsl,fman-memac-mdio";
 614                         reg = <0x0 0x8c1b000 0x0 0x1000>;
 615                         little-endian;
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         status = "disabled";
 619
 620                         pcs6: ethernet-phy@0 {
 621                                 reg = <0>;
 622                         };
 623                 };
 624
 625                 pcs_mdio7: mdio@8c1f000 {
 626                         compatible = "fsl,fman-memac-mdio";
 627                         reg = <0x0 0x8c1f000 0x0 0x1000>;
 628                         little-endian;
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         status = "disabled";
 632
 633                         pcs7: ethernet-phy@0 {
 634                                 reg = <0>;
 635                         };
 636                 };
 637
 638                 pcs_mdio8: mdio@8c23000 {
 639                         compatible = "fsl,fman-memac-mdio";
 640                         reg = <0x0 0x8c23000 0x0 0x1000>;
 641                         little-endian;
 642                         #address-cells = <1>;
 643                         #size-cells = <0>;
 644                         status = "disabled";
 645
 646                         pcs8: ethernet-phy@0 {
 647                                 reg = <0>;
 648                         };
 649                 };
 650
 651                 pcs_mdio9: mdio@8c27000 {
 652                         compatible = "fsl,fman-memac-mdio";
 653                         reg = <0x0 0x8c27000 0x0 0x1000>;
 654                         little-endian;
 655                         #address-cells = <1>;
 656                         #size-cells = <0>;
 657                         status = "disabled";
 658
 659                         pcs9: ethernet-phy@0 {
 660                                 reg = <0>;
 661                         };
 662                 };
 663
 664                 pcs_mdio10: mdio@8c2b000 {
 665                         compatible = "fsl,fman-memac-mdio";
 666                         reg = <0x0 0x8c2b000 0x0 0x1000>;
 667                         little-endian;
 668                         #address-cells = <1>;
 669                         #size-cells = <0>;
 670                         status = "disabled";
 671
 672                         pcs10: ethernet-phy@0 {
 673                                 reg = <0>;
 674                         };
 675                 };
 676
 677                 pcs_mdio11: mdio@8c2f000 {
 678                         compatible = "fsl,fman-memac-mdio";
 679                         reg = <0x0 0x8c2f000 0x0 0x1000>;
 680                         little-endian;
 681                         #address-cells = <1>;
 682                         #size-cells = <0>;
 683                         status = "disabled";
 684
 685                         pcs11: ethernet-phy@0 {
 686                                 reg = <0>;
 687                         };
 688                 };
 689
 690                 pcs_mdio12: mdio@8c33000 {
 691                         compatible = "fsl,fman-memac-mdio";
 692                         reg = <0x0 0x8c33000 0x0 0x1000>;
 693                         little-endian;
 694                         #address-cells = <1>;
 695                         #size-cells = <0>;
 696                         status = "disabled";
 697
 698                         pcs12: ethernet-phy@0 {
 699                                 reg = <0>;
 700                         };
 701                 };
 702
 703                 pcs_mdio13: mdio@8c37000 {
 704                         compatible = "fsl,fman-memac-mdio";
 705                         reg = <0x0 0x8c37000 0x0 0x1000>;
 706                         little-endian;
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709                         status = "disabled";
 710
 711                         pcs13: ethernet-phy@0 {
 712                                 reg = <0>;
 713                         };
 714                 };
 715
 716                 pcs_mdio14: mdio@8c3b000 {
 717                         compatible = "fsl,fman-memac-mdio";
 718                         reg = <0x0 0x8c3b000 0x0 0x1000>;
 719                         little-endian;
 720                         #address-cells = <1>;
 721                         #size-cells = <0>;
 722                         status = "disabled";
 723
 724                         pcs14: ethernet-phy@0 {
 725                                 reg = <0>;
 726                         };
 727                 };
 728
 729                 pcs_mdio15: mdio@8c3f000 {
 730                         compatible = "fsl,fman-memac-mdio";
 731                         reg = <0x0 0x8c3f000 0x0 0x1000>;
 732                         little-endian;
 733                         #address-cells = <1>;
 734                         #size-cells = <0>;
 735                         status = "disabled";
 736
 737                         pcs15: ethernet-phy@0 {
 738                                 reg = <0>;
 739                         };
 740                 };
 741
 742                 pcs_mdio16: mdio@8c43000 {
 743                         compatible = "fsl,fman-memac-mdio";
 744                         reg = <0x0 0x8c43000 0x0 0x1000>;
 745                         little-endian;
 746                         #address-cells = <1>;
 747                         #size-cells = <0>;
 748                         status = "disabled";
 749
 750                         pcs16: ethernet-phy@0 {
 751                                 reg = <0>;
 752                         };
 753                 };
 754
 755                 fsl_mc: fsl-mc@80c000000 {
 756                         compatible = "fsl,qoriq-mc";
 757                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 758                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 759                         msi-parent = <&its>;
 760                         iommu-map = <0 &smmu 0 0>;      /* This is fixed-up by u-boot */
 761                         dma-coherent;
 762                         #address-cells = <3>;
 763                         #size-cells = <1>;
 764
 765                         /*
 766                          * Region type 0x0 - MC portals
 767                          * Region type 0x1 - QBMAN portals
 768                          */
 769                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 770                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 771
 772                         /*
 773                          * Define the maximum number of MACs present on the SoC.
 774                          */
 775                         dpmacs {
 776                                 #address-cells = <1>;
 777                                 #size-cells = <0>;
 778
 779                                 dpmac1: ethernet@1 {
 780                                         compatible = "fsl,qoriq-mc-dpmac";
 781                                         reg = <0x1>;
 782                                         pcs-handle = <&pcs1>;
 783                                 };
 784
 785                                 dpmac2: ethernet@2 {
 786                                         compatible = "fsl,qoriq-mc-dpmac";
 787                                         reg = <0x2>;
 788                                         pcs-handle = <&pcs2>;
 789                                 };
 790
 791                                 dpmac3: ethernet@3 {
 792                                         compatible = "fsl,qoriq-mc-dpmac";
 793                                         reg = <0x3>;
 794                                         pcs-handle = <&pcs3>;
 795                                 };
 796
 797                                 dpmac4: ethernet@4 {
 798                                         compatible = "fsl,qoriq-mc-dpmac";
 799                                         reg = <0x4>;
 800                                         pcs-handle = <&pcs4>;
 801                                 };
 802
 803                                 dpmac5: ethernet@5 {
 804                                         compatible = "fsl,qoriq-mc-dpmac";
 805                                         reg = <0x5>;
 806                                         pcs-handle = <&pcs5>;
 807                                 };
 808
 809                                 dpmac6: ethernet@6 {
 810                                         compatible = "fsl,qoriq-mc-dpmac";
 811                                         reg = <0x6>;
 812                                         pcs-handle = <&pcs6>;
 813                                 };
 814
 815                                 dpmac7: ethernet@7 {
 816                                         compatible = "fsl,qoriq-mc-dpmac";
 817                                         reg = <0x7>;
 818                                         pcs-handle = <&pcs7>;
 819                                 };
 820
 821                                 dpmac8: ethernet@8 {
 822                                         compatible = "fsl,qoriq-mc-dpmac";
 823                                         reg = <0x8>;
 824                                         pcs-handle = <&pcs8>;
 825                                 };
 826
 827                                 dpmac9: ethernet@9 {
 828                                         compatible = "fsl,qoriq-mc-dpmac";
 829                                         reg = <0x9>;
 830                                         pcs-handle = <&pcs9>;
 831                                 };
 832
 833                                 dpmac10: ethernet@a {
 834                                         compatible = "fsl,qoriq-mc-dpmac";
 835                                         reg = <0xa>;
 836                                         pcs-handle = <&pcs10>;
 837                                 };
 838
 839                                 dpmac11: ethernet@b {
 840                                         compatible = "fsl,qoriq-mc-dpmac";
 841                                         reg = <0xb>;
 842                                         pcs-handle = <&pcs11>;
 843                                 };
 844
 845                                 dpmac12: ethernet@c {
 846                                         compatible = "fsl,qoriq-mc-dpmac";
 847                                         reg = <0xc>;
 848                                         pcs-handle = <&pcs12>;
 849                                 };
 850
 851                                 dpmac13: ethernet@d {
 852                                         compatible = "fsl,qoriq-mc-dpmac";
 853                                         reg = <0xd>;
 854                                         pcs-handle = <&pcs13>;
 855                                 };
 856
 857                                 dpmac14: ethernet@e {
 858                                         compatible = "fsl,qoriq-mc-dpmac";
 859                                         reg = <0xe>;
 860                                         pcs-handle = <&pcs14>;
 861                                 };
 862
 863                                 dpmac15: ethernet@f {
 864                                         compatible = "fsl,qoriq-mc-dpmac";
 865                                         reg = <0xf>;
 866                                         pcs-handle = <&pcs15>;
 867                                 };
 868
 869                                 dpmac16: ethernet@10 {
 870                                         compatible = "fsl,qoriq-mc-dpmac";
 871                                         reg = <0x10>;
 872                                         pcs-handle = <&pcs16>;
 873                                 };
 874                         };
 875                 };
 876
 877                 smmu: iommu@5000000 {
 878                         compatible = "arm,mmu-500";
 879                         reg = <0 0x5000000 0 0x800000>;
 880                         #global-interrupts = <12>;
 881                         #iommu-cells = <1>;
 882                         stream-match-mask = <0x7C00>;
 883                         dma-coherent;
 884                         interrupts = <0 13 4>, /* global secure fault */
 885                                      <0 14 4>, /* combined secure interrupt */
 886                                      <0 15 4>, /* global non-secure fault */
 887                                      <0 16 4>, /* combined non-secure interrupt */
 888                                 /* performance counter interrupts 0-7 */
 889                                      <0 211 4>, <0 212 4>,
 890                                      <0 213 4>, <0 214 4>,
 891                                      <0 215 4>, <0 216 4>,
 892                                      <0 217 4>, <0 218 4>,
 893                                 /* per context interrupt, 64 interrupts */
 894                                      <0 146 4>, <0 147 4>,
 895                                      <0 148 4>, <0 149 4>,
 896                                      <0 150 4>, <0 151 4>,
 897                                      <0 152 4>, <0 153 4>,
 898                                      <0 154 4>, <0 155 4>,
 899                                      <0 156 4>, <0 157 4>,
 900                                      <0 158 4>, <0 159 4>,
 901                                      <0 160 4>, <0 161 4>,
 902                                      <0 162 4>, <0 163 4>,
 903                                      <0 164 4>, <0 165 4>,
 904                                      <0 166 4>, <0 167 4>,
 905                                      <0 168 4>, <0 169 4>,
 906                                      <0 170 4>, <0 171 4>,
 907                                      <0 172 4>, <0 173 4>,
 908                                      <0 174 4>, <0 175 4>,
 909                                      <0 176 4>, <0 177 4>,
 910                                      <0 178 4>, <0 179 4>,
 911                                      <0 180 4>, <0 181 4>,
 912                                      <0 182 4>, <0 183 4>,
 913                                      <0 184 4>, <0 185 4>,
 914                                      <0 186 4>, <0 187 4>,
 915                                      <0 188 4>, <0 189 4>,
 916                                      <0 190 4>, <0 191 4>,
 917                                      <0 192 4>, <0 193 4>,
 918                                      <0 194 4>, <0 195 4>,
 919                                      <0 196 4>, <0 197 4>,
 920                                      <0 198 4>, <0 199 4>,
 921                                      <0 200 4>, <0 201 4>,
 922                                      <0 202 4>, <0 203 4>,
 923                                      <0 204 4>, <0 205 4>,
 924                                      <0 206 4>, <0 207 4>,
 925                                      <0 208 4>, <0 209 4>;
 926                 };
 927
 928                 dspi: spi@2100000 {
 929                         status = "disabled";
 930                         compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
 931                         #address-cells = <1>;
 932                         #size-cells = <0>;
 933                         reg = <0x0 0x2100000 0x0 0x10000>;
 934                         interrupts = <0 26 0x4>; /* Level high type */
 935                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 936                                             QORIQ_CLK_PLL_DIV(4)>;
 937                         clock-names = "dspi";
 938                         spi-num-chipselects = <5>;
 939                 };
 940
 941                 esdhc: esdhc@2140000 {
 942                         status = "disabled";
 943                         compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
 944                         reg = <0x0 0x2140000 0x0 0x10000>;
 945                         interrupts = <0 28 0x4>; /* Level high type */
 946                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
 947                                             QORIQ_CLK_PLL_DIV(2)>;
 948                         voltage-ranges = <1800 1800 3300 3300>;
 949                         sdhci,auto-cmd12;
 950                         little-endian;
 951                         bus-width = <4>;
 952                 };
 953
 954                 gpio0: gpio@2300000 {
 955                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 956                         reg = <0x0 0x2300000 0x0 0x10000>;
 957                         interrupts = <0 36 0x4>; /* Level high type */
 958                         gpio-controller;
 959                         little-endian;
 960                         #gpio-cells = <2>;
 961                         interrupt-controller;
 962                         #interrupt-cells = <2>;
 963                 };
 964
 965                 gpio1: gpio@2310000 {
 966                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 967                         reg = <0x0 0x2310000 0x0 0x10000>;
 968                         interrupts = <0 36 0x4>; /* Level high type */
 969                         gpio-controller;
 970                         little-endian;
 971                         #gpio-cells = <2>;
 972                         interrupt-controller;
 973                         #interrupt-cells = <2>;
 974                 };
 975
 976                 gpio2: gpio@2320000 {
 977                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 978                         reg = <0x0 0x2320000 0x0 0x10000>;
 979                         interrupts = <0 37 0x4>; /* Level high type */
 980                         gpio-controller;
 981                         little-endian;
 982                         #gpio-cells = <2>;
 983                         interrupt-controller;
 984                         #interrupt-cells = <2>;
 985                 };
 986
 987                 gpio3: gpio@2330000 {
 988                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 989                         reg = <0x0 0x2330000 0x0 0x10000>;
 990                         interrupts = <0 37 0x4>; /* Level high type */
 991                         gpio-controller;
 992                         little-endian;
 993                         #gpio-cells = <2>;
 994                         interrupt-controller;
 995                         #interrupt-cells = <2>;
 996                 };
 997
 998                 i2c0: i2c@2000000 {
 999                         status = "disabled";
1000                         compatible = "fsl,vf610-i2c";
1001                         #address-cells = <1>;
1002                         #size-cells = <0>;
1003                         reg = <0x0 0x2000000 0x0 0x10000>;
1004                         interrupts = <0 34 0x4>; /* Level high type */
1005                         clock-names = "i2c";
1006                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1007                                             QORIQ_CLK_PLL_DIV(4)>;
1008                 };
1009
1010                 i2c1: i2c@2010000 {
1011                         status = "disabled";
1012                         compatible = "fsl,vf610-i2c";
1013                         #address-cells = <1>;
1014                         #size-cells = <0>;
1015                         reg = <0x0 0x2010000 0x0 0x10000>;
1016                         interrupts = <0 34 0x4>; /* Level high type */
1017                         clock-names = "i2c";
1018                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1019                                             QORIQ_CLK_PLL_DIV(4)>;
1020                 };
1021
1022                 i2c2: i2c@2020000 {
1023                         status = "disabled";
1024                         compatible = "fsl,vf610-i2c";
1025                         #address-cells = <1>;
1026                         #size-cells = <0>;
1027                         reg = <0x0 0x2020000 0x0 0x10000>;
1028                         interrupts = <0 35 0x4>; /* Level high type */
1029                         clock-names = "i2c";
1030                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1031                                             QORIQ_CLK_PLL_DIV(4)>;
1032                 };
1033
1034                 i2c3: i2c@2030000 {
1035                         status = "disabled";
1036                         compatible = "fsl,vf610-i2c";
1037                         #address-cells = <1>;
1038                         #size-cells = <0>;
1039                         reg = <0x0 0x2030000 0x0 0x10000>;
1040                         interrupts = <0 35 0x4>; /* Level high type */
1041                         clock-names = "i2c";
1042                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1043                                             QORIQ_CLK_PLL_DIV(4)>;
1044                 };
1045
1046                 ifc: memory-controller@2240000 {
1047                         compatible = "fsl,ifc";
1048                         reg = <0x0 0x2240000 0x0 0x20000>;
1049                         interrupts = <0 21 0x4>; /* Level high type */
1050                         little-endian;
1051                         #address-cells = <2>;
1052                         #size-cells = <1>;
1053
1054                         ranges = <0 0 0x5 0x80000000 0x08000000
1055                                   2 0 0x5 0x30000000 0x00010000
1056                                   3 0 0x5 0x20000000 0x00010000>;
1057                 };
1058
1059                 qspi: spi@20c0000 {
1060                         compatible = "fsl,ls2080a-qspi";
1061                         #address-cells = <1>;
1062                         #size-cells = <0>;
1063                         reg = <0x0 0x20c0000 0x0 0x10000>,
1064                               <0x0 0x20000000 0x0 0x10000000>;
1065                         reg-names = "QuadSPI", "QuadSPI-memory";
1066                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1067                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1068                                             QORIQ_CLK_PLL_DIV(4)>,
1069                                  <&clockgen QORIQ_CLK_PLATFORM_PLL
1070                                             QORIQ_CLK_PLL_DIV(4)>;
1071                         clock-names = "qspi_en", "qspi";
1072                         status = "disabled";
1073                 };
1074
1075                 pcie1: pcie@3400000 {
1076                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1077                         reg-names = "regs", "config";
1078                         interrupts = <0 108 0x4>; /* Level high type */
1079                         interrupt-names = "intr";
1080                         #address-cells = <3>;
1081                         #size-cells = <2>;
1082                         device_type = "pci";
1083                         dma-coherent;
1084                         num-viewport = <6>;
1085                         bus-range = <0x0 0xff>;
1086                         msi-parent = <&its>;
1087                         #interrupt-cells = <1>;
1088                         interrupt-map-mask = <0 0 0 7>;
1089                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1090                                         <0000 0 0 2 &gic 0 0 0 110 4>,
1091                                         <0000 0 0 3 &gic 0 0 0 111 4>,
1092                                         <0000 0 0 4 &gic 0 0 0 112 4>;
1093                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1094                         status = "disabled";
1095                 };
1096
1097                 pcie2: pcie@3500000 {
1098                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1099                         reg-names = "regs", "config";
1100                         interrupts = <0 113 0x4>; /* Level high type */
1101                         interrupt-names = "intr";
1102                         #address-cells = <3>;
1103                         #size-cells = <2>;
1104                         device_type = "pci";
1105                         dma-coherent;
1106                         num-viewport = <6>;
1107                         bus-range = <0x0 0xff>;
1108                         msi-parent = <&its>;
1109                         #interrupt-cells = <1>;
1110                         interrupt-map-mask = <0 0 0 7>;
1111                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1112                                         <0000 0 0 2 &gic 0 0 0 115 4>,
1113                                         <0000 0 0 3 &gic 0 0 0 116 4>,
1114                                         <0000 0 0 4 &gic 0 0 0 117 4>;
1115                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1116                         status = "disabled";
1117                 };
1118
1119                 pcie3: pcie@3600000 {
1120                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1121                         reg-names = "regs", "config";
1122                         interrupts = <0 118 0x4>; /* Level high type */
1123                         interrupt-names = "intr";
1124                         #address-cells = <3>;
1125                         #size-cells = <2>;
1126                         device_type = "pci";
1127                         dma-coherent;
1128                         num-viewport = <256>;
1129                         bus-range = <0x0 0xff>;
1130                         msi-parent = <&its>;
1131                         #interrupt-cells = <1>;
1132                         interrupt-map-mask = <0 0 0 7>;
1133                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1134                                         <0000 0 0 2 &gic 0 0 0 120 4>,
1135                                         <0000 0 0 3 &gic 0 0 0 121 4>,
1136                                         <0000 0 0 4 &gic 0 0 0 122 4>;
1137                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1138                         status = "disabled";
1139                 };
1140
1141                 pcie4: pcie@3700000 {
1142                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1143                         reg-names = "regs", "config";
1144                         interrupts = <0 123 0x4>; /* Level high type */
1145                         interrupt-names = "intr";
1146                         #address-cells = <3>;
1147                         #size-cells = <2>;
1148                         device_type = "pci";
1149                         dma-coherent;
1150                         num-viewport = <6>;
1151                         bus-range = <0x0 0xff>;
1152                         msi-parent = <&its>;
1153                         #interrupt-cells = <1>;
1154                         interrupt-map-mask = <0 0 0 7>;
1155                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1156                                         <0000 0 0 2 &gic 0 0 0 125 4>,
1157                                         <0000 0 0 3 &gic 0 0 0 126 4>,
1158                                         <0000 0 0 4 &gic 0 0 0 127 4>;
1159                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1160                         status = "disabled";
1161                 };
1162
1163                 sata0: sata@3200000 {
1164                         status = "disabled";
1165                         compatible = "fsl,ls2080a-ahci";
1166                         reg = <0x0 0x3200000 0x0 0x10000>;
1167                         interrupts = <0 133 0x4>; /* Level high type */
1168                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1169                                             QORIQ_CLK_PLL_DIV(4)>;
1170                         dma-coherent;
1171                 };
1172
1173                 sata1: sata@3210000 {
1174                         status = "disabled";
1175                         compatible = "fsl,ls2080a-ahci";
1176                         reg = <0x0 0x3210000 0x0 0x10000>;
1177                         interrupts = <0 136 0x4>; /* Level high type */
1178                         clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1179                                             QORIQ_CLK_PLL_DIV(4)>;
1180                         dma-coherent;
1181                 };
1182
1183                 usb0: usb@3100000 {
1184                         status = "disabled";
1185                         compatible = "snps,dwc3";
1186                         reg = <0x0 0x3100000 0x0 0x10000>;
1187                         interrupts = <0 80 0x4>; /* Level high type */
1188                         dr_mode = "host";
1189                         snps,quirk-frame-length-adjustment = <0x20>;
1190                         snps,dis_rxdet_inp3_quirk;
1191                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1192                 };
1193
1194                 usb1: usb@3110000 {
1195                         status = "disabled";
1196                         compatible = "snps,dwc3";
1197                         reg = <0x0 0x3110000 0x0 0x10000>;
1198                         interrupts = <0 81 0x4>; /* Level high type */
1199                         dr_mode = "host";
1200                         snps,quirk-frame-length-adjustment = <0x20>;
1201                         snps,dis_rxdet_inp3_quirk;
1202                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1203                 };
1204
1205                 ccn@4000000 {
1206                         compatible = "arm,ccn-504";
1207                         reg = <0x0 0x04000000 0x0 0x01000000>;
1208                         interrupts = <0 12 4>;
1209                 };
1210
1211                 rcpm: power-controller@1e34040 {
1212                         compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1213                         reg = <0x0 0x1e34040 0x0 0x18>;
1214                         #fsl,rcpm-wakeup-cells = <6>;
1215                         little-endian;
1216                 };
1217
1218                 ftm_alarm0: timer@2800000 {
1219                         compatible = "fsl,ls208xa-ftm-alarm";
1220                         reg = <0x0 0x2800000 0x0 0x10000>;
1221                         fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1222                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1223                 };
1224         };
1225
1226         ddr1: memory-controller@1080000 {
1227                 compatible = "fsl,qoriq-memory-controller";
1228                 reg = <0x0 0x1080000 0x0 0x1000>;
1229                 interrupts = <0 17 0x4>;
1230                 little-endian;
1231         };
1232
1233         ddr2: memory-controller@1090000 {
1234                 compatible = "fsl,qoriq-memory-controller";
1235                 reg = <0x0 0x1090000 0x0 0x1000>;
1236                 interrupts = <0 18 0x4>;
1237                 little-endian;
1238         };
1239
1240         firmware {
1241                 optee {
1242                         compatible = "linaro,optee-tz";
1243                         method = "smc";
1244                 };
1245         };
1246 };