arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Freescale LS2080A QDS Board.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  * Copyright 2017 NXP
   7  *
   8  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
   9  *
  10  */
  11
  12 /* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
  13 &dpmac9 {
  14         phy-handle = <&mdio0_phy12>;
  15         phy-connection-type = "sgmii";
  16 };
  17
  18 &dpmac10 {
  19         phy-handle = <&mdio0_phy13>;
  20         phy-connection-type = "sgmii";
  21 };
  22
  23 &dpmac11 {
  24         phy-handle = <&mdio0_phy14>;
  25         phy-connection-type = "sgmii";
  26 };
  27
  28 &dpmac12 {
  29         phy-handle = <&mdio0_phy15>;
  30         phy-connection-type = "sgmii";
  31 };
  32
  33 &esdhc {
  34         mmc-hs200-1_8v;
  35         status = "okay";
  36 };
  37
  38 &ifc {
  39         status = "okay";
  40         #address-cells = <2>;
  41         #size-cells = <1>;
  42         ranges = <0x0 0x0 0x5 0x80000000 0x08000000
  43                   0x2 0x0 0x5 0x30000000 0x00010000
  44                   0x3 0x0 0x5 0x20000000 0x00010000>;
  45
  46         nor@0,0 {
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 compatible = "cfi-flash";
  50                 reg = <0x0 0x0 0x8000000>;
  51                 bank-width = <2>;
  52                 device-width = <1>;
  53         };
  54
  55         nand@2,0 {
  56              compatible = "fsl,ifc-nand";
  57              reg = <0x2 0x0 0x10000>;
  58         };
  59
  60         boardctrl: board-control@3,0 {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 compatible = "fsl,ls208xaqds-fpga", "fsl,fpga-qixis", "simple-mfd";
  64                 reg = <3 0 0x1000>;
  65                 ranges = <0 3 0 0x1000>;
  66
  67                 mdio-mux-emi1@54 {
  68                         compatible = "mdio-mux-mmioreg", "mdio-mux";
  69                         mdio-parent-bus = <&emdio1>;
  70                         reg = <0x54 1>;         /* BRDCFG4 */
  71                         mux-mask = <0xe0>;      /* EMI1_MDIO */
  72                         #address-cells=<1>;
  73                         #size-cells = <0>;
  74
  75                         /* Child MDIO buses, one for each riser card:
  76                          * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
  77                          * VSC8234 PHYs on the riser cards.
  78                          */
  79                         mdio_mux3: mdio@60 {
  80                                 reg = <0x60>;
  81                                 #address-cells = <1>;
  82                                 #size-cells = <0>;
  83
  84                                 mdio0_phy12: mdio-phy0@1c {
  85                                         reg = <0x1c>;
  86                                 };
  87
  88                                 mdio0_phy13: mdio-phy1@1d {
  89                                         reg = <0x1d>;
  90                                 };
  91
  92                                 mdio0_phy14: mdio-phy2@1e {
  93                                         reg = <0x1e>;
  94                                 };
  95
  96                                 mdio0_phy15: mdio-phy3@1f {
  97                                         reg = <0x1f>;
  98                                 };
  99                         };
 100                 };
 101         };
 102 };
 103
 104 &i2c0 {
 105         status = "okay";
 106         pca9547@77 {
 107                 compatible = "nxp,pca9547";
 108                 reg = <0x77>;
 109                 #address-cells = <1>;
 110                 #size-cells = <0>;
 111                 i2c@0 {
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         reg = <0x00>;
 115                         rtc@68 {
 116                                 compatible = "dallas,ds3232";
 117                                 reg = <0x68>;
 118                         };
 119                 };
 120
 121                 i2c@2 {
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                         reg = <0x02>;
 125
 126                         ina220@40 {
 127                                 compatible = "ti,ina220";
 128                                 reg = <0x40>;
 129                                 shunt-resistor = <500>;
 130                         };
 131
 132                         ina220@41 {
 133                                 compatible = "ti,ina220";
 134                                 reg = <0x41>;
 135                                 shunt-resistor = <1000>;
 136                         };
 137                 };
 138
 139                 i2c@3 {
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         reg = <0x3>;
 143
 144                         adt7481@4c {
 145                                 compatible = "adi,adt7461";
 146                                 reg = <0x4c>;
 147                         };
 148                 };
 149         };
 150 };
 151
 152 &i2c1 {
 153         status = "disabled";
 154 };
 155
 156 &i2c2 {
 157         status = "disabled";
 158 };
 159
 160 &i2c3 {
 161         status = "disabled";
 162 };
 163
 164 &dspi {
 165         status = "okay";
 166         dflash0: flash@0 {
 167                 #address-cells = <1>;
 168                 #size-cells = <1>;
 169                 compatible = "st,m25p80";
 170                 spi-max-frequency = <3000000>;
 171                 reg = <0>;
 172         };
 173         dflash1: flash@1 {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 compatible = "st,m25p80";
 177                 spi-max-frequency = <3000000>;
 178                 reg = <1>;
 179         };
 180         dflash2: flash@2 {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 compatible = "st,m25p80";
 184                 spi-max-frequency = <3000000>;
 185                 reg = <2>;
 186         };
 187 };
 188
 189 &qspi {
 190         status = "okay";
 191         flash0: flash@0 {
 192                 #address-cells = <1>;
 193                 #size-cells = <1>;
 194                 compatible = "st,m25p80";
 195                 spi-max-frequency = <20000000>;
 196                 spi-rx-bus-width = <4>;
 197                 spi-tx-bus-width = <4>;
 198                 reg = <0>;
 199         };
 200         flash2: flash@2 {
 201                 #address-cells = <1>;
 202                 #size-cells = <1>;
 203                 compatible = "st,m25p80";
 204                 spi-max-frequency = <20000000>;
 205                 spi-rx-bus-width = <4>;
 206                 spi-tx-bus-width = <4>;
 207                 reg = <2>;
 208         };
 209 };
 210
 211 &sata0 {
 212         status = "okay";
 213 };
 214
 215 &sata1 {
 216         status = "okay";
 217 };
 218
 219 &usb0 {
 220         status = "okay";
 221 };
 222
 223 &usb1 {
 224         status = "okay";
 225 };