arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for Travese Ten64 (LS1088) board
   4  * Based on fsl-ls1088a-rdb.dts
   5  * Copyright 2017-2020 NXP
   6  * Copyright 2019-2021 Traverse Technologies
   7  *
   8  * Author: Mathew McBride <matt@traverse.com.au>
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "fsl-ls1088a.dtsi"
  14
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17
  18 / {
  19         model = "Traverse Ten64";
  20         compatible = "traverse,ten64", "fsl,ls1088a";
  21
  22         aliases {
  23                 serial0 = &duart0;
  24                 serial1 = &duart1;
  25         };
  26
  27         chosen {
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         buttons {
  32                 compatible = "gpio-keys";
  33
  34                 /* Fired by system controller when
  35                  * external power off (e.g ATX Power Button)
  36                  * asserted
  37                  */
  38                 button-powerdn {
  39                         label = "External Power Down";
  40                         gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
  41                         linux,code = <KEY_POWER>;
  42                 };
  43
  44                 /* Rear Panel 'ADMIN' button (GPIO_H) */
  45                 button-admin {
  46                         label = "ADMIN button";
  47                         gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
  48                         linux,code = <KEY_WPS_BUTTON>;
  49                 };
  50         };
  51
  52         leds {
  53                 compatible = "gpio-leds";
  54
  55                 led-0 {
  56                         label = "ten64:green:sfp1:down";
  57                         gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>;
  58                 };
  59
  60                 led-1 {
  61                         label = "ten64:green:sfp2:up";
  62                         gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
  63                 };
  64
  65                 led-2 {
  66                         label = "ten64:admin";
  67                         gpios = <&sfpgpio 12 GPIO_ACTIVE_HIGH>;
  68                 };
  69         };
  70
  71         sfp_xg0: dpmac2-sfp {
  72                 compatible = "sff,sfp";
  73                 i2c-bus = <&sfplower_i2c>;
  74                 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
  75                 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
  76                 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
  77                 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
  78                 maximum-power-milliwatt = <2000>;
  79         };
  80
  81         sfp_xg1: dpmac1-sfp {
  82                 compatible = "sff,sfp";
  83                 i2c-bus = <&sfpupper_i2c>;
  84                 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
  85                 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
  86                 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
  87                 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
  88                 maximum-power-milliwatt = <2000>;
  89         };
  90 };
  91
  92 /* XG1 - Upper SFP */
  93 &dpmac1 {
  94         sfp = <&sfp_xg1>;
  95         pcs-handle = <&pcs1>;
  96         phy-connection-type = "10gbase-r";
  97         managed = "in-band-status";
  98 };
  99
 100 /* XG0 - Lower SFP */
 101 &dpmac2 {
 102         sfp = <&sfp_xg0>;
 103         pcs-handle = <&pcs2>;
 104         phy-connection-type = "10gbase-r";
 105         managed = "in-band-status";
 106 };
 107
 108 /* DPMAC3..6 is GE4 to GE8 */
 109 &dpmac3 {
 110         phy-handle = <&mdio1_phy5>;
 111         phy-connection-type = "qsgmii";
 112         managed = "in-band-status";
 113         pcs-handle = <&pcs3_0>;
 114 };
 115
 116 &dpmac4 {
 117         phy-handle = <&mdio1_phy6>;
 118         phy-connection-type = "qsgmii";
 119         managed = "in-band-status";
 120         pcs-handle = <&pcs3_1>;
 121 };
 122
 123 &dpmac5 {
 124         phy-handle = <&mdio1_phy7>;
 125         phy-connection-type = "qsgmii";
 126         managed = "in-band-status";
 127         pcs-handle = <&pcs3_2>;
 128 };
 129
 130 &dpmac6 {
 131         phy-handle = <&mdio1_phy8>;
 132         phy-connection-type = "qsgmii";
 133         managed = "in-band-status";
 134         pcs-handle = <&pcs3_3>;
 135 };
 136
 137 /* DPMAC7..10 is GE0 to GE3 */
 138 &dpmac7 {
 139         phy-handle = <&mdio1_phy1>;
 140         phy-connection-type = "qsgmii";
 141         managed = "in-band-status";
 142         pcs-handle = <&pcs7_0>;
 143 };
 144
 145 &dpmac8 {
 146         phy-handle = <&mdio1_phy2>;
 147         phy-connection-type = "qsgmii";
 148         managed = "in-band-status";
 149         pcs-handle = <&pcs7_1>;
 150 };
 151
 152 &dpmac9 {
 153         phy-handle = <&mdio1_phy3>;
 154         phy-connection-type = "qsgmii";
 155         managed = "in-band-status";
 156         pcs-handle = <&pcs7_2>;
 157 };
 158
 159 &dpmac10 {
 160         phy-handle = <&mdio1_phy4>;
 161         phy-connection-type = "qsgmii";
 162         managed = "in-band-status";
 163         pcs-handle = <&pcs7_3>;
 164 };
 165
 166 &duart0 {
 167         status = "okay";
 168 };
 169
 170 &duart1 {
 171         status = "okay";
 172 };
 173
 174 &emdio1 {
 175         status = "okay";
 176
 177         mdio1_phy5: ethernet-phy@c {
 178                 reg = <0xc>;
 179         };
 180
 181         mdio1_phy6: ethernet-phy@d {
 182                 reg = <0xd>;
 183         };
 184
 185         mdio1_phy7: ethernet-phy@e {
 186                 reg = <0xe>;
 187         };
 188
 189         mdio1_phy8: ethernet-phy@f {
 190                 reg = <0xf>;
 191         };
 192
 193         mdio1_phy1: ethernet-phy@1c {
 194                 reg = <0x1c>;
 195         };
 196
 197         mdio1_phy2: ethernet-phy@1d {
 198                 reg = <0x1d>;
 199         };
 200
 201         mdio1_phy3: ethernet-phy@1e {
 202                 reg = <0x1e>;
 203         };
 204
 205         mdio1_phy4: ethernet-phy@1f {
 206                 reg = <0x1f>;
 207         };
 208 };
 209
 210 &esdhc {
 211         status = "okay";
 212 };
 213
 214 &i2c0 {
 215         status = "okay";
 216
 217         sfpgpio: gpio@76 {
 218                 compatible = "ti,tca9539";
 219                 reg = <0x76>;
 220                 #gpio-cells = <2>;
 221                 gpio-controller;
 222
 223                 admin_led_lower {
 224                         gpio-hog;
 225                         gpios = <13 GPIO_ACTIVE_HIGH>;
 226                         output-low;
 227                 };
 228         };
 229
 230         at97sc: tpm@29 {
 231                 compatible = "atmel,at97sc3204t";
 232                 reg = <0x29>;
 233         };
 234 };
 235
 236 &i2c2 {
 237         status = "okay";
 238
 239         rx8035: rtc@32 {
 240                 compatible = "epson,rx8035";
 241                 reg = <0x32>;
 242         };
 243 };
 244
 245 &i2c3 {
 246         status = "okay";
 247
 248         i2c-switch@70 {
 249                 compatible = "nxp,pca9540";
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 reg = <0x70>;
 253
 254                 sfpupper_i2c: i2c@0 {
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         reg = <0>;
 258                 };
 259
 260                 sfplower_i2c: i2c@1 {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         reg = <1>;
 264                 };
 265         };
 266 };
 267
 268 &pcs_mdio1 {
 269         status = "okay";
 270 };
 271
 272 &pcs_mdio2 {
 273         status = "okay";
 274 };
 275
 276 &pcs_mdio3 {
 277         status = "okay";
 278 };
 279
 280 &pcs_mdio7 {
 281         status = "okay";
 282 };
 283
 284 &qspi {
 285         status = "okay";
 286
 287         en25s64: flash@0 {
 288                 compatible = "jedec,spi-nor";
 289                 #address-cells = <1>;
 290                 #size-cells = <1>;
 291                 reg = <0>;
 292                 spi-max-frequency = <20000000>;
 293                 spi-rx-bus-width = <4>;
 294                 spi-tx-bus-width = <4>;
 295
 296                 partitions {
 297                         compatible = "fixed-partitions";
 298                         #address-cells = <1>;
 299                         #size-cells = <1>;
 300
 301                         partition@0 {
 302                                 label = "bl2";
 303                                 reg = <0 0x100000>;
 304                         };
 305
 306                         partition@100000 {
 307                                 label = "bl3";
 308                                 reg = <0x100000 0x200000>;
 309                         };
 310
 311                         partition@300000 {
 312                                 label = "mcfirmware";
 313                                 reg = <0x300000 0x200000>;
 314                         };
 315
 316                         partition@500000 {
 317                                 label = "ubootenv";
 318                                 reg = <0x500000 0x80000>;
 319                         };
 320
 321                         partition@580000 {
 322                                 label = "dpl";
 323                                 reg = <0x580000 0x40000>;
 324                         };
 325
 326                         partition@5C0000 {
 327                                 label = "dpc";
 328                                 reg = <0x5C0000 0x40000>;
 329                         };
 330
 331                         partition@600000 {
 332                                 label = "devicetree";
 333                                 reg = <0x600000 0x40000>;
 334                         };
 335                 };
 336         };
 337
 338         nand: flash@1 {
 339                 compatible = "spi-nand";
 340                 #address-cells = <1>;
 341                 #size-cells = <1>;
 342                 reg = <1>;
 343                 spi-max-frequency = <20000000>;
 344                 spi-rx-bus-width = <4>;
 345                 spi-tx-bus-width = <4>;
 346
 347                 partitions {
 348                         compatible = "fixed-partitions";
 349                         #address-cells = <1>;
 350                         #size-cells = <1>;
 351
 352                         /* reserved for future boot direct from NAND flash
 353                          * (this would use the same layout as the 8MiB NOR flash)
 354                          */
 355                         partition@0 {
 356                                 label = "nand-boot-reserved";
 357                                 reg = <0 0x800000>;
 358                         };
 359
 360                         /* recovery / install environment */
 361                         partition@800000 {
 362                                 label = "recovery";
 363                                 reg = <0x800000 0x2000000>;
 364                         };
 365
 366                         /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
 367                         partition@2800000 {
 368                                 label = "ubia";
 369                                 reg = <0x2800000 0x6C00000>;
 370                         };
 371
 372                         /* ubib (second OpenWrt) */
 373                         partition@9400000 {
 374                                 label = "ubib";
 375                                 reg = <0x9400000 0x6C00000>;
 376                         };
 377                 };
 378         };
 379 };
 380
 381 &usb0 {
 382         status = "okay";
 383 };
 384
 385 &usb1 {
 386         status = "okay";
 387 };