arch/arm64/boot/dts/exynos/exynos5433.dtsi

   1 /*
   2  * Samsung's Exynos5433 SoC device tree source
   3  *
   4  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   5  *
   6  * Samsung's Exynos5433 SoC device nodes are listed in this file.
   7  * Exynos5433 based board files can include this file and provide
   8  * values for board specific bindings.
   9  *
  10  * Note: This file does not include device nodes for all the controllers in
  11  * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  12  * additional nodes can be added to this file.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <dt-bindings/clock/exynos5433.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21
  22 / {
  23         compatible = "samsung,exynos5433";
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         interrupt-parent = <&gic>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@100 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         enable-method = "psci";
  37                         reg = <0x100>;
  38                         clock-frequency = <1300000000>;
  39                         clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  40                         clock-names = "apolloclk";
  41                         operating-points-v2 = <&cluster_a53_opp_table>;
  42                         #cooling-cells = <2>;
  43                 };
  44
  45                 cpu1: cpu@101 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         enable-method = "psci";
  49                         reg = <0x101>;
  50                         clock-frequency = <1300000000>;
  51                         operating-points-v2 = <&cluster_a53_opp_table>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu2: cpu@102 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53", "arm,armv8";
  58                         enable-method = "psci";
  59                         reg = <0x102>;
  60                         clock-frequency = <1300000000>;
  61                         operating-points-v2 = <&cluster_a53_opp_table>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu3: cpu@103 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         enable-method = "psci";
  69                         reg = <0x103>;
  70                         clock-frequency = <1300000000>;
  71                         operating-points-v2 = <&cluster_a53_opp_table>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu4: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a57", "arm,armv8";
  78                         enable-method = "psci";
  79                         reg = <0x0>;
  80                         clock-frequency = <1900000000>;
  81                         clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
  82                         clock-names = "atlasclk";
  83                         operating-points-v2 = <&cluster_a57_opp_table>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 cpu5: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a57", "arm,armv8";
  90                         enable-method = "psci";
  91                         reg = <0x1>;
  92                         clock-frequency = <1900000000>;
  93                         operating-points-v2 = <&cluster_a57_opp_table>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu6: cpu@2 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a57", "arm,armv8";
 100                         enable-method = "psci";
 101                         reg = <0x2>;
 102                         clock-frequency = <1900000000>;
 103                         operating-points-v2 = <&cluster_a57_opp_table>;
 104                         #cooling-cells = <2>;
 105                 };
 106
 107                 cpu7: cpu@3 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a57", "arm,armv8";
 110                         enable-method = "psci";
 111                         reg = <0x3>;
 112                         clock-frequency = <1900000000>;
 113                         operating-points-v2 = <&cluster_a57_opp_table>;
 114                         #cooling-cells = <2>;
 115                 };
 116         };
 117
 118         cluster_a53_opp_table: opp_table0 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp@400000000 {
 123                         opp-hz = /bits/ 64 <400000000>;
 124                         opp-microvolt = <900000>;
 125                 };
 126                 opp@500000000 {
 127                         opp-hz = /bits/ 64 <500000000>;
 128                         opp-microvolt = <925000>;
 129                 };
 130                 opp@600000000 {
 131                         opp-hz = /bits/ 64 <600000000>;
 132                         opp-microvolt = <950000>;
 133                 };
 134                 opp@700000000 {
 135                         opp-hz = /bits/ 64 <700000000>;
 136                         opp-microvolt = <975000>;
 137                 };
 138                 opp@800000000 {
 139                         opp-hz = /bits/ 64 <800000000>;
 140                         opp-microvolt = <1000000>;
 141                 };
 142                 opp@900000000 {
 143                         opp-hz = /bits/ 64 <900000000>;
 144                         opp-microvolt = <1050000>;
 145                 };
 146                 opp@1000000000 {
 147                         opp-hz = /bits/ 64 <1000000000>;
 148                         opp-microvolt = <1075000>;
 149                 };
 150                 opp@1100000000 {
 151                         opp-hz = /bits/ 64 <1100000000>;
 152                         opp-microvolt = <1112500>;
 153                 };
 154                 opp@1200000000 {
 155                         opp-hz = /bits/ 64 <1200000000>;
 156                         opp-microvolt = <1112500>;
 157                 };
 158                 opp@1300000000 {
 159                         opp-hz = /bits/ 64 <1300000000>;
 160                         opp-microvolt = <1150000>;
 161                 };
 162         };
 163
 164         cluster_a57_opp_table: opp_table1 {
 165                 compatible = "operating-points-v2";
 166                 opp-shared;
 167
 168                 opp@500000000 {
 169                         opp-hz = /bits/ 64 <500000000>;
 170                         opp-microvolt = <900000>;
 171                 };
 172                 opp@600000000 {
 173                         opp-hz = /bits/ 64 <600000000>;
 174                         opp-microvolt = <900000>;
 175                 };
 176                 opp@700000000 {
 177                         opp-hz = /bits/ 64 <700000000>;
 178                         opp-microvolt = <912500>;
 179                 };
 180                 opp@800000000 {
 181                         opp-hz = /bits/ 64 <800000000>;
 182                         opp-microvolt = <912500>;
 183                 };
 184                 opp@900000000 {
 185                         opp-hz = /bits/ 64 <900000000>;
 186                         opp-microvolt = <937500>;
 187                 };
 188                 opp@1000000000 {
 189                         opp-hz = /bits/ 64 <1000000000>;
 190                         opp-microvolt = <975000>;
 191                 };
 192                 opp@1100000000 {
 193                         opp-hz = /bits/ 64 <1100000000>;
 194                         opp-microvolt = <1012500>;
 195                 };
 196                 opp@1200000000 {
 197                         opp-hz = /bits/ 64 <1200000000>;
 198                         opp-microvolt = <1037500>;
 199                 };
 200                 opp@1300000000 {
 201                         opp-hz = /bits/ 64 <1300000000>;
 202                         opp-microvolt = <1062500>;
 203                 };
 204                 opp@1400000000 {
 205                         opp-hz = /bits/ 64 <1400000000>;
 206                         opp-microvolt = <1087500>;
 207                 };
 208                 opp@1500000000 {
 209                         opp-hz = /bits/ 64 <1500000000>;
 210                         opp-microvolt = <1125000>;
 211                 };
 212                 opp@1600000000 {
 213                         opp-hz = /bits/ 64 <1600000000>;
 214                         opp-microvolt = <1137500>;
 215                 };
 216                 opp@1700000000 {
 217                         opp-hz = /bits/ 64 <1700000000>;
 218                         opp-microvolt = <1175000>;
 219                 };
 220                 opp@1800000000 {
 221                         opp-hz = /bits/ 64 <1800000000>;
 222                         opp-microvolt = <1212500>;
 223                 };
 224                 opp@1900000000 {
 225                         opp-hz = /bits/ 64 <1900000000>;
 226                         opp-microvolt = <1262500>;
 227                 };
 228         };
 229
 230         psci {
 231                 compatible = "arm,psci";
 232                 method = "smc";
 233                 cpu_off = <0x84000002>;
 234                 cpu_on = <0xC4000003>;
 235         };
 236
 237         reboot: syscon-reboot {
 238                 compatible = "syscon-reboot";
 239                 regmap = <&pmu_system_controller>;
 240                 offset = <0x400>; /* SWRESET */
 241                 mask = <0x1>;
 242         };
 243
 244         soc: soc {
 245                 compatible = "simple-bus";
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges = <0x0 0x0 0x0 0x18000000>;
 249
 250                 chipid@10000000 {
 251                         compatible = "samsung,exynos4210-chipid";
 252                         reg = <0x10000000 0x100>;
 253                 };
 254
 255                 xxti: xxti {
 256                         compatible = "fixed-clock";
 257                         clock-output-names = "oscclk";
 258                         #clock-cells = <0>;
 259                 };
 260
 261                 cmu_top: clock-controller@10030000 {
 262                         compatible = "samsung,exynos5433-cmu-top";
 263                         reg = <0x10030000 0x1000>;
 264                         #clock-cells = <1>;
 265
 266                         clock-names = "oscclk",
 267                                 "sclk_mphy_pll",
 268                                 "sclk_mfc_pll",
 269                                 "sclk_bus_pll";
 270                         clocks = <&xxti>,
 271                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 272                                 <&cmu_mif CLK_SCLK_MFC_PLL>,
 273                                 <&cmu_mif CLK_SCLK_BUS_PLL>;
 274                 };
 275
 276                 cmu_cpif: clock-controller@10fc0000 {
 277                         compatible = "samsung,exynos5433-cmu-cpif";
 278                         reg = <0x10fc0000 0x1000>;
 279                         #clock-cells = <1>;
 280
 281                         clock-names = "oscclk";
 282                         clocks = <&xxti>;
 283                 };
 284
 285                 cmu_mif: clock-controller@105b0000 {
 286                         compatible = "samsung,exynos5433-cmu-mif";
 287                         reg = <0x105b0000 0x2000>;
 288                         #clock-cells = <1>;
 289
 290                         clock-names = "oscclk",
 291                                 "sclk_mphy_pll";
 292                         clocks = <&xxti>,
 293                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 294                 };
 295
 296                 cmu_peric: clock-controller@14c80000 {
 297                         compatible = "samsung,exynos5433-cmu-peric";
 298                         reg = <0x14c80000 0x1000>;
 299                         #clock-cells = <1>;
 300                 };
 301
 302                 cmu_peris: clock-controller@0x10040000 {
 303                         compatible = "samsung,exynos5433-cmu-peris";
 304                         reg = <0x10040000 0x1000>;
 305                         #clock-cells = <1>;
 306                 };
 307
 308                 cmu_fsys: clock-controller@156e0000 {
 309                         compatible = "samsung,exynos5433-cmu-fsys";
 310                         reg = <0x156e0000 0x1000>;
 311                         #clock-cells = <1>;
 312
 313                         clock-names = "oscclk",
 314                                 "sclk_ufs_mphy",
 315                                 "aclk_fsys_200",
 316                                 "sclk_pcie_100_fsys",
 317                                 "sclk_ufsunipro_fsys",
 318                                 "sclk_mmc2_fsys",
 319                                 "sclk_mmc1_fsys",
 320                                 "sclk_mmc0_fsys",
 321                                 "sclk_usbhost30_fsys",
 322                                 "sclk_usbdrd30_fsys";
 323                         clocks = <&xxti>,
 324                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 325                                 <&cmu_top CLK_ACLK_FSYS_200>,
 326                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 327                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 328                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
 329                                 <&cmu_top CLK_SCLK_MMC1_FSYS>,
 330                                 <&cmu_top CLK_SCLK_MMC0_FSYS>,
 331                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 332                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 333                 };
 334
 335                 cmu_g2d: clock-controller@12460000 {
 336                         compatible = "samsung,exynos5433-cmu-g2d";
 337                         reg = <0x12460000 0x1000>;
 338                         #clock-cells = <1>;
 339
 340                         clock-names = "oscclk",
 341                                 "aclk_g2d_266",
 342                                 "aclk_g2d_400";
 343                         clocks = <&xxti>,
 344                                 <&cmu_top CLK_ACLK_G2D_266>,
 345                                 <&cmu_top CLK_ACLK_G2D_400>;
 346                 };
 347
 348                 cmu_disp: clock-controller@13b90000 {
 349                         compatible = "samsung,exynos5433-cmu-disp";
 350                         reg = <0x13b90000 0x1000>;
 351                         #clock-cells = <1>;
 352
 353                         clock-names = "oscclk",
 354                                 "sclk_dsim1_disp",
 355                                 "sclk_dsim0_disp",
 356                                 "sclk_dsd_disp",
 357                                 "sclk_decon_tv_eclk_disp",
 358                                 "sclk_decon_vclk_disp",
 359                                 "sclk_decon_eclk_disp",
 360                                 "sclk_decon_tv_vclk_disp",
 361                                 "aclk_disp_333";
 362                         clocks = <&xxti>,
 363                                 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 364                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 365                                 <&cmu_mif CLK_SCLK_DSD_DISP>,
 366                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 367                                 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 368                                 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 369                                 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 370                                 <&cmu_mif CLK_ACLK_DISP_333>;
 371                 };
 372
 373                 cmu_aud: clock-controller@114c0000 {
 374                         compatible = "samsung,exynos5433-cmu-aud";
 375                         reg = <0x114c0000 0x1000>;
 376                         #clock-cells = <1>;
 377                 };
 378
 379                 cmu_bus0: clock-controller@13600000 {
 380                         compatible = "samsung,exynos5433-cmu-bus0";
 381                         reg = <0x13600000 0x1000>;
 382                         #clock-cells = <1>;
 383
 384                         clock-names = "aclk_bus0_400";
 385                         clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 386                 };
 387
 388                 cmu_bus1: clock-controller@14800000 {
 389                         compatible = "samsung,exynos5433-cmu-bus1";
 390                         reg = <0x14800000 0x1000>;
 391                         #clock-cells = <1>;
 392
 393                         clock-names = "aclk_bus1_400";
 394                         clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 395                 };
 396
 397                 cmu_bus2: clock-controller@13400000 {
 398                         compatible = "samsung,exynos5433-cmu-bus2";
 399                         reg = <0x13400000 0x1000>;
 400                         #clock-cells = <1>;
 401
 402                         clock-names = "oscclk", "aclk_bus2_400";
 403                         clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 404                 };
 405
 406                 cmu_g3d: clock-controller@14aa0000 {
 407                         compatible = "samsung,exynos5433-cmu-g3d";
 408                         reg = <0x14aa0000 0x2000>;
 409                         #clock-cells = <1>;
 410
 411                         clock-names = "oscclk", "aclk_g3d_400";
 412                         clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 413                 };
 414
 415                 cmu_gscl: clock-controller@13cf0000 {
 416                         compatible = "samsung,exynos5433-cmu-gscl";
 417                         reg = <0x13cf0000 0x1000>;
 418                         #clock-cells = <1>;
 419
 420                         clock-names = "oscclk",
 421                                 "aclk_gscl_111",
 422                                 "aclk_gscl_333";
 423                         clocks = <&xxti>,
 424                                 <&cmu_top CLK_ACLK_GSCL_111>,
 425                                 <&cmu_top CLK_ACLK_GSCL_333>;
 426                 };
 427
 428                 cmu_apollo: clock-controller@11900000 {
 429                         compatible = "samsung,exynos5433-cmu-apollo";
 430                         reg = <0x11900000 0x2000>;
 431                         #clock-cells = <1>;
 432
 433                         clock-names = "oscclk", "sclk_bus_pll_apollo";
 434                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 435                 };
 436
 437                 cmu_atlas: clock-controller@11800000 {
 438                         compatible = "samsung,exynos5433-cmu-atlas";
 439                         reg = <0x11800000 0x2000>;
 440                         #clock-cells = <1>;
 441
 442                         clock-names = "oscclk", "sclk_bus_pll_atlas";
 443                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 444                 };
 445
 446                 cmu_mscl: clock-controller@105d0000 {
 447                         compatible = "samsung,exynos5433-cmu-mscl";
 448                         reg = <0x150d0000 0x1000>;
 449                         #clock-cells = <1>;
 450
 451                         clock-names = "oscclk",
 452                                 "sclk_jpeg_mscl",
 453                                 "aclk_mscl_400";
 454                         clocks = <&xxti>,
 455                                 <&cmu_top CLK_SCLK_JPEG_MSCL>,
 456                                 <&cmu_top CLK_ACLK_MSCL_400>;
 457                 };
 458
 459                 cmu_mfc: clock-controller@15280000 {
 460                         compatible = "samsung,exynos5433-cmu-mfc";
 461                         reg = <0x15280000 0x1000>;
 462                         #clock-cells = <1>;
 463
 464                         clock-names = "oscclk", "aclk_mfc_400";
 465                         clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 466                 };
 467
 468                 cmu_hevc: clock-controller@14f80000 {
 469                         compatible = "samsung,exynos5433-cmu-hevc";
 470                         reg = <0x14f80000 0x1000>;
 471                         #clock-cells = <1>;
 472
 473                         clock-names = "oscclk", "aclk_hevc_400";
 474                         clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 475                 };
 476
 477                 cmu_isp: clock-controller@146d0000 {
 478                         compatible = "samsung,exynos5433-cmu-isp";
 479                         reg = <0x146d0000 0x1000>;
 480                         #clock-cells = <1>;
 481
 482                         clock-names = "oscclk",
 483                                 "aclk_isp_dis_400",
 484                                 "aclk_isp_400";
 485                         clocks = <&xxti>,
 486                                 <&cmu_top CLK_ACLK_ISP_DIS_400>,
 487                                 <&cmu_top CLK_ACLK_ISP_400>;
 488                 };
 489
 490                 cmu_cam0: clock-controller@120d0000 {
 491                         compatible = "samsung,exynos5433-cmu-cam0";
 492                         reg = <0x120d0000 0x1000>;
 493                         #clock-cells = <1>;
 494
 495                         clock-names = "oscclk",
 496                                 "aclk_cam0_333",
 497                                 "aclk_cam0_400",
 498                                 "aclk_cam0_552";
 499                         clocks = <&xxti>,
 500                                 <&cmu_top CLK_ACLK_CAM0_333>,
 501                                 <&cmu_top CLK_ACLK_CAM0_400>,
 502                                 <&cmu_top CLK_ACLK_CAM0_552>;
 503                 };
 504
 505                 cmu_cam1: clock-controller@145d0000 {
 506                         compatible = "samsung,exynos5433-cmu-cam1";
 507                         reg = <0x145d0000 0x1000>;
 508                         #clock-cells = <1>;
 509
 510                         clock-names = "oscclk",
 511                                 "sclk_isp_uart_cam1",
 512                                 "sclk_isp_spi1_cam1",
 513                                 "sclk_isp_spi0_cam1",
 514                                 "aclk_cam1_333",
 515                                 "aclk_cam1_400",
 516                                 "aclk_cam1_552";
 517                         clocks = <&xxti>,
 518                                 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 519                                 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 520                                 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 521                                 <&cmu_top CLK_ACLK_CAM1_333>,
 522                                 <&cmu_top CLK_ACLK_CAM1_400>,
 523                                 <&cmu_top CLK_ACLK_CAM1_552>;
 524                 };
 525
 526                 tmu_atlas0: tmu@10060000 {
 527                         compatible = "samsung,exynos5433-tmu";
 528                         reg = <0x10060000 0x200>;
 529                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 530                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 531                                 <&cmu_peris CLK_SCLK_TMU0>;
 532                         clock-names = "tmu_apbif", "tmu_sclk";
 533                         #include "exynos5433-tmu-sensor-conf.dtsi"
 534                         status = "disabled";
 535                 };
 536
 537                 tmu_atlas1: tmu@10068000 {
 538                         compatible = "samsung,exynos5433-tmu";
 539                         reg = <0x10068000 0x200>;
 540                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 542                                 <&cmu_peris CLK_SCLK_TMU0>;
 543                         clock-names = "tmu_apbif", "tmu_sclk";
 544                         #include "exynos5433-tmu-sensor-conf.dtsi"
 545                         status = "disabled";
 546                 };
 547
 548                 tmu_g3d: tmu@10070000 {
 549                         compatible = "samsung,exynos5433-tmu";
 550                         reg = <0x10070000 0x200>;
 551                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 553                                 <&cmu_peris CLK_SCLK_TMU1>;
 554                         clock-names = "tmu_apbif", "tmu_sclk";
 555                         #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
 556                         status = "disabled";
 557                 };
 558
 559                 tmu_apollo: tmu@10078000 {
 560                         compatible = "samsung,exynos5433-tmu";
 561                         reg = <0x10078000 0x200>;
 562                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 564                                 <&cmu_peris CLK_SCLK_TMU1>;
 565                         clock-names = "tmu_apbif", "tmu_sclk";
 566                         #include "exynos5433-tmu-sensor-conf.dtsi"
 567                         status = "disabled";
 568                 };
 569
 570                 tmu_isp: tmu@1007c000 {
 571                         compatible = "samsung,exynos5433-tmu";
 572                         reg = <0x1007c000 0x200>;
 573                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 575                                 <&cmu_peris CLK_SCLK_TMU1>;
 576                         clock-names = "tmu_apbif", "tmu_sclk";
 577                         #include "exynos5433-tmu-sensor-conf.dtsi"
 578                         status = "disabled";
 579                 };
 580
 581                 mct@101c0000 {
 582                         compatible = "samsung,exynos4210-mct";
 583                         reg = <0x101c0000 0x800>;
 584                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 585                                 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 586                                 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 587                                 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 588                                 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 589                                 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 591                                 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 592                                 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 593                                 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 594                                 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 595                                 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 596                         clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 597                         clock-names = "fin_pll", "mct";
 598                 };
 599
 600                 pinctrl_alive: pinctrl@10580000 {
 601                         compatible = "samsung,exynos5433-pinctrl";
 602                         reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 603
 604                         wakeup-interrupt-controller {
 605                                 compatible = "samsung,exynos7-wakeup-eint";
 606                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 607                         };
 608                 };
 609
 610                 pinctrl_aud: pinctrl@114b0000 {
 611                         compatible = "samsung,exynos5433-pinctrl";
 612                         reg = <0x114b0000 0x1000>;
 613                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 614                 };
 615
 616                 pinctrl_cpif: pinctrl@10fe0000 {
 617                         compatible = "samsung,exynos5433-pinctrl";
 618                         reg = <0x10fe0000 0x1000>;
 619                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 620                 };
 621
 622                 pinctrl_ese: pinctrl@14ca0000 {
 623                         compatible = "samsung,exynos5433-pinctrl";
 624                         reg = <0x14ca0000 0x1000>;
 625                         interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 626                 };
 627
 628                 pinctrl_finger: pinctrl@14cb0000 {
 629                         compatible = "samsung,exynos5433-pinctrl";
 630                         reg = <0x14cb0000 0x1000>;
 631                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 632                 };
 633
 634                 pinctrl_fsys: pinctrl@15690000 {
 635                         compatible = "samsung,exynos5433-pinctrl";
 636                         reg = <0x15690000 0x1000>;
 637                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 638                 };
 639
 640                 pinctrl_imem: pinctrl@11090000 {
 641                         compatible = "samsung,exynos5433-pinctrl";
 642                         reg = <0x11090000 0x1000>;
 643                         interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 644                 };
 645
 646                 pinctrl_nfc: pinctrl@14cd0000 {
 647                         compatible = "samsung,exynos5433-pinctrl";
 648                         reg = <0x14cd0000 0x1000>;
 649                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 650                 };
 651
 652                 pinctrl_peric: pinctrl@14cc0000 {
 653                         compatible = "samsung,exynos5433-pinctrl";
 654                         reg = <0x14cc0000 0x1100>;
 655                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 656                 };
 657
 658                 pinctrl_touch: pinctrl@14ce0000 {
 659                         compatible = "samsung,exynos5433-pinctrl";
 660                         reg = <0x14ce0000 0x1100>;
 661                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 662                 };
 663
 664                 pmu_system_controller: system-controller@105c0000 {
 665                         compatible = "samsung,exynos5433-pmu", "syscon";
 666                         reg = <0x105c0000 0x5008>;
 667                         #clock-cells = <1>;
 668                         clock-names = "clkout16";
 669                         clocks = <&xxti>;
 670                 };
 671
 672                 gic: interrupt-controller@11001000 {
 673                         compatible = "arm,gic-400";
 674                         #interrupt-cells = <3>;
 675                         interrupt-controller;
 676                         reg = <0x11001000 0x1000>,
 677                                 <0x11002000 0x2000>,
 678                                 <0x11004000 0x2000>,
 679                                 <0x11006000 0x2000>;
 680                         interrupts = <GIC_PPI 9 0xf04>;
 681                 };
 682
 683                 mipi_phy: video-phy@105c0710 {
 684                         compatible = "samsung,exynos5433-mipi-video-phy";
 685                         #phy-cells = <1>;
 686                         samsung,pmu-syscon = <&pmu_system_controller>;
 687                         samsung,cam0-sysreg = <&syscon_cam0>;
 688                         samsung,cam1-sysreg = <&syscon_cam1>;
 689                         samsung,disp-sysreg = <&syscon_disp>;
 690                 };
 691
 692                 decon: decon@13800000 {
 693                         compatible = "samsung,exynos5433-decon";
 694                         reg = <0x13800000 0x2104>;
 695                         clocks = <&cmu_disp CLK_PCLK_DECON>,
 696                                 <&cmu_disp CLK_ACLK_DECON>,
 697                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 698                                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
 699                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 700                                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
 701                                 <&cmu_disp CLK_SCLK_DECON_ECLK>;
 702                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 703                                 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 704                                 "sclk_decon_vclk", "sclk_decon_eclk";
 705                         interrupt-names = "fifo", "vsync", "lcd_sys";
 706                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 709                         samsung,disp-sysreg = <&syscon_disp>;
 710                         status = "disabled";
 711                         iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 712                         iommu-names = "m0", "m1";
 713
 714                         ports {
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717
 718                                 port@0 {
 719                                         reg = <0>;
 720                                         decon_to_mic: endpoint {
 721                                                 remote-endpoint =
 722                                                         <&mic_to_decon>;
 723                                         };
 724                                 };
 725                         };
 726                 };
 727
 728                 dsi: dsi@13900000 {
 729                         compatible = "samsung,exynos5433-mipi-dsi";
 730                         reg = <0x13900000 0xC0>;
 731                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 732                         phys = <&mipi_phy 1>;
 733                         phy-names = "dsim";
 734                         clocks = <&cmu_disp CLK_PCLK_DSIM0>,
 735                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
 736                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
 737                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
 738                                 <&cmu_disp CLK_SCLK_DSIM0>;
 739                         clock-names = "bus_clk",
 740                                         "phyclk_mipidphy0_bitclkdiv8",
 741                                         "phyclk_mipidphy0_rxclkesc0",
 742                                         "sclk_rgb_vclk_to_dsim0",
 743                                         "sclk_mipi";
 744                         status = "disabled";
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747
 748                         ports {
 749                                 #address-cells = <1>;
 750                                 #size-cells = <0>;
 751
 752                                 port@0 {
 753                                         reg = <0>;
 754                                         dsi_to_mic: endpoint {
 755                                                 remote-endpoint = <&mic_to_dsi>;
 756                                         };
 757                                 };
 758                         };
 759                 };
 760
 761                 mic: mic@13930000 {
 762                         compatible = "samsung,exynos5433-mic";
 763                         reg = <0x13930000 0x48>;
 764                         clocks = <&cmu_disp CLK_PCLK_MIC0>,
 765                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 766                         clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
 767                         samsung,disp-syscon = <&syscon_disp>;
 768                         status = "disabled";
 769
 770                         ports {
 771                                 #address-cells = <1>;
 772                                 #size-cells = <0>;
 773
 774                                 port@0 {
 775                                         reg = <0>;
 776                                         mic_to_decon: endpoint {
 777                                                 remote-endpoint =
 778                                                         <&decon_to_mic>;
 779                                         };
 780                                 };
 781
 782                                 port@1 {
 783                                         reg = <1>;
 784                                         mic_to_dsi: endpoint {
 785                                                 remote-endpoint = <&dsi_to_mic>;
 786                                         };
 787                                 };
 788                         };
 789                 };
 790
 791                 syscon_disp: syscon@13b80000 {
 792                         compatible = "syscon";
 793                         reg = <0x13b80000 0x1010>;
 794                 };
 795
 796                 syscon_cam0: syscon@120f0000 {
 797                         compatible = "syscon";
 798                         reg = <0x120f0000 0x1020>;
 799                 };
 800
 801                 syscon_cam1: syscon@145f0000 {
 802                         compatible = "syscon";
 803                         reg = <0x145f0000 0x1038>;
 804                 };
 805
 806                 sysmmu_decon0x: sysmmu@0x13a00000 {
 807                         compatible = "samsung,exynos-sysmmu";
 808                         reg = <0x13a00000 0x1000>;
 809                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 810                         clock-names = "pclk", "aclk";
 811                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 812                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
 813                         #iommu-cells = <0>;
 814                 };
 815
 816                 sysmmu_decon1x: sysmmu@0x13a10000 {
 817                         compatible = "samsung,exynos-sysmmu";
 818                         reg = <0x13a10000 0x1000>;
 819                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 820                         clock-names = "pclk", "aclk";
 821                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 822                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
 823                         #iommu-cells = <0>;
 824                 };
 825
 826                 serial_0: serial@14c10000 {
 827                         compatible = "samsung,exynos5433-uart";
 828                         reg = <0x14c10000 0x100>;
 829                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 830                         clocks = <&cmu_peric CLK_PCLK_UART0>,
 831                                 <&cmu_peric CLK_SCLK_UART0>;
 832                         clock-names = "uart", "clk_uart_baud0";
 833                         pinctrl-names = "default";
 834                         pinctrl-0 = <&uart0_bus>;
 835                         status = "disabled";
 836                 };
 837
 838                 serial_1: serial@14c20000 {
 839                         compatible = "samsung,exynos5433-uart";
 840                         reg = <0x14c20000 0x100>;
 841                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 842                         clocks = <&cmu_peric CLK_PCLK_UART1>,
 843                                 <&cmu_peric CLK_SCLK_UART1>;
 844                         clock-names = "uart", "clk_uart_baud0";
 845                         pinctrl-names = "default";
 846                         pinctrl-0 = <&uart1_bus>;
 847                         status = "disabled";
 848                 };
 849
 850                 serial_2: serial@14c30000 {
 851                         compatible = "samsung,exynos5433-uart";
 852                         reg = <0x14c30000 0x100>;
 853                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
 854                         clocks = <&cmu_peric CLK_PCLK_UART2>,
 855                                 <&cmu_peric CLK_SCLK_UART2>;
 856                         clock-names = "uart", "clk_uart_baud0";
 857                         pinctrl-names = "default";
 858                         pinctrl-0 = <&uart2_bus>;
 859                         status = "disabled";
 860                 };
 861
 862                 spi_0: spi@14d20000 {
 863                         compatible = "samsung,exynos5433-spi";
 864                         reg = <0x14d20000 0x100>;
 865                         interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
 866                         dmas = <&pdma0 9>, <&pdma0 8>;
 867                         dma-names = "tx", "rx";
 868                         #address-cells = <1>;
 869                         #size-cells = <0>;
 870                         clocks = <&cmu_peric CLK_PCLK_SPI0>,
 871                                 <&cmu_peric CLK_SCLK_SPI0>,
 872                                 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
 873                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 874                         samsung,spi-src-clk = <0>;
 875                         pinctrl-names = "default";
 876                         pinctrl-0 = <&spi0_bus>;
 877                         num-cs = <1>;
 878                         status = "disabled";
 879                 };
 880
 881                 spi_1: spi@14d30000 {
 882                         compatible = "samsung,exynos5433-spi";
 883                         reg = <0x14d30000 0x100>;
 884                         interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
 885                         dmas = <&pdma0 11>, <&pdma0 10>;
 886                         dma-names = "tx", "rx";
 887                         #address-cells = <1>;
 888                         #size-cells = <0>;
 889                         clocks = <&cmu_peric CLK_PCLK_SPI1>,
 890                                 <&cmu_peric CLK_SCLK_SPI1>,
 891                                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
 892                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 893                         samsung,spi-src-clk = <0>;
 894                         pinctrl-names = "default";
 895                         pinctrl-0 = <&spi1_bus>;
 896                         num-cs = <1>;
 897                         status = "disabled";
 898                 };
 899
 900                 spi_2: spi@14d40000 {
 901                         compatible = "samsung,exynos5433-spi";
 902                         reg = <0x14d40000 0x100>;
 903                         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
 904                         dmas = <&pdma0 13>, <&pdma0 12>;
 905                         dma-names = "tx", "rx";
 906                         #address-cells = <1>;
 907                         #size-cells = <0>;
 908                         clocks = <&cmu_peric CLK_PCLK_SPI2>,
 909                                 <&cmu_peric CLK_SCLK_SPI2>,
 910                                 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
 911                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 912                         samsung,spi-src-clk = <0>;
 913                         pinctrl-names = "default";
 914                         pinctrl-0 = <&spi2_bus>;
 915                         num-cs = <1>;
 916                         status = "disabled";
 917                 };
 918
 919                 spi_3: spi@14d50000 {
 920                         compatible = "samsung,exynos5433-spi";
 921                         reg = <0x14d50000 0x100>;
 922                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
 923                         dmas = <&pdma0 23>, <&pdma0 22>;
 924                         dma-names = "tx", "rx";
 925                         #address-cells = <1>;
 926                         #size-cells = <0>;
 927                         clocks = <&cmu_peric CLK_PCLK_SPI3>,
 928                                 <&cmu_peric CLK_SCLK_SPI3>,
 929                                 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
 930                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 931                         samsung,spi-src-clk = <0>;
 932                         pinctrl-names = "default";
 933                         pinctrl-0 = <&spi3_bus>;
 934                         num-cs = <1>;
 935                         status = "disabled";
 936                 };
 937
 938                 spi_4: spi@14d00000 {
 939                         compatible = "samsung,exynos5433-spi";
 940                         reg = <0x14d00000 0x100>;
 941                         interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 942                         dmas = <&pdma0 25>, <&pdma0 24>;
 943                         dma-names = "tx", "rx";
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         clocks = <&cmu_peric CLK_PCLK_SPI4>,
 947                                 <&cmu_peric CLK_SCLK_SPI4>,
 948                                 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
 949                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 950                         samsung,spi-src-clk = <0>;
 951                         pinctrl-names = "default";
 952                         pinctrl-0 = <&spi4_bus>;
 953                         num-cs = <1>;
 954                         status = "disabled";
 955                 };
 956
 957                 adc: adc@14d10000 {
 958                         compatible = "samsung,exynos7-adc";
 959                         reg = <0x14d10000 0x100>;
 960                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 961                         clock-names = "adc";
 962                         clocks = <&cmu_peric CLK_PCLK_ADCIF>;
 963                         #io-channel-cells = <1>;
 964                         io-channel-ranges;
 965                         status = "disabled";
 966                 };
 967
 968                 pwm: pwm@14dd0000 {
 969                         compatible = "samsung,exynos4210-pwm";
 970                         reg = <0x14dd0000 0x100>;
 971                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 972                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 973                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 974                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 975                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 976                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
 977                         clocks = <&cmu_peric CLK_PCLK_PWM>;
 978                         clock-names = "timers";
 979                         #pwm-cells = <3>;
 980                         status = "disabled";
 981                 };
 982
 983                 hsi2c_0: hsi2c@14e40000 {
 984                         compatible = "samsung,exynos7-hsi2c";
 985                         reg = <0x14e40000 0x1000>;
 986                         interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
 987                         #address-cells = <1>;
 988                         #size-cells = <0>;
 989                         pinctrl-names = "default";
 990                         pinctrl-0 = <&hs_i2c0_bus>;
 991                         clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
 992                         clock-names = "hsi2c";
 993                         status = "disabled";
 994                 };
 995
 996                 hsi2c_1: hsi2c@14e50000 {
 997                         compatible = "samsung,exynos7-hsi2c";
 998                         reg = <0x14e50000 0x1000>;
 999                         interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1000                         #address-cells = <1>;
1001                         #size-cells = <0>;
1002                         pinctrl-names = "default";
1003                         pinctrl-0 = <&hs_i2c1_bus>;
1004                         clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1005                         clock-names = "hsi2c";
1006                         status = "disabled";
1007                 };
1008
1009                 hsi2c_2: hsi2c@14e60000 {
1010                         compatible = "samsung,exynos7-hsi2c";
1011                         reg = <0x14e60000 0x1000>;
1012                         interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1013                         #address-cells = <1>;
1014                         #size-cells = <0>;
1015                         pinctrl-names = "default";
1016                         pinctrl-0 = <&hs_i2c2_bus>;
1017                         clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1018                         clock-names = "hsi2c";
1019                         status = "disabled";
1020                 };
1021
1022                 hsi2c_3: hsi2c@14e70000 {
1023                         compatible = "samsung,exynos7-hsi2c";
1024                         reg = <0x14e70000 0x1000>;
1025                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1026                         #address-cells = <1>;
1027                         #size-cells = <0>;
1028                         pinctrl-names = "default";
1029                         pinctrl-0 = <&hs_i2c3_bus>;
1030                         clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1031                         clock-names = "hsi2c";
1032                         status = "disabled";
1033                 };
1034
1035                 hsi2c_4: hsi2c@14ec0000 {
1036                         compatible = "samsung,exynos7-hsi2c";
1037                         reg = <0x14ec0000 0x1000>;
1038                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                         pinctrl-names = "default";
1042                         pinctrl-0 = <&hs_i2c4_bus>;
1043                         clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1044                         clock-names = "hsi2c";
1045                         status = "disabled";
1046                 };
1047
1048                 hsi2c_5: hsi2c@14ed0000 {
1049                         compatible = "samsung,exynos7-hsi2c";
1050                         reg = <0x14ed0000 0x1000>;
1051                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1052                         #address-cells = <1>;
1053                         #size-cells = <0>;
1054                         pinctrl-names = "default";
1055                         pinctrl-0 = <&hs_i2c5_bus>;
1056                         clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1057                         clock-names = "hsi2c";
1058                         status = "disabled";
1059                 };
1060
1061                 hsi2c_6: hsi2c@14ee0000 {
1062                         compatible = "samsung,exynos7-hsi2c";
1063                         reg = <0x14ee0000 0x1000>;
1064                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1065                         #address-cells = <1>;
1066                         #size-cells = <0>;
1067                         pinctrl-names = "default";
1068                         pinctrl-0 = <&hs_i2c6_bus>;
1069                         clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1070                         clock-names = "hsi2c";
1071                         status = "disabled";
1072                 };
1073
1074                 hsi2c_7: hsi2c@14ef0000 {
1075                         compatible = "samsung,exynos7-hsi2c";
1076                         reg = <0x14ef0000 0x1000>;
1077                         interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1078                         #address-cells = <1>;
1079                         #size-cells = <0>;
1080                         pinctrl-names = "default";
1081                         pinctrl-0 = <&hs_i2c7_bus>;
1082                         clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1083                         clock-names = "hsi2c";
1084                         status = "disabled";
1085                 };
1086
1087                 hsi2c_8: hsi2c@14d90000 {
1088                         compatible = "samsung,exynos7-hsi2c";
1089                         reg = <0x14d90000 0x1000>;
1090                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1091                         #address-cells = <1>;
1092                         #size-cells = <0>;
1093                         pinctrl-names = "default";
1094                         pinctrl-0 = <&hs_i2c8_bus>;
1095                         clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1096                         clock-names = "hsi2c";
1097                         status = "disabled";
1098                 };
1099
1100                 hsi2c_9: hsi2c@14da0000 {
1101                         compatible = "samsung,exynos7-hsi2c";
1102                         reg = <0x14da0000 0x1000>;
1103                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1104                         #address-cells = <1>;
1105                         #size-cells = <0>;
1106                         pinctrl-names = "default";
1107                         pinctrl-0 = <&hs_i2c9_bus>;
1108                         clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1109                         clock-names = "hsi2c";
1110                         status = "disabled";
1111                 };
1112
1113                 hsi2c_10: hsi2c@14de0000 {
1114                         compatible = "samsung,exynos7-hsi2c";
1115                         reg = <0x14de0000 0x1000>;
1116                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1117                         #address-cells = <1>;
1118                         #size-cells = <0>;
1119                         pinctrl-names = "default";
1120                         pinctrl-0 = <&hs_i2c10_bus>;
1121                         clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1122                         clock-names = "hsi2c";
1123                         status = "disabled";
1124                 };
1125
1126                 hsi2c_11: hsi2c@14df0000 {
1127                         compatible = "samsung,exynos7-hsi2c";
1128                         reg = <0x14df0000 0x1000>;
1129                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1130                         #address-cells = <1>;
1131                         #size-cells = <0>;
1132                         pinctrl-names = "default";
1133                         pinctrl-0 = <&hs_i2c11_bus>;
1134                         clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1135                         clock-names = "hsi2c";
1136                         status = "disabled";
1137                 };
1138
1139                 usbdrd30: usb@15400000  {
1140                         compatible = "samsung,exynos5250-dwusb3";
1141                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1142                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1143                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1144                         assigned-clocks =
1145                                 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
1146                                 <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
1147                                 <&cmu_top CLK_DIV_SCLK_USBDRD30>;
1148                         assigned-clock-parents =
1149                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
1150                                 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1151                         assigned-clock-rates = <0>, <0>, <66700000>;
1152                         #address-cells = <1>;
1153                         #size-cells = <1>;
1154                         ranges;
1155                         status = "disabled";
1156
1157                         dwc3@15400000 {
1158                                 compatible = "snps,dwc3";
1159                                 reg = <0x15400000 0x10000>;
1160                                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1161                                 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1162                                 phy-names = "usb2-phy", "usb3-phy";
1163                         };
1164                 };
1165
1166                 usbdrd30_phy: phy@15500000 {
1167                         compatible = "samsung,exynos5433-usbdrd-phy";
1168                         reg = <0x15500000 0x100>;
1169                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1170                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1171                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1172                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1173                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1174                                         "itp";
1175                         assigned-clocks =
1176                                 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
1177                                 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
1178                         assigned-clock-parents =
1179                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
1180                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
1181                         #phy-cells = <1>;
1182                         samsung,pmu-syscon = <&pmu_system_controller>;
1183                         status = "disabled";
1184                 };
1185
1186                 usbhost30_phy: phy@15580000 {
1187                         compatible = "samsung,exynos5433-usbdrd-phy";
1188                         reg = <0x15580000 0x100>;
1189                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1190                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1191                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1192                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1193                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1194                                         "itp";
1195                         assigned-clocks =
1196                                 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
1197                                 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
1198                         assigned-clock-parents =
1199                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
1200                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
1201                         #phy-cells = <1>;
1202                         samsung,pmu-syscon = <&pmu_system_controller>;
1203                         status = "disabled";
1204                 };
1205
1206                 usbhost30: usb@15a00000 {
1207                         compatible = "samsung,exynos5250-dwusb3";
1208                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1209                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1210                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1211                         assigned-clocks =
1212                                 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
1213                                 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
1214                                 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
1215                         assigned-clock-parents =
1216                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
1217                                 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
1218                         assigned-clock-rates = <0>, <0>, <66700000>;
1219                         #address-cells = <1>;
1220                         #size-cells = <1>;
1221                         ranges;
1222                         status = "disabled";
1223
1224                         usbdrd_dwc3_0: dwc3@15a00000 {
1225                                 compatible = "snps,dwc3";
1226                                 reg = <0x15a00000 0x10000>;
1227                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1228                                 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1229                                 phy-names = "usb2-phy", "usb3-phy";
1230                         };
1231                 };
1232
1233                 mshc_0: mshc@15540000 {
1234                         compatible = "samsung,exynos7-dw-mshc-smu";
1235                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1236                         #address-cells = <1>;
1237                         #size-cells = <0>;
1238                         reg = <0x15540000 0x2000>;
1239                         clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1240                                 <&cmu_fsys CLK_SCLK_MMC0>;
1241                         clock-names = "biu", "ciu";
1242                         fifo-depth = <0x40>;
1243                         status = "disabled";
1244                 };
1245
1246                 mshc_1: mshc@15550000 {
1247                         compatible = "samsung,exynos7-dw-mshc-smu";
1248                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1249                         #address-cells = <1>;
1250                         #size-cells = <0>;
1251                         reg = <0x15550000 0x2000>;
1252                         clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1253                                 <&cmu_fsys CLK_SCLK_MMC1>;
1254                         clock-names = "biu", "ciu";
1255                         fifo-depth = <0x40>;
1256                         status = "disabled";
1257                 };
1258
1259                 mshc_2: mshc@15560000 {
1260                         compatible = "samsung,exynos7-dw-mshc-smu";
1261                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1262                         #address-cells = <1>;
1263                         #size-cells = <0>;
1264                         reg = <0x15560000 0x2000>;
1265                         clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1266                                 <&cmu_fsys CLK_SCLK_MMC2>;
1267                         clock-names = "biu", "ciu";
1268                         fifo-depth = <0x40>;
1269                         status = "disabled";
1270                 };
1271
1272                 amba {
1273                         compatible = "arm,amba-bus";
1274                         #address-cells = <1>;
1275                         #size-cells = <1>;
1276                         ranges;
1277
1278                         pdma0: pdma@15610000 {
1279                                 compatible = "arm,pl330", "arm,primecell";
1280                                 reg = <0x15610000 0x1000>;
1281                                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1282                                 clocks = <&cmu_fsys CLK_PDMA0>;
1283                                 clock-names = "apb_pclk";
1284                                 #dma-cells = <1>;
1285                                 #dma-channels = <8>;
1286                                 #dma-requests = <32>;
1287                         };
1288
1289                         pdma1: pdma@15600000 {
1290                                 compatible = "arm,pl330", "arm,primecell";
1291                                 reg = <0x15600000 0x1000>;
1292                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1293                                 clocks = <&cmu_fsys CLK_PDMA1>;
1294                                 clock-names = "apb_pclk";
1295                                 #dma-cells = <1>;
1296                                 #dma-channels = <8>;
1297                                 #dma-requests = <32>;
1298                         };
1299                 };
1300
1301                 audio-subsystem@11400000 {
1302                         compatible = "samsung,exynos5433-lpass";
1303                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
1304                         samsung,pmu-syscon = <&pmu_system_controller>;
1305                         #address-cells = <1>;
1306                         #size-cells = <1>;
1307                         ranges;
1308
1309                         adma: adma@11420000 {
1310                                 compatible = "arm,pl330", "arm,primecell";
1311                                 reg = <0x11420000 0x1000>;
1312                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1313                                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1314                                 clock-names = "apb_pclk";
1315                                 #dma-cells = <1>;
1316                                 #dma-channels = <8>;
1317                                 #dma-requests = <32>;
1318                         };
1319
1320                         i2s0: i2s0@11440000 {
1321                                 compatible = "samsung,exynos7-i2s";
1322                                 reg = <0x11440000 0x100>;
1323                                 dmas = <&adma 0 &adma 2>;
1324                                 dma-names = "tx", "rx";
1325                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1326                                 #address-cells = <1>;
1327                                 #size-cells = <0>;
1328                                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1329                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
1330                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
1331                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1332                                 pinctrl-names = "default";
1333                                 pinctrl-0 = <&i2s0_bus>;
1334                                 status = "disabled";
1335                         };
1336
1337                         serial_3: serial@11460000 {
1338                                 compatible = "samsung,exynos5433-uart";
1339                                 reg = <0x11460000 0x100>;
1340                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1341                                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1342                                         <&cmu_aud CLK_SCLK_AUD_UART>;
1343                                 clock-names = "uart", "clk_uart_baud0";
1344                                 pinctrl-names = "default";
1345                                 pinctrl-0 = <&uart_aud_bus>;
1346                                 status = "disabled";
1347                         };
1348                 };
1349         };
1350
1351         timer: timer {
1352                 compatible = "arm,armv8-timer";
1353                 interrupts = <GIC_PPI 13
1354                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1355                         <GIC_PPI 14
1356                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1357                         <GIC_PPI 11
1358                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1359                         <GIC_PPI 10
1360                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1361         };
1362 };
1363
1364 #include "exynos5433-pinctrl.dtsi"
1365 #include "exynos5433-tmu.dtsi"