arch/arm64/boot/dts/broadcom/ns2.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright (c) 2015 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/clock/bcm-ns2.h>
  35
  36 / {
  37         compatible = "brcm,ns2";
  38         interrupt-parent = <&gic>;
  39         #address-cells = <2>;
  40         #size-cells = <2>;
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 A57_0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a57", "arm,armv8";
  49                         reg = <0 0>;
  50                         enable-method = "psci";
  51                         next-level-cache = <&CLUSTER0_L2>;
  52                 };
  53
  54                 A57_1: cpu@1 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a57", "arm,armv8";
  57                         reg = <0 1>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&CLUSTER0_L2>;
  60                 };
  61
  62                 A57_2: cpu@2 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a57", "arm,armv8";
  65                         reg = <0 2>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&CLUSTER0_L2>;
  68                 };
  69
  70                 A57_3: cpu@3 {
  71                         device_type = "cpu";
  72                         compatible = "arm,cortex-a57", "arm,armv8";
  73                         reg = <0 3>;
  74                         enable-method = "psci";
  75                         next-level-cache = <&CLUSTER0_L2>;
  76                 };
  77
  78                 CLUSTER0_L2: l2-cache@000 {
  79                         compatible = "cache";
  80                 };
  81         };
  82
  83         psci {
  84                 compatible = "arm,psci-1.0";
  85                 method = "smc";
  86         };
  87
  88         timer {
  89                 compatible = "arm,armv8-timer";
  90                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
  91                               IRQ_TYPE_EDGE_RISING)>,
  92                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
  93                               IRQ_TYPE_EDGE_RISING)>,
  94                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
  95                               IRQ_TYPE_EDGE_RISING)>,
  96                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
  97                               IRQ_TYPE_EDGE_RISING)>;
  98         };
  99
 100         pmu {
 101                 compatible = "arm,armv8-pmuv3";
 102                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
 106                 interrupt-affinity = <&A57_0>,
 107                                      <&A57_1>,
 108                                      <&A57_2>,
 109                                      <&A57_3>;
 110         };
 111
 112         pcie0: pcie@20020000 {
 113                 compatible = "brcm,iproc-pcie";
 114                 reg = <0 0x20020000 0 0x1000>;
 115
 116                 #interrupt-cells = <1>;
 117                 interrupt-map-mask = <0 0 0 0>;
 118                 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
 119
 120                 linux,pci-domain = <0>;
 121
 122                 bus-range = <0x00 0xff>;
 123
 124                 #address-cells = <3>;
 125                 #size-cells = <2>;
 126                 device_type = "pci";
 127                 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
 128
 129                 brcm,pcie-ob;
 130                 brcm,pcie-ob-oarr-size;
 131                 brcm,pcie-ob-axi-offset = <0x00000000>;
 132                 brcm,pcie-ob-window-size = <256>;
 133
 134                 status = "disabled";
 135
 136                 msi-parent = <&msi0>;
 137                 msi0: msi@20020000 {
 138                         compatible = "brcm,iproc-msi";
 139                         msi-controller;
 140                         interrupt-parent = <&gic>;
 141                         interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
 142                                      <GIC_SPI 278 IRQ_TYPE_NONE>,
 143                                      <GIC_SPI 279 IRQ_TYPE_NONE>,
 144                                      <GIC_SPI 280 IRQ_TYPE_NONE>;
 145                         brcm,num-eq-region = <1>;
 146                         brcm,num-msi-msg-region = <1>;
 147                 };
 148         };
 149
 150         pcie4: pcie@50020000 {
 151                 compatible = "brcm,iproc-pcie";
 152                 reg = <0 0x50020000 0 0x1000>;
 153
 154                 #interrupt-cells = <1>;
 155                 interrupt-map-mask = <0 0 0 0>;
 156                 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
 157
 158                 linux,pci-domain = <4>;
 159
 160                 bus-range = <0x00 0xff>;
 161
 162                 #address-cells = <3>;
 163                 #size-cells = <2>;
 164                 device_type = "pci";
 165                 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
 166
 167                 brcm,pcie-ob;
 168                 brcm,pcie-ob-oarr-size;
 169                 brcm,pcie-ob-axi-offset = <0x30000000>;
 170                 brcm,pcie-ob-window-size = <256>;
 171
 172                 status = "disabled";
 173
 174                 msi-parent = <&msi4>;
 175                 msi4: msi@50020000 {
 176                         compatible = "brcm,iproc-msi";
 177                         msi-controller;
 178                         interrupt-parent = <&gic>;
 179                         interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
 180                                      <GIC_SPI 302 IRQ_TYPE_NONE>,
 181                                      <GIC_SPI 303 IRQ_TYPE_NONE>,
 182                                      <GIC_SPI 304 IRQ_TYPE_NONE>;
 183                 };
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 #address-cells = <1>;
 189                 #size-cells = <1>;
 190                 ranges = <0 0 0 0xffffffff>;
 191
 192                 #include "ns2-clock.dtsi"
 193
 194                 dma0: dma@61360000 {
 195                         compatible = "arm,pl330", "arm,primecell";
 196                         reg = <0x61360000 0x1000>;
 197                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
 206                         #dma-cells = <1>;
 207                         #dma-channels = <8>;
 208                         #dma-requests = <32>;
 209                         clocks = <&iprocslow>;
 210                         clock-names = "apb_pclk";
 211                 };
 212
 213                 smmu: mmu@64000000 {
 214                         compatible = "arm,mmu-500";
 215                         reg = <0x64000000 0x40000>;
 216                         #global-interrupts = <2>;
 217                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
 251                         mmu-masters;
 252                 };
 253
 254                 pinctrl: pinctrl@6501d130 {
 255                         compatible = "brcm,ns2-pinmux";
 256                         reg = <0x6501d130 0x08>,
 257                               <0x660a0028 0x04>,
 258                               <0x660009b0 0x40>;
 259                 };
 260
 261                 gpio_aon: gpio@65024800 {
 262                         compatible = "brcm,iproc-gpio";
 263                         reg = <0x65024800 0x50>,
 264                               <0x65024008 0x18>;
 265                         ngpios = <6>;
 266                         #gpio-cells = <2>;
 267                         gpio-controller;
 268                 };
 269
 270                 gic: interrupt-controller@65210000 {
 271                         compatible = "arm,gic-400";
 272                         #interrupt-cells = <3>;
 273                         interrupt-controller;
 274                         reg = <0x65210000 0x1000>,
 275                               <0x65220000 0x1000>,
 276                               <0x65240000 0x2000>,
 277                               <0x65260000 0x1000>;
 278                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 279                                       IRQ_TYPE_LEVEL_HIGH)>;
 280                 };
 281
 282                 cci@65590000 {
 283                         compatible = "arm,cci-400";
 284                         #address-cells = <1>;
 285                         #size-cells = <1>;
 286                         reg = <0x65590000 0x1000>;
 287                         ranges = <0 0x65590000 0x10000>;
 288
 289                         pmu@9000 {
 290                                 compatible = "arm,cci-400-pmu,r1",
 291                                              "arm,cci-400-pmu";
 292                                 reg = <0x9000 0x4000>;
 293                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 294                                              <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 295                                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 296                                              <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 297                                              <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 298                                              <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
 299                         };
 300                 };
 301
 302                 timer0: timer@66030000 {
 303                         compatible = "arm,sp804", "arm,primecell";
 304                         reg = <0x66030000 0x1000>;
 305                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&iprocslow>,
 307                                  <&iprocslow>,
 308                                  <&iprocslow>;
 309                         clock-names = "timer1", "timer2", "apb_pclk";
 310                 };
 311
 312                 timer1: timer@66040000 {
 313                         compatible = "arm,sp804", "arm,primecell";
 314                         reg = <0x66040000 0x1000>;
 315                         interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&iprocslow>,
 317                                  <&iprocslow>,
 318                                  <&iprocslow>;
 319                         clock-names = "timer1", "timer2", "apb_pclk";
 320                 };
 321
 322                 timer2: timer@66050000 {
 323                         compatible = "arm,sp804", "arm,primecell";
 324                         reg = <0x66050000 0x1000>;
 325                         interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&iprocslow>,
 327                                  <&iprocslow>,
 328                                  <&iprocslow>;
 329                         clock-names = "timer1", "timer2", "apb_pclk";
 330                 };
 331
 332                 timer3: timer@66060000 {
 333                         compatible = "arm,sp804", "arm,primecell";
 334                         reg = <0x66060000 0x1000>;
 335                         interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&iprocslow>,
 337                                  <&iprocslow>,
 338                                  <&iprocslow>;
 339                         clock-names = "timer1", "timer2", "apb_pclk";
 340                 };
 341
 342                 i2c0: i2c@66080000 {
 343                         compatible = "brcm,iproc-i2c";
 344                         reg = <0x66080000 0x100>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
 348                         clock-frequency = <100000>;
 349                         status = "disabled";
 350                 };
 351
 352                 wdt0: watchdog@66090000 {
 353                         compatible = "arm,sp805", "arm,primecell";
 354                         reg = <0x66090000 0x1000>;
 355                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
 356                         clocks = <&iprocslow>, <&iprocslow>;
 357                         clock-names = "wdogclk", "apb_pclk";
 358                 };
 359
 360                 gpio_g: gpio@660a0000 {
 361                         compatible = "brcm,iproc-gpio";
 362                         reg = <0x660a0000 0x50>;
 363                         ngpios = <32>;
 364                         #gpio-cells = <2>;
 365                         gpio-controller;
 366                         interrupt-controller;
 367                         interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
 368                 };
 369
 370                 i2c1: i2c@660b0000 {
 371                         compatible = "brcm,iproc-i2c";
 372                         reg = <0x660b0000 0x100>;
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
 376                         clock-frequency = <100000>;
 377                         status = "disabled";
 378                 };
 379
 380                 uart0: serial@66100000 {
 381                         compatible = "snps,dw-apb-uart";
 382                         reg = <0x66100000 0x100>;
 383                         interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
 384                         clocks = <&iprocslow>;
 385                         reg-shift = <2>;
 386                         reg-io-width = <4>;
 387                         status = "disabled";
 388                 };
 389
 390                 uart1: serial@66110000 {
 391                         compatible = "snps,dw-apb-uart";
 392                         reg = <0x66110000 0x100>;
 393                         interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&iprocslow>;
 395                         reg-shift = <2>;
 396                         reg-io-width = <4>;
 397                         status = "disabled";
 398                 };
 399
 400                 uart2: serial@66120000 {
 401                         compatible = "snps,dw-apb-uart";
 402                         reg = <0x66120000 0x100>;
 403                         interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&iprocslow>;
 405                         reg-shift = <2>;
 406                         reg-io-width = <4>;
 407                         status = "disabled";
 408                 };
 409
 410                 uart3: serial@66130000 {
 411                         compatible = "snps,dw-apb-uart";
 412                         reg = <0x66130000 0x100>;
 413                         interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
 414                         reg-shift = <2>;
 415                         reg-io-width = <4>;
 416                         clocks = <&osc>;
 417                         status = "disabled";
 418                 };
 419
 420                 ssp0: ssp@66180000 {
 421                         compatible = "arm,pl022", "arm,primecell";
 422                         reg = <0x66180000 0x1000>;
 423                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&iprocslow>, <&iprocslow>;
 425                         clock-names = "spiclk", "apb_pclk";
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         status = "disabled";
 429                 };
 430
 431                 ssp1: ssp@66190000 {
 432                         compatible = "arm,pl022", "arm,primecell";
 433                         reg = <0x66190000 0x1000>;
 434                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 435                         clocks = <&iprocslow>, <&iprocslow>;
 436                         clock-names = "spiclk", "apb_pclk";
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         status = "disabled";
 440                 };
 441
 442                 hwrng: hwrng@66220000 {
 443                         compatible = "brcm,iproc-rng200";
 444                         reg = <0x66220000 0x28>;
 445                 };
 446
 447                 sata_phy: sata_phy@663f0100 {
 448                         compatible = "brcm,iproc-ns2-sata-phy";
 449                         reg = <0x663f0100 0x1f00>,
 450                               <0x663f004c 0x10>;
 451                         reg-names = "phy", "phy-ctrl";
 452                         #address-cells = <1>;
 453                         #size-cells = <0>;
 454
 455                         sata_phy0: sata-phy@0 {
 456                                 reg = <0>;
 457                                 #phy-cells = <0>;
 458                                 status = "disabled";
 459                         };
 460
 461                         sata_phy1: sata-phy@1 {
 462                                 reg = <1>;
 463                                 #phy-cells = <0>;
 464                                 status = "disabled";
 465                         };
 466                 };
 467
 468                 sata: ahci@663f2000 {
 469                         compatible = "brcm,iproc-ahci", "generic-ahci";
 470                         reg = <0x663f2000 0x1000>;
 471                         reg-names = "ahci";
 472                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                         status = "disabled";
 476
 477                         sata0: sata-port@0 {
 478                                 reg = <0>;
 479                                 phys = <&sata_phy0>;
 480                                 phy-names = "sata-phy";
 481                         };
 482
 483                         sata1: sata-port@1 {
 484                                 reg = <1>;
 485                                 phys = <&sata_phy1>;
 486                                 phy-names = "sata-phy";
 487                         };
 488                 };
 489
 490                 sdio0: sdhci@66420000 {
 491                         compatible = "brcm,sdhci-iproc-cygnus";
 492                         reg = <0x66420000 0x100>;
 493                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 494                         bus-width = <8>;
 495                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 496                         status = "disabled";
 497                 };
 498
 499                 sdio1: sdhci@66430000 {
 500                         compatible = "brcm,sdhci-iproc-cygnus";
 501                         reg = <0x66430000 0x100>;
 502                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 503                         bus-width = <8>;
 504                         clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
 505                         status = "disabled";
 506                 };
 507
 508                 nand: nand@66460000 {
 509                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 510                         reg = <0x66460000 0x600>,
 511                               <0x67015408 0x600>,
 512                               <0x66460f00 0x20>;
 513                         reg-names = "nand", "iproc-idm", "iproc-ext";
 514                         interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
 515
 516                         #address-cells = <1>;
 517                         #size-cells = <0>;
 518
 519                         brcm,nand-has-wp;
 520                 };
 521         };
 522 };