arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                         next-level-cache = <&xgene_L2_0>;
  29                 };
  30                 cpu@001 {
  31                         device_type = "cpu";
  32                         compatible = "apm,potenza", "arm,armv8";
  33                         reg = <0x0 0x001>;
  34                         enable-method = "spin-table";
  35                         cpu-release-addr = <0x1 0x0000fff8>;
  36                         next-level-cache = <&xgene_L2_0>;
  37                 };
  38                 cpu@100 {
  39                         device_type = "cpu";
  40                         compatible = "apm,potenza", "arm,armv8";
  41                         reg = <0x0 0x100>;
  42                         enable-method = "spin-table";
  43                         cpu-release-addr = <0x1 0x0000fff8>;
  44                         next-level-cache = <&xgene_L2_1>;
  45                 };
  46                 cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "apm,potenza", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "spin-table";
  51                         cpu-release-addr = <0x1 0x0000fff8>;
  52                         next-level-cache = <&xgene_L2_1>;
  53                 };
  54                 cpu@200 {
  55                         device_type = "cpu";
  56                         compatible = "apm,potenza", "arm,armv8";
  57                         reg = <0x0 0x200>;
  58                         enable-method = "spin-table";
  59                         cpu-release-addr = <0x1 0x0000fff8>;
  60                         next-level-cache = <&xgene_L2_2>;
  61                 };
  62                 cpu@201 {
  63                         device_type = "cpu";
  64                         compatible = "apm,potenza", "arm,armv8";
  65                         reg = <0x0 0x201>;
  66                         enable-method = "spin-table";
  67                         cpu-release-addr = <0x1 0x0000fff8>;
  68                         next-level-cache = <&xgene_L2_2>;
  69                 };
  70                 cpu@300 {
  71                         device_type = "cpu";
  72                         compatible = "apm,potenza", "arm,armv8";
  73                         reg = <0x0 0x300>;
  74                         enable-method = "spin-table";
  75                         cpu-release-addr = <0x1 0x0000fff8>;
  76                         next-level-cache = <&xgene_L2_3>;
  77                 };
  78                 cpu@301 {
  79                         device_type = "cpu";
  80                         compatible = "apm,potenza", "arm,armv8";
  81                         reg = <0x0 0x301>;
  82                         enable-method = "spin-table";
  83                         cpu-release-addr = <0x1 0x0000fff8>;
  84                         next-level-cache = <&xgene_L2_3>;
  85                 };
  86                 xgene_L2_0: l2-cache-0 {
  87                         compatible = "cache";
  88                 };
  89                 xgene_L2_1: l2-cache-1 {
  90                         compatible = "cache";
  91                 };
  92                 xgene_L2_2: l2-cache-2 {
  93                         compatible = "cache";
  94                 };
  95                 xgene_L2_3: l2-cache-3 {
  96                         compatible = "cache";
  97                 };
  98         };
  99
 100         gic: interrupt-controller@78010000 {
 101                 compatible = "arm,cortex-a15-gic";
 102                 #interrupt-cells = <3>;
 103                 interrupt-controller;
 104                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
 105                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
 106                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
 107                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
 108                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
 114                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
 115                              <1 14 0xff01>,     /* Virt IRQ */
 116                              <1 15 0xff01>;     /* Hyp IRQ */
 117                 clock-frequency = <50000000>;
 118         };
 119
 120         pmu {
 121                 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
 122                 interrupts = <1 12 0xff04>;
 123         };
 124
 125         soc {
 126                 compatible = "simple-bus";
 127                 #address-cells = <2>;
 128                 #size-cells = <2>;
 129                 ranges;
 130                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 131
 132                 clocks {
 133                         #address-cells = <2>;
 134                         #size-cells = <2>;
 135                         ranges;
 136                         refclk: refclk {
 137                                 compatible = "fixed-clock";
 138                                 #clock-cells = <1>;
 139                                 clock-frequency = <100000000>;
 140                                 clock-output-names = "refclk";
 141                         };
 142
 143                         pcppll: pcppll@17000100 {
 144                                 compatible = "apm,xgene-pcppll-clock";
 145                                 #clock-cells = <1>;
 146                                 clocks = <&refclk 0>;
 147                                 clock-names = "pcppll";
 148                                 reg = <0x0 0x17000100 0x0 0x1000>;
 149                                 clock-output-names = "pcppll";
 150                                 type = <0>;
 151                         };
 152
 153                         socpll: socpll@17000120 {
 154                                 compatible = "apm,xgene-socpll-clock";
 155                                 #clock-cells = <1>;
 156                                 clocks = <&refclk 0>;
 157                                 clock-names = "socpll";
 158                                 reg = <0x0 0x17000120 0x0 0x1000>;
 159                                 clock-output-names = "socpll";
 160                                 type = <1>;
 161                         };
 162
 163                         socplldiv2: socplldiv2  {
 164                                 compatible = "fixed-factor-clock";
 165                                 #clock-cells = <1>;
 166                                 clocks = <&socpll 0>;
 167                                 clock-names = "socplldiv2";
 168                                 clock-mult = <1>;
 169                                 clock-div = <2>;
 170                                 clock-output-names = "socplldiv2";
 171                         };
 172
 173                         ahbclk: ahbclk@17000000 {
 174                                 compatible = "apm,xgene-device-clock";
 175                                 #clock-cells = <1>;
 176                                 clocks = <&socplldiv2 0>;
 177                                 reg = <0x0 0x17000000 0x0 0x2000>;
 178                                 reg-names = "div-reg";
 179                                 divider-offset = <0x164>;
 180                                 divider-width = <0x5>;
 181                                 divider-shift = <0x0>;
 182                                 clock-output-names = "ahbclk";
 183                         };
 184
 185                         sdioclk: sdioclk@1f2ac000 {
 186                                 compatible = "apm,xgene-device-clock";
 187                                 #clock-cells = <1>;
 188                                 clocks = <&socplldiv2 0>;
 189                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 190                                         0x0 0x17000000 0x0 0x2000>;
 191                                 reg-names = "csr-reg", "div-reg";
 192                                 csr-offset = <0x0>;
 193                                 csr-mask = <0x2>;
 194                                 enable-offset = <0x8>;
 195                                 enable-mask = <0x2>;
 196                                 divider-offset = <0x178>;
 197                                 divider-width = <0x8>;
 198                                 divider-shift = <0x0>;
 199                                 clock-output-names = "sdioclk";
 200                         };
 201
 202                         ethclk: ethclk {
 203                                 compatible = "apm,xgene-device-clock";
 204                                 #clock-cells = <1>;
 205                                 clocks = <&socplldiv2 0>;
 206                                 clock-names = "ethclk";
 207                                 reg = <0x0 0x17000000 0x0 0x1000>;
 208                                 reg-names = "div-reg";
 209                                 divider-offset = <0x238>;
 210                                 divider-width = <0x9>;
 211                                 divider-shift = <0x0>;
 212                                 clock-output-names = "ethclk";
 213                         };
 214
 215                         menetclk: menetclk {
 216                                 compatible = "apm,xgene-device-clock";
 217                                 #clock-cells = <1>;
 218                                 clocks = <&ethclk 0>;
 219                                 reg = <0x0 0x1702c000 0x0 0x1000>;
 220                                 reg-names = "csr-reg";
 221                                 clock-output-names = "menetclk";
 222                         };
 223
 224                         sge0clk: sge0clk@1f21c000 {
 225                                 compatible = "apm,xgene-device-clock";
 226                                 #clock-cells = <1>;
 227                                 clocks = <&socplldiv2 0>;
 228                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 229                                 reg-names = "csr-reg";
 230                                 csr-mask = <0x3>;
 231                                 clock-output-names = "sge0clk";
 232                         };
 233
 234                         sge1clk: sge1clk@1f21c000 {
 235                                 compatible = "apm,xgene-device-clock";
 236                                 #clock-cells = <1>;
 237                                 clocks = <&socplldiv2 0>;
 238                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 239                                 reg-names = "csr-reg";
 240                                 csr-mask = <0xc>;
 241                                 clock-output-names = "sge1clk";
 242                         };
 243
 244                         xge0clk: xge0clk@1f61c000 {
 245                                 compatible = "apm,xgene-device-clock";
 246                                 #clock-cells = <1>;
 247                                 clocks = <&socplldiv2 0>;
 248                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 249                                 reg-names = "csr-reg";
 250                                 csr-mask = <0x3>;
 251                                 clock-output-names = "xge0clk";
 252                         };
 253
 254                         xge1clk: xge1clk@1f62c000 {
 255                                 compatible = "apm,xgene-device-clock";
 256                                 status = "disabled";
 257                                 #clock-cells = <1>;
 258                                 clocks = <&socplldiv2 0>;
 259                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 260                                 reg-names = "csr-reg";
 261                                 csr-mask = <0x3>;
 262                                 clock-output-names = "xge1clk";
 263                         };
 264
 265                         sataphy1clk: sataphy1clk@1f21c000 {
 266                                 compatible = "apm,xgene-device-clock";
 267                                 #clock-cells = <1>;
 268                                 clocks = <&socplldiv2 0>;
 269                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 270                                 reg-names = "csr-reg";
 271                                 clock-output-names = "sataphy1clk";
 272                                 status = "disabled";
 273                                 csr-offset = <0x4>;
 274                                 csr-mask = <0x00>;
 275                                 enable-offset = <0x0>;
 276                                 enable-mask = <0x06>;
 277                         };
 278
 279                         sataphy2clk: sataphy1clk@1f22c000 {
 280                                 compatible = "apm,xgene-device-clock";
 281                                 #clock-cells = <1>;
 282                                 clocks = <&socplldiv2 0>;
 283                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 284                                 reg-names = "csr-reg";
 285                                 clock-output-names = "sataphy2clk";
 286                                 status = "ok";
 287                                 csr-offset = <0x4>;
 288                                 csr-mask = <0x3a>;
 289                                 enable-offset = <0x0>;
 290                                 enable-mask = <0x06>;
 291                         };
 292
 293                         sataphy3clk: sataphy1clk@1f23c000 {
 294                                 compatible = "apm,xgene-device-clock";
 295                                 #clock-cells = <1>;
 296                                 clocks = <&socplldiv2 0>;
 297                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 298                                 reg-names = "csr-reg";
 299                                 clock-output-names = "sataphy3clk";
 300                                 status = "ok";
 301                                 csr-offset = <0x4>;
 302                                 csr-mask = <0x3a>;
 303                                 enable-offset = <0x0>;
 304                                 enable-mask = <0x06>;
 305                         };
 306
 307                         sata01clk: sata01clk@1f21c000 {
 308                                 compatible = "apm,xgene-device-clock";
 309                                 #clock-cells = <1>;
 310                                 clocks = <&socplldiv2 0>;
 311                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 312                                 reg-names = "csr-reg";
 313                                 clock-output-names = "sata01clk";
 314                                 csr-offset = <0x4>;
 315                                 csr-mask = <0x05>;
 316                                 enable-offset = <0x0>;
 317                                 enable-mask = <0x39>;
 318                         };
 319
 320                         sata23clk: sata23clk@1f22c000 {
 321                                 compatible = "apm,xgene-device-clock";
 322                                 #clock-cells = <1>;
 323                                 clocks = <&socplldiv2 0>;
 324                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 325                                 reg-names = "csr-reg";
 326                                 clock-output-names = "sata23clk";
 327                                 csr-offset = <0x4>;
 328                                 csr-mask = <0x05>;
 329                                 enable-offset = <0x0>;
 330                                 enable-mask = <0x39>;
 331                         };
 332
 333                         sata45clk: sata45clk@1f23c000 {
 334                                 compatible = "apm,xgene-device-clock";
 335                                 #clock-cells = <1>;
 336                                 clocks = <&socplldiv2 0>;
 337                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 338                                 reg-names = "csr-reg";
 339                                 clock-output-names = "sata45clk";
 340                                 csr-offset = <0x4>;
 341                                 csr-mask = <0x05>;
 342                                 enable-offset = <0x0>;
 343                                 enable-mask = <0x39>;
 344                         };
 345
 346                         rtcclk: rtcclk@17000000 {
 347                                 compatible = "apm,xgene-device-clock";
 348                                 #clock-cells = <1>;
 349                                 clocks = <&socplldiv2 0>;
 350                                 reg = <0x0 0x17000000 0x0 0x2000>;
 351                                 reg-names = "csr-reg";
 352                                 csr-offset = <0xc>;
 353                                 csr-mask = <0x2>;
 354                                 enable-offset = <0x10>;
 355                                 enable-mask = <0x2>;
 356                                 clock-output-names = "rtcclk";
 357                         };
 358
 359                         rngpkaclk: rngpkaclk@17000000 {
 360                                 compatible = "apm,xgene-device-clock";
 361                                 #clock-cells = <1>;
 362                                 clocks = <&socplldiv2 0>;
 363                                 reg = <0x0 0x17000000 0x0 0x2000>;
 364                                 reg-names = "csr-reg";
 365                                 csr-offset = <0xc>;
 366                                 csr-mask = <0x10>;
 367                                 enable-offset = <0x10>;
 368                                 enable-mask = <0x10>;
 369                                 clock-output-names = "rngpkaclk";
 370                         };
 371
 372                         pcie0clk: pcie0clk@1f2bc000 {
 373                                 status = "disabled";
 374                                 compatible = "apm,xgene-device-clock";
 375                                 #clock-cells = <1>;
 376                                 clocks = <&socplldiv2 0>;
 377                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 378                                 reg-names = "csr-reg";
 379                                 clock-output-names = "pcie0clk";
 380                         };
 381
 382                         pcie1clk: pcie1clk@1f2cc000 {
 383                                 status = "disabled";
 384                                 compatible = "apm,xgene-device-clock";
 385                                 #clock-cells = <1>;
 386                                 clocks = <&socplldiv2 0>;
 387                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 388                                 reg-names = "csr-reg";
 389                                 clock-output-names = "pcie1clk";
 390                         };
 391
 392                         pcie2clk: pcie2clk@1f2dc000 {
 393                                 status = "disabled";
 394                                 compatible = "apm,xgene-device-clock";
 395                                 #clock-cells = <1>;
 396                                 clocks = <&socplldiv2 0>;
 397                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 398                                 reg-names = "csr-reg";
 399                                 clock-output-names = "pcie2clk";
 400                         };
 401
 402                         pcie3clk: pcie3clk@1f50c000 {
 403                                 status = "disabled";
 404                                 compatible = "apm,xgene-device-clock";
 405                                 #clock-cells = <1>;
 406                                 clocks = <&socplldiv2 0>;
 407                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 408                                 reg-names = "csr-reg";
 409                                 clock-output-names = "pcie3clk";
 410                         };
 411
 412                         pcie4clk: pcie4clk@1f51c000 {
 413                                 status = "disabled";
 414                                 compatible = "apm,xgene-device-clock";
 415                                 #clock-cells = <1>;
 416                                 clocks = <&socplldiv2 0>;
 417                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 418                                 reg-names = "csr-reg";
 419                                 clock-output-names = "pcie4clk";
 420                         };
 421
 422                         dmaclk: dmaclk@1f27c000 {
 423                                 compatible = "apm,xgene-device-clock";
 424                                 #clock-cells = <1>;
 425                                 clocks = <&socplldiv2 0>;
 426                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 427                                 reg-names = "csr-reg";
 428                                 clock-output-names = "dmaclk";
 429                         };
 430                 };
 431
 432                 msi: msi@79000000 {
 433                         compatible = "apm,xgene1-msi";
 434                         msi-controller;
 435                         reg = <0x00 0x79000000 0x0 0x900000>;
 436                         interrupts = <  0x0 0x10 0x4
 437                                         0x0 0x11 0x4
 438                                         0x0 0x12 0x4
 439                                         0x0 0x13 0x4
 440                                         0x0 0x14 0x4
 441                                         0x0 0x15 0x4
 442                                         0x0 0x16 0x4
 443                                         0x0 0x17 0x4
 444                                         0x0 0x18 0x4
 445                                         0x0 0x19 0x4
 446                                         0x0 0x1a 0x4
 447                                         0x0 0x1b 0x4
 448                                         0x0 0x1c 0x4
 449                                         0x0 0x1d 0x4
 450                                         0x0 0x1e 0x4
 451                                         0x0 0x1f 0x4>;
 452                 };
 453
 454                 scu: system-clk-controller@17000000 {
 455                         compatible = "apm,xgene-scu","syscon";
 456                         reg = <0x0 0x17000000 0x0 0x400>;
 457                 };
 458
 459                 reboot: reboot@17000014 {
 460                         compatible = "syscon-reboot";
 461                         regmap = <&scu>;
 462                         offset = <0x14>;
 463                         mask = <0x1>;
 464                 };
 465
 466                 csw: csw@7e200000 {
 467                         compatible = "apm,xgene-csw", "syscon";
 468                         reg = <0x0 0x7e200000 0x0 0x1000>;
 469                 };
 470
 471                 mcba: mcba@7e700000 {
 472                         compatible = "apm,xgene-mcb", "syscon";
 473                         reg = <0x0 0x7e700000 0x0 0x1000>;
 474                 };
 475
 476                 mcbb: mcbb@7e720000 {
 477                         compatible = "apm,xgene-mcb", "syscon";
 478                         reg = <0x0 0x7e720000 0x0 0x1000>;
 479                 };
 480
 481                 efuse: efuse@1054a000 {
 482                         compatible = "apm,xgene-efuse", "syscon";
 483                         reg = <0x0 0x1054a000 0x0 0x20>;
 484                 };
 485
 486                 rb: rb@7e000000 {
 487                         compatible = "apm,xgene-rb", "syscon";
 488                         reg = <0x0 0x7e000000 0x0 0x10>;
 489                 };
 490
 491                 edac@78800000 {
 492                         compatible = "apm,xgene-edac";
 493                         #address-cells = <2>;
 494                         #size-cells = <2>;
 495                         ranges;
 496                         regmap-csw = <&csw>;
 497                         regmap-mcba = <&mcba>;
 498                         regmap-mcbb = <&mcbb>;
 499                         regmap-efuse = <&efuse>;
 500                         regmap-rb = <&rb>;
 501                         reg = <0x0 0x78800000 0x0 0x100>;
 502                         interrupts = <0x0 0x20 0x4>,
 503                                      <0x0 0x21 0x4>,
 504                                      <0x0 0x27 0x4>;
 505
 506                         edacmc@7e800000 {
 507                                 compatible = "apm,xgene-edac-mc";
 508                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 509                                 memory-controller = <0>;
 510                         };
 511
 512                         edacmc@7e840000 {
 513                                 compatible = "apm,xgene-edac-mc";
 514                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 515                                 memory-controller = <1>;
 516                         };
 517
 518                         edacmc@7e880000 {
 519                                 compatible = "apm,xgene-edac-mc";
 520                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 521                                 memory-controller = <2>;
 522                         };
 523
 524                         edacmc@7e8c0000 {
 525                                 compatible = "apm,xgene-edac-mc";
 526                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 527                                 memory-controller = <3>;
 528                         };
 529
 530                         edacpmd@7c000000 {
 531                                 compatible = "apm,xgene-edac-pmd";
 532                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 533                                 pmd-controller = <0>;
 534                         };
 535
 536                         edacpmd@7c200000 {
 537                                 compatible = "apm,xgene-edac-pmd";
 538                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 539                                 pmd-controller = <1>;
 540                         };
 541
 542                         edacpmd@7c400000 {
 543                                 compatible = "apm,xgene-edac-pmd";
 544                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 545                                 pmd-controller = <2>;
 546                         };
 547
 548                         edacpmd@7c600000 {
 549                                 compatible = "apm,xgene-edac-pmd";
 550                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 551                                 pmd-controller = <3>;
 552                         };
 553
 554                         edacl3@7e600000 {
 555                                 compatible = "apm,xgene-edac-l3";
 556                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 557                         };
 558
 559                         edacsoc@7e930000 {
 560                                 compatible = "apm,xgene-edac-soc-v1";
 561                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 562                         };
 563                 };
 564
 565                 pcie0: pcie@1f2b0000 {
 566                         status = "disabled";
 567                         device_type = "pci";
 568                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 569                         #interrupt-cells = <1>;
 570                         #size-cells = <2>;
 571                         #address-cells = <3>;
 572                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 573                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 574                         reg-names = "csr", "cfg";
 575                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 576                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 577                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 578                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 579                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 580                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 581                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 582                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 583                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 584                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 585                         dma-coherent;
 586                         clocks = <&pcie0clk 0>;
 587                         msi-parent = <&msi>;
 588                 };
 589
 590                 pcie1: pcie@1f2c0000 {
 591                         status = "disabled";
 592                         device_type = "pci";
 593                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 594                         #interrupt-cells = <1>;
 595                         #size-cells = <2>;
 596                         #address-cells = <3>;
 597                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 598                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 599                         reg-names = "csr", "cfg";
 600                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 601                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 602                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 603                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 604                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 605                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 606                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 607                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 608                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 609                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 610                         dma-coherent;
 611                         clocks = <&pcie1clk 0>;
 612                         msi-parent = <&msi>;
 613                 };
 614
 615                 pcie2: pcie@1f2d0000 {
 616                         status = "disabled";
 617                         device_type = "pci";
 618                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 619                         #interrupt-cells = <1>;
 620                         #size-cells = <2>;
 621                         #address-cells = <3>;
 622                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 623                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 624                         reg-names = "csr", "cfg";
 625                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 626                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 627                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 628                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 629                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 630                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 631                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 632                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 633                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 634                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 635                         dma-coherent;
 636                         clocks = <&pcie2clk 0>;
 637                         msi-parent = <&msi>;
 638                 };
 639
 640                 pcie3: pcie@1f500000 {
 641                         status = "disabled";
 642                         device_type = "pci";
 643                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 644                         #interrupt-cells = <1>;
 645                         #size-cells = <2>;
 646                         #address-cells = <3>;
 647                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 648                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 649                         reg-names = "csr", "cfg";
 650                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 651                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 652                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 653                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 654                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 655                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 656                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 657                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 658                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 659                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 660                         dma-coherent;
 661                         clocks = <&pcie3clk 0>;
 662                         msi-parent = <&msi>;
 663                 };
 664
 665                 pcie4: pcie@1f510000 {
 666                         status = "disabled";
 667                         device_type = "pci";
 668                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 669                         #interrupt-cells = <1>;
 670                         #size-cells = <2>;
 671                         #address-cells = <3>;
 672                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 673                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 674                         reg-names = "csr", "cfg";
 675                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 676                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 677                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 678                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 679                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 680                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 681                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 682                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 683                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 684                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 685                         dma-coherent;
 686                         clocks = <&pcie4clk 0>;
 687                         msi-parent = <&msi>;
 688                 };
 689
 690                 mailbox: mailbox@10540000 {
 691                         compatible = "apm,xgene-slimpro-mbox";
 692                         reg = <0x0 0x10540000 0x0 0xa000>;
 693                         #mbox-cells = <1>;
 694                         interrupts =    <0x0 0x0 0x4>,
 695                                         <0x0 0x1 0x4>,
 696                                         <0x0 0x2 0x4>,
 697                                         <0x0 0x3 0x4>,
 698                                         <0x0 0x4 0x4>,
 699                                         <0x0 0x5 0x4>,
 700                                         <0x0 0x6 0x4>,
 701                                         <0x0 0x7 0x4>;
 702                 };
 703
 704                 i2cslimpro {
 705                         compatible = "apm,xgene-slimpro-i2c";
 706                         mboxes = <&mailbox 0>;
 707                 };
 708
 709                 serial0: serial@1c020000 {
 710                         status = "disabled";
 711                         device_type = "serial";
 712                         compatible = "ns16550a";
 713                         reg = <0 0x1c020000 0x0 0x1000>;
 714                         reg-shift = <2>;
 715                         clock-frequency = <10000000>; /* Updated by bootloader */
 716                         interrupt-parent = <&gic>;
 717                         interrupts = <0x0 0x4c 0x4>;
 718                 };
 719
 720                 serial1: serial@1c021000 {
 721                         status = "disabled";
 722                         device_type = "serial";
 723                         compatible = "ns16550a";
 724                         reg = <0 0x1c021000 0x0 0x1000>;
 725                         reg-shift = <2>;
 726                         clock-frequency = <10000000>; /* Updated by bootloader */
 727                         interrupt-parent = <&gic>;
 728                         interrupts = <0x0 0x4d 0x4>;
 729                 };
 730
 731                 serial2: serial@1c022000 {
 732                         status = "disabled";
 733                         device_type = "serial";
 734                         compatible = "ns16550a";
 735                         reg = <0 0x1c022000 0x0 0x1000>;
 736                         reg-shift = <2>;
 737                         clock-frequency = <10000000>; /* Updated by bootloader */
 738                         interrupt-parent = <&gic>;
 739                         interrupts = <0x0 0x4e 0x4>;
 740                 };
 741
 742                 serial3: serial@1c023000 {
 743                         status = "disabled";
 744                         device_type = "serial";
 745                         compatible = "ns16550a";
 746                         reg = <0 0x1c023000 0x0 0x1000>;
 747                         reg-shift = <2>;
 748                         clock-frequency = <10000000>; /* Updated by bootloader */
 749                         interrupt-parent = <&gic>;
 750                         interrupts = <0x0 0x4f 0x4>;
 751                 };
 752
 753                 mmc0: mmc@1c000000 {
 754                         compatible = "arasan,sdhci-4.9a";
 755                         reg = <0x0 0x1c000000 0x0 0x100>;
 756                         interrupts = <0x0 0x49 0x4>;
 757                         dma-coherent;
 758                         no-1-8-v;
 759                         clock-names = "clk_xin", "clk_ahb";
 760                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 761                 };
 762
 763                 gfcgpio: gpio0@1701c000 {
 764                         compatible = "apm,xgene-gpio";
 765                         reg = <0x0 0x1701c000 0x0 0x40>;
 766                         gpio-controller;
 767                         #gpio-cells = <2>;
 768                 };
 769
 770                 dwgpio: gpio@1c024000 {
 771                         compatible = "snps,dw-apb-gpio";
 772                         reg = <0x0 0x1c024000 0x0 0x1000>;
 773                         reg-io-width = <4>;
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776
 777                         porta: gpio-controller@0 {
 778                                 compatible = "snps,dw-apb-gpio-port";
 779                                 gpio-controller;
 780                                 snps,nr-gpios = <32>;
 781                                 reg = <0>;
 782                         };
 783                 };
 784
 785                 i2c0: i2c@10512000 {
 786                         status = "disabled";
 787                         #address-cells = <1>;
 788                         #size-cells = <0>;
 789                         compatible = "snps,designware-i2c";
 790                         reg = <0x0 0x10512000 0x0 0x1000>;
 791                         interrupts = <0 0x44 0x4>;
 792                         #clock-cells = <1>;
 793                         clocks = <&ahbclk 0>;
 794                         bus_num = <0>;
 795                 };
 796
 797                 phy1: phy@1f21a000 {
 798                         compatible = "apm,xgene-phy";
 799                         reg = <0x0 0x1f21a000 0x0 0x100>;
 800                         #phy-cells = <1>;
 801                         clocks = <&sataphy1clk 0>;
 802                         status = "disabled";
 803                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 804                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 805                 };
 806
 807                 phy2: phy@1f22a000 {
 808                         compatible = "apm,xgene-phy";
 809                         reg = <0x0 0x1f22a000 0x0 0x100>;
 810                         #phy-cells = <1>;
 811                         clocks = <&sataphy2clk 0>;
 812                         status = "ok";
 813                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 814                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 815                 };
 816
 817                 phy3: phy@1f23a000 {
 818                         compatible = "apm,xgene-phy";
 819                         reg = <0x0 0x1f23a000 0x0 0x100>;
 820                         #phy-cells = <1>;
 821                         clocks = <&sataphy3clk 0>;
 822                         status = "ok";
 823                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 824                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 825                 };
 826
 827                 sata1: sata@1a000000 {
 828                         compatible = "apm,xgene-ahci";
 829                         reg = <0x0 0x1a000000 0x0 0x1000>,
 830                               <0x0 0x1f210000 0x0 0x1000>,
 831                               <0x0 0x1f21d000 0x0 0x1000>,
 832                               <0x0 0x1f21e000 0x0 0x1000>,
 833                               <0x0 0x1f217000 0x0 0x1000>;
 834                         interrupts = <0x0 0x86 0x4>;
 835                         dma-coherent;
 836                         status = "disabled";
 837                         clocks = <&sata01clk 0>;
 838                         phys = <&phy1 0>;
 839                         phy-names = "sata-phy";
 840                 };
 841
 842                 sata2: sata@1a400000 {
 843                         compatible = "apm,xgene-ahci";
 844                         reg = <0x0 0x1a400000 0x0 0x1000>,
 845                               <0x0 0x1f220000 0x0 0x1000>,
 846                               <0x0 0x1f22d000 0x0 0x1000>,
 847                               <0x0 0x1f22e000 0x0 0x1000>,
 848                               <0x0 0x1f227000 0x0 0x1000>;
 849                         interrupts = <0x0 0x87 0x4>;
 850                         dma-coherent;
 851                         status = "ok";
 852                         clocks = <&sata23clk 0>;
 853                         phys = <&phy2 0>;
 854                         phy-names = "sata-phy";
 855                 };
 856
 857                 sata3: sata@1a800000 {
 858                         compatible = "apm,xgene-ahci";
 859                         reg = <0x0 0x1a800000 0x0 0x1000>,
 860                               <0x0 0x1f230000 0x0 0x1000>,
 861                               <0x0 0x1f23d000 0x0 0x1000>,
 862                               <0x0 0x1f23e000 0x0 0x1000>;
 863                         interrupts = <0x0 0x88 0x4>;
 864                         dma-coherent;
 865                         status = "ok";
 866                         clocks = <&sata45clk 0>;
 867                         phys = <&phy3 0>;
 868                         phy-names = "sata-phy";
 869                 };
 870
 871                 /* Do not change dwusb name, coded for backward compatibility */
 872                 usb0: dwusb@19000000 {
 873                         status = "disabled";
 874                         compatible = "snps,dwc3";
 875                         reg =  <0x0 0x19000000 0x0 0x100000>;
 876                         interrupts = <0x0 0x89 0x4>;
 877                         dma-coherent;
 878                         dr_mode = "host";
 879                 };
 880
 881                 usb1: dwusb@19800000 {
 882                         status = "disabled";
 883                         compatible = "snps,dwc3";
 884                         reg =  <0x0 0x19800000 0x0 0x100000>;
 885                         interrupts = <0x0 0x8a 0x4>;
 886                         dma-coherent;
 887                         dr_mode = "host";
 888                 };
 889
 890                 sbgpio: gpio@17001000{
 891                         compatible = "apm,xgene-gpio-sb";
 892                         reg = <0x0 0x17001000 0x0 0x400>;
 893                         #gpio-cells = <2>;
 894                         gpio-controller;
 895                         interrupts =    <0x0 0x28 0x1>,
 896                                         <0x0 0x29 0x1>,
 897                                         <0x0 0x2a 0x1>,
 898                                         <0x0 0x2b 0x1>,
 899                                         <0x0 0x2c 0x1>,
 900                                         <0x0 0x2d 0x1>;
 901                         interrupt-parent = <&gic>;
 902                         #interrupt-cells = <2>;
 903                         interrupt-controller;
 904                 };
 905
 906                 rtc: rtc@10510000 {
 907                         compatible = "apm,xgene-rtc";
 908                         reg = <0x0 0x10510000 0x0 0x400>;
 909                         interrupts = <0x0 0x46 0x4>;
 910                         #clock-cells = <1>;
 911                         clocks = <&rtcclk 0>;
 912                 };
 913
 914                 menet: ethernet@17020000 {
 915                         compatible = "apm,xgene-enet";
 916                         status = "disabled";
 917                         reg = <0x0 0x17020000 0x0 0xd100>,
 918                               <0x0 0x17030000 0x0 0xc300>,
 919                               <0x0 0x10000000 0x0 0x200>;
 920                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 921                         interrupts = <0x0 0x3c 0x4>;
 922                         dma-coherent;
 923                         clocks = <&menetclk 0>;
 924                         /* mac address will be overwritten by the bootloader */
 925                         local-mac-address = [00 00 00 00 00 00];
 926                         phy-connection-type = "rgmii";
 927                         phy-handle = <&menetphy>;
 928                         mdio {
 929                                 compatible = "apm,xgene-mdio";
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 menetphy: menetphy@3 {
 933                                         compatible = "ethernet-phy-id001c.c915";
 934                                         reg = <0x3>;
 935                                 };
 936
 937                         };
 938                 };
 939
 940                 sgenet0: ethernet@1f210000 {
 941                         compatible = "apm,xgene1-sgenet";
 942                         status = "disabled";
 943                         reg = <0x0 0x1f210000 0x0 0xd100>,
 944                               <0x0 0x1f200000 0x0 0xc300>,
 945                               <0x0 0x1b000000 0x0 0x200>;
 946                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 947                         interrupts = <0x0 0xa0 0x4>,
 948                                      <0x0 0xa1 0x4>;
 949                         dma-coherent;
 950                         clocks = <&sge0clk 0>;
 951                         local-mac-address = [00 00 00 00 00 00];
 952                         phy-connection-type = "sgmii";
 953                 };
 954
 955                 sgenet1: ethernet@1f210030 {
 956                         compatible = "apm,xgene1-sgenet";
 957                         status = "disabled";
 958                         reg = <0x0 0x1f210030 0x0 0xd100>,
 959                               <0x0 0x1f200000 0x0 0xc300>,
 960                               <0x0 0x1b000000 0x0 0x8000>;
 961                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 962                         interrupts = <0x0 0xac 0x4>,
 963                                      <0x0 0xad 0x4>;
 964                         port-id = <1>;
 965                         dma-coherent;
 966                         clocks = <&sge1clk 0>;
 967                         local-mac-address = [00 00 00 00 00 00];
 968                         phy-connection-type = "sgmii";
 969                 };
 970
 971                 xgenet: ethernet@1f610000 {
 972                         compatible = "apm,xgene1-xgenet";
 973                         status = "disabled";
 974                         reg = <0x0 0x1f610000 0x0 0xd100>,
 975                               <0x0 0x1f600000 0x0 0xc300>,
 976                               <0x0 0x18000000 0x0 0x200>;
 977                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 978                         interrupts = <0x0 0x60 0x4>,
 979                                      <0x0 0x61 0x4>,
 980                                      <0x0 0x62 0x4>,
 981                                      <0x0 0x63 0x4>,
 982                                      <0x0 0x64 0x4>,
 983                                      <0x0 0x65 0x4>,
 984                                      <0x0 0x66 0x4>,
 985                                      <0x0 0x67 0x4>;
 986                         channel = <0>;
 987                         dma-coherent;
 988                         clocks = <&xge0clk 0>;
 989                         /* mac address will be overwritten by the bootloader */
 990                         local-mac-address = [00 00 00 00 00 00];
 991                         phy-connection-type = "xgmii";
 992                 };
 993
 994                 xgenet1: ethernet@1f620000 {
 995                         compatible = "apm,xgene1-xgenet";
 996                         status = "disabled";
 997                         reg = <0x0 0x1f620000 0x0 0xd100>,
 998                               <0x0 0x1f600000 0x0 0xc300>,
 999                               <0x0 0x18000000 0x0 0x8000>;
1000                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1001                         interrupts = <0x0 0x6c 0x4>,
1002                                      <0x0 0x6d 0x4>;
1003                         port-id = <1>;
1004                         dma-coherent;
1005                         clocks = <&xge1clk 0>;
1006                         /* mac address will be overwritten by the bootloader */
1007                         local-mac-address = [00 00 00 00 00 00];
1008                         phy-connection-type = "xgmii";
1009                 };
1010
1011                 rng: rng@10520000 {
1012                         compatible = "apm,xgene-rng";
1013                         reg = <0x0 0x10520000 0x0 0x100>;
1014                         interrupts = <0x0 0x41 0x4>;
1015                         clocks = <&rngpkaclk 0>;
1016                 };
1017
1018                 dma: dma@1f270000 {
1019                         compatible = "apm,xgene-storm-dma";
1020                         device_type = "dma";
1021                         reg = <0x0 0x1f270000 0x0 0x10000>,
1022                               <0x0 0x1f200000 0x0 0x10000>,
1023                               <0x0 0x1b000000 0x0 0x400000>,
1024                               <0x0 0x1054a000 0x0 0x100>;
1025                         interrupts = <0x0 0x82 0x4>,
1026                                      <0x0 0xb8 0x4>,
1027                                      <0x0 0xb9 0x4>,
1028                                      <0x0 0xba 0x4>,
1029                                      <0x0 0xbb 0x4>;
1030                         dma-coherent;
1031                         clocks = <&dmaclk 0>;
1032                 };
1033         };
1034 };