arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                         next-level-cache = <&xgene_L2_0>;
  29                 };
  30                 cpu@001 {
  31                         device_type = "cpu";
  32                         compatible = "apm,potenza", "arm,armv8";
  33                         reg = <0x0 0x001>;
  34                         enable-method = "spin-table";
  35                         cpu-release-addr = <0x1 0x0000fff8>;
  36                         next-level-cache = <&xgene_L2_0>;
  37                 };
  38                 cpu@100 {
  39                         device_type = "cpu";
  40                         compatible = "apm,potenza", "arm,armv8";
  41                         reg = <0x0 0x100>;
  42                         enable-method = "spin-table";
  43                         cpu-release-addr = <0x1 0x0000fff8>;
  44                         next-level-cache = <&xgene_L2_1>;
  45                 };
  46                 cpu@101 {
  47                         device_type = "cpu";
  48                         compatible = "apm,potenza", "arm,armv8";
  49                         reg = <0x0 0x101>;
  50                         enable-method = "spin-table";
  51                         cpu-release-addr = <0x1 0x0000fff8>;
  52                         next-level-cache = <&xgene_L2_1>;
  53                 };
  54                 cpu@200 {
  55                         device_type = "cpu";
  56                         compatible = "apm,potenza", "arm,armv8";
  57                         reg = <0x0 0x200>;
  58                         enable-method = "spin-table";
  59                         cpu-release-addr = <0x1 0x0000fff8>;
  60                         next-level-cache = <&xgene_L2_2>;
  61                 };
  62                 cpu@201 {
  63                         device_type = "cpu";
  64                         compatible = "apm,potenza", "arm,armv8";
  65                         reg = <0x0 0x201>;
  66                         enable-method = "spin-table";
  67                         cpu-release-addr = <0x1 0x0000fff8>;
  68                         next-level-cache = <&xgene_L2_2>;
  69                 };
  70                 cpu@300 {
  71                         device_type = "cpu";
  72                         compatible = "apm,potenza", "arm,armv8";
  73                         reg = <0x0 0x300>;
  74                         enable-method = "spin-table";
  75                         cpu-release-addr = <0x1 0x0000fff8>;
  76                         next-level-cache = <&xgene_L2_3>;
  77                 };
  78                 cpu@301 {
  79                         device_type = "cpu";
  80                         compatible = "apm,potenza", "arm,armv8";
  81                         reg = <0x0 0x301>;
  82                         enable-method = "spin-table";
  83                         cpu-release-addr = <0x1 0x0000fff8>;
  84                         next-level-cache = <&xgene_L2_3>;
  85                 };
  86                 xgene_L2_0: l2-cache-0 {
  87                         compatible = "cache";
  88                 };
  89                 xgene_L2_1: l2-cache-1 {
  90                         compatible = "cache";
  91                 };
  92                 xgene_L2_2: l2-cache-2 {
  93                         compatible = "cache";
  94                 };
  95                 xgene_L2_3: l2-cache-3 {
  96                         compatible = "cache";
  97                 };
  98         };
  99
 100         gic: interrupt-controller@78010000 {
 101                 compatible = "arm,cortex-a15-gic";
 102                 #interrupt-cells = <3>;
 103                 interrupt-controller;
 104                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
 105                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
 106                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
 107                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
 108                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
 109         };
 110
 111         timer {
 112                 compatible = "arm,armv8-timer";
 113                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
 114                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
 115                              <1 14 0xff01>,     /* Virt IRQ */
 116                              <1 15 0xff01>;     /* Hyp IRQ */
 117                 clock-frequency = <50000000>;
 118         };
 119
 120         pmu {
 121                 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
 122                 interrupts = <1 12 0xff04>;
 123         };
 124
 125         soc {
 126                 compatible = "simple-bus";
 127                 #address-cells = <2>;
 128                 #size-cells = <2>;
 129                 ranges;
 130                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 131
 132                 clocks {
 133                         #address-cells = <2>;
 134                         #size-cells = <2>;
 135                         ranges;
 136                         refclk: refclk {
 137                                 compatible = "fixed-clock";
 138                                 #clock-cells = <1>;
 139                                 clock-frequency = <100000000>;
 140                                 clock-output-names = "refclk";
 141                         };
 142
 143                         pcppll: pcppll@17000100 {
 144                                 compatible = "apm,xgene-pcppll-clock";
 145                                 #clock-cells = <1>;
 146                                 clocks = <&refclk 0>;
 147                                 clock-names = "pcppll";
 148                                 reg = <0x0 0x17000100 0x0 0x1000>;
 149                                 clock-output-names = "pcppll";
 150                                 type = <0>;
 151                         };
 152
 153                         socpll: socpll@17000120 {
 154                                 compatible = "apm,xgene-socpll-clock";
 155                                 #clock-cells = <1>;
 156                                 clocks = <&refclk 0>;
 157                                 clock-names = "socpll";
 158                                 reg = <0x0 0x17000120 0x0 0x1000>;
 159                                 clock-output-names = "socpll";
 160                                 type = <1>;
 161                         };
 162
 163                         socplldiv2: socplldiv2  {
 164                                 compatible = "fixed-factor-clock";
 165                                 #clock-cells = <1>;
 166                                 clocks = <&socpll 0>;
 167                                 clock-names = "socplldiv2";
 168                                 clock-mult = <1>;
 169                                 clock-div = <2>;
 170                                 clock-output-names = "socplldiv2";
 171                         };
 172
 173                         ahbclk: ahbclk@17000000 {
 174                                 compatible = "apm,xgene-device-clock";
 175                                 #clock-cells = <1>;
 176                                 clocks = <&socplldiv2 0>;
 177                                 reg = <0x0 0x17000000 0x0 0x2000>;
 178                                 reg-names = "div-reg";
 179                                 divider-offset = <0x164>;
 180                                 divider-width = <0x5>;
 181                                 divider-shift = <0x0>;
 182                                 clock-output-names = "ahbclk";
 183                         };
 184
 185                         sdioclk: sdioclk@1f2ac000 {
 186                                 compatible = "apm,xgene-device-clock";
 187                                 #clock-cells = <1>;
 188                                 clocks = <&socplldiv2 0>;
 189                                 reg = <0x0 0x1f2ac000 0x0 0x1000
 190                                         0x0 0x17000000 0x0 0x2000>;
 191                                 reg-names = "csr-reg", "div-reg";
 192                                 csr-offset = <0x0>;
 193                                 csr-mask = <0x2>;
 194                                 enable-offset = <0x8>;
 195                                 enable-mask = <0x2>;
 196                                 divider-offset = <0x178>;
 197                                 divider-width = <0x8>;
 198                                 divider-shift = <0x0>;
 199                                 clock-output-names = "sdioclk";
 200                         };
 201
 202                         qmlclk: qmlclk {
 203                                 compatible = "apm,xgene-device-clock";
 204                                 #clock-cells = <1>;
 205                                 clocks = <&socplldiv2 0>;
 206                                 clock-names = "qmlclk";
 207                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 208                                 reg-names = "csr-reg";
 209                                 clock-output-names = "qmlclk";
 210                         };
 211
 212                         ethclk: ethclk {
 213                                 compatible = "apm,xgene-device-clock";
 214                                 #clock-cells = <1>;
 215                                 clocks = <&socplldiv2 0>;
 216                                 clock-names = "ethclk";
 217                                 reg = <0x0 0x17000000 0x0 0x1000>;
 218                                 reg-names = "div-reg";
 219                                 divider-offset = <0x238>;
 220                                 divider-width = <0x9>;
 221                                 divider-shift = <0x0>;
 222                                 clock-output-names = "ethclk";
 223                         };
 224
 225                         menetclk: menetclk {
 226                                 compatible = "apm,xgene-device-clock";
 227                                 #clock-cells = <1>;
 228                                 clocks = <&ethclk 0>;
 229                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 230                                 reg-names = "csr-reg";
 231                                 clock-output-names = "menetclk";
 232                         };
 233
 234                         sge0clk: sge0clk@1f21c000 {
 235                                 compatible = "apm,xgene-device-clock";
 236                                 #clock-cells = <1>;
 237                                 clocks = <&socplldiv2 0>;
 238                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 239                                 reg-names = "csr-reg";
 240                                 csr-mask = <0xa>;
 241                                 enable-mask = <0xf>;
 242                                 clock-output-names = "sge0clk";
 243                         };
 244
 245                         xge0clk: xge0clk@1f61c000 {
 246                                 compatible = "apm,xgene-device-clock";
 247                                 #clock-cells = <1>;
 248                                 clocks = <&socplldiv2 0>;
 249                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 250                                 reg-names = "csr-reg";
 251                                 csr-mask = <0x3>;
 252                                 clock-output-names = "xge0clk";
 253                         };
 254
 255                         xge1clk: xge1clk@1f62c000 {
 256                                 compatible = "apm,xgene-device-clock";
 257                                 status = "disabled";
 258                                 #clock-cells = <1>;
 259                                 clocks = <&socplldiv2 0>;
 260                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 261                                 reg-names = "csr-reg";
 262                                 csr-mask = <0x3>;
 263                                 clock-output-names = "xge1clk";
 264                         };
 265
 266                         sataphy1clk: sataphy1clk@1f21c000 {
 267                                 compatible = "apm,xgene-device-clock";
 268                                 #clock-cells = <1>;
 269                                 clocks = <&socplldiv2 0>;
 270                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 271                                 reg-names = "csr-reg";
 272                                 clock-output-names = "sataphy1clk";
 273                                 status = "disabled";
 274                                 csr-offset = <0x4>;
 275                                 csr-mask = <0x00>;
 276                                 enable-offset = <0x0>;
 277                                 enable-mask = <0x06>;
 278                         };
 279
 280                         sataphy2clk: sataphy1clk@1f22c000 {
 281                                 compatible = "apm,xgene-device-clock";
 282                                 #clock-cells = <1>;
 283                                 clocks = <&socplldiv2 0>;
 284                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 285                                 reg-names = "csr-reg";
 286                                 clock-output-names = "sataphy2clk";
 287                                 status = "ok";
 288                                 csr-offset = <0x4>;
 289                                 csr-mask = <0x3a>;
 290                                 enable-offset = <0x0>;
 291                                 enable-mask = <0x06>;
 292                         };
 293
 294                         sataphy3clk: sataphy1clk@1f23c000 {
 295                                 compatible = "apm,xgene-device-clock";
 296                                 #clock-cells = <1>;
 297                                 clocks = <&socplldiv2 0>;
 298                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 299                                 reg-names = "csr-reg";
 300                                 clock-output-names = "sataphy3clk";
 301                                 status = "ok";
 302                                 csr-offset = <0x4>;
 303                                 csr-mask = <0x3a>;
 304                                 enable-offset = <0x0>;
 305                                 enable-mask = <0x06>;
 306                         };
 307
 308                         sata01clk: sata01clk@1f21c000 {
 309                                 compatible = "apm,xgene-device-clock";
 310                                 #clock-cells = <1>;
 311                                 clocks = <&socplldiv2 0>;
 312                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 313                                 reg-names = "csr-reg";
 314                                 clock-output-names = "sata01clk";
 315                                 csr-offset = <0x4>;
 316                                 csr-mask = <0x05>;
 317                                 enable-offset = <0x0>;
 318                                 enable-mask = <0x39>;
 319                         };
 320
 321                         sata23clk: sata23clk@1f22c000 {
 322                                 compatible = "apm,xgene-device-clock";
 323                                 #clock-cells = <1>;
 324                                 clocks = <&socplldiv2 0>;
 325                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 326                                 reg-names = "csr-reg";
 327                                 clock-output-names = "sata23clk";
 328                                 csr-offset = <0x4>;
 329                                 csr-mask = <0x05>;
 330                                 enable-offset = <0x0>;
 331                                 enable-mask = <0x39>;
 332                         };
 333
 334                         sata45clk: sata45clk@1f23c000 {
 335                                 compatible = "apm,xgene-device-clock";
 336                                 #clock-cells = <1>;
 337                                 clocks = <&socplldiv2 0>;
 338                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 339                                 reg-names = "csr-reg";
 340                                 clock-output-names = "sata45clk";
 341                                 csr-offset = <0x4>;
 342                                 csr-mask = <0x05>;
 343                                 enable-offset = <0x0>;
 344                                 enable-mask = <0x39>;
 345                         };
 346
 347                         rtcclk: rtcclk@17000000 {
 348                                 compatible = "apm,xgene-device-clock";
 349                                 #clock-cells = <1>;
 350                                 clocks = <&socplldiv2 0>;
 351                                 reg = <0x0 0x17000000 0x0 0x2000>;
 352                                 reg-names = "csr-reg";
 353                                 csr-offset = <0xc>;
 354                                 csr-mask = <0x2>;
 355                                 enable-offset = <0x10>;
 356                                 enable-mask = <0x2>;
 357                                 clock-output-names = "rtcclk";
 358                         };
 359
 360                         rngpkaclk: rngpkaclk@17000000 {
 361                                 compatible = "apm,xgene-device-clock";
 362                                 #clock-cells = <1>;
 363                                 clocks = <&socplldiv2 0>;
 364                                 reg = <0x0 0x17000000 0x0 0x2000>;
 365                                 reg-names = "csr-reg";
 366                                 csr-offset = <0xc>;
 367                                 csr-mask = <0x10>;
 368                                 enable-offset = <0x10>;
 369                                 enable-mask = <0x10>;
 370                                 clock-output-names = "rngpkaclk";
 371                         };
 372
 373                         pcie0clk: pcie0clk@1f2bc000 {
 374                                 status = "disabled";
 375                                 compatible = "apm,xgene-device-clock";
 376                                 #clock-cells = <1>;
 377                                 clocks = <&socplldiv2 0>;
 378                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 379                                 reg-names = "csr-reg";
 380                                 clock-output-names = "pcie0clk";
 381                         };
 382
 383                         pcie1clk: pcie1clk@1f2cc000 {
 384                                 status = "disabled";
 385                                 compatible = "apm,xgene-device-clock";
 386                                 #clock-cells = <1>;
 387                                 clocks = <&socplldiv2 0>;
 388                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 389                                 reg-names = "csr-reg";
 390                                 clock-output-names = "pcie1clk";
 391                         };
 392
 393                         pcie2clk: pcie2clk@1f2dc000 {
 394                                 status = "disabled";
 395                                 compatible = "apm,xgene-device-clock";
 396                                 #clock-cells = <1>;
 397                                 clocks = <&socplldiv2 0>;
 398                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 399                                 reg-names = "csr-reg";
 400                                 clock-output-names = "pcie2clk";
 401                         };
 402
 403                         pcie3clk: pcie3clk@1f50c000 {
 404                                 status = "disabled";
 405                                 compatible = "apm,xgene-device-clock";
 406                                 #clock-cells = <1>;
 407                                 clocks = <&socplldiv2 0>;
 408                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 409                                 reg-names = "csr-reg";
 410                                 clock-output-names = "pcie3clk";
 411                         };
 412
 413                         pcie4clk: pcie4clk@1f51c000 {
 414                                 status = "disabled";
 415                                 compatible = "apm,xgene-device-clock";
 416                                 #clock-cells = <1>;
 417                                 clocks = <&socplldiv2 0>;
 418                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 419                                 reg-names = "csr-reg";
 420                                 clock-output-names = "pcie4clk";
 421                         };
 422
 423                         dmaclk: dmaclk@1f27c000 {
 424                                 compatible = "apm,xgene-device-clock";
 425                                 #clock-cells = <1>;
 426                                 clocks = <&socplldiv2 0>;
 427                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 428                                 reg-names = "csr-reg";
 429                                 clock-output-names = "dmaclk";
 430                         };
 431                 };
 432
 433                 msi: msi@79000000 {
 434                         compatible = "apm,xgene1-msi";
 435                         msi-controller;
 436                         reg = <0x00 0x79000000 0x0 0x900000>;
 437                         interrupts = <  0x0 0x10 0x4
 438                                         0x0 0x11 0x4
 439                                         0x0 0x12 0x4
 440                                         0x0 0x13 0x4
 441                                         0x0 0x14 0x4
 442                                         0x0 0x15 0x4
 443                                         0x0 0x16 0x4
 444                                         0x0 0x17 0x4
 445                                         0x0 0x18 0x4
 446                                         0x0 0x19 0x4
 447                                         0x0 0x1a 0x4
 448                                         0x0 0x1b 0x4
 449                                         0x0 0x1c 0x4
 450                                         0x0 0x1d 0x4
 451                                         0x0 0x1e 0x4
 452                                         0x0 0x1f 0x4>;
 453                 };
 454
 455                 scu: system-clk-controller@17000000 {
 456                         compatible = "apm,xgene-scu","syscon";
 457                         reg = <0x0 0x17000000 0x0 0x400>;
 458                 };
 459
 460                 reboot: reboot@17000014 {
 461                         compatible = "syscon-reboot";
 462                         regmap = <&scu>;
 463                         offset = <0x14>;
 464                         mask = <0x1>;
 465                 };
 466
 467                 csw: csw@7e200000 {
 468                         compatible = "apm,xgene-csw", "syscon";
 469                         reg = <0x0 0x7e200000 0x0 0x1000>;
 470                 };
 471
 472                 mcba: mcba@7e700000 {
 473                         compatible = "apm,xgene-mcb", "syscon";
 474                         reg = <0x0 0x7e700000 0x0 0x1000>;
 475                 };
 476
 477                 mcbb: mcbb@7e720000 {
 478                         compatible = "apm,xgene-mcb", "syscon";
 479                         reg = <0x0 0x7e720000 0x0 0x1000>;
 480                 };
 481
 482                 efuse: efuse@1054a000 {
 483                         compatible = "apm,xgene-efuse", "syscon";
 484                         reg = <0x0 0x1054a000 0x0 0x20>;
 485                 };
 486
 487                 rb: rb@7e000000 {
 488                         compatible = "apm,xgene-rb", "syscon";
 489                         reg = <0x0 0x7e000000 0x0 0x10>;
 490                 };
 491
 492                 edac@78800000 {
 493                         compatible = "apm,xgene-edac";
 494                         #address-cells = <2>;
 495                         #size-cells = <2>;
 496                         ranges;
 497                         regmap-csw = <&csw>;
 498                         regmap-mcba = <&mcba>;
 499                         regmap-mcbb = <&mcbb>;
 500                         regmap-efuse = <&efuse>;
 501                         regmap-rb = <&rb>;
 502                         reg = <0x0 0x78800000 0x0 0x100>;
 503                         interrupts = <0x0 0x20 0x4>,
 504                                      <0x0 0x21 0x4>,
 505                                      <0x0 0x27 0x4>;
 506
 507                         edacmc@7e800000 {
 508                                 compatible = "apm,xgene-edac-mc";
 509                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 510                                 memory-controller = <0>;
 511                         };
 512
 513                         edacmc@7e840000 {
 514                                 compatible = "apm,xgene-edac-mc";
 515                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 516                                 memory-controller = <1>;
 517                         };
 518
 519                         edacmc@7e880000 {
 520                                 compatible = "apm,xgene-edac-mc";
 521                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 522                                 memory-controller = <2>;
 523                         };
 524
 525                         edacmc@7e8c0000 {
 526                                 compatible = "apm,xgene-edac-mc";
 527                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 528                                 memory-controller = <3>;
 529                         };
 530
 531                         edacpmd@7c000000 {
 532                                 compatible = "apm,xgene-edac-pmd";
 533                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 534                                 pmd-controller = <0>;
 535                         };
 536
 537                         edacpmd@7c200000 {
 538                                 compatible = "apm,xgene-edac-pmd";
 539                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 540                                 pmd-controller = <1>;
 541                         };
 542
 543                         edacpmd@7c400000 {
 544                                 compatible = "apm,xgene-edac-pmd";
 545                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 546                                 pmd-controller = <2>;
 547                         };
 548
 549                         edacpmd@7c600000 {
 550                                 compatible = "apm,xgene-edac-pmd";
 551                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 552                                 pmd-controller = <3>;
 553                         };
 554
 555                         edacl3@7e600000 {
 556                                 compatible = "apm,xgene-edac-l3";
 557                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 558                         };
 559
 560                         edacsoc@7e930000 {
 561                                 compatible = "apm,xgene-edac-soc-v1";
 562                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 563                         };
 564                 };
 565
 566                 pcie0: pcie@1f2b0000 {
 567                         status = "disabled";
 568                         device_type = "pci";
 569                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 570                         #interrupt-cells = <1>;
 571                         #size-cells = <2>;
 572                         #address-cells = <3>;
 573                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 574                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 575                         reg-names = "csr", "cfg";
 576                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 577                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 578                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 579                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 580                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 581                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 582                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 583                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 584                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 585                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 586                         dma-coherent;
 587                         clocks = <&pcie0clk 0>;
 588                         msi-parent = <&msi>;
 589                 };
 590
 591                 pcie1: pcie@1f2c0000 {
 592                         status = "disabled";
 593                         device_type = "pci";
 594                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 595                         #interrupt-cells = <1>;
 596                         #size-cells = <2>;
 597                         #address-cells = <3>;
 598                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 599                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 600                         reg-names = "csr", "cfg";
 601                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 602                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 603                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 604                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 605                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 606                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 607                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 608                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 609                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 610                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 611                         dma-coherent;
 612                         clocks = <&pcie1clk 0>;
 613                         msi-parent = <&msi>;
 614                 };
 615
 616                 pcie2: pcie@1f2d0000 {
 617                         status = "disabled";
 618                         device_type = "pci";
 619                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 620                         #interrupt-cells = <1>;
 621                         #size-cells = <2>;
 622                         #address-cells = <3>;
 623                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 624                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 625                         reg-names = "csr", "cfg";
 626                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 627                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 628                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 629                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 630                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 631                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 632                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 633                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 634                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 635                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 636                         dma-coherent;
 637                         clocks = <&pcie2clk 0>;
 638                         msi-parent = <&msi>;
 639                 };
 640
 641                 pcie3: pcie@1f500000 {
 642                         status = "disabled";
 643                         device_type = "pci";
 644                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 645                         #interrupt-cells = <1>;
 646                         #size-cells = <2>;
 647                         #address-cells = <3>;
 648                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 649                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 650                         reg-names = "csr", "cfg";
 651                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 652                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 653                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 654                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 655                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 656                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 657                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 658                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 659                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 660                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 661                         dma-coherent;
 662                         clocks = <&pcie3clk 0>;
 663                         msi-parent = <&msi>;
 664                 };
 665
 666                 pcie4: pcie@1f510000 {
 667                         status = "disabled";
 668                         device_type = "pci";
 669                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 670                         #interrupt-cells = <1>;
 671                         #size-cells = <2>;
 672                         #address-cells = <3>;
 673                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 674                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 675                         reg-names = "csr", "cfg";
 676                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 677                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 678                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 679                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 680                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 681                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 682                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 683                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 684                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 685                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 686                         dma-coherent;
 687                         clocks = <&pcie4clk 0>;
 688                         msi-parent = <&msi>;
 689                 };
 690
 691                 mailbox: mailbox@10540000 {
 692                         compatible = "apm,xgene-slimpro-mbox";
 693                         reg = <0x0 0x10540000 0x0 0xa000>;
 694                         #mbox-cells = <1>;
 695                         interrupts =    <0x0 0x0 0x4>,
 696                                         <0x0 0x1 0x4>,
 697                                         <0x0 0x2 0x4>,
 698                                         <0x0 0x3 0x4>,
 699                                         <0x0 0x4 0x4>,
 700                                         <0x0 0x5 0x4>,
 701                                         <0x0 0x6 0x4>,
 702                                         <0x0 0x7 0x4>;
 703                 };
 704
 705                 i2cslimpro {
 706                         compatible = "apm,xgene-slimpro-i2c";
 707                         mboxes = <&mailbox 0>;
 708                 };
 709
 710                 serial0: serial@1c020000 {
 711                         status = "disabled";
 712                         device_type = "serial";
 713                         compatible = "ns16550a";
 714                         reg = <0 0x1c020000 0x0 0x1000>;
 715                         reg-shift = <2>;
 716                         clock-frequency = <10000000>; /* Updated by bootloader */
 717                         interrupt-parent = <&gic>;
 718                         interrupts = <0x0 0x4c 0x4>;
 719                 };
 720
 721                 serial1: serial@1c021000 {
 722                         status = "disabled";
 723                         device_type = "serial";
 724                         compatible = "ns16550a";
 725                         reg = <0 0x1c021000 0x0 0x1000>;
 726                         reg-shift = <2>;
 727                         clock-frequency = <10000000>; /* Updated by bootloader */
 728                         interrupt-parent = <&gic>;
 729                         interrupts = <0x0 0x4d 0x4>;
 730                 };
 731
 732                 serial2: serial@1c022000 {
 733                         status = "disabled";
 734                         device_type = "serial";
 735                         compatible = "ns16550a";
 736                         reg = <0 0x1c022000 0x0 0x1000>;
 737                         reg-shift = <2>;
 738                         clock-frequency = <10000000>; /* Updated by bootloader */
 739                         interrupt-parent = <&gic>;
 740                         interrupts = <0x0 0x4e 0x4>;
 741                 };
 742
 743                 serial3: serial@1c023000 {
 744                         status = "disabled";
 745                         device_type = "serial";
 746                         compatible = "ns16550a";
 747                         reg = <0 0x1c023000 0x0 0x1000>;
 748                         reg-shift = <2>;
 749                         clock-frequency = <10000000>; /* Updated by bootloader */
 750                         interrupt-parent = <&gic>;
 751                         interrupts = <0x0 0x4f 0x4>;
 752                 };
 753
 754                 mmc0: mmc@1c000000 {
 755                         compatible = "arasan,sdhci-4.9a";
 756                         reg = <0x0 0x1c000000 0x0 0x100>;
 757                         interrupts = <0x0 0x49 0x4>;
 758                         dma-coherent;
 759                         no-1-8-v;
 760                         clock-names = "clk_xin", "clk_ahb";
 761                         clocks = <&sdioclk 0>, <&ahbclk 0>;
 762                 };
 763
 764                 gfcgpio: gpio0@1701c000 {
 765                         compatible = "apm,xgene-gpio";
 766                         reg = <0x0 0x1701c000 0x0 0x40>;
 767                         gpio-controller;
 768                         #gpio-cells = <2>;
 769                 };
 770
 771                 dwgpio: gpio@1c024000 {
 772                         compatible = "snps,dw-apb-gpio";
 773                         reg = <0x0 0x1c024000 0x0 0x1000>;
 774                         reg-io-width = <4>;
 775                         #address-cells = <1>;
 776                         #size-cells = <0>;
 777
 778                         porta: gpio-controller@0 {
 779                                 compatible = "snps,dw-apb-gpio-port";
 780                                 gpio-controller;
 781                                 snps,nr-gpios = <32>;
 782                                 reg = <0>;
 783                         };
 784                 };
 785
 786                 i2c0: i2c@10512000 {
 787                         status = "disabled";
 788                         #address-cells = <1>;
 789                         #size-cells = <0>;
 790                         compatible = "snps,designware-i2c";
 791                         reg = <0x0 0x10512000 0x0 0x1000>;
 792                         interrupts = <0 0x44 0x4>;
 793                         #clock-cells = <1>;
 794                         clocks = <&ahbclk 0>;
 795                         bus_num = <0>;
 796                 };
 797
 798                 phy1: phy@1f21a000 {
 799                         compatible = "apm,xgene-phy";
 800                         reg = <0x0 0x1f21a000 0x0 0x100>;
 801                         #phy-cells = <1>;
 802                         clocks = <&sataphy1clk 0>;
 803                         status = "disabled";
 804                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 805                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 806                 };
 807
 808                 phy2: phy@1f22a000 {
 809                         compatible = "apm,xgene-phy";
 810                         reg = <0x0 0x1f22a000 0x0 0x100>;
 811                         #phy-cells = <1>;
 812                         clocks = <&sataphy2clk 0>;
 813                         status = "ok";
 814                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 815                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 816                 };
 817
 818                 phy3: phy@1f23a000 {
 819                         compatible = "apm,xgene-phy";
 820                         reg = <0x0 0x1f23a000 0x0 0x100>;
 821                         #phy-cells = <1>;
 822                         clocks = <&sataphy3clk 0>;
 823                         status = "ok";
 824                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 825                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 826                 };
 827
 828                 sata1: sata@1a000000 {
 829                         compatible = "apm,xgene-ahci";
 830                         reg = <0x0 0x1a000000 0x0 0x1000>,
 831                               <0x0 0x1f210000 0x0 0x1000>,
 832                               <0x0 0x1f21d000 0x0 0x1000>,
 833                               <0x0 0x1f21e000 0x0 0x1000>,
 834                               <0x0 0x1f217000 0x0 0x1000>;
 835                         interrupts = <0x0 0x86 0x4>;
 836                         dma-coherent;
 837                         status = "disabled";
 838                         clocks = <&sata01clk 0>;
 839                         phys = <&phy1 0>;
 840                         phy-names = "sata-phy";
 841                 };
 842
 843                 sata2: sata@1a400000 {
 844                         compatible = "apm,xgene-ahci";
 845                         reg = <0x0 0x1a400000 0x0 0x1000>,
 846                               <0x0 0x1f220000 0x0 0x1000>,
 847                               <0x0 0x1f22d000 0x0 0x1000>,
 848                               <0x0 0x1f22e000 0x0 0x1000>,
 849                               <0x0 0x1f227000 0x0 0x1000>;
 850                         interrupts = <0x0 0x87 0x4>;
 851                         dma-coherent;
 852                         status = "ok";
 853                         clocks = <&sata23clk 0>;
 854                         phys = <&phy2 0>;
 855                         phy-names = "sata-phy";
 856                 };
 857
 858                 sata3: sata@1a800000 {
 859                         compatible = "apm,xgene-ahci";
 860                         reg = <0x0 0x1a800000 0x0 0x1000>,
 861                               <0x0 0x1f230000 0x0 0x1000>,
 862                               <0x0 0x1f23d000 0x0 0x1000>,
 863                               <0x0 0x1f23e000 0x0 0x1000>;
 864                         interrupts = <0x0 0x88 0x4>;
 865                         dma-coherent;
 866                         status = "ok";
 867                         clocks = <&sata45clk 0>;
 868                         phys = <&phy3 0>;
 869                         phy-names = "sata-phy";
 870                 };
 871
 872                 /* Do not change dwusb name, coded for backward compatibility */
 873                 usb0: dwusb@19000000 {
 874                         status = "disabled";
 875                         compatible = "snps,dwc3";
 876                         reg =  <0x0 0x19000000 0x0 0x100000>;
 877                         interrupts = <0x0 0x89 0x4>;
 878                         dma-coherent;
 879                         dr_mode = "host";
 880                 };
 881
 882                 usb1: dwusb@19800000 {
 883                         status = "disabled";
 884                         compatible = "snps,dwc3";
 885                         reg =  <0x0 0x19800000 0x0 0x100000>;
 886                         interrupts = <0x0 0x8a 0x4>;
 887                         dma-coherent;
 888                         dr_mode = "host";
 889                 };
 890
 891                 sbgpio: gpio@17001000{
 892                         compatible = "apm,xgene-gpio-sb";
 893                         reg = <0x0 0x17001000 0x0 0x400>;
 894                         #gpio-cells = <2>;
 895                         gpio-controller;
 896                         interrupts =    <0x0 0x28 0x1>,
 897                                         <0x0 0x29 0x1>,
 898                                         <0x0 0x2a 0x1>,
 899                                         <0x0 0x2b 0x1>,
 900                                         <0x0 0x2c 0x1>,
 901                                         <0x0 0x2d 0x1>;
 902                         interrupt-parent = <&gic>;
 903                         #interrupt-cells = <2>;
 904                         interrupt-controller;
 905                 };
 906
 907                 rtc: rtc@10510000 {
 908                         compatible = "apm,xgene-rtc";
 909                         reg = <0x0 0x10510000 0x0 0x400>;
 910                         interrupts = <0x0 0x46 0x4>;
 911                         #clock-cells = <1>;
 912                         clocks = <&rtcclk 0>;
 913                 };
 914
 915                 mdio: mdio@17020000 {
 916                         compatible = "apm,xgene-mdio-rgmii";
 917                         #address-cells = <1>;
 918                         #size-cells = <0>;
 919                         reg = <0x0 0x17020000 0x0 0xd100>;
 920                         clocks = <&menetclk 0>;
 921                 };
 922
 923                 menet: ethernet@17020000 {
 924                         compatible = "apm,xgene-enet";
 925                         status = "disabled";
 926                         reg = <0x0 0x17020000 0x0 0xd100>,
 927                               <0x0 0X17030000 0x0 0Xc300>,
 928                               <0x0 0X10000000 0x0 0X200>;
 929                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 930                         interrupts = <0x0 0x3c 0x4>;
 931                         dma-coherent;
 932                         clocks = <&menetclk 0>;
 933                         /* mac address will be overwritten by the bootloader */
 934                         local-mac-address = [00 00 00 00 00 00];
 935                         phy-connection-type = "rgmii";
 936                         phy-handle = <&menet0phy>,<&menetphy>;
 937                         mdio {
 938                                 compatible = "apm,xgene-mdio";
 939                                 #address-cells = <1>;
 940                                 #size-cells = <0>;
 941                                 menetphy: menetphy@3 {
 942                                         compatible = "ethernet-phy-id001c.c915";
 943                                         reg = <0x3>;
 944                                 };
 945
 946                         };
 947                 };
 948
 949                 sgenet0: ethernet@1f210000 {
 950                         compatible = "apm,xgene1-sgenet";
 951                         status = "disabled";
 952                         reg = <0x0 0x1f210000 0x0 0xd100>,
 953                               <0x0 0x1f200000 0x0 0Xc300>,
 954                               <0x0 0x1B000000 0x0 0X200>;
 955                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 956                         interrupts = <0x0 0xA0 0x4>,
 957                                      <0x0 0xA1 0x4>;
 958                         dma-coherent;
 959                         clocks = <&sge0clk 0>;
 960                         local-mac-address = [00 00 00 00 00 00];
 961                         phy-connection-type = "sgmii";
 962                         phy-handle = <&sgenet0phy>;
 963                 };
 964
 965                 sgenet1: ethernet@1f210030 {
 966                         compatible = "apm,xgene1-sgenet";
 967                         status = "disabled";
 968                         reg = <0x0 0x1f210030 0x0 0xd100>,
 969                               <0x0 0x1f200000 0x0 0Xc300>,
 970                               <0x0 0x1B000000 0x0 0X8000>;
 971                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 972                         interrupts = <0x0 0xAC 0x4>,
 973                                      <0x0 0xAD 0x4>;
 974                         port-id = <1>;
 975                         dma-coherent;
 976                         local-mac-address = [00 00 00 00 00 00];
 977                         phy-connection-type = "sgmii";
 978                         phy-handle = <&sgenet1phy>;
 979                 };
 980
 981                 xgenet: ethernet@1f610000 {
 982                         compatible = "apm,xgene1-xgenet";
 983                         status = "disabled";
 984                         reg = <0x0 0x1f610000 0x0 0xd100>,
 985                               <0x0 0x1f600000 0x0 0Xc300>,
 986                               <0x0 0x18000000 0x0 0X200>;
 987                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 988                         interrupts = <0x0 0x60 0x4>,
 989                                      <0x0 0x61 0x4>,
 990                                      <0x0 0x62 0x4>,
 991                                      <0x0 0x63 0x4>,
 992                                      <0x0 0x64 0x4>,
 993                                      <0x0 0x65 0x4>,
 994                                      <0x0 0x66 0x4>,
 995                                      <0x0 0x67 0x4>;
 996                         channel = <0>;
 997                         dma-coherent;
 998                         clocks = <&xge0clk 0>;
 999                         /* mac address will be overwritten by the bootloader */
1000                         local-mac-address = [00 00 00 00 00 00];
1001                         phy-connection-type = "xgmii";
1002                 };
1003
1004                 xgenet1: ethernet@1f620000 {
1005                         compatible = "apm,xgene1-xgenet";
1006                         status = "disabled";
1007                         reg = <0x0 0x1f620000 0x0 0xd100>,
1008                               <0x0 0x1f600000 0x0 0Xc300>,
1009                               <0x0 0x18000000 0x0 0X8000>;
1010                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
1011                         interrupts = <0x0 0x6C 0x4>,
1012                                      <0x0 0x6D 0x4>;
1013                         port-id = <1>;
1014                         dma-coherent;
1015                         clocks = <&xge1clk 0>;
1016                         /* mac address will be overwritten by the bootloader */
1017                         local-mac-address = [00 00 00 00 00 00];
1018                         phy-connection-type = "xgmii";
1019                 };
1020
1021                 rng: rng@10520000 {
1022                         compatible = "apm,xgene-rng";
1023                         reg = <0x0 0x10520000 0x0 0x100>;
1024                         interrupts = <0x0 0x41 0x4>;
1025                         clocks = <&rngpkaclk 0>;
1026                 };
1027
1028                 dma: dma@1f270000 {
1029                         compatible = "apm,xgene-storm-dma";
1030                         device_type = "dma";
1031                         reg = <0x0 0x1f270000 0x0 0x10000>,
1032                               <0x0 0x1f200000 0x0 0x10000>,
1033                               <0x0 0x1b000000 0x0 0x400000>,
1034                               <0x0 0x1054a000 0x0 0x100>;
1035                         interrupts = <0x0 0x82 0x4>,
1036                                      <0x0 0xb8 0x4>,
1037                                      <0x0 0xb9 0x4>,
1038                                      <0x0 0xba 0x4>,
1039                                      <0x0 0xbb 0x4>;
1040                         dma-coherent;
1041                         clocks = <&dmaclk 0>;
1042                 };
1043         };
1044 };