1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2016 Andreas Färber
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
14 compatible = "amlogic,meson-gxbb";
17 usb0_phy: phy@c0000000 {
18 compatible = "amlogic,meson-gxbb-usb2-phy";
20 reg = <0x0 0xc0000000 0x0 0x20>;
21 resets = <&reset RESET_USB_OTG>;
22 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23 clock-names = "usb_general", "usb";
27 usb1_phy: phy@c0000020 {
28 compatible = "amlogic,meson-gxbb-usb2-phy";
30 reg = <0x0 0xc0000020 0x0 0x20>;
31 resets = <&reset RESET_USB_OTG>;
32 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33 clock-names = "usb_general", "usb";
38 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39 reg = <0x0 0xc9000000 0x0 0x40000>;
40 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
44 phy-names = "usb2-phy";
50 compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51 reg = <0x0 0xc9100000 0x0 0x40000>;
52 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
56 phy-names = "usb2-phy";
64 compatible = "amlogic,aiu-gxbb", "amlogic,aiu";
65 clocks = <&clkc CLKID_AIU_GLUE>,
66 <&clkc CLKID_I2S_OUT>,
67 <&clkc CLKID_AOCLK_GATE>,
68 <&clkc CLKID_CTS_AMCLK>,
69 <&clkc CLKID_MIXER_IFACE>,
71 <&clkc CLKID_IEC958_GATE>,
72 <&clkc CLKID_CTS_MCLK_I958>,
73 <&clkc CLKID_CTS_I958>;
83 resets = <&reset RESET_AIU>;
87 pinctrl_aobus: pinctrl@14 {
88 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
94 reg = <0x0 0x00014 0x0 0x8>,
95 <0x0 0x0002c 0x0 0x4>,
96 <0x0 0x00024 0x0 0x8>;
97 reg-names = "mux", "pull", "gpio";
100 gpio-ranges = <&pinctrl_aobus 0 0 14>;
103 uart_ao_a_pins: uart_ao_a {
105 groups = "uart_tx_ao_a", "uart_rx_ao_a";
106 function = "uart_ao";
111 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
113 groups = "uart_cts_ao_a",
115 function = "uart_ao";
120 uart_ao_b_pins: uart_ao_b {
122 groups = "uart_tx_ao_b", "uart_rx_ao_b";
123 function = "uart_ao_b";
128 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
130 groups = "uart_cts_ao_b",
132 function = "uart_ao_b";
137 remote_input_ao_pins: remote_input_ao {
139 groups = "remote_input_ao";
140 function = "remote_input_ao";
145 i2c_ao_pins: i2c_ao {
147 groups = "i2c_sck_ao",
154 pwm_ao_a_3_pins: pwm_ao_a_3 {
156 groups = "pwm_ao_a_3";
157 function = "pwm_ao_a_3";
162 pwm_ao_a_6_pins: pwm_ao_a_6 {
164 groups = "pwm_ao_a_6";
165 function = "pwm_ao_a_6";
170 pwm_ao_a_12_pins: pwm_ao_a_12 {
172 groups = "pwm_ao_a_12";
173 function = "pwm_ao_a_12";
178 pwm_ao_b_pins: pwm_ao_b {
181 function = "pwm_ao_b";
186 i2s_am_clk_pins: i2s_am_clk {
188 groups = "i2s_am_clk";
189 function = "i2s_out_ao";
194 i2s_out_ao_clk_pins: i2s_out_ao_clk {
196 groups = "i2s_out_ao_clk";
197 function = "i2s_out_ao";
202 i2s_out_lr_clk_pins: i2s_out_lr_clk {
204 groups = "i2s_out_lr_clk";
205 function = "i2s_out_ao";
210 i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
212 groups = "i2s_out_ch01_ao";
213 function = "i2s_out_ao";
218 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
220 groups = "i2s_out_ch23_ao";
221 function = "i2s_out_ao";
226 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
228 groups = "i2s_out_ch45_ao";
229 function = "i2s_out_ao";
234 spdif_out_ao_6_pins: spdif_out_ao_6 {
236 groups = "spdif_out_ao_6";
237 function = "spdif_out_ao";
241 spdif_out_ao_13_pins: spdif_out_ao_13 {
243 groups = "spdif_out_ao_13";
244 function = "spdif_out_ao";
249 ao_cec_pins: ao_cec {
257 ee_cec_pins: ee_cec {
269 compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
270 reg = <0x0 0xc0000 0x0 0x40000>;
271 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "gp", "gpmmu", "pp", "pmu",
282 "pp0", "ppmmu0", "pp1", "ppmmu1",
284 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
285 clock-names = "bus", "core";
288 * Mali clocking is provided by two identical clock paths
289 * MALI_0 and MALI_1 muxed to a single clock by a glitch
290 * free mux to safely change frequency while running.
292 assigned-clocks = <&clkc CLKID_GP0_PLL>,
293 <&clkc CLKID_MALI_0_SEL>,
294 <&clkc CLKID_MALI_0>,
295 <&clkc CLKID_MALI>; /* Glitch free mux */
296 assigned-clock-parents = <0>, /* Do Nothing */
297 <&clkc CLKID_GP0_PLL>,
298 <0>, /* Do Nothing */
299 <&clkc CLKID_MALI_0>;
300 assigned-clock-rates = <744000000>,
301 <0>, /* Do Nothing */
303 <0>; /* Do Nothing */
309 compatible = "amlogic,meson-gxbb-spifc";
310 reg = <0x0 0x08c80 0x0 0x80>;
311 #address-cells = <1>;
313 clocks = <&clkc CLKID_SPI>;
319 clocks = <&clkc_AO CLKID_AO_CEC_32K>;
320 clock-names = "core";
324 compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
325 clocks = <&xtal>, <&clkc CLKID_CLK81>;
326 clock-names = "xtal", "mpeg-clk";
330 clocks = <&clkc CLKID_EFUSE>;
334 clocks = <&clkc CLKID_ETH>,
335 <&clkc CLKID_FCLK_DIV2>,
337 clock-names = "stmmaceth", "clkin0", "clkin1";
341 compatible = "amlogic,meson-gpio-intc",
342 "amlogic,meson-gxbb-gpio-intc";
347 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
348 resets = <&reset RESET_HDMITX_CAPB3>,
349 <&reset RESET_HDMI_SYSTEM_RESET>,
350 <&reset RESET_HDMI_TX>;
351 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
352 clocks = <&clkc CLKID_HDMI_PCLK>,
354 <&clkc CLKID_GCLK_VENCI_INT0>;
355 clock-names = "isfr", "iahb", "venci";
359 clkc: clock-controller {
360 compatible = "amlogic,gxbb-clkc";
363 clock-names = "xtal";
368 clocks = <&clkc CLKID_RNG0>;
369 clock-names = "core";
373 clocks = <&clkc CLKID_I2C>;
377 clocks = <&clkc CLKID_AO_I2C>;
381 clocks = <&clkc CLKID_I2C>;
385 clocks = <&clkc CLKID_I2C>;
389 pinctrl_periphs: pinctrl@4b0 {
390 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
391 #address-cells = <2>;
396 reg = <0x0 0x004b0 0x0 0x28>,
397 <0x0 0x004e8 0x0 0x14>,
398 <0x0 0x00520 0x0 0x14>,
399 <0x0 0x00430 0x0 0x40>;
400 reg-names = "mux", "pull", "pull-enable", "gpio";
403 gpio-ranges = <&pinctrl_periphs 0 0 119>;
408 groups = "emmc_nand_d07",
421 emmc_ds_pins: emmc-ds {
429 emmc_clk_gate_pins: emmc_clk_gate {
432 function = "gpio_periphs";
458 spi_ss0_pins: spi-ss0 {
466 sdcard_pins: sdcard {
468 groups = "sdcard_d0",
478 groups = "sdcard_clk";
484 sdcard_clk_gate_pins: sdcard_clk_gate {
487 function = "gpio_periphs";
510 sdio_clk_gate_pins: sdio_clk_gate {
513 function = "gpio_periphs";
518 sdio_irq_pins: sdio_irq {
526 uart_a_pins: uart_a {
528 groups = "uart_tx_a",
535 uart_a_cts_rts_pins: uart_a_cts_rts {
537 groups = "uart_cts_a",
544 uart_b_pins: uart_b {
546 groups = "uart_tx_b",
553 uart_b_cts_rts_pins: uart_b_cts_rts {
555 groups = "uart_cts_b",
562 uart_c_pins: uart_c {
564 groups = "uart_tx_c",
571 uart_c_cts_rts_pins: uart_c_cts_rts {
573 groups = "uart_cts_c",
582 groups = "i2c_sck_a",
591 groups = "i2c_sck_b",
600 groups = "i2c_sck_c",
607 eth_rgmii_pins: eth-rgmii {
628 eth_rmii_pins: eth-rmii {
644 pwm_a_x_pins: pwm_a_x {
647 function = "pwm_a_x";
652 pwm_a_y_pins: pwm_a_y {
655 function = "pwm_a_y";
684 pwm_f_x_pins: pwm_f_x {
687 function = "pwm_f_x";
692 pwm_f_y_pins: pwm_f_y {
695 function = "pwm_f_y";
700 hdmi_hpd_pins: hdmi_hpd {
703 function = "hdmi_hpd";
708 hdmi_i2c_pins: hdmi_i2c {
710 groups = "hdmi_sda", "hdmi_scl";
711 function = "hdmi_i2c";
716 i2sout_ch23_y_pins: i2sout_ch23_y {
718 groups = "i2sout_ch23_y";
719 function = "i2s_out";
724 i2sout_ch45_y_pins: i2sout_ch45_y {
726 groups = "i2sout_ch45_y";
727 function = "i2s_out";
732 i2sout_ch67_y_pins: i2sout_ch67_y {
734 groups = "i2sout_ch67_y";
735 function = "i2s_out";
740 spdif_out_y_pins: spdif_out_y {
742 groups = "spdif_out_y";
743 function = "spdif_out";
751 resets = <&reset RESET_VIU>,
753 <&reset RESET_VCBUS>,
754 <&reset RESET_BT656>,
755 <&reset RESET_DVIN_RESET>,
757 <&reset RESET_VENCI>,
758 <&reset RESET_VENCP>,
761 <&reset RESET_VENCL>,
762 <&reset RESET_VID_LOCK>;
763 clocks = <&clkc CLKID_VPU>,
765 clock-names = "vpu", "vapb";
767 * VPU clocking is provided by two identical clock paths
768 * VPU_0 and VPU_1 muxed to a single clock by a glitch
769 * free mux to safely change frequency while running.
770 * Same for VAPB but with a final gate after the glitch free mux.
772 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
774 <&clkc CLKID_VPU>, /* Glitch free mux */
775 <&clkc CLKID_VAPB_0_SEL>,
776 <&clkc CLKID_VAPB_0>,
777 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
778 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
779 <0>, /* Do Nothing */
781 <&clkc CLKID_FCLK_DIV4>,
782 <0>, /* Do Nothing */
783 <&clkc CLKID_VAPB_0>;
784 assigned-clock-rates = <0>, /* Do Nothing */
786 <0>, /* Do Nothing */
787 <0>, /* Do Nothing */
789 <0>; /* Do Nothing */
793 compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
795 <&clkc CLKID_SAR_ADC>,
796 <&clkc CLKID_SAR_ADC_CLK>,
797 <&clkc CLKID_SAR_ADC_SEL>;
798 clock-names = "clkin", "core", "adc_clk", "adc_sel";
802 clocks = <&clkc CLKID_SD_EMMC_A>,
803 <&clkc CLKID_SD_EMMC_A_CLK0>,
804 <&clkc CLKID_FCLK_DIV2>;
805 clock-names = "core", "clkin0", "clkin1";
806 resets = <&reset RESET_SD_EMMC_A>;
810 clocks = <&clkc CLKID_SD_EMMC_B>,
811 <&clkc CLKID_SD_EMMC_B_CLK0>,
812 <&clkc CLKID_FCLK_DIV2>;
813 clock-names = "core", "clkin0", "clkin1";
814 resets = <&reset RESET_SD_EMMC_B>;
818 clocks = <&clkc CLKID_SD_EMMC_C>,
819 <&clkc CLKID_SD_EMMC_C_CLK0>,
820 <&clkc CLKID_FCLK_DIV2>;
821 clock-names = "core", "clkin0", "clkin1";
822 resets = <&reset RESET_SD_EMMC_C>;
826 clocks = <&clkc CLKID_HDMI_PCLK>,
828 <&clkc CLKID_GCLK_VENCI_INT0>;
832 clocks = <&clkc CLKID_SPICC>;
833 clock-names = "core";
834 resets = <&reset RESET_PERIPHS_SPICC>;
839 clocks = <&clkc CLKID_SPI>;
843 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
844 clock-names = "xtal", "pclk", "baud";
848 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
849 clock-names = "xtal", "pclk", "baud";
853 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
854 clock-names = "xtal", "pclk", "baud";
858 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
859 clock-names = "xtal", "pclk", "baud";
863 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
864 clock-names = "xtal", "pclk", "baud";
868 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
869 power-domains = <&pwrc_vpu>;
873 compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
874 clocks = <&clkc CLKID_DOS_PARSER>,
876 <&clkc CLKID_VDEC_1>,
877 <&clkc CLKID_VDEC_HEVC>;
878 clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
879 resets = <&reset RESET_PARSER>;
880 reset-names = "esparser";