1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
15 interrupt-parent = <&gic>;
20 compatible = "amlogic,meson-gxbb-efuse";
21 clocks = <&clkc CLKID_EFUSE>;
28 compatible = "arm,psci-1.0";
37 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
38 secmon_reserved: secmon@5000000 {
39 reg = <0x0 0x05000000 0x0 0x300000>;
44 compatible = "shared-dma-pool";
46 size = <0x0 0x10000000>;
47 alignment = <0x0 0x400000>;
53 compatible = "amlogic,meson-gxbb-sm";
57 compatible = "simple-bus";
62 ethmac: ethernet@ff3f0000 {
63 compatible = "amlogic,meson-axg-dwmac",
66 reg = <0x0 0xff3f0000 0x0 0x10000>,
67 <0x0 0xff634540 0x0 0x8>;
68 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-names = "macirq";
70 clocks = <&clkc CLKID_ETH>,
71 <&clkc CLKID_FCLK_DIV2>,
73 clock-names = "stmmaceth", "clkin0", "clkin1";
74 rx-fifo-depth = <4096>;
75 tx-fifo-depth = <2048>;
81 compatible = "snps,dwmac-mdio";
86 compatible = "simple-bus";
87 reg = <0x0 0xff600000 0x0 0x200000>;
90 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
93 compatible = "amlogic,meson-g12a-dw-hdmi";
94 reg = <0x0 0x0 0x0 0x10000>;
95 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
96 resets = <&reset RESET_HDMITX_CAPB3>,
97 <&reset RESET_HDMITX_PHY>,
98 <&reset RESET_HDMITX>;
99 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
100 clocks = <&clkc CLKID_HDMI>,
101 <&clkc CLKID_HTX_PCLK>,
102 <&clkc CLKID_VPU_INTR>;
103 clock-names = "isfr", "iahb", "venci";
104 #address-cells = <1>;
106 #sound-dai-cells = <0>;
110 hdmi_tx_venc_port: port@0 {
113 hdmi_tx_in: endpoint {
114 remote-endpoint = <&hdmi_tx_out>;
119 hdmi_tx_tmds_port: port@1 {
124 apb_efuse: bus@30000 {
125 compatible = "simple-bus";
126 reg = <0x0 0x30000 0x0 0x2000>;
127 #address-cells = <2>;
129 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
132 compatible = "amlogic,meson-rng";
133 reg = <0x0 0x218 0x0 0x4>;
138 compatible = "simple-bus";
139 reg = <0x0 0x34400 0x0 0x400>;
140 #address-cells = <2>;
142 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
144 periphs_pinctrl: pinctrl@40 {
145 compatible = "amlogic,meson-g12a-periphs-pinctrl";
146 #address-cells = <2>;
151 reg = <0x0 0x40 0x0 0x4c>,
153 <0x0 0x120 0x0 0x18>,
154 <0x0 0x2c0 0x0 0x40>,
155 <0x0 0x340 0x0 0x1c>;
163 gpio-ranges = <&periphs_pinctrl 0 0 86>;
166 cec_ao_a_h_pins: cec_ao_a_h {
168 groups = "cec_ao_a_h";
169 function = "cec_ao_a_h";
174 cec_ao_b_h_pins: cec_ao_b_h {
176 groups = "cec_ao_b_h";
177 function = "cec_ao_b_h";
184 groups = "emmc_nand_d0",
195 drive-strength-microamp = <4000>;
202 drive-strength-microamp = <4000>;
206 emmc_ds_pins: emmc-ds {
208 groups = "emmc_nand_ds";
211 drive-strength-microamp = <4000>;
215 emmc_clk_gate_pins: emmc_clk_gate {
218 function = "gpio_periphs";
220 drive-strength-microamp = <4000>;
224 hdmitx_ddc_pins: hdmitx_ddc {
226 groups = "hdmitx_sda",
230 drive-strength-microamp = <4000>;
234 hdmitx_hpd_pins: hdmitx_hpd {
236 groups = "hdmitx_hpd_in";
243 i2c0_sda_c_pins: i2c0-sda-c {
245 groups = "i2c0_sda_c";
248 drive-strength-microamp = <3000>;
253 i2c0_sck_c_pins: i2c0-sck-c {
255 groups = "i2c0_sck_c";
258 drive-strength-microamp = <3000>;
262 i2c0_sda_z0_pins: i2c0-sda-z0 {
264 groups = "i2c0_sda_z0";
267 drive-strength-microamp = <3000>;
271 i2c0_sck_z1_pins: i2c0-sck-z1 {
273 groups = "i2c0_sck_z1";
276 drive-strength-microamp = <3000>;
280 i2c0_sda_z7_pins: i2c0-sda-z7 {
282 groups = "i2c0_sda_z7";
285 drive-strength-microamp = <3000>;
289 i2c0_sda_z8_pins: i2c0-sda-z8 {
291 groups = "i2c0_sda_z8";
294 drive-strength-microamp = <3000>;
298 i2c1_sda_x_pins: i2c1-sda-x {
300 groups = "i2c1_sda_x";
303 drive-strength-microamp = <3000>;
307 i2c1_sck_x_pins: i2c1-sck-x {
309 groups = "i2c1_sck_x";
312 drive-strength-microamp = <3000>;
316 i2c1_sda_h2_pins: i2c1-sda-h2 {
318 groups = "i2c1_sda_h2";
321 drive-strength-microamp = <3000>;
325 i2c1_sck_h3_pins: i2c1-sck-h3 {
327 groups = "i2c1_sck_h3";
330 drive-strength-microamp = <3000>;
334 i2c1_sda_h6_pins: i2c1-sda-h6 {
336 groups = "i2c1_sda_h6";
339 drive-strength-microamp = <3000>;
343 i2c1_sck_h7_pins: i2c1-sck-h7 {
345 groups = "i2c1_sck_h7";
348 drive-strength-microamp = <3000>;
352 i2c2_sda_x_pins: i2c2-sda-x {
354 groups = "i2c2_sda_x";
357 drive-strength-microamp = <3000>;
361 i2c2_sck_x_pins: i2c2-sck-x {
363 groups = "i2c2_sck_x";
366 drive-strength-microamp = <3000>;
370 i2c2_sda_z_pins: i2c2-sda-z {
372 groups = "i2c2_sda_z";
375 drive-strength-microamp = <3000>;
379 i2c2_sck_z_pins: i2c2-sck-z {
381 groups = "i2c2_sck_z";
384 drive-strength-microamp = <3000>;
388 i2c3_sda_h_pins: i2c3-sda-h {
390 groups = "i2c3_sda_h";
393 drive-strength-microamp = <3000>;
397 i2c3_sck_h_pins: i2c3-sck-h {
399 groups = "i2c3_sck_h";
402 drive-strength-microamp = <3000>;
406 i2c3_sda_a_pins: i2c3-sda-a {
408 groups = "i2c3_sda_a";
411 drive-strength-microamp = <3000>;
415 i2c3_sck_a_pins: i2c3-sck-a {
417 groups = "i2c3_sck_a";
420 drive-strength-microamp = <3000>;
424 mclk0_a_pins: mclk0-a {
429 drive-strength-microamp = <3000>;
433 mclk1_a_pins: mclk1-a {
438 drive-strength-microamp = <3000>;
442 mclk1_x_pins: mclk1-x {
447 drive-strength-microamp = <3000>;
451 mclk1_z_pins: mclk1-z {
456 drive-strength-microamp = <3000>;
460 pdm_din0_a_pins: pdm-din0-a {
462 groups = "pdm_din0_a";
468 pdm_din0_c_pins: pdm-din0-c {
470 groups = "pdm_din0_c";
476 pdm_din0_x_pins: pdm-din0-x {
478 groups = "pdm_din0_x";
484 pdm_din0_z_pins: pdm-din0-z {
486 groups = "pdm_din0_z";
492 pdm_din1_a_pins: pdm-din1-a {
494 groups = "pdm_din1_a";
500 pdm_din1_c_pins: pdm-din1-c {
502 groups = "pdm_din1_c";
508 pdm_din1_x_pins: pdm-din1-x {
510 groups = "pdm_din1_x";
516 pdm_din1_z_pins: pdm-din1-z {
518 groups = "pdm_din1_z";
524 pdm_din2_a_pins: pdm-din2-a {
526 groups = "pdm_din2_a";
532 pdm_din2_c_pins: pdm-din2-c {
534 groups = "pdm_din2_c";
540 pdm_din2_x_pins: pdm-din2-x {
542 groups = "pdm_din2_x";
548 pdm_din2_z_pins: pdm-din2-z {
550 groups = "pdm_din2_z";
556 pdm_din3_a_pins: pdm-din3-a {
558 groups = "pdm_din3_a";
564 pdm_din3_c_pins: pdm-din3-c {
566 groups = "pdm_din3_c";
572 pdm_din3_x_pins: pdm-din3-x {
574 groups = "pdm_din3_x";
580 pdm_din3_z_pins: pdm-din3-z {
582 groups = "pdm_din3_z";
588 pdm_dclk_a_pins: pdm-dclk-a {
590 groups = "pdm_dclk_a";
593 drive-strength-microamp = <500>;
597 pdm_dclk_c_pins: pdm-dclk-c {
599 groups = "pdm_dclk_c";
602 drive-strength-microamp = <500>;
606 pdm_dclk_x_pins: pdm-dclk-x {
608 groups = "pdm_dclk_x";
611 drive-strength-microamp = <500>;
615 pdm_dclk_z_pins: pdm-dclk-z {
617 groups = "pdm_dclk_z";
620 drive-strength-microamp = <500>;
632 pwm_b_x7_pins: pwm-b-x7 {
640 pwm_b_x19_pins: pwm-b-x19 {
642 groups = "pwm_b_x19";
648 pwm_c_c_pins: pwm-c-c {
656 pwm_c_x5_pins: pwm-c-x5 {
664 pwm_c_x8_pins: pwm-c-x8 {
672 pwm_d_x3_pins: pwm-d-x3 {
680 pwm_d_x6_pins: pwm-d-x6 {
696 pwm_f_x_pins: pwm-f-x {
704 pwm_f_h_pins: pwm-f-h {
712 sdcard_c_pins: sdcard_c {
714 groups = "sdcard_d0_c",
721 drive-strength-microamp = <4000>;
725 groups = "sdcard_clk_c";
728 drive-strength-microamp = <4000>;
732 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
735 function = "gpio_periphs";
737 drive-strength-microamp = <4000>;
741 sdcard_z_pins: sdcard_z {
743 groups = "sdcard_d0_z",
750 drive-strength-microamp = <4000>;
754 groups = "sdcard_clk_z";
757 drive-strength-microamp = <4000>;
761 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
764 function = "gpio_periphs";
766 drive-strength-microamp = <4000>;
780 drive-strength-microamp = <4000>;
784 sdio_clk_gate_pins: sdio_clk_gate {
787 function = "gpio_periphs";
789 drive-strength-microamp = <4000>;
793 spdif_in_a10_pins: spdif-in-a10 {
795 groups = "spdif_in_a10";
796 function = "spdif_in";
801 spdif_in_a12_pins: spdif-in-a12 {
803 groups = "spdif_in_a12";
804 function = "spdif_in";
809 spdif_in_h_pins: spdif-in-h {
811 groups = "spdif_in_h";
812 function = "spdif_in";
817 spdif_out_h_pins: spdif-out-h {
819 groups = "spdif_out_h";
820 function = "spdif_out";
821 drive-strength-microamp = <500>;
826 spdif_out_a11_pins: spdif-out-a11 {
828 groups = "spdif_out_a11";
829 function = "spdif_out";
830 drive-strength-microamp = <500>;
835 spdif_out_a13_pins: spdif-out-a13 {
837 groups = "spdif_out_a13";
838 function = "spdif_out";
839 drive-strength-microamp = <500>;
844 tdm_a_din0_pins: tdm-a-din0 {
846 groups = "tdm_a_din0";
853 tdm_a_din1_pins: tdm-a-din1 {
855 groups = "tdm_a_din1";
861 tdm_a_dout0_pins: tdm-a-dout0 {
863 groups = "tdm_a_dout0";
866 drive-strength-microamp = <3000>;
870 tdm_a_dout1_pins: tdm-a-dout1 {
872 groups = "tdm_a_dout1";
875 drive-strength-microamp = <3000>;
879 tdm_a_fs_pins: tdm-a-fs {
884 drive-strength-microamp = <3000>;
888 tdm_a_sclk_pins: tdm-a-sclk {
890 groups = "tdm_a_sclk";
893 drive-strength-microamp = <3000>;
897 tdm_a_slv_fs_pins: tdm-a-slv-fs {
899 groups = "tdm_a_slv_fs";
906 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
908 groups = "tdm_a_slv_sclk";
914 tdm_b_din0_pins: tdm-b-din0 {
916 groups = "tdm_b_din0";
922 tdm_b_din1_pins: tdm-b-din1 {
924 groups = "tdm_b_din1";
930 tdm_b_din2_pins: tdm-b-din2 {
932 groups = "tdm_b_din2";
938 tdm_b_din3_a_pins: tdm-b-din3-a {
940 groups = "tdm_b_din3_a";
946 tdm_b_din3_h_pins: tdm-b-din3-h {
948 groups = "tdm_b_din3_h";
954 tdm_b_dout0_pins: tdm-b-dout0 {
956 groups = "tdm_b_dout0";
959 drive-strength-microamp = <3000>;
963 tdm_b_dout1_pins: tdm-b-dout1 {
965 groups = "tdm_b_dout1";
968 drive-strength-microamp = <3000>;
972 tdm_b_dout2_pins: tdm-b-dout2 {
974 groups = "tdm_b_dout2";
977 drive-strength-microamp = <3000>;
981 tdm_b_dout3_a_pins: tdm-b-dout3-a {
983 groups = "tdm_b_dout3_a";
986 drive-strength-microamp = <3000>;
990 tdm_b_dout3_h_pins: tdm-b-dout3-h {
992 groups = "tdm_b_dout3_h";
995 drive-strength-microamp = <3000>;
999 tdm_b_fs_pins: tdm-b-fs {
1001 groups = "tdm_b_fs";
1004 drive-strength-microamp = <3000>;
1008 tdm_b_sclk_pins: tdm-b-sclk {
1010 groups = "tdm_b_sclk";
1013 drive-strength-microamp = <3000>;
1017 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1019 groups = "tdm_b_slv_fs";
1025 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1027 groups = "tdm_b_slv_sclk";
1033 tdm_c_din0_a_pins: tdm-c-din0-a {
1035 groups = "tdm_c_din0_a";
1041 tdm_c_din0_z_pins: tdm-c-din0-z {
1043 groups = "tdm_c_din0_z";
1049 tdm_c_din1_a_pins: tdm-c-din1-a {
1051 groups = "tdm_c_din1_a";
1057 tdm_c_din1_z_pins: tdm-c-din1-z {
1059 groups = "tdm_c_din1_z";
1065 tdm_c_din2_a_pins: tdm-c-din2-a {
1067 groups = "tdm_c_din2_a";
1073 eth_leds_pins: eth-leds {
1075 groups = "eth_link_led",
1084 groups = "eth_mdio",
1094 drive-strength-microamp = <4000>;
1099 eth_rgmii_pins: eth-rgmii {
1101 groups = "eth_rxd2_rgmii",
1107 drive-strength-microamp = <4000>;
1112 tdm_c_din2_z_pins: tdm-c-din2-z {
1114 groups = "tdm_c_din2_z";
1120 tdm_c_din3_a_pins: tdm-c-din3-a {
1122 groups = "tdm_c_din3_a";
1128 tdm_c_din3_z_pins: tdm-c-din3-z {
1130 groups = "tdm_c_din3_z";
1136 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1138 groups = "tdm_c_dout0_a";
1141 drive-strength-microamp = <3000>;
1145 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1147 groups = "tdm_c_dout0_z";
1150 drive-strength-microamp = <3000>;
1154 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1156 groups = "tdm_c_dout1_a";
1159 drive-strength-microamp = <3000>;
1163 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1165 groups = "tdm_c_dout1_z";
1168 drive-strength-microamp = <3000>;
1172 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1174 groups = "tdm_c_dout2_a";
1177 drive-strength-microamp = <3000>;
1181 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1183 groups = "tdm_c_dout2_z";
1186 drive-strength-microamp = <3000>;
1190 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1192 groups = "tdm_c_dout3_a";
1195 drive-strength-microamp = <3000>;
1199 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1201 groups = "tdm_c_dout3_z";
1204 drive-strength-microamp = <3000>;
1208 tdm_c_fs_a_pins: tdm-c-fs-a {
1210 groups = "tdm_c_fs_a";
1213 drive-strength-microamp = <3000>;
1217 tdm_c_fs_z_pins: tdm-c-fs-z {
1219 groups = "tdm_c_fs_z";
1222 drive-strength-microamp = <3000>;
1226 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1228 groups = "tdm_c_sclk_a";
1231 drive-strength-microamp = <3000>;
1235 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1237 groups = "tdm_c_sclk_z";
1240 drive-strength-microamp = <3000>;
1244 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1246 groups = "tdm_c_slv_fs_a";
1252 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1254 groups = "tdm_c_slv_fs_z";
1260 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1262 groups = "tdm_c_slv_sclk_a";
1268 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1270 groups = "tdm_c_slv_sclk_z";
1276 uart_a_pins: uart-a {
1278 groups = "uart_a_tx",
1280 function = "uart_a";
1285 uart_a_cts_rts_pins: uart-a-cts-rts {
1287 groups = "uart_a_cts",
1289 function = "uart_a";
1294 uart_b_pins: uart-b {
1296 groups = "uart_b_tx",
1298 function = "uart_b";
1303 uart_c_pins: uart-c {
1305 groups = "uart_c_tx",
1307 function = "uart_c";
1312 uart_c_cts_rts_pins: uart-c-cts-rts {
1314 groups = "uart_c_cts",
1316 function = "uart_c";
1323 usb2_phy0: phy@36000 {
1324 compatible = "amlogic,g12a-usb2-phy";
1325 reg = <0x0 0x36000 0x0 0x2000>;
1327 clock-names = "xtal";
1328 resets = <&reset RESET_USB_PHY20>;
1329 reset-names = "phy";
1334 compatible = "simple-bus";
1335 reg = <0x0 0x38000 0x0 0x400>;
1336 #address-cells = <2>;
1338 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1340 canvas: video-lut@48 {
1341 compatible = "amlogic,canvas";
1342 reg = <0x0 0x48 0x0 0x14>;
1346 usb2_phy1: phy@3a000 {
1347 compatible = "amlogic,g12a-usb2-phy";
1348 reg = <0x0 0x3a000 0x0 0x2000>;
1350 clock-names = "xtal";
1351 resets = <&reset RESET_USB_PHY21>;
1352 reset-names = "phy";
1357 compatible = "simple-bus";
1358 reg = <0x0 0x3c000 0x0 0x1400>;
1359 #address-cells = <2>;
1361 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1363 hhi: system-controller@0 {
1364 compatible = "amlogic,meson-gx-hhi-sysctrl",
1365 "simple-mfd", "syscon";
1366 reg = <0 0 0 0x400>;
1368 clkc: clock-controller {
1369 compatible = "amlogic,g12a-clkc";
1372 clock-names = "xtal";
1375 pwrc: power-controller {
1376 compatible = "amlogic,meson-g12a-pwrc";
1377 #power-domain-cells = <1>;
1378 amlogic,ao-sysctrl = <&rti>;
1379 resets = <&reset RESET_VIU>,
1380 <&reset RESET_VENC>,
1381 <&reset RESET_VCBUS>,
1382 <&reset RESET_BT656>,
1383 <&reset RESET_RDMA>,
1384 <&reset RESET_VENCI>,
1385 <&reset RESET_VENCP>,
1386 <&reset RESET_VDAC>,
1387 <&reset RESET_VDI6>,
1388 <&reset RESET_VENCL>,
1389 <&reset RESET_VID_LOCK>;
1390 reset-names = "viu", "venc", "vcbus", "bt656",
1391 "rdma", "venci", "vencp", "vdac",
1392 "vdi6", "vencl", "vid_lock";
1393 clocks = <&clkc CLKID_VPU>,
1395 clock-names = "vpu", "vapb";
1397 * VPU clocking is provided by two identical clock paths
1398 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1399 * free mux to safely change frequency while running.
1400 * Same for VAPB but with a final gate after the glitch free mux.
1402 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1403 <&clkc CLKID_VPU_0>,
1404 <&clkc CLKID_VPU>, /* Glitch free mux */
1405 <&clkc CLKID_VAPB_0_SEL>,
1406 <&clkc CLKID_VAPB_0>,
1407 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1408 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1409 <0>, /* Do Nothing */
1410 <&clkc CLKID_VPU_0>,
1411 <&clkc CLKID_FCLK_DIV4>,
1412 <0>, /* Do Nothing */
1413 <&clkc CLKID_VAPB_0>;
1414 assigned-clock-rates = <0>, /* Do Nothing */
1416 <0>, /* Do Nothing */
1417 <0>, /* Do Nothing */
1419 <0>; /* Do Nothing */
1424 usb3_pcie_phy: phy@46000 {
1425 compatible = "amlogic,g12a-usb3-pcie-phy";
1426 reg = <0x0 0x46000 0x0 0x2000>;
1427 clocks = <&clkc CLKID_PCIE_PLL>;
1428 clock-names = "ref_clk";
1429 resets = <&reset RESET_PCIE_PHY>;
1430 reset-names = "phy";
1431 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1432 assigned-clock-rates = <100000000>;
1436 eth_phy: mdio-multiplexer@4c000 {
1437 compatible = "amlogic,g12a-mdio-mux";
1438 reg = <0x0 0x4c000 0x0 0xa4>;
1439 clocks = <&clkc CLKID_ETH_PHY>,
1441 <&clkc CLKID_MPLL_50M>;
1442 clock-names = "pclk", "clkin0", "clkin1";
1443 mdio-parent-bus = <&mdio0>;
1444 #address-cells = <1>;
1449 #address-cells = <1>;
1455 #address-cells = <1>;
1458 internal_ephy: ethernet_phy@8 {
1459 compatible = "ethernet-phy-id0180.3301",
1460 "ethernet-phy-ieee802.3-c22";
1461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1469 aobus: bus@ff800000 {
1470 compatible = "simple-bus";
1471 reg = <0x0 0xff800000 0x0 0x100000>;
1472 #address-cells = <2>;
1474 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1477 compatible = "amlogic,meson-gx-ao-sysctrl",
1478 "simple-mfd", "syscon";
1479 reg = <0x0 0x0 0x0 0x100>;
1480 #address-cells = <2>;
1482 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1484 clkc_AO: clock-controller {
1485 compatible = "amlogic,meson-g12a-aoclkc";
1488 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1489 clock-names = "xtal", "mpeg-clk";
1492 ao_pinctrl: pinctrl@14 {
1493 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1494 #address-cells = <2>;
1499 reg = <0x0 0x14 0x0 0x8>,
1501 <0x0 0x24 0x0 0x14>;
1507 gpio-ranges = <&ao_pinctrl 0 0 15>;
1510 i2c_ao_sck_pins: i2c_ao_sck_pins {
1512 groups = "i2c_ao_sck";
1513 function = "i2c_ao";
1515 drive-strength-microamp = <3000>;
1519 i2c_ao_sda_pins: i2c_ao_sda {
1521 groups = "i2c_ao_sda";
1522 function = "i2c_ao";
1524 drive-strength-microamp = <3000>;
1528 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1530 groups = "i2c_ao_sck_e";
1531 function = "i2c_ao";
1533 drive-strength-microamp = <3000>;
1537 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1539 groups = "i2c_ao_sda_e";
1540 function = "i2c_ao";
1542 drive-strength-microamp = <3000>;
1546 mclk0_ao_pins: mclk0-ao {
1548 groups = "mclk0_ao";
1549 function = "mclk0_ao";
1551 drive-strength-microamp = <3000>;
1555 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1557 groups = "tdm_ao_b_din0";
1558 function = "tdm_ao_b";
1563 spdif_ao_out_pins: spdif-ao-out {
1565 groups = "spdif_ao_out";
1566 function = "spdif_ao_out";
1567 drive-strength-microamp = <500>;
1572 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1574 groups = "tdm_ao_b_din1";
1575 function = "tdm_ao_b";
1580 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1582 groups = "tdm_ao_b_din2";
1583 function = "tdm_ao_b";
1588 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1590 groups = "tdm_ao_b_dout0";
1591 function = "tdm_ao_b";
1593 drive-strength-microamp = <3000>;
1597 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1599 groups = "tdm_ao_b_dout1";
1600 function = "tdm_ao_b";
1602 drive-strength-microamp = <3000>;
1606 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1608 groups = "tdm_ao_b_dout2";
1609 function = "tdm_ao_b";
1611 drive-strength-microamp = <3000>;
1615 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1617 groups = "tdm_ao_b_fs";
1618 function = "tdm_ao_b";
1620 drive-strength-microamp = <3000>;
1624 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1626 groups = "tdm_ao_b_sclk";
1627 function = "tdm_ao_b";
1629 drive-strength-microamp = <3000>;
1633 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1635 groups = "tdm_ao_b_slv_fs";
1636 function = "tdm_ao_b";
1641 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1643 groups = "tdm_ao_b_slv_sclk";
1644 function = "tdm_ao_b";
1649 uart_ao_a_pins: uart-a-ao {
1651 groups = "uart_ao_a_tx",
1653 function = "uart_ao_a";
1658 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1660 groups = "uart_ao_a_cts",
1662 function = "uart_ao_a";
1667 pwm_a_e_pins: pwm-a-e {
1670 function = "pwm_a_e";
1675 pwm_ao_a_pins: pwm-ao-a {
1677 groups = "pwm_ao_a";
1678 function = "pwm_ao_a";
1683 pwm_ao_b_pins: pwm-ao-b {
1685 groups = "pwm_ao_b";
1686 function = "pwm_ao_b";
1691 pwm_ao_c_4_pins: pwm-ao-c-4 {
1693 groups = "pwm_ao_c_4";
1694 function = "pwm_ao_c";
1699 pwm_ao_c_6_pins: pwm-ao-c-6 {
1701 groups = "pwm_ao_c_6";
1702 function = "pwm_ao_c";
1707 pwm_ao_d_5_pins: pwm-ao-d-5 {
1709 groups = "pwm_ao_d_5";
1710 function = "pwm_ao_d";
1715 pwm_ao_d_10_pins: pwm-ao-d-10 {
1717 groups = "pwm_ao_d_10";
1718 function = "pwm_ao_d";
1723 pwm_ao_d_e_pins: pwm-ao-d-e {
1725 groups = "pwm_ao_d_e";
1726 function = "pwm_ao_d";
1730 remote_input_ao_pins: remote-input-ao {
1732 groups = "remote_ao_input";
1733 function = "remote_ao_input";
1741 compatible = "amlogic,meson-vrtc";
1742 reg = <0x0 0x000a8 0x0 0x4>;
1746 compatible = "amlogic,meson-gx-ao-cec";
1747 reg = <0x0 0x00100 0x0 0x14>;
1748 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
1749 clocks = <&clkc_AO CLKID_AO_CEC>;
1750 clock-names = "core";
1751 status = "disabled";
1754 sec_AO: ao-secure@140 {
1755 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1756 reg = <0x0 0x140 0x0 0x140>;
1757 amlogic,has-chip-id;
1761 compatible = "amlogic,meson-g12a-ao-cec";
1762 reg = <0x0 0x00280 0x0 0x1c>;
1763 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
1764 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
1765 clock-names = "oscin";
1766 status = "disabled";
1769 pwm_AO_cd: pwm@2000 {
1770 compatible = "amlogic,meson-g12a-ao-pwm-cd";
1771 reg = <0x0 0x2000 0x0 0x20>;
1773 status = "disabled";
1776 uart_AO: serial@3000 {
1777 compatible = "amlogic,meson-gx-uart",
1778 "amlogic,meson-ao-uart";
1779 reg = <0x0 0x3000 0x0 0x18>;
1780 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1781 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
1782 clock-names = "xtal", "pclk", "baud";
1783 status = "disabled";
1786 uart_AO_B: serial@4000 {
1787 compatible = "amlogic,meson-gx-uart",
1788 "amlogic,meson-ao-uart";
1789 reg = <0x0 0x4000 0x0 0x18>;
1790 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1791 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1792 clock-names = "xtal", "pclk", "baud";
1793 status = "disabled";
1797 compatible = "amlogic,meson-axg-i2c";
1798 status = "disabled";
1799 reg = <0x0 0x05000 0x0 0x20>;
1800 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1801 #address-cells = <1>;
1803 clocks = <&clkc CLKID_I2C>;
1806 pwm_AO_ab: pwm@7000 {
1807 compatible = "amlogic,meson-g12a-ao-pwm-ab";
1808 reg = <0x0 0x7000 0x0 0x20>;
1810 status = "disabled";
1814 compatible = "amlogic,meson-gxbb-ir";
1815 reg = <0x0 0x8000 0x0 0x20>;
1816 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1817 status = "disabled";
1821 compatible = "amlogic,meson-g12a-saradc",
1822 "amlogic,meson-saradc";
1823 reg = <0x0 0x9000 0x0 0x48>;
1824 #io-channel-cells = <1>;
1825 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
1827 <&clkc_AO CLKID_AO_SAR_ADC>,
1828 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1829 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1830 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1831 status = "disabled";
1836 compatible = "amlogic,meson-g12a-vpu";
1837 reg = <0x0 0xff900000 0x0 0x100000>,
1838 <0x0 0xff63c000 0x0 0x1000>;
1839 reg-names = "vpu", "hhi";
1840 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
1841 #address-cells = <1>;
1843 amlogic,canvas = <&canvas>;
1845 /* CVBS VDAC output port */
1846 cvbs_vdac_port: port@0 {
1850 /* HDMI-TX output port */
1851 hdmi_tx_port: port@1 {
1854 hdmi_tx_out: endpoint {
1855 remote-endpoint = <&hdmi_tx_in>;
1860 gic: interrupt-controller@ffc01000 {
1861 compatible = "arm,gic-400";
1862 reg = <0x0 0xffc01000 0 0x1000>,
1863 <0x0 0xffc02000 0 0x2000>,
1864 <0x0 0xffc04000 0 0x2000>,
1865 <0x0 0xffc06000 0 0x2000>;
1866 interrupt-controller;
1867 interrupts = <GIC_PPI 9
1868 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1869 #interrupt-cells = <3>;
1870 #address-cells = <0>;
1873 cbus: bus@ffd00000 {
1874 compatible = "simple-bus";
1875 reg = <0x0 0xffd00000 0x0 0x100000>;
1876 #address-cells = <2>;
1878 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
1880 reset: reset-controller@1004 {
1881 compatible = "amlogic,meson-axg-reset";
1882 reg = <0x0 0x1004 0x0 0x9c>;
1886 gpio_intc: interrupt-controller@f080 {
1887 compatible = "amlogic,meson-g12a-gpio-intc",
1888 "amlogic,meson-gpio-intc";
1889 reg = <0x0 0xf080 0x0 0x10>;
1890 interrupt-controller;
1891 #interrupt-cells = <2>;
1892 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1896 compatible = "amlogic,meson-g12a-ee-pwm";
1897 reg = <0x0 0x19000 0x0 0x20>;
1899 status = "disabled";
1903 compatible = "amlogic,meson-g12a-ee-pwm";
1904 reg = <0x0 0x1a000 0x0 0x20>;
1906 status = "disabled";
1910 compatible = "amlogic,meson-g12a-ee-pwm";
1911 reg = <0x0 0x1b000 0x0 0x20>;
1913 status = "disabled";
1917 compatible = "amlogic,meson-axg-i2c";
1918 status = "disabled";
1919 reg = <0x0 0x1c000 0x0 0x20>;
1920 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1921 #address-cells = <1>;
1923 clocks = <&clkc CLKID_I2C>;
1927 compatible = "amlogic,meson-axg-i2c";
1928 status = "disabled";
1929 reg = <0x0 0x1d000 0x0 0x20>;
1930 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1931 #address-cells = <1>;
1933 clocks = <&clkc CLKID_I2C>;
1937 compatible = "amlogic,meson-axg-i2c";
1938 status = "disabled";
1939 reg = <0x0 0x1e000 0x0 0x20>;
1940 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1941 #address-cells = <1>;
1943 clocks = <&clkc CLKID_I2C>;
1947 compatible = "amlogic,meson-axg-i2c";
1948 status = "disabled";
1949 reg = <0x0 0x1f000 0x0 0x20>;
1950 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1951 #address-cells = <1>;
1953 clocks = <&clkc CLKID_I2C>;
1956 clk_msr: clock-measure@18000 {
1957 compatible = "amlogic,meson-g12a-clk-measure";
1958 reg = <0x0 0x18000 0x0 0x10>;
1961 uart_C: serial@22000 {
1962 compatible = "amlogic,meson-gx-uart";
1963 reg = <0x0 0x22000 0x0 0x18>;
1964 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
1965 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
1966 clock-names = "xtal", "pclk", "baud";
1967 status = "disabled";
1970 uart_B: serial@23000 {
1971 compatible = "amlogic,meson-gx-uart";
1972 reg = <0x0 0x23000 0x0 0x18>;
1973 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1974 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1975 clock-names = "xtal", "pclk", "baud";
1976 status = "disabled";
1979 uart_A: serial@24000 {
1980 compatible = "amlogic,meson-gx-uart";
1981 reg = <0x0 0x24000 0x0 0x18>;
1982 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1983 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1984 clock-names = "xtal", "pclk", "baud";
1985 status = "disabled";
1989 sd_emmc_a: sd@ffe03000 {
1990 compatible = "amlogic,meson-axg-mmc";
1991 reg = <0x0 0xffe03000 0x0 0x800>;
1992 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
1993 status = "disabled";
1994 clocks = <&clkc CLKID_SD_EMMC_A>,
1995 <&clkc CLKID_SD_EMMC_A_CLK0>,
1996 <&clkc CLKID_FCLK_DIV2>;
1997 clock-names = "core", "clkin0", "clkin1";
1998 resets = <&reset RESET_SD_EMMC_A>;
2001 sd_emmc_b: sd@ffe05000 {
2002 compatible = "amlogic,meson-axg-mmc";
2003 reg = <0x0 0xffe05000 0x0 0x800>;
2004 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2005 status = "disabled";
2006 clocks = <&clkc CLKID_SD_EMMC_B>,
2007 <&clkc CLKID_SD_EMMC_B_CLK0>,
2008 <&clkc CLKID_FCLK_DIV2>;
2009 clock-names = "core", "clkin0", "clkin1";
2010 resets = <&reset RESET_SD_EMMC_B>;
2013 sd_emmc_c: mmc@ffe07000 {
2014 compatible = "amlogic,meson-axg-mmc";
2015 reg = <0x0 0xffe07000 0x0 0x800>;
2016 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2017 status = "disabled";
2018 clocks = <&clkc CLKID_SD_EMMC_C>,
2019 <&clkc CLKID_SD_EMMC_C_CLK0>,
2020 <&clkc CLKID_FCLK_DIV2>;
2021 clock-names = "core", "clkin0", "clkin1";
2022 resets = <&reset RESET_SD_EMMC_C>;
2026 status = "disabled";
2027 compatible = "amlogic,meson-g12a-usb-ctrl";
2028 reg = <0x0 0xffe09000 0x0 0xa0>;
2029 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2030 #address-cells = <2>;
2034 clocks = <&clkc CLKID_USB>;
2035 resets = <&reset RESET_USB>;
2039 phys = <&usb2_phy0>, <&usb2_phy1>,
2040 <&usb3_pcie_phy PHY_TYPE_USB3>;
2041 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2043 dwc2: usb@ff400000 {
2044 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2045 reg = <0x0 0xff400000 0x0 0x40000>;
2046 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2047 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2048 clock-names = "ddr";
2049 phys = <&usb2_phy1>;
2050 phy-names = "usb2-phy";
2051 dr_mode = "peripheral";
2052 g-rx-fifo-size = <192>;
2053 g-np-tx-fifo-size = <128>;
2054 g-tx-fifo-size = <128 128 16 16 16>;
2057 dwc3: usb@ff500000 {
2058 compatible = "snps,dwc3";
2059 reg = <0x0 0xff500000 0x0 0x100000>;
2060 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2062 snps,dis_u2_susphy_quirk;
2063 snps,quirk-frame-length-adjustment;
2067 mali: gpu@ffe40000 {
2068 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2069 reg = <0x0 0xffe40000 0x0 0x40000>;
2070 interrupt-parent = <&gic>;
2071 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
2072 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2073 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
2074 interrupt-names = "gpu", "mmu", "job";
2075 clocks = <&clkc CLKID_MALI>;
2076 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2079 * Mali clocking is provided by two identical clock paths
2080 * MALI_0 and MALI_1 muxed to a single clock by a glitch
2081 * free mux to safely change frequency while running.
2083 assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
2084 <&clkc CLKID_MALI_0>,
2085 <&clkc CLKID_MALI>; /* Glitch free mux */
2086 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
2087 <0>, /* Do Nothing */
2088 <&clkc CLKID_MALI_0>;
2089 assigned-clock-rates = <0>, /* Do Nothing */
2091 <0>; /* Do Nothing */
2096 compatible = "arm,armv8-timer";
2097 interrupts = <GIC_PPI 13
2098 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2100 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2102 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2104 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2105 arm,no-tick-in-suspend;
2109 compatible = "fixed-clock";
2110 clock-frequency = <24000000>;
2111 clock-output-names = "xtal";