1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
25 simplefb_cvbs: framebuffer-cvbs {
26 compatible = "amlogic,simple-framebuffer",
28 amlogic,pipeline = "vpu-cvbs";
29 clocks = <&clkc CLKID_HDMI>,
30 <&clkc CLKID_HTX_PCLK>,
31 <&clkc CLKID_VPU_INTR>;
35 simplefb_hdmi: framebuffer-hdmi {
36 compatible = "amlogic,simple-framebuffer",
38 amlogic,pipeline = "vpu-hdmi";
39 clocks = <&clkc CLKID_HDMI>,
40 <&clkc CLKID_HTX_PCLK>,
41 <&clkc CLKID_VPU_INTR>;
47 compatible = "amlogic,meson-gxbb-efuse";
48 clocks = <&clkc CLKID_EFUSE>;
52 secure-monitor = <&sm>;
55 gpu_opp_table: gpu-opp-table {
56 compatible = "operating-points-v2";
59 opp-hz = /bits/ 64 <124999998>;
60 opp-microvolt = <800000>;
63 opp-hz = /bits/ 64 <249999996>;
64 opp-microvolt = <800000>;
67 opp-hz = /bits/ 64 <285714281>;
68 opp-microvolt = <800000>;
71 opp-hz = /bits/ 64 <399999994>;
72 opp-microvolt = <800000>;
75 opp-hz = /bits/ 64 <499999992>;
76 opp-microvolt = <800000>;
79 opp-hz = /bits/ 64 <666666656>;
80 opp-microvolt = <800000>;
83 opp-hz = /bits/ 64 <799999987>;
84 opp-microvolt = <800000>;
89 compatible = "arm,psci-1.0";
98 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */
99 secmon_reserved: secmon@5000000 {
100 reg = <0x0 0x05000000 0x0 0x300000>;
105 compatible = "shared-dma-pool";
107 size = <0x0 0x10000000>;
108 alignment = <0x0 0x400000>;
114 compatible = "amlogic,meson-gxbb-sm";
118 compatible = "simple-bus";
119 #address-cells = <2>;
123 pcie: pcie@fc000000 {
124 compatible = "amlogic,g12a-pcie", "snps,dw-pcie";
125 reg = <0x0 0xfc000000 0x0 0x400000
126 0x0 0xff648000 0x0 0x2000
127 0x0 0xfc400000 0x0 0x200000>;
128 reg-names = "elbi", "cfg", "config";
129 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
130 #interrupt-cells = <1>;
131 interrupt-map-mask = <0 0 0 0>;
132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
133 bus-range = <0x0 0xff>;
134 #address-cells = <3>;
137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000
138 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>;
140 clocks = <&clkc CLKID_PCIE_PHY
141 &clkc CLKID_PCIE_COMB
142 &clkc CLKID_PCIE_PLL>;
143 clock-names = "general",
146 resets = <&reset RESET_PCIE_CTRL_A>,
147 <&reset RESET_PCIE_APB>;
148 reset-names = "port",
151 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>;
157 cpu_thermal: cpu-thermal {
158 polling-delay = <1000>;
159 polling-delay-passive = <100>;
160 thermal-sensors = <&cpu_temp>;
163 cpu_passive: cpu-passive {
164 temperature = <85000>; /* millicelsius */
165 hysteresis = <2000>; /* millicelsius */
170 temperature = <95000>; /* millicelsius */
171 hysteresis = <2000>; /* millicelsius */
175 cpu_critical: cpu-critical {
176 temperature = <110000>; /* millicelsius */
177 hysteresis = <2000>; /* millicelsius */
183 ddr_thermal: ddr-thermal {
184 polling-delay = <1000>;
185 polling-delay-passive = <100>;
186 thermal-sensors = <&ddr_temp>;
189 ddr_passive: ddr-passive {
190 temperature = <85000>; /* millicelsius */
191 hysteresis = <2000>; /* millicelsius */
195 ddr_critical: ddr-critical {
196 temperature = <110000>; /* millicelsius */
197 hysteresis = <2000>; /* millicelsius */
204 trip = <&ddr_passive>;
205 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 ethmac: ethernet@ff3f0000 {
212 compatible = "amlogic,meson-axg-dwmac",
215 reg = <0x0 0xff3f0000 0x0 0x10000>,
216 <0x0 0xff634540 0x0 0x8>;
217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
218 interrupt-names = "macirq";
219 clocks = <&clkc CLKID_ETH>,
220 <&clkc CLKID_FCLK_DIV2>,
222 <&clkc CLKID_FCLK_DIV2>;
223 clock-names = "stmmaceth", "clkin0", "clkin1",
225 rx-fifo-depth = <4096>;
226 tx-fifo-depth = <2048>;
230 #address-cells = <1>;
232 compatible = "snps,dwmac-mdio";
237 compatible = "simple-bus";
238 reg = <0x0 0xff600000 0x0 0x200000>;
239 #address-cells = <2>;
241 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>;
244 compatible = "amlogic,meson-g12a-dw-hdmi";
245 reg = <0x0 0x0 0x0 0x10000>;
246 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
247 resets = <&reset RESET_HDMITX_CAPB3>,
248 <&reset RESET_HDMITX_PHY>,
249 <&reset RESET_HDMITX>;
250 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
251 clocks = <&clkc CLKID_HDMI>,
252 <&clkc CLKID_HTX_PCLK>,
253 <&clkc CLKID_VPU_INTR>;
254 clock-names = "isfr", "iahb", "venci";
255 #address-cells = <1>;
257 #sound-dai-cells = <0>;
261 hdmi_tx_venc_port: port@0 {
264 hdmi_tx_in: endpoint {
265 remote-endpoint = <&hdmi_tx_out>;
270 hdmi_tx_tmds_port: port@1 {
275 apb_efuse: bus@30000 {
276 compatible = "simple-bus";
277 reg = <0x0 0x30000 0x0 0x2000>;
278 #address-cells = <2>;
280 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>;
283 compatible = "amlogic,meson-rng";
284 reg = <0x0 0x218 0x0 0x4>;
288 acodec: audio-controller@32000 {
289 compatible = "amlogic,t9015";
290 reg = <0x0 0x32000 0x0 0x14>;
291 #sound-dai-cells = <0>;
292 sound-name-prefix = "ACODEC";
293 clocks = <&clkc CLKID_AUDIO_CODEC>;
294 clock-names = "pclk";
295 resets = <&reset RESET_AUDIO_CODEC>;
300 compatible = "simple-bus";
301 reg = <0x0 0x34400 0x0 0x400>;
302 #address-cells = <2>;
304 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>;
306 periphs_pinctrl: pinctrl@40 {
307 compatible = "amlogic,meson-g12a-periphs-pinctrl";
308 #address-cells = <2>;
313 reg = <0x0 0x40 0x0 0x4c>,
315 <0x0 0x120 0x0 0x18>,
316 <0x0 0x2c0 0x0 0x40>,
317 <0x0 0x340 0x0 0x1c>;
325 gpio-ranges = <&periphs_pinctrl 0 0 86>;
328 cec_ao_a_h_pins: cec_ao_a_h {
330 groups = "cec_ao_a_h";
331 function = "cec_ao_a_h";
336 cec_ao_b_h_pins: cec_ao_b_h {
338 groups = "cec_ao_b_h";
339 function = "cec_ao_b_h";
344 emmc_ctrl_pins: emmc-ctrl {
349 drive-strength-microamp = <4000>;
356 drive-strength-microamp = <4000>;
360 emmc_data_4b_pins: emmc-data-4b {
362 groups = "emmc_nand_d0",
368 drive-strength-microamp = <4000>;
372 emmc_data_8b_pins: emmc-data-8b {
374 groups = "emmc_nand_d0",
384 drive-strength-microamp = <4000>;
388 emmc_ds_pins: emmc-ds {
390 groups = "emmc_nand_ds";
393 drive-strength-microamp = <4000>;
397 emmc_clk_gate_pins: emmc_clk_gate {
400 function = "gpio_periphs";
402 drive-strength-microamp = <4000>;
406 hdmitx_ddc_pins: hdmitx_ddc {
408 groups = "hdmitx_sda",
412 drive-strength-microamp = <4000>;
416 hdmitx_hpd_pins: hdmitx_hpd {
418 groups = "hdmitx_hpd_in";
425 i2c0_sda_c_pins: i2c0-sda-c {
427 groups = "i2c0_sda_c";
430 drive-strength-microamp = <3000>;
435 i2c0_sck_c_pins: i2c0-sck-c {
437 groups = "i2c0_sck_c";
440 drive-strength-microamp = <3000>;
444 i2c0_sda_z0_pins: i2c0-sda-z0 {
446 groups = "i2c0_sda_z0";
449 drive-strength-microamp = <3000>;
453 i2c0_sck_z1_pins: i2c0-sck-z1 {
455 groups = "i2c0_sck_z1";
458 drive-strength-microamp = <3000>;
462 i2c0_sda_z7_pins: i2c0-sda-z7 {
464 groups = "i2c0_sda_z7";
467 drive-strength-microamp = <3000>;
471 i2c0_sda_z8_pins: i2c0-sda-z8 {
473 groups = "i2c0_sda_z8";
476 drive-strength-microamp = <3000>;
480 i2c1_sda_x_pins: i2c1-sda-x {
482 groups = "i2c1_sda_x";
485 drive-strength-microamp = <3000>;
489 i2c1_sck_x_pins: i2c1-sck-x {
491 groups = "i2c1_sck_x";
494 drive-strength-microamp = <3000>;
498 i2c1_sda_h2_pins: i2c1-sda-h2 {
500 groups = "i2c1_sda_h2";
503 drive-strength-microamp = <3000>;
507 i2c1_sck_h3_pins: i2c1-sck-h3 {
509 groups = "i2c1_sck_h3";
512 drive-strength-microamp = <3000>;
516 i2c1_sda_h6_pins: i2c1-sda-h6 {
518 groups = "i2c1_sda_h6";
521 drive-strength-microamp = <3000>;
525 i2c1_sck_h7_pins: i2c1-sck-h7 {
527 groups = "i2c1_sck_h7";
530 drive-strength-microamp = <3000>;
534 i2c2_sda_x_pins: i2c2-sda-x {
536 groups = "i2c2_sda_x";
539 drive-strength-microamp = <3000>;
543 i2c2_sck_x_pins: i2c2-sck-x {
545 groups = "i2c2_sck_x";
548 drive-strength-microamp = <3000>;
552 i2c2_sda_z_pins: i2c2-sda-z {
554 groups = "i2c2_sda_z";
557 drive-strength-microamp = <3000>;
561 i2c2_sck_z_pins: i2c2-sck-z {
563 groups = "i2c2_sck_z";
566 drive-strength-microamp = <3000>;
570 i2c3_sda_h_pins: i2c3-sda-h {
572 groups = "i2c3_sda_h";
575 drive-strength-microamp = <3000>;
579 i2c3_sck_h_pins: i2c3-sck-h {
581 groups = "i2c3_sck_h";
584 drive-strength-microamp = <3000>;
588 i2c3_sda_a_pins: i2c3-sda-a {
590 groups = "i2c3_sda_a";
593 drive-strength-microamp = <3000>;
597 i2c3_sck_a_pins: i2c3-sck-a {
599 groups = "i2c3_sck_a";
602 drive-strength-microamp = <3000>;
606 mclk0_a_pins: mclk0-a {
611 drive-strength-microamp = <3000>;
615 mclk1_a_pins: mclk1-a {
620 drive-strength-microamp = <3000>;
624 mclk1_x_pins: mclk1-x {
629 drive-strength-microamp = <3000>;
633 mclk1_z_pins: mclk1-z {
638 drive-strength-microamp = <3000>;
653 pdm_din0_a_pins: pdm-din0-a {
655 groups = "pdm_din0_a";
661 pdm_din0_c_pins: pdm-din0-c {
663 groups = "pdm_din0_c";
669 pdm_din0_x_pins: pdm-din0-x {
671 groups = "pdm_din0_x";
677 pdm_din0_z_pins: pdm-din0-z {
679 groups = "pdm_din0_z";
685 pdm_din1_a_pins: pdm-din1-a {
687 groups = "pdm_din1_a";
693 pdm_din1_c_pins: pdm-din1-c {
695 groups = "pdm_din1_c";
701 pdm_din1_x_pins: pdm-din1-x {
703 groups = "pdm_din1_x";
709 pdm_din1_z_pins: pdm-din1-z {
711 groups = "pdm_din1_z";
717 pdm_din2_a_pins: pdm-din2-a {
719 groups = "pdm_din2_a";
725 pdm_din2_c_pins: pdm-din2-c {
727 groups = "pdm_din2_c";
733 pdm_din2_x_pins: pdm-din2-x {
735 groups = "pdm_din2_x";
741 pdm_din2_z_pins: pdm-din2-z {
743 groups = "pdm_din2_z";
749 pdm_din3_a_pins: pdm-din3-a {
751 groups = "pdm_din3_a";
757 pdm_din3_c_pins: pdm-din3-c {
759 groups = "pdm_din3_c";
765 pdm_din3_x_pins: pdm-din3-x {
767 groups = "pdm_din3_x";
773 pdm_din3_z_pins: pdm-din3-z {
775 groups = "pdm_din3_z";
781 pdm_dclk_a_pins: pdm-dclk-a {
783 groups = "pdm_dclk_a";
786 drive-strength-microamp = <500>;
790 pdm_dclk_c_pins: pdm-dclk-c {
792 groups = "pdm_dclk_c";
795 drive-strength-microamp = <500>;
799 pdm_dclk_x_pins: pdm-dclk-x {
801 groups = "pdm_dclk_x";
804 drive-strength-microamp = <500>;
808 pdm_dclk_z_pins: pdm-dclk-z {
810 groups = "pdm_dclk_z";
813 drive-strength-microamp = <500>;
825 pwm_b_x7_pins: pwm-b-x7 {
833 pwm_b_x19_pins: pwm-b-x19 {
835 groups = "pwm_b_x19";
841 pwm_c_c_pins: pwm-c-c {
849 pwm_c_x5_pins: pwm-c-x5 {
857 pwm_c_x8_pins: pwm-c-x8 {
865 pwm_d_x3_pins: pwm-d-x3 {
873 pwm_d_x6_pins: pwm-d-x6 {
889 pwm_f_x_pins: pwm-f-x {
897 pwm_f_h_pins: pwm-f-h {
905 sdcard_c_pins: sdcard_c {
907 groups = "sdcard_d0_c",
914 drive-strength-microamp = <4000>;
918 groups = "sdcard_clk_c";
921 drive-strength-microamp = <4000>;
925 sdcard_clk_gate_c_pins: sdcard_clk_gate_c {
928 function = "gpio_periphs";
930 drive-strength-microamp = <4000>;
934 sdcard_z_pins: sdcard_z {
936 groups = "sdcard_d0_z",
943 drive-strength-microamp = <4000>;
947 groups = "sdcard_clk_z";
950 drive-strength-microamp = <4000>;
954 sdcard_clk_gate_z_pins: sdcard_clk_gate_z {
957 function = "gpio_periphs";
959 drive-strength-microamp = <4000>;
973 drive-strength-microamp = <4000>;
977 sdio_clk_gate_pins: sdio_clk_gate {
980 function = "gpio_periphs";
982 drive-strength-microamp = <4000>;
986 spdif_in_a10_pins: spdif-in-a10 {
988 groups = "spdif_in_a10";
989 function = "spdif_in";
994 spdif_in_a12_pins: spdif-in-a12 {
996 groups = "spdif_in_a12";
997 function = "spdif_in";
1002 spdif_in_h_pins: spdif-in-h {
1004 groups = "spdif_in_h";
1005 function = "spdif_in";
1010 spdif_out_h_pins: spdif-out-h {
1012 groups = "spdif_out_h";
1013 function = "spdif_out";
1014 drive-strength-microamp = <500>;
1019 spdif_out_a11_pins: spdif-out-a11 {
1021 groups = "spdif_out_a11";
1022 function = "spdif_out";
1023 drive-strength-microamp = <500>;
1028 spdif_out_a13_pins: spdif-out-a13 {
1030 groups = "spdif_out_a13";
1031 function = "spdif_out";
1032 drive-strength-microamp = <500>;
1037 spicc0_x_pins: spicc0-x {
1039 groups = "spi0_mosi_x",
1043 drive-strength-microamp = <4000>;
1048 spicc0_ss0_x_pins: spicc0-ss0-x {
1050 groups = "spi0_ss0_x";
1052 drive-strength-microamp = <4000>;
1057 spicc0_c_pins: spicc0-c {
1059 groups = "spi0_mosi_c",
1064 drive-strength-microamp = <4000>;
1069 spicc1_pins: spicc1 {
1071 groups = "spi1_mosi",
1075 drive-strength-microamp = <4000>;
1079 spicc1_ss0_pins: spicc1-ss0 {
1081 groups = "spi1_ss0";
1083 drive-strength-microamp = <4000>;
1088 tdm_a_din0_pins: tdm-a-din0 {
1090 groups = "tdm_a_din0";
1097 tdm_a_din1_pins: tdm-a-din1 {
1099 groups = "tdm_a_din1";
1105 tdm_a_dout0_pins: tdm-a-dout0 {
1107 groups = "tdm_a_dout0";
1110 drive-strength-microamp = <3000>;
1114 tdm_a_dout1_pins: tdm-a-dout1 {
1116 groups = "tdm_a_dout1";
1119 drive-strength-microamp = <3000>;
1123 tdm_a_fs_pins: tdm-a-fs {
1125 groups = "tdm_a_fs";
1128 drive-strength-microamp = <3000>;
1132 tdm_a_sclk_pins: tdm-a-sclk {
1134 groups = "tdm_a_sclk";
1137 drive-strength-microamp = <3000>;
1141 tdm_a_slv_fs_pins: tdm-a-slv-fs {
1143 groups = "tdm_a_slv_fs";
1150 tdm_a_slv_sclk_pins: tdm-a-slv-sclk {
1152 groups = "tdm_a_slv_sclk";
1158 tdm_b_din0_pins: tdm-b-din0 {
1160 groups = "tdm_b_din0";
1166 tdm_b_din1_pins: tdm-b-din1 {
1168 groups = "tdm_b_din1";
1174 tdm_b_din2_pins: tdm-b-din2 {
1176 groups = "tdm_b_din2";
1182 tdm_b_din3_a_pins: tdm-b-din3-a {
1184 groups = "tdm_b_din3_a";
1190 tdm_b_din3_h_pins: tdm-b-din3-h {
1192 groups = "tdm_b_din3_h";
1198 tdm_b_dout0_pins: tdm-b-dout0 {
1200 groups = "tdm_b_dout0";
1203 drive-strength-microamp = <3000>;
1207 tdm_b_dout1_pins: tdm-b-dout1 {
1209 groups = "tdm_b_dout1";
1212 drive-strength-microamp = <3000>;
1216 tdm_b_dout2_pins: tdm-b-dout2 {
1218 groups = "tdm_b_dout2";
1221 drive-strength-microamp = <3000>;
1225 tdm_b_dout3_a_pins: tdm-b-dout3-a {
1227 groups = "tdm_b_dout3_a";
1230 drive-strength-microamp = <3000>;
1234 tdm_b_dout3_h_pins: tdm-b-dout3-h {
1236 groups = "tdm_b_dout3_h";
1239 drive-strength-microamp = <3000>;
1243 tdm_b_fs_pins: tdm-b-fs {
1245 groups = "tdm_b_fs";
1248 drive-strength-microamp = <3000>;
1252 tdm_b_sclk_pins: tdm-b-sclk {
1254 groups = "tdm_b_sclk";
1257 drive-strength-microamp = <3000>;
1261 tdm_b_slv_fs_pins: tdm-b-slv-fs {
1263 groups = "tdm_b_slv_fs";
1269 tdm_b_slv_sclk_pins: tdm-b-slv-sclk {
1271 groups = "tdm_b_slv_sclk";
1277 tdm_c_din0_a_pins: tdm-c-din0-a {
1279 groups = "tdm_c_din0_a";
1285 tdm_c_din0_z_pins: tdm-c-din0-z {
1287 groups = "tdm_c_din0_z";
1293 tdm_c_din1_a_pins: tdm-c-din1-a {
1295 groups = "tdm_c_din1_a";
1301 tdm_c_din1_z_pins: tdm-c-din1-z {
1303 groups = "tdm_c_din1_z";
1309 tdm_c_din2_a_pins: tdm-c-din2-a {
1311 groups = "tdm_c_din2_a";
1317 eth_leds_pins: eth-leds {
1319 groups = "eth_link_led",
1328 groups = "eth_mdio",
1338 drive-strength-microamp = <4000>;
1343 eth_rgmii_pins: eth-rgmii {
1345 groups = "eth_rxd2_rgmii",
1351 drive-strength-microamp = <4000>;
1356 tdm_c_din2_z_pins: tdm-c-din2-z {
1358 groups = "tdm_c_din2_z";
1364 tdm_c_din3_a_pins: tdm-c-din3-a {
1366 groups = "tdm_c_din3_a";
1372 tdm_c_din3_z_pins: tdm-c-din3-z {
1374 groups = "tdm_c_din3_z";
1380 tdm_c_dout0_a_pins: tdm-c-dout0-a {
1382 groups = "tdm_c_dout0_a";
1385 drive-strength-microamp = <3000>;
1389 tdm_c_dout0_z_pins: tdm-c-dout0-z {
1391 groups = "tdm_c_dout0_z";
1394 drive-strength-microamp = <3000>;
1398 tdm_c_dout1_a_pins: tdm-c-dout1-a {
1400 groups = "tdm_c_dout1_a";
1403 drive-strength-microamp = <3000>;
1407 tdm_c_dout1_z_pins: tdm-c-dout1-z {
1409 groups = "tdm_c_dout1_z";
1412 drive-strength-microamp = <3000>;
1416 tdm_c_dout2_a_pins: tdm-c-dout2-a {
1418 groups = "tdm_c_dout2_a";
1421 drive-strength-microamp = <3000>;
1425 tdm_c_dout2_z_pins: tdm-c-dout2-z {
1427 groups = "tdm_c_dout2_z";
1430 drive-strength-microamp = <3000>;
1434 tdm_c_dout3_a_pins: tdm-c-dout3-a {
1436 groups = "tdm_c_dout3_a";
1439 drive-strength-microamp = <3000>;
1443 tdm_c_dout3_z_pins: tdm-c-dout3-z {
1445 groups = "tdm_c_dout3_z";
1448 drive-strength-microamp = <3000>;
1452 tdm_c_fs_a_pins: tdm-c-fs-a {
1454 groups = "tdm_c_fs_a";
1457 drive-strength-microamp = <3000>;
1461 tdm_c_fs_z_pins: tdm-c-fs-z {
1463 groups = "tdm_c_fs_z";
1466 drive-strength-microamp = <3000>;
1470 tdm_c_sclk_a_pins: tdm-c-sclk-a {
1472 groups = "tdm_c_sclk_a";
1475 drive-strength-microamp = <3000>;
1479 tdm_c_sclk_z_pins: tdm-c-sclk-z {
1481 groups = "tdm_c_sclk_z";
1484 drive-strength-microamp = <3000>;
1488 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a {
1490 groups = "tdm_c_slv_fs_a";
1496 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z {
1498 groups = "tdm_c_slv_fs_z";
1504 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a {
1506 groups = "tdm_c_slv_sclk_a";
1512 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z {
1514 groups = "tdm_c_slv_sclk_z";
1520 uart_a_pins: uart-a {
1522 groups = "uart_a_tx",
1524 function = "uart_a";
1529 uart_a_cts_rts_pins: uart-a-cts-rts {
1531 groups = "uart_a_cts",
1533 function = "uart_a";
1538 uart_b_pins: uart-b {
1540 groups = "uart_b_tx",
1542 function = "uart_b";
1547 uart_c_pins: uart-c {
1549 groups = "uart_c_tx",
1551 function = "uart_c";
1556 uart_c_cts_rts_pins: uart-c-cts-rts {
1558 groups = "uart_c_cts",
1560 function = "uart_c";
1567 cpu_temp: temperature-sensor@34800 {
1568 compatible = "amlogic,g12a-cpu-thermal",
1569 "amlogic,g12a-thermal";
1570 reg = <0x0 0x34800 0x0 0x50>;
1571 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
1572 clocks = <&clkc CLKID_TS>;
1573 #thermal-sensor-cells = <0>;
1574 amlogic,ao-secure = <&sec_AO>;
1577 ddr_temp: temperature-sensor@34c00 {
1578 compatible = "amlogic,g12a-ddr-thermal",
1579 "amlogic,g12a-thermal";
1580 reg = <0x0 0x34c00 0x0 0x50>;
1581 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1582 clocks = <&clkc CLKID_TS>;
1583 #thermal-sensor-cells = <0>;
1584 amlogic,ao-secure = <&sec_AO>;
1587 usb2_phy0: phy@36000 {
1588 compatible = "amlogic,g12a-usb2-phy";
1589 reg = <0x0 0x36000 0x0 0x2000>;
1591 clock-names = "xtal";
1592 resets = <&reset RESET_USB_PHY20>;
1593 reset-names = "phy";
1598 compatible = "simple-bus";
1599 reg = <0x0 0x38000 0x0 0x400>;
1600 #address-cells = <2>;
1602 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>;
1604 canvas: video-lut@48 {
1605 compatible = "amlogic,canvas";
1606 reg = <0x0 0x48 0x0 0x14>;
1610 usb2_phy1: phy@3a000 {
1611 compatible = "amlogic,g12a-usb2-phy";
1612 reg = <0x0 0x3a000 0x0 0x2000>;
1614 clock-names = "xtal";
1615 resets = <&reset RESET_USB_PHY21>;
1616 reset-names = "phy";
1621 compatible = "simple-bus";
1622 reg = <0x0 0x3c000 0x0 0x1400>;
1623 #address-cells = <2>;
1625 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>;
1627 hhi: system-controller@0 {
1628 compatible = "amlogic,meson-gx-hhi-sysctrl",
1629 "simple-mfd", "syscon";
1630 reg = <0 0 0 0x400>;
1632 clkc: clock-controller {
1633 compatible = "amlogic,g12a-clkc";
1636 clock-names = "xtal";
1639 pwrc: power-controller {
1640 compatible = "amlogic,meson-g12a-pwrc";
1641 #power-domain-cells = <1>;
1642 amlogic,ao-sysctrl = <&rti>;
1643 resets = <&reset RESET_VIU>,
1644 <&reset RESET_VENC>,
1645 <&reset RESET_VCBUS>,
1646 <&reset RESET_BT656>,
1647 <&reset RESET_RDMA>,
1648 <&reset RESET_VENCI>,
1649 <&reset RESET_VENCP>,
1650 <&reset RESET_VDAC>,
1651 <&reset RESET_VDI6>,
1652 <&reset RESET_VENCL>,
1653 <&reset RESET_VID_LOCK>;
1654 reset-names = "viu", "venc", "vcbus", "bt656",
1655 "rdma", "venci", "vencp", "vdac",
1656 "vdi6", "vencl", "vid_lock";
1657 clocks = <&clkc CLKID_VPU>,
1659 clock-names = "vpu", "vapb";
1661 * VPU clocking is provided by two identical clock paths
1662 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1663 * free mux to safely change frequency while running.
1664 * Same for VAPB but with a final gate after the glitch free mux.
1666 assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1667 <&clkc CLKID_VPU_0>,
1668 <&clkc CLKID_VPU>, /* Glitch free mux */
1669 <&clkc CLKID_VAPB_0_SEL>,
1670 <&clkc CLKID_VAPB_0>,
1671 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1672 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
1673 <0>, /* Do Nothing */
1674 <&clkc CLKID_VPU_0>,
1675 <&clkc CLKID_FCLK_DIV4>,
1676 <0>, /* Do Nothing */
1677 <&clkc CLKID_VAPB_0>;
1678 assigned-clock-rates = <0>, /* Do Nothing */
1680 <0>, /* Do Nothing */
1681 <0>, /* Do Nothing */
1683 <0>; /* Do Nothing */
1688 usb3_pcie_phy: phy@46000 {
1689 compatible = "amlogic,g12a-usb3-pcie-phy";
1690 reg = <0x0 0x46000 0x0 0x2000>;
1691 clocks = <&clkc CLKID_PCIE_PLL>;
1692 clock-names = "ref_clk";
1693 resets = <&reset RESET_PCIE_PHY>;
1694 reset-names = "phy";
1695 assigned-clocks = <&clkc CLKID_PCIE_PLL>;
1696 assigned-clock-rates = <100000000>;
1700 eth_phy: mdio-multiplexer@4c000 {
1701 compatible = "amlogic,g12a-mdio-mux";
1702 reg = <0x0 0x4c000 0x0 0xa4>;
1703 clocks = <&clkc CLKID_ETH_PHY>,
1705 <&clkc CLKID_MPLL_50M>;
1706 clock-names = "pclk", "clkin0", "clkin1";
1707 mdio-parent-bus = <&mdio0>;
1708 #address-cells = <1>;
1713 #address-cells = <1>;
1719 #address-cells = <1>;
1722 internal_ephy: ethernet_phy@8 {
1723 compatible = "ethernet-phy-id0180.3301",
1724 "ethernet-phy-ieee802.3-c22";
1725 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1733 aobus: bus@ff800000 {
1734 compatible = "simple-bus";
1735 reg = <0x0 0xff800000 0x0 0x100000>;
1736 #address-cells = <2>;
1738 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1741 compatible = "amlogic,meson-gx-ao-sysctrl",
1742 "simple-mfd", "syscon";
1743 reg = <0x0 0x0 0x0 0x100>;
1744 #address-cells = <2>;
1746 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>;
1748 clkc_AO: clock-controller {
1749 compatible = "amlogic,meson-g12a-aoclkc";
1752 clocks = <&xtal>, <&clkc CLKID_CLK81>;
1753 clock-names = "xtal", "mpeg-clk";
1756 ao_pinctrl: pinctrl@14 {
1757 compatible = "amlogic,meson-g12a-aobus-pinctrl";
1758 #address-cells = <2>;
1763 reg = <0x0 0x14 0x0 0x8>,
1765 <0x0 0x24 0x0 0x14>;
1771 gpio-ranges = <&ao_pinctrl 0 0 15>;
1774 i2c_ao_sck_pins: i2c_ao_sck_pins {
1776 groups = "i2c_ao_sck";
1777 function = "i2c_ao";
1779 drive-strength-microamp = <3000>;
1783 i2c_ao_sda_pins: i2c_ao_sda {
1785 groups = "i2c_ao_sda";
1786 function = "i2c_ao";
1788 drive-strength-microamp = <3000>;
1792 i2c_ao_sck_e_pins: i2c_ao_sck_e {
1794 groups = "i2c_ao_sck_e";
1795 function = "i2c_ao";
1797 drive-strength-microamp = <3000>;
1801 i2c_ao_sda_e_pins: i2c_ao_sda_e {
1803 groups = "i2c_ao_sda_e";
1804 function = "i2c_ao";
1806 drive-strength-microamp = <3000>;
1810 mclk0_ao_pins: mclk0-ao {
1812 groups = "mclk0_ao";
1813 function = "mclk0_ao";
1815 drive-strength-microamp = <3000>;
1819 tdm_ao_b_din0_pins: tdm-ao-b-din0 {
1821 groups = "tdm_ao_b_din0";
1822 function = "tdm_ao_b";
1827 spdif_ao_out_pins: spdif-ao-out {
1829 groups = "spdif_ao_out";
1830 function = "spdif_ao_out";
1831 drive-strength-microamp = <500>;
1836 tdm_ao_b_din1_pins: tdm-ao-b-din1 {
1838 groups = "tdm_ao_b_din1";
1839 function = "tdm_ao_b";
1844 tdm_ao_b_din2_pins: tdm-ao-b-din2 {
1846 groups = "tdm_ao_b_din2";
1847 function = "tdm_ao_b";
1852 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 {
1854 groups = "tdm_ao_b_dout0";
1855 function = "tdm_ao_b";
1857 drive-strength-microamp = <3000>;
1861 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 {
1863 groups = "tdm_ao_b_dout1";
1864 function = "tdm_ao_b";
1866 drive-strength-microamp = <3000>;
1870 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 {
1872 groups = "tdm_ao_b_dout2";
1873 function = "tdm_ao_b";
1875 drive-strength-microamp = <3000>;
1879 tdm_ao_b_fs_pins: tdm-ao-b-fs {
1881 groups = "tdm_ao_b_fs";
1882 function = "tdm_ao_b";
1884 drive-strength-microamp = <3000>;
1888 tdm_ao_b_sclk_pins: tdm-ao-b-sclk {
1890 groups = "tdm_ao_b_sclk";
1891 function = "tdm_ao_b";
1893 drive-strength-microamp = <3000>;
1897 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs {
1899 groups = "tdm_ao_b_slv_fs";
1900 function = "tdm_ao_b";
1905 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk {
1907 groups = "tdm_ao_b_slv_sclk";
1908 function = "tdm_ao_b";
1913 uart_ao_a_pins: uart-a-ao {
1915 groups = "uart_ao_a_tx",
1917 function = "uart_ao_a";
1922 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts {
1924 groups = "uart_ao_a_cts",
1926 function = "uart_ao_a";
1931 pwm_a_e_pins: pwm-a-e {
1934 function = "pwm_a_e";
1939 pwm_ao_a_pins: pwm-ao-a {
1941 groups = "pwm_ao_a";
1942 function = "pwm_ao_a";
1947 pwm_ao_b_pins: pwm-ao-b {
1949 groups = "pwm_ao_b";
1950 function = "pwm_ao_b";
1955 pwm_ao_c_4_pins: pwm-ao-c-4 {
1957 groups = "pwm_ao_c_4";
1958 function = "pwm_ao_c";
1963 pwm_ao_c_6_pins: pwm-ao-c-6 {
1965 groups = "pwm_ao_c_6";
1966 function = "pwm_ao_c";
1971 pwm_ao_d_5_pins: pwm-ao-d-5 {
1973 groups = "pwm_ao_d_5";
1974 function = "pwm_ao_d";
1979 pwm_ao_d_10_pins: pwm-ao-d-10 {
1981 groups = "pwm_ao_d_10";
1982 function = "pwm_ao_d";
1987 pwm_ao_d_e_pins: pwm-ao-d-e {
1989 groups = "pwm_ao_d_e";
1990 function = "pwm_ao_d";
1994 remote_input_ao_pins: remote-input-ao {
1996 groups = "remote_ao_input";
1997 function = "remote_ao_input";
2005 compatible = "amlogic,meson-vrtc";
2006 reg = <0x0 0x000a8 0x0 0x4>;
2010 compatible = "amlogic,meson-gx-ao-cec";
2011 reg = <0x0 0x00100 0x0 0x14>;
2012 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
2013 clocks = <&clkc_AO CLKID_AO_CEC>;
2014 clock-names = "core";
2015 status = "disabled";
2018 sec_AO: ao-secure@140 {
2019 compatible = "amlogic,meson-gx-ao-secure", "syscon";
2020 reg = <0x0 0x140 0x0 0x140>;
2021 amlogic,has-chip-id;
2025 compatible = "amlogic,meson-g12a-ao-cec";
2026 reg = <0x0 0x00280 0x0 0x1c>;
2027 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
2028 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>;
2029 clock-names = "oscin";
2030 status = "disabled";
2033 pwm_AO_cd: pwm@2000 {
2034 compatible = "amlogic,meson-g12a-ao-pwm-cd";
2035 reg = <0x0 0x2000 0x0 0x20>;
2037 status = "disabled";
2040 uart_AO: serial@3000 {
2041 compatible = "amlogic,meson-gx-uart",
2042 "amlogic,meson-ao-uart";
2043 reg = <0x0 0x3000 0x0 0x18>;
2044 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
2045 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>;
2046 clock-names = "xtal", "pclk", "baud";
2047 status = "disabled";
2050 uart_AO_B: serial@4000 {
2051 compatible = "amlogic,meson-gx-uart",
2052 "amlogic,meson-ao-uart";
2053 reg = <0x0 0x4000 0x0 0x18>;
2054 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
2055 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
2056 clock-names = "xtal", "pclk", "baud";
2057 status = "disabled";
2061 compatible = "amlogic,meson-axg-i2c";
2062 status = "disabled";
2063 reg = <0x0 0x05000 0x0 0x20>;
2064 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
2065 #address-cells = <1>;
2067 clocks = <&clkc CLKID_I2C>;
2070 pwm_AO_ab: pwm@7000 {
2071 compatible = "amlogic,meson-g12a-ao-pwm-ab";
2072 reg = <0x0 0x7000 0x0 0x20>;
2074 status = "disabled";
2078 compatible = "amlogic,meson-gxbb-ir";
2079 reg = <0x0 0x8000 0x0 0x20>;
2080 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
2081 status = "disabled";
2085 compatible = "amlogic,meson-g12a-saradc",
2086 "amlogic,meson-saradc";
2087 reg = <0x0 0x9000 0x0 0x48>;
2088 #io-channel-cells = <1>;
2089 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>;
2091 <&clkc_AO CLKID_AO_SAR_ADC>,
2092 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
2093 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
2094 clock-names = "clkin", "core", "adc_clk", "adc_sel";
2095 status = "disabled";
2099 vdec: video-decoder@ff620000 {
2100 compatible = "amlogic,g12a-vdec";
2101 reg = <0x0 0xff620000 0x0 0x10000>,
2102 <0x0 0xffd0e180 0x0 0xe4>;
2103 reg-names = "dos", "esparser";
2104 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
2105 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
2106 interrupt-names = "vdec", "esparser";
2108 amlogic,ao-sysctrl = <&rti>;
2109 amlogic,canvas = <&canvas>;
2111 clocks = <&clkc CLKID_PARSER>,
2113 <&clkc CLKID_VDEC_1>,
2114 <&clkc CLKID_VDEC_HEVC>,
2115 <&clkc CLKID_VDEC_HEVCF>;
2116 clock-names = "dos_parser", "dos", "vdec_1",
2117 "vdec_hevc", "vdec_hevcf";
2118 resets = <&reset RESET_PARSER>;
2119 reset-names = "esparser";
2123 compatible = "amlogic,meson-g12a-vpu";
2124 reg = <0x0 0xff900000 0x0 0x100000>,
2125 <0x0 0xff63c000 0x0 0x1000>;
2126 reg-names = "vpu", "hhi";
2127 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
2128 #address-cells = <1>;
2130 amlogic,canvas = <&canvas>;
2132 /* CVBS VDAC output port */
2133 cvbs_vdac_port: port@0 {
2137 /* HDMI-TX output port */
2138 hdmi_tx_port: port@1 {
2141 hdmi_tx_out: endpoint {
2142 remote-endpoint = <&hdmi_tx_in>;
2147 gic: interrupt-controller@ffc01000 {
2148 compatible = "arm,gic-400";
2149 reg = <0x0 0xffc01000 0 0x1000>,
2150 <0x0 0xffc02000 0 0x2000>,
2151 <0x0 0xffc04000 0 0x2000>,
2152 <0x0 0xffc06000 0 0x2000>;
2153 interrupt-controller;
2154 interrupts = <GIC_PPI 9
2155 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
2156 #interrupt-cells = <3>;
2157 #address-cells = <0>;
2160 cbus: bus@ffd00000 {
2161 compatible = "simple-bus";
2162 reg = <0x0 0xffd00000 0x0 0x100000>;
2163 #address-cells = <2>;
2165 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>;
2167 reset: reset-controller@1004 {
2168 compatible = "amlogic,meson-axg-reset";
2169 reg = <0x0 0x1004 0x0 0x9c>;
2173 gpio_intc: interrupt-controller@f080 {
2174 compatible = "amlogic,meson-g12a-gpio-intc",
2175 "amlogic,meson-gpio-intc";
2176 reg = <0x0 0xf080 0x0 0x10>;
2177 interrupt-controller;
2178 #interrupt-cells = <2>;
2179 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
2183 compatible = "amlogic,meson-g12a-spicc";
2184 reg = <0x0 0x13000 0x0 0x44>;
2185 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2186 clocks = <&clkc CLKID_SPICC0>,
2187 <&clkc CLKID_SPICC0_SCLK>;
2188 clock-names = "core", "pclk";
2189 #address-cells = <1>;
2191 status = "disabled";
2195 compatible = "amlogic,meson-g12a-spicc";
2196 reg = <0x0 0x15000 0x0 0x44>;
2197 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
2198 clocks = <&clkc CLKID_SPICC1>,
2199 <&clkc CLKID_SPICC1_SCLK>;
2200 clock-names = "core", "pclk";
2201 #address-cells = <1>;
2203 status = "disabled";
2207 compatible = "amlogic,meson-gxbb-spifc";
2208 status = "disabled";
2209 reg = <0x0 0x14000 0x0 0x80>;
2210 #address-cells = <1>;
2212 clocks = <&clkc CLKID_CLK81>;
2216 compatible = "amlogic,meson-g12a-ee-pwm";
2217 reg = <0x0 0x19000 0x0 0x20>;
2219 status = "disabled";
2223 compatible = "amlogic,meson-g12a-ee-pwm";
2224 reg = <0x0 0x1a000 0x0 0x20>;
2226 status = "disabled";
2230 compatible = "amlogic,meson-g12a-ee-pwm";
2231 reg = <0x0 0x1b000 0x0 0x20>;
2233 status = "disabled";
2237 compatible = "amlogic,meson-axg-i2c";
2238 status = "disabled";
2239 reg = <0x0 0x1c000 0x0 0x20>;
2240 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
2241 #address-cells = <1>;
2243 clocks = <&clkc CLKID_I2C>;
2247 compatible = "amlogic,meson-axg-i2c";
2248 status = "disabled";
2249 reg = <0x0 0x1d000 0x0 0x20>;
2250 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
2251 #address-cells = <1>;
2253 clocks = <&clkc CLKID_I2C>;
2257 compatible = "amlogic,meson-axg-i2c";
2258 status = "disabled";
2259 reg = <0x0 0x1e000 0x0 0x20>;
2260 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
2261 #address-cells = <1>;
2263 clocks = <&clkc CLKID_I2C>;
2267 compatible = "amlogic,meson-axg-i2c";
2268 status = "disabled";
2269 reg = <0x0 0x1f000 0x0 0x20>;
2270 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
2271 #address-cells = <1>;
2273 clocks = <&clkc CLKID_I2C>;
2276 clk_msr: clock-measure@18000 {
2277 compatible = "amlogic,meson-g12a-clk-measure";
2278 reg = <0x0 0x18000 0x0 0x10>;
2281 uart_C: serial@22000 {
2282 compatible = "amlogic,meson-gx-uart";
2283 reg = <0x0 0x22000 0x0 0x18>;
2284 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
2285 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
2286 clock-names = "xtal", "pclk", "baud";
2287 status = "disabled";
2290 uart_B: serial@23000 {
2291 compatible = "amlogic,meson-gx-uart";
2292 reg = <0x0 0x23000 0x0 0x18>;
2293 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
2294 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
2295 clock-names = "xtal", "pclk", "baud";
2296 status = "disabled";
2299 uart_A: serial@24000 {
2300 compatible = "amlogic,meson-gx-uart";
2301 reg = <0x0 0x24000 0x0 0x18>;
2302 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
2303 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
2304 clock-names = "xtal", "pclk", "baud";
2305 status = "disabled";
2309 sd_emmc_a: sd@ffe03000 {
2310 compatible = "amlogic,meson-axg-mmc";
2311 reg = <0x0 0xffe03000 0x0 0x800>;
2312 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
2313 status = "disabled";
2314 clocks = <&clkc CLKID_SD_EMMC_A>,
2315 <&clkc CLKID_SD_EMMC_A_CLK0>,
2316 <&clkc CLKID_FCLK_DIV2>;
2317 clock-names = "core", "clkin0", "clkin1";
2318 resets = <&reset RESET_SD_EMMC_A>;
2321 sd_emmc_b: sd@ffe05000 {
2322 compatible = "amlogic,meson-axg-mmc";
2323 reg = <0x0 0xffe05000 0x0 0x800>;
2324 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
2325 status = "disabled";
2326 clocks = <&clkc CLKID_SD_EMMC_B>,
2327 <&clkc CLKID_SD_EMMC_B_CLK0>,
2328 <&clkc CLKID_FCLK_DIV2>;
2329 clock-names = "core", "clkin0", "clkin1";
2330 resets = <&reset RESET_SD_EMMC_B>;
2333 sd_emmc_c: mmc@ffe07000 {
2334 compatible = "amlogic,meson-axg-mmc";
2335 reg = <0x0 0xffe07000 0x0 0x800>;
2336 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
2337 status = "disabled";
2338 clocks = <&clkc CLKID_SD_EMMC_C>,
2339 <&clkc CLKID_SD_EMMC_C_CLK0>,
2340 <&clkc CLKID_FCLK_DIV2>;
2341 clock-names = "core", "clkin0", "clkin1";
2342 resets = <&reset RESET_SD_EMMC_C>;
2346 status = "disabled";
2347 compatible = "amlogic,meson-g12a-usb-ctrl";
2348 reg = <0x0 0xffe09000 0x0 0xa0>;
2349 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2350 #address-cells = <2>;
2354 clocks = <&clkc CLKID_USB>;
2355 resets = <&reset RESET_USB>;
2359 phys = <&usb2_phy0>, <&usb2_phy1>,
2360 <&usb3_pcie_phy PHY_TYPE_USB3>;
2361 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
2363 dwc2: usb@ff400000 {
2364 compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
2365 reg = <0x0 0xff400000 0x0 0x40000>;
2366 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
2367 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
2368 clock-names = "otg";
2369 phys = <&usb2_phy1>;
2370 phy-names = "usb2-phy";
2371 dr_mode = "peripheral";
2372 g-rx-fifo-size = <192>;
2373 g-np-tx-fifo-size = <128>;
2374 g-tx-fifo-size = <128 128 16 16 16>;
2377 dwc3: usb@ff500000 {
2378 compatible = "snps,dwc3";
2379 reg = <0x0 0xff500000 0x0 0x100000>;
2380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2382 snps,dis_u2_susphy_quirk;
2383 snps,quirk-frame-length-adjustment;
2384 snps,parkmode-disable-ss-quirk;
2388 mali: gpu@ffe40000 {
2389 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
2390 reg = <0x0 0xffe40000 0x0 0x40000>;
2391 interrupt-parent = <&gic>;
2392 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2393 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2394 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2395 interrupt-names = "job", "mmu", "gpu";
2396 clocks = <&clkc CLKID_MALI>;
2397 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>;
2398 operating-points-v2 = <&gpu_opp_table>;
2399 #cooling-cells = <2>;
2404 compatible = "arm,armv8-timer";
2405 interrupts = <GIC_PPI 13
2406 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2408 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2410 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
2412 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
2413 arm,no-tick-in-suspend;
2417 compatible = "fixed-clock";
2418 clock-frequency = <24000000>;
2419 clock-output-names = "xtal";