arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

   1 /*
   2  * Copyright (C) 2016 ARM Ltd.
   3  * based on the Allwinner H3 dtsi:
   4  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
  46 #include <dt-bindings/clock/sun8i-r-ccu.h>
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  49
  50 / {
  51         interrupt-parent = <&gic>;
  52         #address-cells = <1>;
  53         #size-cells = <1>;
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 cpu0: cpu@0 {
  60                         compatible = "arm,cortex-a53", "arm,armv8";
  61                         device_type = "cpu";
  62                         reg = <0>;
  63                         enable-method = "psci";
  64                 };
  65
  66                 cpu1: cpu@1 {
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         device_type = "cpu";
  69                         reg = <1>;
  70                         enable-method = "psci";
  71                 };
  72
  73                 cpu2: cpu@2 {
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         device_type = "cpu";
  76                         reg = <2>;
  77                         enable-method = "psci";
  78                 };
  79
  80                 cpu3: cpu@3 {
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         device_type = "cpu";
  83                         reg = <3>;
  84                         enable-method = "psci";
  85                 };
  86         };
  87
  88         osc24M: osc24M_clk {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <24000000>;
  92                 clock-output-names = "osc24M";
  93         };
  94
  95         osc32k: osc32k_clk {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99                 clock-output-names = "osc32k";
 100         };
 101
 102         iosc: internal-osc-clk {
 103                 #clock-cells = <0>;
 104                 compatible = "fixed-clock";
 105                 clock-frequency = <16000000>;
 106                 clock-accuracy = <300000000>;
 107                 clock-output-names = "iosc";
 108         };
 109
 110         psci {
 111                 compatible = "arm,psci-0.2";
 112                 method = "smc";
 113         };
 114
 115         sound_spdif {
 116                 compatible = "simple-audio-card";
 117                 simple-audio-card,name = "On-board SPDIF";
 118
 119                 simple-audio-card,cpu {
 120                         sound-dai = <&spdif>;
 121                 };
 122
 123                 simple-audio-card,codec {
 124                         sound-dai = <&spdif_out>;
 125                 };
 126         };
 127
 128         spdif_out: spdif-out {
 129                 #sound-dai-cells = <0>;
 130                 compatible = "linux,spdif-dit";
 131         };
 132
 133         timer {
 134                 compatible = "arm,armv8-timer";
 135                 interrupts = <GIC_PPI 13
 136                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 137                              <GIC_PPI 14
 138                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 139                              <GIC_PPI 11
 140                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 141                              <GIC_PPI 10
 142                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 143         };
 144
 145         soc {
 146                 compatible = "simple-bus";
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 ranges;
 150
 151                 syscon: syscon@1c00000 {
 152                         compatible = "allwinner,sun50i-a64-system-controller",
 153                                 "syscon";
 154                         reg = <0x01c00000 0x1000>;
 155                 };
 156
 157                 dma: dma-controller@1c02000 {
 158                         compatible = "allwinner,sun50i-a64-dma";
 159                         reg = <0x01c02000 0x1000>;
 160                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 161                         clocks = <&ccu CLK_BUS_DMA>;
 162                         dma-channels = <8>;
 163                         dma-requests = <27>;
 164                         resets = <&ccu RST_BUS_DMA>;
 165                         #dma-cells = <1>;
 166                 };
 167
 168                 mmc0: mmc@1c0f000 {
 169                         compatible = "allwinner,sun50i-a64-mmc";
 170                         reg = <0x01c0f000 0x1000>;
 171                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 172                         clock-names = "ahb", "mmc";
 173                         resets = <&ccu RST_BUS_MMC0>;
 174                         reset-names = "ahb";
 175                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 176                         max-frequency = <150000000>;
 177                         status = "disabled";
 178                         #address-cells = <1>;
 179                         #size-cells = <0>;
 180                 };
 181
 182                 mmc1: mmc@1c10000 {
 183                         compatible = "allwinner,sun50i-a64-mmc";
 184                         reg = <0x01c10000 0x1000>;
 185                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 186                         clock-names = "ahb", "mmc";
 187                         resets = <&ccu RST_BUS_MMC1>;
 188                         reset-names = "ahb";
 189                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 190                         max-frequency = <150000000>;
 191                         status = "disabled";
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                 };
 195
 196                 mmc2: mmc@1c11000 {
 197                         compatible = "allwinner,sun50i-a64-emmc";
 198                         reg = <0x01c11000 0x1000>;
 199                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 200                         clock-names = "ahb", "mmc";
 201                         resets = <&ccu RST_BUS_MMC2>;
 202                         reset-names = "ahb";
 203                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 204                         max-frequency = <200000000>;
 205                         status = "disabled";
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                 };
 209
 210                 usb_otg: usb@1c19000 {
 211                         compatible = "allwinner,sun8i-a33-musb";
 212                         reg = <0x01c19000 0x0400>;
 213                         clocks = <&ccu CLK_BUS_OTG>;
 214                         resets = <&ccu RST_BUS_OTG>;
 215                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 216                         interrupt-names = "mc";
 217                         phys = <&usbphy 0>;
 218                         phy-names = "usb";
 219                         extcon = <&usbphy 0>;
 220                         status = "disabled";
 221                 };
 222
 223                 usbphy: phy@1c19400 {
 224                         compatible = "allwinner,sun50i-a64-usb-phy";
 225                         reg = <0x01c19400 0x14>,
 226                               <0x01c1a800 0x4>,
 227                               <0x01c1b800 0x4>;
 228                         reg-names = "phy_ctrl",
 229                                     "pmu0",
 230                                     "pmu1";
 231                         clocks = <&ccu CLK_USB_PHY0>,
 232                                  <&ccu CLK_USB_PHY1>;
 233                         clock-names = "usb0_phy",
 234                                       "usb1_phy";
 235                         resets = <&ccu RST_USB_PHY0>,
 236                                  <&ccu RST_USB_PHY1>;
 237                         reset-names = "usb0_reset",
 238                                       "usb1_reset";
 239                         status = "disabled";
 240                         #phy-cells = <1>;
 241                 };
 242
 243                 ehci0: usb@1c1a000 {
 244                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 245                         reg = <0x01c1a000 0x100>;
 246                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 247                         clocks = <&ccu CLK_BUS_OHCI0>,
 248                                  <&ccu CLK_BUS_EHCI0>,
 249                                  <&ccu CLK_USB_OHCI0>;
 250                         resets = <&ccu RST_BUS_OHCI0>,
 251                                  <&ccu RST_BUS_EHCI0>;
 252                         status = "disabled";
 253                 };
 254
 255                 ohci0: usb@1c1a400 {
 256                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 257                         reg = <0x01c1a400 0x100>;
 258                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 259                         clocks = <&ccu CLK_BUS_OHCI0>,
 260                                  <&ccu CLK_USB_OHCI0>;
 261                         resets = <&ccu RST_BUS_OHCI0>;
 262                         status = "disabled";
 263                 };
 264
 265                 ehci1: usb@1c1b000 {
 266                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 267                         reg = <0x01c1b000 0x100>;
 268                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&ccu CLK_BUS_OHCI1>,
 270                                  <&ccu CLK_BUS_EHCI1>,
 271                                  <&ccu CLK_USB_OHCI1>;
 272                         resets = <&ccu RST_BUS_OHCI1>,
 273                                  <&ccu RST_BUS_EHCI1>;
 274                         phys = <&usbphy 1>;
 275                         phy-names = "usb";
 276                         status = "disabled";
 277                 };
 278
 279                 ohci1: usb@1c1b400 {
 280                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 281                         reg = <0x01c1b400 0x100>;
 282                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&ccu CLK_BUS_OHCI1>,
 284                                  <&ccu CLK_USB_OHCI1>;
 285                         resets = <&ccu RST_BUS_OHCI1>;
 286                         phys = <&usbphy 1>;
 287                         phy-names = "usb";
 288                         status = "disabled";
 289                 };
 290
 291                 ccu: clock@1c20000 {
 292                         compatible = "allwinner,sun50i-a64-ccu";
 293                         reg = <0x01c20000 0x400>;
 294                         clocks = <&osc24M>, <&osc32k>;
 295                         clock-names = "hosc", "losc";
 296                         #clock-cells = <1>;
 297                         #reset-cells = <1>;
 298                 };
 299
 300                 pio: pinctrl@1c20800 {
 301                         compatible = "allwinner,sun50i-a64-pinctrl";
 302                         reg = <0x01c20800 0x400>;
 303                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 305                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&ccu 58>;
 307                         gpio-controller;
 308                         #gpio-cells = <3>;
 309                         interrupt-controller;
 310                         #interrupt-cells = <3>;
 311
 312                         i2c1_pins: i2c1_pins {
 313                                 pins = "PH2", "PH3";
 314                                 function = "i2c1";
 315                         };
 316
 317                         mmc0_pins: mmc0-pins {
 318                                 pins = "PF0", "PF1", "PF2", "PF3",
 319                                        "PF4", "PF5";
 320                                 function = "mmc0";
 321                                 drive-strength = <30>;
 322                                 bias-pull-up;
 323                         };
 324
 325                         mmc1_pins: mmc1-pins {
 326                                 pins = "PG0", "PG1", "PG2", "PG3",
 327                                        "PG4", "PG5";
 328                                 function = "mmc1";
 329                                 drive-strength = <30>;
 330                                 bias-pull-up;
 331                         };
 332
 333                         mmc2_pins: mmc2-pins {
 334                                 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
 335                                        "PC10","PC11", "PC12", "PC13",
 336                                        "PC14", "PC15", "PC16";
 337                                 function = "mmc2";
 338                                 drive-strength = <30>;
 339                                 bias-pull-up;
 340                         };
 341
 342                         rmii_pins: rmii_pins {
 343                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 344                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 345                                 function = "emac";
 346                                 drive-strength = <40>;
 347                         };
 348
 349                         rgmii_pins: rgmii_pins {
 350                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 351                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 352                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 353                                 function = "emac";
 354                                 drive-strength = <40>;
 355                         };
 356
 357                         spdif_tx_pin: spdif {
 358                                 pins = "PH8";
 359                                 function = "spdif";
 360                         };
 361
 362                         spi0_pins: spi0 {
 363                                 pins = "PC0", "PC1", "PC2", "PC3";
 364                                 function = "spi0";
 365                         };
 366
 367                         spi1_pins: spi1 {
 368                                 pins = "PD0", "PD1", "PD2", "PD3";
 369                                 function = "spi1";
 370                         };
 371
 372                         uart0_pins_a: uart0 {
 373                                 pins = "PB8", "PB9";
 374                                 function = "uart0";
 375                         };
 376
 377                         uart1_pins: uart1_pins {
 378                                 pins = "PG6", "PG7";
 379                                 function = "uart1";
 380                         };
 381
 382                         uart1_rts_cts_pins: uart1_rts_cts_pins {
 383                                 pins = "PG8", "PG9";
 384                                 function = "uart1";
 385                         };
 386
 387                         uart2_pins: uart2-pins {
 388                                 pins = "PB0", "PB1";
 389                                 function = "uart2";
 390                         };
 391
 392                         uart3_pins: uart3-pins {
 393                                 pins = "PD0", "PD1";
 394                                 function = "uart3";
 395                         };
 396
 397                         uart4_pins: uart4-pins {
 398                                 pins = "PD2", "PD3";
 399                                 function = "uart4";
 400                         };
 401
 402                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 403                                 pins = "PD4", "PD5";
 404                                 function = "uart4";
 405                         };
 406                 };
 407
 408                 spdif: spdif@1c21000 {
 409                         #sound-dai-cells = <0>;
 410                         compatible = "allwinner,sun50i-a64-spdif",
 411                                      "allwinner,sun8i-h3-spdif";
 412                         reg = <0x01c21000 0x400>;
 413                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 415                         resets = <&ccu RST_BUS_SPDIF>;
 416                         clock-names = "apb", "spdif";
 417                         dmas = <&dma 2>;
 418                         dma-names = "tx";
 419                         pinctrl-names = "default";
 420                         pinctrl-0 = <&spdif_tx_pin>;
 421                         status = "disabled";
 422                 };
 423
 424                 uart0: serial@1c28000 {
 425                         compatible = "snps,dw-apb-uart";
 426                         reg = <0x01c28000 0x400>;
 427                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 428                         reg-shift = <2>;
 429                         reg-io-width = <4>;
 430                         clocks = <&ccu CLK_BUS_UART0>;
 431                         resets = <&ccu RST_BUS_UART0>;
 432                         status = "disabled";
 433                 };
 434
 435                 uart1: serial@1c28400 {
 436                         compatible = "snps,dw-apb-uart";
 437                         reg = <0x01c28400 0x400>;
 438                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 439                         reg-shift = <2>;
 440                         reg-io-width = <4>;
 441                         clocks = <&ccu CLK_BUS_UART1>;
 442                         resets = <&ccu RST_BUS_UART1>;
 443                         status = "disabled";
 444                 };
 445
 446                 uart2: serial@1c28800 {
 447                         compatible = "snps,dw-apb-uart";
 448                         reg = <0x01c28800 0x400>;
 449                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 450                         reg-shift = <2>;
 451                         reg-io-width = <4>;
 452                         clocks = <&ccu CLK_BUS_UART2>;
 453                         resets = <&ccu RST_BUS_UART2>;
 454                         status = "disabled";
 455                 };
 456
 457                 uart3: serial@1c28c00 {
 458                         compatible = "snps,dw-apb-uart";
 459                         reg = <0x01c28c00 0x400>;
 460                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 461                         reg-shift = <2>;
 462                         reg-io-width = <4>;
 463                         clocks = <&ccu CLK_BUS_UART3>;
 464                         resets = <&ccu RST_BUS_UART3>;
 465                         status = "disabled";
 466                 };
 467
 468                 uart4: serial@1c29000 {
 469                         compatible = "snps,dw-apb-uart";
 470                         reg = <0x01c29000 0x400>;
 471                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 472                         reg-shift = <2>;
 473                         reg-io-width = <4>;
 474                         clocks = <&ccu CLK_BUS_UART4>;
 475                         resets = <&ccu RST_BUS_UART4>;
 476                         status = "disabled";
 477                 };
 478
 479                 i2c0: i2c@1c2ac00 {
 480                         compatible = "allwinner,sun6i-a31-i2c";
 481                         reg = <0x01c2ac00 0x400>;
 482                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&ccu CLK_BUS_I2C0>;
 484                         resets = <&ccu RST_BUS_I2C0>;
 485                         status = "disabled";
 486                         #address-cells = <1>;
 487                         #size-cells = <0>;
 488                 };
 489
 490                 i2c1: i2c@1c2b000 {
 491                         compatible = "allwinner,sun6i-a31-i2c";
 492                         reg = <0x01c2b000 0x400>;
 493                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 494                         clocks = <&ccu CLK_BUS_I2C1>;
 495                         resets = <&ccu RST_BUS_I2C1>;
 496                         status = "disabled";
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                 };
 500
 501                 i2c2: i2c@1c2b400 {
 502                         compatible = "allwinner,sun6i-a31-i2c";
 503                         reg = <0x01c2b400 0x400>;
 504                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&ccu CLK_BUS_I2C2>;
 506                         resets = <&ccu RST_BUS_I2C2>;
 507                         status = "disabled";
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                 };
 511
 512
 513                 spi0: spi@1c68000 {
 514                         compatible = "allwinner,sun8i-h3-spi";
 515                         reg = <0x01c68000 0x1000>;
 516                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 518                         clock-names = "ahb", "mod";
 519                         dmas = <&dma 23>, <&dma 23>;
 520                         dma-names = "rx", "tx";
 521                         pinctrl-names = "default";
 522                         pinctrl-0 = <&spi0_pins>;
 523                         resets = <&ccu RST_BUS_SPI0>;
 524                         status = "disabled";
 525                         num-cs = <1>;
 526                         #address-cells = <1>;
 527                         #size-cells = <0>;
 528                 };
 529
 530                 spi1: spi@1c69000 {
 531                         compatible = "allwinner,sun8i-h3-spi";
 532                         reg = <0x01c69000 0x1000>;
 533                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 535                         clock-names = "ahb", "mod";
 536                         dmas = <&dma 24>, <&dma 24>;
 537                         dma-names = "rx", "tx";
 538                         pinctrl-names = "default";
 539                         pinctrl-0 = <&spi1_pins>;
 540                         resets = <&ccu RST_BUS_SPI1>;
 541                         status = "disabled";
 542                         num-cs = <1>;
 543                         #address-cells = <1>;
 544                         #size-cells = <0>;
 545                 };
 546
 547                 emac: ethernet@1c30000 {
 548                         compatible = "allwinner,sun50i-a64-emac";
 549                         syscon = <&syscon>;
 550                         reg = <0x01c30000 0x10000>;
 551                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 552                         interrupt-names = "macirq";
 553                         resets = <&ccu RST_BUS_EMAC>;
 554                         reset-names = "stmmaceth";
 555                         clocks = <&ccu CLK_BUS_EMAC>;
 556                         clock-names = "stmmaceth";
 557                         status = "disabled";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560
 561                         mdio: mdio {
 562                                 compatible = "snps,dwmac-mdio";
 563                                 #address-cells = <1>;
 564                                 #size-cells = <0>;
 565                         };
 566                 };
 567
 568                 gic: interrupt-controller@1c81000 {
 569                         compatible = "arm,gic-400";
 570                         reg = <0x01c81000 0x1000>,
 571                               <0x01c82000 0x2000>,
 572                               <0x01c84000 0x2000>,
 573                               <0x01c86000 0x2000>;
 574                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 575                         interrupt-controller;
 576                         #interrupt-cells = <3>;
 577                 };
 578
 579                 rtc: rtc@1f00000 {
 580                         compatible = "allwinner,sun6i-a31-rtc";
 581                         reg = <0x01f00000 0x54>;
 582                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 584                 };
 585
 586                 r_intc: interrupt-controller@1f00c00 {
 587                         compatible = "allwinner,sun50i-a64-r-intc",
 588                                      "allwinner,sun6i-a31-r-intc";
 589                         interrupt-controller;
 590                         #interrupt-cells = <2>;
 591                         reg = <0x01f00c00 0x400>;
 592                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 593                 };
 594
 595                 r_ccu: clock@1f01400 {
 596                         compatible = "allwinner,sun50i-a64-r-ccu";
 597                         reg = <0x01f01400 0x100>;
 598                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 599                                  <&ccu 11>;
 600                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 601                         #clock-cells = <1>;
 602                         #reset-cells = <1>;
 603                 };
 604
 605                 r_pio: pinctrl@1f02c00 {
 606                         compatible = "allwinner,sun50i-a64-r-pinctrl";
 607                         reg = <0x01f02c00 0x400>;
 608                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 610                         clock-names = "apb", "hosc", "losc";
 611                         gpio-controller;
 612                         #gpio-cells = <3>;
 613                         interrupt-controller;
 614                         #interrupt-cells = <3>;
 615
 616                         r_rsb_pins: rsb {
 617                                 pins = "PL0", "PL1";
 618                                 function = "s_rsb";
 619                         };
 620                 };
 621
 622                 r_rsb: rsb@1f03400 {
 623                         compatible = "allwinner,sun8i-a23-rsb";
 624                         reg = <0x01f03400 0x400>;
 625                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 626                         clocks = <&r_ccu 6>;
 627                         clock-frequency = <3000000>;
 628                         resets = <&r_ccu 2>;
 629                         pinctrl-names = "default";
 630                         pinctrl-0 = <&r_rsb_pins>;
 631                         status = "disabled";
 632                         #address-cells = <1>;
 633                         #size-cells = <0>;
 634                 };
 635         };
 636 };