1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HANDLE_DOMAIN_IRQ
137 select HARDIRQS_SW_RESEND
141 select HAVE_ACPI_APEI if (ACPI && EFI)
142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143 select HAVE_ARCH_AUDITSYSCALL
144 select HAVE_ARCH_BITREVERSE
145 select HAVE_ARCH_COMPILER_H
146 select HAVE_ARCH_HUGE_VMAP
147 select HAVE_ARCH_JUMP_LABEL
148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153 select HAVE_ARCH_KFENCE
154 select HAVE_ARCH_KGDB
155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157 select HAVE_ARCH_PREL32_RELOCATIONS
158 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
159 select HAVE_ARCH_SECCOMP_FILTER
160 select HAVE_ARCH_STACKLEAK
161 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
162 select HAVE_ARCH_TRACEHOOK
163 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
164 select HAVE_ARCH_VMAP_STACK
165 select HAVE_ARM_SMCCC
166 select HAVE_ASM_MODVERSIONS
168 select HAVE_C_RECORDMCOUNT
169 select HAVE_CMPXCHG_DOUBLE
170 select HAVE_CMPXCHG_LOCAL
171 select HAVE_CONTEXT_TRACKING
172 select HAVE_DEBUG_KMEMLEAK
173 select HAVE_DMA_CONTIGUOUS
174 select HAVE_DYNAMIC_FTRACE
175 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176 if $(cc-option,-fpatchable-function-entry=2)
177 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178 if DYNAMIC_FTRACE_WITH_REGS
179 select HAVE_EFFICIENT_UNALIGNED_ACCESS
181 select HAVE_FTRACE_MCOUNT_RECORD
182 select HAVE_FUNCTION_TRACER
183 select HAVE_FUNCTION_ERROR_INJECTION
184 select HAVE_FUNCTION_GRAPH_TRACER
185 select HAVE_GCC_PLUGINS
186 select HAVE_HW_BREAKPOINT if PERF_EVENTS
187 select HAVE_IRQ_TIME_ACCOUNTING
189 select HAVE_PATA_PLATFORM
190 select HAVE_PERF_EVENTS
191 select HAVE_PERF_REGS
192 select HAVE_PERF_USER_STACK_DUMP
193 select HAVE_REGS_AND_STACK_ACCESS_API
194 select HAVE_FUNCTION_ARG_ACCESS_API
195 select HAVE_FUTEX_CMPXCHG if FUTEX
196 select MMU_GATHER_RCU_TABLE_FREE
198 select HAVE_STACKPROTECTOR
199 select HAVE_SYSCALL_TRACEPOINTS
201 select HAVE_KRETPROBES
202 select HAVE_GENERIC_VDSO
203 select IOMMU_DMA if IOMMU_SUPPORT
205 select IRQ_FORCED_THREADING
206 select KASAN_VMALLOC if KASAN_GENERIC
207 select MODULES_USE_ELF_RELA
208 select NEED_DMA_MAP_STATE
209 select NEED_SG_DMA_LENGTH
211 select OF_EARLY_FLATTREE
212 select PCI_DOMAINS_GENERIC if PCI
213 select PCI_ECAM if (ACPI && PCI)
214 select PCI_SYSCALL if PCI
219 select SYSCTL_EXCEPTION_TRACE
220 select THREAD_INFO_IN_TASK
221 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
222 select TRACE_IRQFLAGS_SUPPORT
223 select TRACE_IRQFLAGS_NMI_SUPPORT
225 ARM 64-bit (AArch64) Linux support.
233 config ARM64_PAGE_SHIFT
235 default 16 if ARM64_64K_PAGES
236 default 14 if ARM64_16K_PAGES
239 config ARM64_CONT_PTE_SHIFT
241 default 5 if ARM64_64K_PAGES
242 default 7 if ARM64_16K_PAGES
245 config ARM64_CONT_PMD_SHIFT
247 default 5 if ARM64_64K_PAGES
248 default 5 if ARM64_16K_PAGES
251 config ARCH_MMAP_RND_BITS_MIN
252 default 14 if ARM64_64K_PAGES
253 default 16 if ARM64_16K_PAGES
256 # max bits determined by the following formula:
257 # VA_BITS - PAGE_SHIFT - 3
258 config ARCH_MMAP_RND_BITS_MAX
259 default 19 if ARM64_VA_BITS=36
260 default 24 if ARM64_VA_BITS=39
261 default 27 if ARM64_VA_BITS=42
262 default 30 if ARM64_VA_BITS=47
263 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
264 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
265 default 33 if ARM64_VA_BITS=48
266 default 14 if ARM64_64K_PAGES
267 default 16 if ARM64_16K_PAGES
270 config ARCH_MMAP_RND_COMPAT_BITS_MIN
271 default 7 if ARM64_64K_PAGES
272 default 9 if ARM64_16K_PAGES
275 config ARCH_MMAP_RND_COMPAT_BITS_MAX
281 config STACKTRACE_SUPPORT
284 config ILLEGAL_POINTER_VALUE
286 default 0xdead000000000000
288 config LOCKDEP_SUPPORT
295 config GENERIC_BUG_RELATIVE_POINTERS
297 depends on GENERIC_BUG
299 config GENERIC_HWEIGHT
305 config GENERIC_CALIBRATE_DELAY
308 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
314 config KERNEL_MODE_NEON
317 config FIX_EARLYCON_MEM
320 config PGTABLE_LEVELS
322 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
323 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
324 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
325 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
326 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
327 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329 config ARCH_SUPPORTS_UPROBES
332 config ARCH_PROC_KCORE_TEXT
335 config BROKEN_GAS_INST
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338 config KASAN_SHADOW_OFFSET
340 depends on KASAN_GENERIC || KASAN_SW_TAGS
341 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
342 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
343 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
344 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
345 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
346 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
347 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
348 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
349 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
350 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
351 default 0xffffffffffffffff
353 source "arch/arm64/Kconfig.platforms"
355 menu "Kernel Features"
357 menu "ARM errata workarounds via the alternatives framework"
359 config ARM64_WORKAROUND_CLEAN_CACHE
362 config ARM64_ERRATUM_826319
363 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365 select ARM64_WORKAROUND_CLEAN_CACHE
367 This option adds an alternative code sequence to work around ARM
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
369 AXI master interface and an L2 cache.
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
372 and is unable to accept a certain write via this interface, it will
373 not progress on read data presented on the read data channel and the
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_827319
385 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387 select ARM64_WORKAROUND_CLEAN_CACHE
389 This option adds an alternative code sequence to work around ARM
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
391 master interface and an L2 cache.
393 Under certain conditions this erratum can cause a clean line eviction
394 to occur at the same time as another transaction to the same address
395 on the AMBA 5 CHI interface, which can cause data corruption if the
396 interconnect reorders the two transactions.
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this does not necessarily enable the workaround,
401 as it depends on the alternative framework, which will only patch
402 the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_824069
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
413 to a coherent interconnect.
415 If a Cortex-A53 processor is executing a store or prefetch for
416 write instruction at the same time as a processor in another
417 cluster is executing a cache maintenance operation to the same
418 address, then this erratum might cause a clean cache line to be
419 incorrectly marked as dirty.
421 The workaround promotes data cache clean instructions to
422 data cache clean-and-invalidate.
423 Please note that this option does not necessarily enable the
424 workaround, as it depends on the alternative framework, which will
425 only patch the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_819472
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432 select ARM64_WORKAROUND_CLEAN_CACHE
434 This option adds an alternative code sequence to work around ARM
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
436 present when it is connected to a coherent interconnect.
438 If the processor is executing a load and store exclusive sequence at
439 the same time as a processor in another cluster is executing a cache
440 maintenance operation to the same address, then this erratum might
441 cause data corruption.
443 The workaround promotes data cache clean instructions to
444 data cache clean-and-invalidate.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_832075
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
455 This option adds an alternative code sequence to work around ARM
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
463 Please note that this does not necessarily enable the workaround,
464 as it depends on the alternative framework, which will only patch
465 the kernel if an affected CPU is detected.
469 config ARM64_ERRATUM_834220
470 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
474 This option adds an alternative code sequence to work around ARM
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
478 fault as the result of a Stage 1 fault for load crossing a
479 page boundary when there is a permission or device memory
480 alignment fault at Stage 1 and a translation fault at Stage 2.
482 The workaround is to verify that the Stage 1 translation
483 doesn't generate a fault before handling the Stage 2 fault.
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_845719
491 bool "Cortex-A53: 845719: a load might read incorrect data"
495 This option adds an alternative code sequence to work around ARM
496 erratum 845719 on Cortex-A53 parts up to r0p4.
498 When running a compat (AArch32) userspace on an affected Cortex-A53
499 part, a load at EL0 from a virtual address that matches the bottom 32
500 bits of the virtual address used by a recent load at (AArch64) EL1
501 might return incorrect data.
503 The workaround is to write the contextidr_el1 register on exception
504 return to a 32-bit task.
505 Please note that this does not necessarily enable the workaround,
506 as it depends on the alternative framework, which will only patch
507 the kernel if an affected CPU is detected.
511 config ARM64_ERRATUM_843419
512 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
514 select ARM64_MODULE_PLTS if MODULES
516 This option links the kernel with '--fix-cortex-a53-843419' and
517 enables PLT support to replace certain ADRP instructions, which can
518 cause subsequent memory accesses to use an incorrect address on
519 Cortex-A53 parts up to r0p4.
523 config ARM64_LD_HAS_FIX_ERRATUM_843419
524 def_bool $(ld-option,--fix-cortex-a53-843419)
526 config ARM64_ERRATUM_1024718
527 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
530 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
532 Affected Cortex-A55 cores (all revisions) could cause incorrect
533 update of the hardware dirty bit when the DBM/AP bits are updated
534 without a break-before-make. The workaround is to disable the usage
535 of hardware DBM locally on the affected cores. CPUs not affected by
536 this erratum will continue to use the feature.
540 config ARM64_ERRATUM_1418040
541 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
545 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
546 errata 1188873 and 1418040.
548 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
549 cause register corruption when accessing the timer registers
550 from AArch32 userspace.
554 config ARM64_WORKAROUND_SPECULATIVE_AT
557 config ARM64_ERRATUM_1165522
558 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
560 select ARM64_WORKAROUND_SPECULATIVE_AT
562 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
564 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
565 corrupted TLBs by speculating an AT instruction during a guest
570 config ARM64_ERRATUM_1319367
571 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573 select ARM64_WORKAROUND_SPECULATIVE_AT
575 This option adds work arounds for ARM Cortex-A57 erratum 1319537
576 and A72 erratum 1319367
578 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
579 speculating an AT instruction during a guest context switch.
583 config ARM64_ERRATUM_1530923
584 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586 select ARM64_WORKAROUND_SPECULATIVE_AT
588 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
591 corrupted TLBs by speculating an AT instruction during a guest
596 config ARM64_WORKAROUND_REPEAT_TLBI
599 config ARM64_ERRATUM_1286807
600 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
602 select ARM64_WORKAROUND_REPEAT_TLBI
604 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
606 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
607 address for a cacheable mapping of a location is being
608 accessed by a core while another core is remapping the virtual
609 address to a new physical page using the recommended
610 break-before-make sequence, then under very rare circumstances
611 TLBI+DSB completes before a read using the translation being
612 invalidated has been observed by other observers. The
613 workaround repeats the TLBI+DSB operation.
615 config ARM64_ERRATUM_1463225
616 bool "Cortex-A76: Software Step might prevent interrupt recognition"
619 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
621 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
622 of a system call instruction (SVC) can prevent recognition of
623 subsequent interrupts when software stepping is disabled in the
624 exception handler of the system call and either kernel debugging
625 is enabled or VHE is in use.
627 Work around the erratum by triggering a dummy step exception
628 when handling a system call from a task that is being stepped
629 in a VHE configuration of the kernel.
633 config ARM64_ERRATUM_1542419
634 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
637 This option adds a workaround for ARM Neoverse-N1 erratum
640 Affected Neoverse-N1 cores could execute a stale instruction when
641 modified by another CPU. The workaround depends on a firmware
644 Workaround the issue by hiding the DIC feature from EL0. This
645 forces user-space to perform cache maintenance.
649 config ARM64_ERRATUM_1508412
650 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
653 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
655 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
656 of a store-exclusive or read of PAR_EL1 and a load with device or
657 non-cacheable memory attributes. The workaround depends on a firmware
660 KVM guests must also have the workaround implemented or they can
663 Work around the issue by inserting DMB SY barriers around PAR_EL1
664 register reads and warning KVM users. The DMB barrier is sufficient
665 to prevent a speculative PAR_EL1 read.
669 config ARM64_ERRATUM_2441009
670 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
672 select ARM64_WORKAROUND_REPEAT_TLBI
674 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
676 Under very rare circumstances, affected Cortex-A510 CPUs
677 may not handle a race between a break-before-make sequence on one
678 CPU, and another CPU accessing the same page. This could allow a
679 store to a page that has been unmapped.
681 Work around this by adding the affected CPUs to the list that needs
682 TLB sequences to be done twice.
686 config CAVIUM_ERRATUM_22375
687 bool "Cavium erratum 22375, 24313"
690 Enable workaround for errata 22375 and 24313.
692 This implements two gicv3-its errata workarounds for ThunderX. Both
693 with a small impact affecting only ITS table allocation.
695 erratum 22375: only alloc 8MB table size
696 erratum 24313: ignore memory access type
698 The fixes are in ITS initialization and basically ignore memory access
699 type and table size provided by the TYPER and BASER registers.
703 config CAVIUM_ERRATUM_23144
704 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
708 ITS SYNC command hang for cross node io and collections/cpu mapping.
712 config CAVIUM_ERRATUM_23154
713 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
716 The gicv3 of ThunderX requires a modified version for
717 reading the IAR status to ensure data synchronization
718 (access to icc_iar1_el1 is not sync'ed before and after).
722 config CAVIUM_ERRATUM_27456
723 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
726 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
727 instructions may cause the icache to become corrupted if it
728 contains data for a non-current ASID. The fix is to
729 invalidate the icache when changing the mm context.
733 config CAVIUM_ERRATUM_30115
734 bool "Cavium erratum 30115: Guest may disable interrupts in host"
737 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
738 1.2, and T83 Pass 1.0, KVM guest execution may disable
739 interrupts in host. Trapping both GICv3 group-0 and group-1
740 accesses sidesteps the issue.
744 config CAVIUM_TX2_ERRATUM_219
745 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
748 On Cavium ThunderX2, a load, store or prefetch instruction between a
749 TTBR update and the corresponding context synchronizing operation can
750 cause a spurious Data Abort to be delivered to any hardware thread in
753 Work around the issue by avoiding the problematic code sequence and
754 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
755 trap handler performs the corresponding register access, skips the
756 instruction and ensures context synchronization by virtue of the
761 config FUJITSU_ERRATUM_010001
762 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
765 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
766 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
767 accesses may cause undefined fault (Data abort, DFSC=0b111111).
768 This fault occurs under a specific hardware condition when a
769 load/store instruction performs an address translation using:
770 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
771 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
772 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
773 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
775 The workaround is to ensure these bits are clear in TCR_ELx.
776 The workaround only affects the Fujitsu-A64FX.
780 config HISILICON_ERRATUM_161600802
781 bool "Hip07 161600802: Erroneous redistributor VLPI base"
784 The HiSilicon Hip07 SoC uses the wrong redistributor base
785 when issued ITS commands such as VMOVP and VMAPP, and requires
786 a 128kB offset to be applied to the target address in this commands.
790 config QCOM_FALKOR_ERRATUM_1003
791 bool "Falkor E1003: Incorrect translation due to ASID change"
794 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
795 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
796 in TTBR1_EL1, this situation only occurs in the entry trampoline and
797 then only for entries in the walk cache, since the leaf translation
798 is unchanged. Work around the erratum by invalidating the walk cache
799 entries for the trampoline before entering the kernel proper.
801 config QCOM_FALKOR_ERRATUM_1009
802 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
804 select ARM64_WORKAROUND_REPEAT_TLBI
806 On Falkor v1, the CPU may prematurely complete a DSB following a
807 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
808 one more time to fix the issue.
812 config QCOM_QDF2400_ERRATUM_0065
813 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
816 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
817 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
818 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
822 config QCOM_FALKOR_ERRATUM_E1041
823 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
826 Falkor CPU may speculatively fetch instructions from an improper
827 memory location when MMU translation is changed from SCTLR_ELn[M]=1
828 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
832 config NVIDIA_CARMEL_CNP_ERRATUM
833 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
836 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
837 invalidate shared TLB entries installed by a different core, as it would
838 on standard ARM cores.
842 config SOCIONEXT_SYNQUACER_PREITS
843 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
846 Socionext Synquacer SoCs implement a separate h/w block to generate
847 MSI doorbell writes with non-zero values for the device ID.
856 default ARM64_4K_PAGES
858 Page size (translation granule) configuration.
860 config ARM64_4K_PAGES
863 This feature enables 4KB pages support.
865 config ARM64_16K_PAGES
868 The system will use 16KB pages support. AArch32 emulation
869 requires applications compiled with 16K (or a multiple of 16K)
872 config ARM64_64K_PAGES
875 This feature enables 64KB pages support (4KB by default)
876 allowing only two levels of page tables and faster TLB
877 look-up. AArch32 emulation requires applications compiled
878 with 64K aligned segments.
883 prompt "Virtual address space size"
884 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
885 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
886 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
888 Allows choosing one of multiple possible virtual address
889 space sizes. The level of translation table is determined by
890 a combination of page size and virtual address space size.
892 config ARM64_VA_BITS_36
893 bool "36-bit" if EXPERT
894 depends on ARM64_16K_PAGES
896 config ARM64_VA_BITS_39
898 depends on ARM64_4K_PAGES
900 config ARM64_VA_BITS_42
902 depends on ARM64_64K_PAGES
904 config ARM64_VA_BITS_47
906 depends on ARM64_16K_PAGES
908 config ARM64_VA_BITS_48
911 config ARM64_VA_BITS_52
913 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
915 Enable 52-bit virtual addressing for userspace when explicitly
916 requested via a hint to mmap(). The kernel will also use 52-bit
917 virtual addresses for its own mappings (provided HW support for
918 this feature is available, otherwise it reverts to 48-bit).
920 NOTE: Enabling 52-bit virtual addressing in conjunction with
921 ARMv8.3 Pointer Authentication will result in the PAC being
922 reduced from 7 bits to 3 bits, which may have a significant
923 impact on its susceptibility to brute-force attacks.
925 If unsure, select 48-bit virtual addressing instead.
929 config ARM64_FORCE_52BIT
930 bool "Force 52-bit virtual addresses for userspace"
931 depends on ARM64_VA_BITS_52 && EXPERT
933 For systems with 52-bit userspace VAs enabled, the kernel will attempt
934 to maintain compatibility with older software by providing 48-bit VAs
935 unless a hint is supplied to mmap.
937 This configuration option disables the 48-bit compatibility logic, and
938 forces all userspace addresses to be 52-bit on HW that supports it. One
939 should only enable this configuration option for stress testing userspace
940 memory management code. If unsure say N here.
944 default 36 if ARM64_VA_BITS_36
945 default 39 if ARM64_VA_BITS_39
946 default 42 if ARM64_VA_BITS_42
947 default 47 if ARM64_VA_BITS_47
948 default 48 if ARM64_VA_BITS_48
949 default 52 if ARM64_VA_BITS_52
952 prompt "Physical address space size"
953 default ARM64_PA_BITS_48
955 Choose the maximum physical address range that the kernel will
958 config ARM64_PA_BITS_48
961 config ARM64_PA_BITS_52
962 bool "52-bit (ARMv8.2)"
963 depends on ARM64_64K_PAGES
964 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
966 Enable support for a 52-bit physical address space, introduced as
967 part of the ARMv8.2-LPA extension.
969 With this enabled, the kernel will also continue to work on CPUs that
970 do not support ARMv8.2-LPA, but with some added memory overhead (and
971 minor performance overhead).
977 default 48 if ARM64_PA_BITS_48
978 default 52 if ARM64_PA_BITS_52
982 default CPU_LITTLE_ENDIAN
984 Select the endianness of data accesses performed by the CPU. Userspace
985 applications will need to be compiled and linked for the endianness
986 that is selected here.
988 config CPU_BIG_ENDIAN
989 bool "Build big-endian kernel"
990 depends on !LD_IS_LLD || LLD_VERSION >= 130000
992 Say Y if you plan on running a kernel with a big-endian userspace.
994 config CPU_LITTLE_ENDIAN
995 bool "Build little-endian kernel"
997 Say Y if you plan on running a kernel with a little-endian userspace.
998 This is usually the case for distributions targeting arm64.
1003 bool "Multi-core scheduler support"
1005 Multi-core scheduler support improves the CPU scheduler's decision
1006 making when dealing with multi-core CPU chips at a cost of slightly
1007 increased overhead in some places. If unsure say N here.
1010 bool "SMT scheduler support"
1012 Improves the CPU scheduler's decision making when dealing with
1013 MultiThreading at a cost of slightly increased overhead in some
1014 places. If unsure say N here.
1017 int "Maximum number of CPUs (2-4096)"
1022 bool "Support for hot-pluggable CPUs"
1023 select GENERIC_IRQ_MIGRATION
1025 Say Y here to experiment with turning CPUs off and on. CPUs
1026 can be controlled through /sys/devices/system/cpu.
1028 # Common NUMA Features
1030 bool "NUMA Memory Allocation and Scheduler Support"
1031 select GENERIC_ARCH_NUMA
1032 select ACPI_NUMA if ACPI
1035 Enable NUMA (Non-Uniform Memory Access) support.
1037 The kernel will try to allocate memory used by a CPU on the
1038 local memory of the CPU and add some more
1039 NUMA awareness to the kernel.
1042 int "Maximum NUMA Nodes (as a power of 2)"
1047 Specify the maximum number of NUMA Nodes available on the target
1048 system. Increases memory reserved to accommodate various tables.
1050 config USE_PERCPU_NUMA_NODE_ID
1054 config HAVE_SETUP_PER_CPU_AREA
1058 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1062 source "kernel/Kconfig.hz"
1064 config ARCH_SPARSEMEM_ENABLE
1066 select SPARSEMEM_VMEMMAP_ENABLE
1067 select SPARSEMEM_VMEMMAP
1069 config HW_PERF_EVENTS
1073 # Supported by clang >= 7.0
1074 config CC_HAVE_SHADOW_CALL_STACK
1075 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1078 bool "Enable paravirtualization code"
1080 This changes the kernel so it can modify itself when it is run
1081 under a hypervisor, potentially improving performance significantly
1082 over full virtualization.
1084 config PARAVIRT_TIME_ACCOUNTING
1085 bool "Paravirtual steal time accounting"
1088 Select this option to enable fine granularity task steal time
1089 accounting. Time spent executing other tasks in parallel with
1090 the current vCPU is discounted from the vCPU power. To account for
1091 that, there can be a small performance impact.
1093 If in doubt, say N here.
1096 depends on PM_SLEEP_SMP
1098 bool "kexec system call"
1100 kexec is a system call that implements the ability to shutdown your
1101 current kernel, and to start another kernel. It is like a reboot
1102 but it is independent of the system firmware. And like a reboot
1103 you can start any kernel with it, not just Linux.
1106 bool "kexec file based system call"
1108 select HAVE_IMA_KEXEC if IMA
1110 This is new version of kexec system call. This system call is
1111 file based and takes file descriptors as system call argument
1112 for kernel and initramfs as opposed to list of segments as
1113 accepted by previous system call.
1116 bool "Verify kernel signature during kexec_file_load() syscall"
1117 depends on KEXEC_FILE
1119 Select this option to verify a signature with loaded kernel
1120 image. If configured, any attempt of loading a image without
1121 valid signature will fail.
1123 In addition to that option, you need to enable signature
1124 verification for the corresponding kernel image type being
1125 loaded in order for this to work.
1127 config KEXEC_IMAGE_VERIFY_SIG
1128 bool "Enable Image signature verification support"
1130 depends on KEXEC_SIG
1131 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1133 Enable Image signature verification support.
1135 comment "Support for PE file signature verification disabled"
1136 depends on KEXEC_SIG
1137 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1140 bool "Build kdump crash kernel"
1142 Generate crash dump after being started by kexec. This should
1143 be normally only set in special crash dump kernels which are
1144 loaded in the main kernel with kexec-tools into a specially
1145 reserved region and then later executed after a crash by
1148 For more details see Documentation/admin-guide/kdump/kdump.rst
1152 depends on HIBERNATION
1159 bool "Xen guest support on ARM64"
1160 depends on ARM64 && OF
1164 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1166 config FORCE_MAX_ZONEORDER
1168 default "14" if ARM64_64K_PAGES
1169 default "12" if ARM64_16K_PAGES
1172 The kernel memory allocator divides physically contiguous memory
1173 blocks into "zones", where each zone is a power of two number of
1174 pages. This option selects the largest power of two that the kernel
1175 keeps in the memory allocator. If you need to allocate very large
1176 blocks of physically contiguous memory, then you may need to
1177 increase this value.
1179 This config option is actually maximum order plus one. For example,
1180 a value of 11 means that the largest free memory block is 2^10 pages.
1182 We make sure that we can allocate upto a HugePage size for each configuration.
1184 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1186 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1187 4M allocations matching the default size used by generic code.
1189 config UNMAP_KERNEL_AT_EL0
1190 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1193 Speculation attacks against some high-performance processors can
1194 be used to bypass MMU permission checks and leak kernel data to
1195 userspace. This can be defended against by unmapping the kernel
1196 when running in userspace, mapping it back in on exception entry
1197 via a trampoline page in the vector table.
1201 config MITIGATE_SPECTRE_BRANCH_HISTORY
1202 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1205 Speculation attacks against some high-performance processors can
1206 make use of branch history to influence future speculation.
1207 When taking an exception from user-space, a sequence of branches
1208 or a firmware call overwrites the branch history.
1210 config RODATA_FULL_DEFAULT_ENABLED
1211 bool "Apply r/o permissions of VM areas also to their linear aliases"
1214 Apply read-only attributes of VM areas to the linear alias of
1215 the backing pages as well. This prevents code or read-only data
1216 from being modified (inadvertently or intentionally) via another
1217 mapping of the same memory page. This additional enhancement can
1218 be turned off at runtime by passing rodata=[off|on] (and turned on
1219 with rodata=full if this option is set to 'n')
1221 This requires the linear region to be mapped down to pages,
1222 which may adversely affect performance in some cases.
1224 config ARM64_SW_TTBR0_PAN
1225 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1227 Enabling this option prevents the kernel from accessing
1228 user-space memory directly by pointing TTBR0_EL1 to a reserved
1229 zeroed area and reserved ASID. The user access routines
1230 restore the valid TTBR0_EL1 temporarily.
1232 config ARM64_TAGGED_ADDR_ABI
1233 bool "Enable the tagged user addresses syscall ABI"
1236 When this option is enabled, user applications can opt in to a
1237 relaxed ABI via prctl() allowing tagged addresses to be passed
1238 to system calls as pointer arguments. For details, see
1239 Documentation/arm64/tagged-address-abi.rst.
1242 bool "Kernel support for 32-bit EL0"
1243 depends on ARM64_4K_PAGES || EXPERT
1245 select OLD_SIGSUSPEND3
1246 select COMPAT_OLD_SIGACTION
1248 This option enables support for a 32-bit EL0 running under a 64-bit
1249 kernel at EL1. AArch32-specific components such as system calls,
1250 the user helper functions, VFP support and the ptrace interface are
1251 handled appropriately by the kernel.
1253 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1254 that you will only be able to execute AArch32 binaries that were compiled
1255 with page size aligned segments.
1257 If you want to execute 32-bit userspace applications, say Y.
1261 config KUSER_HELPERS
1262 bool "Enable kuser helpers page for 32-bit applications"
1265 Warning: disabling this option may break 32-bit user programs.
1267 Provide kuser helpers to compat tasks. The kernel provides
1268 helper code to userspace in read only form at a fixed location
1269 to allow userspace to be independent of the CPU type fitted to
1270 the system. This permits binaries to be run on ARMv4 through
1271 to ARMv8 without modification.
1273 See Documentation/arm/kernel_user_helpers.rst for details.
1275 However, the fixed address nature of these helpers can be used
1276 by ROP (return orientated programming) authors when creating
1279 If all of the binaries and libraries which run on your platform
1280 are built specifically for your platform, and make no use of
1281 these helpers, then you can turn this option off to hinder
1282 such exploits. However, in that case, if a binary or library
1283 relying on those helpers is run, it will not function correctly.
1285 Say N here only if you are absolutely certain that you do not
1286 need these helpers; otherwise, the safe option is to say Y.
1289 bool "Enable vDSO for 32-bit applications"
1290 depends on !CPU_BIG_ENDIAN
1291 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1292 select GENERIC_COMPAT_VDSO
1295 Place in the process address space of 32-bit applications an
1296 ELF shared object providing fast implementations of gettimeofday
1299 You must have a 32-bit build of glibc 2.22 or later for programs
1300 to seamlessly take advantage of this.
1302 config THUMB2_COMPAT_VDSO
1303 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1304 depends on COMPAT_VDSO
1307 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1308 otherwise with '-marm'.
1310 menuconfig ARMV8_DEPRECATED
1311 bool "Emulate deprecated/obsolete ARMv8 instructions"
1314 Legacy software support may require certain instructions
1315 that have been deprecated or obsoleted in the architecture.
1317 Enable this config to enable selective emulation of these
1324 config SWP_EMULATION
1325 bool "Emulate SWP/SWPB instructions"
1327 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1328 they are always undefined. Say Y here to enable software
1329 emulation of these instructions for userspace using LDXR/STXR.
1330 This feature can be controlled at runtime with the abi.swp
1331 sysctl which is disabled by default.
1333 In some older versions of glibc [<=2.8] SWP is used during futex
1334 trylock() operations with the assumption that the code will not
1335 be preempted. This invalid assumption may be more likely to fail
1336 with SWP emulation enabled, leading to deadlock of the user
1339 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1340 on an external transaction monitoring block called a global
1341 monitor to maintain update atomicity. If your system does not
1342 implement a global monitor, this option can cause programs that
1343 perform SWP operations to uncached memory to deadlock.
1347 config CP15_BARRIER_EMULATION
1348 bool "Emulate CP15 Barrier instructions"
1350 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1351 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1352 strongly recommended to use the ISB, DSB, and DMB
1353 instructions instead.
1355 Say Y here to enable software emulation of these
1356 instructions for AArch32 userspace code. When this option is
1357 enabled, CP15 barrier usage is traced which can help
1358 identify software that needs updating. This feature can be
1359 controlled at runtime with the abi.cp15_barrier sysctl.
1363 config SETEND_EMULATION
1364 bool "Emulate SETEND instruction"
1366 The SETEND instruction alters the data-endianness of the
1367 AArch32 EL0, and is deprecated in ARMv8.
1369 Say Y here to enable software emulation of the instruction
1370 for AArch32 userspace code. This feature can be controlled
1371 at runtime with the abi.setend sysctl.
1373 Note: All the cpus on the system must have mixed endian support at EL0
1374 for this feature to be enabled. If a new CPU - which doesn't support mixed
1375 endian - is hotplugged in after this feature has been enabled, there could
1376 be unexpected results in the applications.
1383 menu "ARMv8.1 architectural features"
1385 config ARM64_HW_AFDBM
1386 bool "Support for hardware updates of the Access and Dirty page flags"
1389 The ARMv8.1 architecture extensions introduce support for
1390 hardware updates of the access and dirty information in page
1391 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1392 capable processors, accesses to pages with PTE_AF cleared will
1393 set this bit instead of raising an access flag fault.
1394 Similarly, writes to read-only pages with the DBM bit set will
1395 clear the read-only bit (AP[2]) instead of raising a
1398 Kernels built with this configuration option enabled continue
1399 to work on pre-ARMv8.1 hardware and the performance impact is
1400 minimal. If unsure, say Y.
1403 bool "Enable support for Privileged Access Never (PAN)"
1406 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1407 prevents the kernel or hypervisor from accessing user-space (EL0)
1410 Choosing this option will cause any unprotected (not using
1411 copy_to_user et al) memory access to fail with a permission fault.
1413 The feature is detected at runtime, and will remain as a 'nop'
1414 instruction if the cpu does not implement the feature.
1417 def_bool $(as-instr,.arch_extension rcpc)
1419 config AS_HAS_LSE_ATOMICS
1420 def_bool $(as-instr,.arch_extension lse)
1422 config ARM64_LSE_ATOMICS
1424 default ARM64_USE_LSE_ATOMICS
1425 depends on AS_HAS_LSE_ATOMICS
1427 config ARM64_USE_LSE_ATOMICS
1428 bool "Atomic instructions"
1429 depends on JUMP_LABEL
1432 As part of the Large System Extensions, ARMv8.1 introduces new
1433 atomic instructions that are designed specifically to scale in
1436 Say Y here to make use of these instructions for the in-kernel
1437 atomic routines. This incurs a small overhead on CPUs that do
1438 not support these instructions and requires the kernel to be
1439 built with binutils >= 2.25 in order for the new instructions
1444 menu "ARMv8.2 architectural features"
1447 bool "Enable support for persistent memory"
1448 select ARCH_HAS_PMEM_API
1449 select ARCH_HAS_UACCESS_FLUSHCACHE
1451 Say Y to enable support for the persistent memory API based on the
1452 ARMv8.2 DCPoP feature.
1454 The feature is detected at runtime, and the kernel will use DC CVAC
1455 operations if DC CVAP is not supported (following the behaviour of
1456 DC CVAP itself if the system does not define a point of persistence).
1458 config ARM64_RAS_EXTN
1459 bool "Enable support for RAS CPU Extensions"
1462 CPUs that support the Reliability, Availability and Serviceability
1463 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1464 errors, classify them and report them to software.
1466 On CPUs with these extensions system software can use additional
1467 barriers to determine if faults are pending and read the
1468 classification from a new set of registers.
1470 Selecting this feature will allow the kernel to use these barriers
1471 and access the new registers if the system supports the extension.
1472 Platform RAS features may additionally depend on firmware support.
1475 bool "Enable support for Common Not Private (CNP) translations"
1477 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1479 Common Not Private (CNP) allows translation table entries to
1480 be shared between different PEs in the same inner shareable
1481 domain, so the hardware can use this fact to optimise the
1482 caching of such entries in the TLB.
1484 Selecting this option allows the CNP feature to be detected
1485 at runtime, and does not affect PEs that do not implement
1490 menu "ARMv8.3 architectural features"
1492 config ARM64_PTR_AUTH
1493 bool "Enable support for pointer authentication"
1496 Pointer authentication (part of the ARMv8.3 Extensions) provides
1497 instructions for signing and authenticating pointers against secret
1498 keys, which can be used to mitigate Return Oriented Programming (ROP)
1501 This option enables these instructions at EL0 (i.e. for userspace).
1502 Choosing this option will cause the kernel to initialise secret keys
1503 for each process at exec() time, with these keys being
1504 context-switched along with the process.
1506 The feature is detected at runtime. If the feature is not present in
1507 hardware it will not be advertised to userspace/KVM guest nor will it
1510 If the feature is present on the boot CPU but not on a late CPU, then
1511 the late CPU will be parked. Also, if the boot CPU does not have
1512 address auth and the late CPU has then the late CPU will still boot
1513 but with the feature disabled. On such a system, this option should
1516 config ARM64_PTR_AUTH_KERNEL
1517 bool "Use pointer authentication for kernel"
1519 depends on ARM64_PTR_AUTH
1520 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1521 # Modern compilers insert a .note.gnu.property section note for PAC
1522 # which is only understood by binutils starting with version 2.33.1.
1523 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1524 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1525 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1527 If the compiler supports the -mbranch-protection or
1528 -msign-return-address flag (e.g. GCC 7 or later), then this option
1529 will cause the kernel itself to be compiled with return address
1530 protection. In this case, and if the target hardware is known to
1531 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1532 disabled with minimal loss of protection.
1534 This feature works with FUNCTION_GRAPH_TRACER option only if
1535 DYNAMIC_FTRACE_WITH_REGS is enabled.
1537 config CC_HAS_BRANCH_PROT_PAC_RET
1538 # GCC 9 or later, clang 8 or later
1539 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1541 config CC_HAS_SIGN_RETURN_ADDRESS
1543 def_bool $(cc-option,-msign-return-address=all)
1546 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1548 config AS_HAS_CFI_NEGATE_RA_STATE
1549 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1553 menu "ARMv8.4 architectural features"
1555 config ARM64_AMU_EXTN
1556 bool "Enable support for the Activity Monitors Unit CPU extension"
1559 The activity monitors extension is an optional extension introduced
1560 by the ARMv8.4 CPU architecture. This enables support for version 1
1561 of the activity monitors architecture, AMUv1.
1563 To enable the use of this extension on CPUs that implement it, say Y.
1565 Note that for architectural reasons, firmware _must_ implement AMU
1566 support when running on CPUs that present the activity monitors
1567 extension. The required support is present in:
1568 * Version 1.5 and later of the ARM Trusted Firmware
1570 For kernels that have this configuration enabled but boot with broken
1571 firmware, you may need to say N here until the firmware is fixed.
1572 Otherwise you may experience firmware panics or lockups when
1573 accessing the counter registers. Even if you are not observing these
1574 symptoms, the values returned by the register reads might not
1575 correctly reflect reality. Most commonly, the value read will be 0,
1576 indicating that the counter is not enabled.
1578 config AS_HAS_ARMV8_4
1579 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1581 config ARM64_TLB_RANGE
1582 bool "Enable support for tlbi range feature"
1584 depends on AS_HAS_ARMV8_4
1586 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1587 range of input addresses.
1589 The feature introduces new assembly instructions, and they were
1590 support when binutils >= 2.30.
1594 menu "ARMv8.5 architectural features"
1596 config AS_HAS_ARMV8_5
1597 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1600 bool "Branch Target Identification support"
1603 Branch Target Identification (part of the ARMv8.5 Extensions)
1604 provides a mechanism to limit the set of locations to which computed
1605 branch instructions such as BR or BLR can jump.
1607 To make use of BTI on CPUs that support it, say Y.
1609 BTI is intended to provide complementary protection to other control
1610 flow integrity protection mechanisms, such as the Pointer
1611 authentication mechanism provided as part of the ARMv8.3 Extensions.
1612 For this reason, it does not make sense to enable this option without
1613 also enabling support for pointer authentication. Thus, when
1614 enabling this option you should also select ARM64_PTR_AUTH=y.
1616 Userspace binaries must also be specifically compiled to make use of
1617 this mechanism. If you say N here or the hardware does not support
1618 BTI, such binaries can still run, but you get no additional
1619 enforcement of branch destinations.
1621 config ARM64_BTI_KERNEL
1622 bool "Use Branch Target Identification for kernel"
1624 depends on ARM64_BTI
1625 depends on ARM64_PTR_AUTH_KERNEL
1626 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1627 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1628 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1629 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1630 depends on !CC_IS_GCC
1631 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1632 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1633 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1635 Build the kernel with Branch Target Identification annotations
1636 and enable enforcement of this for kernel code. When this option
1637 is enabled and the system supports BTI all kernel code including
1638 modular code must have BTI enabled.
1640 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1641 # GCC 9 or later, clang 8 or later
1642 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1645 bool "Enable support for E0PD"
1648 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1649 that EL0 accesses made via TTBR1 always fault in constant time,
1650 providing similar benefits to KASLR as those provided by KPTI, but
1651 with lower overhead and without disrupting legitimate access to
1652 kernel memory such as SPE.
1654 This option enables E0PD for TTBR1 where available.
1657 bool "Enable support for random number generation"
1660 Random number generation (part of the ARMv8.5 Extensions)
1661 provides a high bandwidth, cryptographically secure
1662 hardware random number generator.
1664 config ARM64_AS_HAS_MTE
1665 # Initial support for MTE went in binutils 2.32.0, checked with
1666 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1667 # as a late addition to the final architecture spec (LDGM/STGM)
1668 # is only supported in the newer 2.32.x and 2.33 binutils
1669 # versions, hence the extra "stgm" instruction check below.
1670 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1673 bool "Memory Tagging Extension support"
1675 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1676 depends on AS_HAS_ARMV8_5
1677 depends on AS_HAS_LSE_ATOMICS
1678 # Required for tag checking in the uaccess routines
1679 depends on ARM64_PAN
1680 select ARCH_USES_HIGH_VMA_FLAGS
1682 Memory Tagging (part of the ARMv8.5 Extensions) provides
1683 architectural support for run-time, always-on detection of
1684 various classes of memory error to aid with software debugging
1685 to eliminate vulnerabilities arising from memory-unsafe
1688 This option enables the support for the Memory Tagging
1689 Extension at EL0 (i.e. for userspace).
1691 Selecting this option allows the feature to be detected at
1692 runtime. Any secondary CPU not implementing this feature will
1693 not be allowed a late bring-up.
1695 Userspace binaries that want to use this feature must
1696 explicitly opt in. The mechanism for the userspace is
1699 Documentation/arm64/memory-tagging-extension.rst.
1703 menu "ARMv8.7 architectural features"
1706 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1708 depends on ARM64_PAN
1710 Enhanced Privileged Access Never (EPAN) allows Privileged
1711 Access Never to be used with Execute-only mappings.
1713 The feature is detected at runtime, and will remain disabled
1714 if the cpu does not implement the feature.
1718 bool "ARM Scalable Vector Extension support"
1721 The Scalable Vector Extension (SVE) is an extension to the AArch64
1722 execution state which complements and extends the SIMD functionality
1723 of the base architecture to support much larger vectors and to enable
1724 additional vectorisation opportunities.
1726 To enable use of this extension on CPUs that implement it, say Y.
1728 On CPUs that support the SVE2 extensions, this option will enable
1731 Note that for architectural reasons, firmware _must_ implement SVE
1732 support when running on SVE capable hardware. The required support
1735 * version 1.5 and later of the ARM Trusted Firmware
1736 * the AArch64 boot wrapper since commit 5e1261e08abf
1737 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1739 For other firmware implementations, consult the firmware documentation
1742 If you need the kernel to boot on SVE-capable hardware with broken
1743 firmware, you may need to say N here until you get your firmware
1744 fixed. Otherwise, you may experience firmware panics or lockups when
1745 booting the kernel. If unsure and you are not observing these
1746 symptoms, you should assume that it is safe to say Y.
1748 config ARM64_MODULE_PLTS
1749 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1751 select HAVE_MOD_ARCH_SPECIFIC
1753 Allocate PLTs when loading modules so that jumps and calls whose
1754 targets are too far away for their relative offsets to be encoded
1755 in the instructions themselves can be bounced via veneers in the
1756 module's PLT. This allows modules to be allocated in the generic
1757 vmalloc area after the dedicated module memory area has been
1760 When running with address space randomization (KASLR), the module
1761 region itself may be too far away for ordinary relative jumps and
1762 calls, and so in that case, module PLTs are required and cannot be
1765 Specific errata workaround(s) might also force module PLTs to be
1766 enabled (ARM64_ERRATUM_843419).
1768 config ARM64_PSEUDO_NMI
1769 bool "Support for NMI-like interrupts"
1772 Adds support for mimicking Non-Maskable Interrupts through the use of
1773 GIC interrupt priority. This support requires version 3 or later of
1776 This high priority configuration for interrupts needs to be
1777 explicitly enabled by setting the kernel parameter
1778 "irqchip.gicv3_pseudo_nmi" to 1.
1783 config ARM64_DEBUG_PRIORITY_MASKING
1784 bool "Debug interrupt priority masking"
1786 This adds runtime checks to functions enabling/disabling
1787 interrupts when using priority masking. The additional checks verify
1788 the validity of ICC_PMR_EL1 when calling concerned functions.
1794 bool "Build a relocatable kernel image" if EXPERT
1795 select ARCH_HAS_RELR
1798 This builds the kernel as a Position Independent Executable (PIE),
1799 which retains all relocation metadata required to relocate the
1800 kernel binary at runtime to a different virtual address than the
1801 address it was linked at.
1802 Since AArch64 uses the RELA relocation format, this requires a
1803 relocation pass at runtime even if the kernel is loaded at the
1804 same address it was linked at.
1806 config RANDOMIZE_BASE
1807 bool "Randomize the address of the kernel image"
1808 select ARM64_MODULE_PLTS if MODULES
1811 Randomizes the virtual address at which the kernel image is
1812 loaded, as a security feature that deters exploit attempts
1813 relying on knowledge of the location of kernel internals.
1815 It is the bootloader's job to provide entropy, by passing a
1816 random u64 value in /chosen/kaslr-seed at kernel entry.
1818 When booting via the UEFI stub, it will invoke the firmware's
1819 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1820 to the kernel proper. In addition, it will randomise the physical
1821 location of the kernel Image as well.
1825 config RANDOMIZE_MODULE_REGION_FULL
1826 bool "Randomize the module region over a 2 GB range"
1827 depends on RANDOMIZE_BASE
1830 Randomizes the location of the module region inside a 2 GB window
1831 covering the core kernel. This way, it is less likely for modules
1832 to leak information about the location of core kernel data structures
1833 but it does imply that function calls between modules and the core
1834 kernel will need to be resolved via veneers in the module PLT.
1836 When this option is not set, the module region will be randomized over
1837 a limited range that contains the [_stext, _etext] interval of the
1838 core kernel, so branch relocations are almost always in range unless
1839 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1840 particular case of region exhaustion, modules might be able to fall
1841 back to a larger 2GB area.
1843 config CC_HAVE_STACKPROTECTOR_SYSREG
1844 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1846 config STACKPROTECTOR_PER_TASK
1848 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1854 config ARM64_ACPI_PARKING_PROTOCOL
1855 bool "Enable support for the ARM64 ACPI parking protocol"
1858 Enable support for the ARM64 ACPI parking protocol. If disabled
1859 the kernel will not allow booting through the ARM64 ACPI parking
1860 protocol even if the corresponding data is present in the ACPI
1864 string "Default kernel command string"
1867 Provide a set of default command-line options at build time by
1868 entering them here. As a minimum, you should specify the the
1869 root device (e.g. root=/dev/nfs).
1872 prompt "Kernel command line type" if CMDLINE != ""
1873 default CMDLINE_FROM_BOOTLOADER
1875 Choose how the kernel will handle the provided default kernel
1876 command line string.
1878 config CMDLINE_FROM_BOOTLOADER
1879 bool "Use bootloader kernel arguments if available"
1881 Uses the command-line options passed by the boot loader. If
1882 the boot loader doesn't provide any, the default kernel command
1883 string provided in CMDLINE will be used.
1885 config CMDLINE_FORCE
1886 bool "Always use the default kernel command string"
1888 Always use the default kernel command string, even if the boot
1889 loader passes other arguments to the kernel.
1890 This is useful if you cannot or don't want to change the
1891 command-line options your boot loader passes to the kernel.
1899 bool "UEFI runtime support"
1900 depends on OF && !CPU_BIG_ENDIAN
1901 depends on KERNEL_MODE_NEON
1902 select ARCH_SUPPORTS_ACPI
1905 select EFI_PARAMS_FROM_FDT
1906 select EFI_RUNTIME_WRAPPERS
1908 select EFI_GENERIC_STUB
1909 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1912 This option provides support for runtime services provided
1913 by UEFI firmware (such as non-volatile variables, realtime
1914 clock, and platform reset). A UEFI stub is also provided to
1915 allow the kernel to be booted as an EFI application. This
1916 is only useful on systems that have UEFI firmware.
1919 bool "Enable support for SMBIOS (DMI) tables"
1923 This enables SMBIOS/DMI feature for systems.
1925 This option is only useful on systems that have UEFI firmware.
1926 However, even with this option, the resultant kernel should
1927 continue to boot on existing non-UEFI platforms.
1931 config SYSVIPC_COMPAT
1933 depends on COMPAT && SYSVIPC
1935 menu "Power management options"
1937 source "kernel/power/Kconfig"
1939 config ARCH_HIBERNATION_POSSIBLE
1943 config ARCH_HIBERNATION_HEADER
1945 depends on HIBERNATION
1947 config ARCH_SUSPEND_POSSIBLE
1952 menu "CPU Power Management"
1954 source "drivers/cpuidle/Kconfig"
1956 source "drivers/cpufreq/Kconfig"
1960 source "drivers/acpi/Kconfig"
1962 source "arch/arm64/kvm/Kconfig"
1965 source "arch/arm64/crypto/Kconfig"