1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HANDLE_DOMAIN_IRQ
137 select HARDIRQS_SW_RESEND
141 select HAVE_ACPI_APEI if (ACPI && EFI)
142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143 select HAVE_ARCH_AUDITSYSCALL
144 select HAVE_ARCH_BITREVERSE
145 select HAVE_ARCH_COMPILER_H
146 select HAVE_ARCH_HUGE_VMAP
147 select HAVE_ARCH_JUMP_LABEL
148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153 select HAVE_ARCH_KFENCE
154 select HAVE_ARCH_KGDB
155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157 select HAVE_ARCH_PREL32_RELOCATIONS
158 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
159 select HAVE_ARCH_SECCOMP_FILTER
160 select HAVE_ARCH_STACKLEAK
161 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
162 select HAVE_ARCH_TRACEHOOK
163 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
164 select HAVE_ARCH_VMAP_STACK
165 select HAVE_ARM_SMCCC
166 select HAVE_ASM_MODVERSIONS
168 select HAVE_C_RECORDMCOUNT
169 select HAVE_CMPXCHG_DOUBLE
170 select HAVE_CMPXCHG_LOCAL
171 select HAVE_CONTEXT_TRACKING
172 select HAVE_DEBUG_KMEMLEAK
173 select HAVE_DMA_CONTIGUOUS
174 select HAVE_DYNAMIC_FTRACE
175 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176 if $(cc-option,-fpatchable-function-entry=2)
177 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178 if DYNAMIC_FTRACE_WITH_REGS
179 select HAVE_EFFICIENT_UNALIGNED_ACCESS
181 select HAVE_FTRACE_MCOUNT_RECORD
182 select HAVE_FUNCTION_TRACER
183 select HAVE_FUNCTION_ERROR_INJECTION
184 select HAVE_FUNCTION_GRAPH_TRACER
185 select HAVE_GCC_PLUGINS
186 select HAVE_HW_BREAKPOINT if PERF_EVENTS
187 select HAVE_IRQ_TIME_ACCOUNTING
189 select HAVE_PATA_PLATFORM
190 select HAVE_PERF_EVENTS
191 select HAVE_PERF_REGS
192 select HAVE_PERF_USER_STACK_DUMP
193 select HAVE_REGS_AND_STACK_ACCESS_API
194 select HAVE_FUNCTION_ARG_ACCESS_API
195 select HAVE_FUTEX_CMPXCHG if FUTEX
196 select MMU_GATHER_RCU_TABLE_FREE
198 select HAVE_STACKPROTECTOR
199 select HAVE_SYSCALL_TRACEPOINTS
201 select HAVE_KRETPROBES
202 select HAVE_GENERIC_VDSO
203 select IOMMU_DMA if IOMMU_SUPPORT
205 select IRQ_FORCED_THREADING
206 select KASAN_VMALLOC if KASAN_GENERIC
207 select MODULES_USE_ELF_RELA
208 select NEED_DMA_MAP_STATE
209 select NEED_SG_DMA_LENGTH
211 select OF_EARLY_FLATTREE
212 select PCI_DOMAINS_GENERIC if PCI
213 select PCI_ECAM if (ACPI && PCI)
214 select PCI_SYSCALL if PCI
219 select SYSCTL_EXCEPTION_TRACE
220 select THREAD_INFO_IN_TASK
221 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
222 select TRACE_IRQFLAGS_SUPPORT
223 select TRACE_IRQFLAGS_NMI_SUPPORT
225 ARM 64-bit (AArch64) Linux support.
233 config ARM64_PAGE_SHIFT
235 default 16 if ARM64_64K_PAGES
236 default 14 if ARM64_16K_PAGES
239 config ARM64_CONT_PTE_SHIFT
241 default 5 if ARM64_64K_PAGES
242 default 7 if ARM64_16K_PAGES
245 config ARM64_CONT_PMD_SHIFT
247 default 5 if ARM64_64K_PAGES
248 default 5 if ARM64_16K_PAGES
251 config ARCH_MMAP_RND_BITS_MIN
252 default 14 if ARM64_64K_PAGES
253 default 16 if ARM64_16K_PAGES
256 # max bits determined by the following formula:
257 # VA_BITS - PAGE_SHIFT - 3
258 config ARCH_MMAP_RND_BITS_MAX
259 default 19 if ARM64_VA_BITS=36
260 default 24 if ARM64_VA_BITS=39
261 default 27 if ARM64_VA_BITS=42
262 default 30 if ARM64_VA_BITS=47
263 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
264 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
265 default 33 if ARM64_VA_BITS=48
266 default 14 if ARM64_64K_PAGES
267 default 16 if ARM64_16K_PAGES
270 config ARCH_MMAP_RND_COMPAT_BITS_MIN
271 default 7 if ARM64_64K_PAGES
272 default 9 if ARM64_16K_PAGES
275 config ARCH_MMAP_RND_COMPAT_BITS_MAX
281 config STACKTRACE_SUPPORT
284 config ILLEGAL_POINTER_VALUE
286 default 0xdead000000000000
288 config LOCKDEP_SUPPORT
295 config GENERIC_BUG_RELATIVE_POINTERS
297 depends on GENERIC_BUG
299 config GENERIC_HWEIGHT
305 config GENERIC_CALIBRATE_DELAY
308 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
314 config KERNEL_MODE_NEON
317 config FIX_EARLYCON_MEM
320 config PGTABLE_LEVELS
322 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
323 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
324 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
325 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
326 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
327 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329 config ARCH_SUPPORTS_UPROBES
332 config ARCH_PROC_KCORE_TEXT
335 config BROKEN_GAS_INST
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338 config KASAN_SHADOW_OFFSET
340 depends on KASAN_GENERIC || KASAN_SW_TAGS
341 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
342 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
343 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
344 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
345 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
346 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
347 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
348 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
349 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
350 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
351 default 0xffffffffffffffff
353 source "arch/arm64/Kconfig.platforms"
355 menu "Kernel Features"
357 menu "ARM errata workarounds via the alternatives framework"
359 config ARM64_WORKAROUND_CLEAN_CACHE
362 config ARM64_ERRATUM_826319
363 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365 select ARM64_WORKAROUND_CLEAN_CACHE
367 This option adds an alternative code sequence to work around ARM
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
369 AXI master interface and an L2 cache.
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
372 and is unable to accept a certain write via this interface, it will
373 not progress on read data presented on the read data channel and the
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_827319
385 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387 select ARM64_WORKAROUND_CLEAN_CACHE
389 This option adds an alternative code sequence to work around ARM
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
391 master interface and an L2 cache.
393 Under certain conditions this erratum can cause a clean line eviction
394 to occur at the same time as another transaction to the same address
395 on the AMBA 5 CHI interface, which can cause data corruption if the
396 interconnect reorders the two transactions.
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this does not necessarily enable the workaround,
401 as it depends on the alternative framework, which will only patch
402 the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_824069
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
413 to a coherent interconnect.
415 If a Cortex-A53 processor is executing a store or prefetch for
416 write instruction at the same time as a processor in another
417 cluster is executing a cache maintenance operation to the same
418 address, then this erratum might cause a clean cache line to be
419 incorrectly marked as dirty.
421 The workaround promotes data cache clean instructions to
422 data cache clean-and-invalidate.
423 Please note that this option does not necessarily enable the
424 workaround, as it depends on the alternative framework, which will
425 only patch the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_819472
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432 select ARM64_WORKAROUND_CLEAN_CACHE
434 This option adds an alternative code sequence to work around ARM
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
436 present when it is connected to a coherent interconnect.
438 If the processor is executing a load and store exclusive sequence at
439 the same time as a processor in another cluster is executing a cache
440 maintenance operation to the same address, then this erratum might
441 cause data corruption.
443 The workaround promotes data cache clean instructions to
444 data cache clean-and-invalidate.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_832075
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
455 This option adds an alternative code sequence to work around ARM
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
463 Please note that this does not necessarily enable the workaround,
464 as it depends on the alternative framework, which will only patch
465 the kernel if an affected CPU is detected.
469 config ARM64_ERRATUM_834220
470 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
474 This option adds an alternative code sequence to work around ARM
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
478 fault as the result of a Stage 1 fault for load crossing a
479 page boundary when there is a permission or device memory
480 alignment fault at Stage 1 and a translation fault at Stage 2.
482 The workaround is to verify that the Stage 1 translation
483 doesn't generate a fault before handling the Stage 2 fault.
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_845719
491 bool "Cortex-A53: 845719: a load might read incorrect data"
495 This option adds an alternative code sequence to work around ARM
496 erratum 845719 on Cortex-A53 parts up to r0p4.
498 When running a compat (AArch32) userspace on an affected Cortex-A53
499 part, a load at EL0 from a virtual address that matches the bottom 32
500 bits of the virtual address used by a recent load at (AArch64) EL1
501 might return incorrect data.
503 The workaround is to write the contextidr_el1 register on exception
504 return to a 32-bit task.
505 Please note that this does not necessarily enable the workaround,
506 as it depends on the alternative framework, which will only patch
507 the kernel if an affected CPU is detected.
511 config ARM64_ERRATUM_843419
512 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
514 select ARM64_MODULE_PLTS if MODULES
516 This option links the kernel with '--fix-cortex-a53-843419' and
517 enables PLT support to replace certain ADRP instructions, which can
518 cause subsequent memory accesses to use an incorrect address on
519 Cortex-A53 parts up to r0p4.
523 config ARM64_LD_HAS_FIX_ERRATUM_843419
524 def_bool $(ld-option,--fix-cortex-a53-843419)
526 config ARM64_ERRATUM_1024718
527 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
530 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
532 Affected Cortex-A55 cores (all revisions) could cause incorrect
533 update of the hardware dirty bit when the DBM/AP bits are updated
534 without a break-before-make. The workaround is to disable the usage
535 of hardware DBM locally on the affected cores. CPUs not affected by
536 this erratum will continue to use the feature.
540 config ARM64_ERRATUM_1418040
541 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
545 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
546 errata 1188873 and 1418040.
548 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
549 cause register corruption when accessing the timer registers
550 from AArch32 userspace.
554 config ARM64_WORKAROUND_SPECULATIVE_AT
557 config ARM64_ERRATUM_1165522
558 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
560 select ARM64_WORKAROUND_SPECULATIVE_AT
562 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
564 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
565 corrupted TLBs by speculating an AT instruction during a guest
570 config ARM64_ERRATUM_1319367
571 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573 select ARM64_WORKAROUND_SPECULATIVE_AT
575 This option adds work arounds for ARM Cortex-A57 erratum 1319537
576 and A72 erratum 1319367
578 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
579 speculating an AT instruction during a guest context switch.
583 config ARM64_ERRATUM_1530923
584 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586 select ARM64_WORKAROUND_SPECULATIVE_AT
588 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
590 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
591 corrupted TLBs by speculating an AT instruction during a guest
596 config ARM64_WORKAROUND_REPEAT_TLBI
599 config ARM64_ERRATUM_2441007
600 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
602 select ARM64_WORKAROUND_REPEAT_TLBI
604 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
606 Under very rare circumstances, affected Cortex-A55 CPUs
607 may not handle a race between a break-before-make sequence on one
608 CPU, and another CPU accessing the same page. This could allow a
609 store to a page that has been unmapped.
611 Work around this by adding the affected CPUs to the list that needs
612 TLB sequences to be done twice.
616 config ARM64_ERRATUM_1286807
617 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
619 select ARM64_WORKAROUND_REPEAT_TLBI
621 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
623 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
624 address for a cacheable mapping of a location is being
625 accessed by a core while another core is remapping the virtual
626 address to a new physical page using the recommended
627 break-before-make sequence, then under very rare circumstances
628 TLBI+DSB completes before a read using the translation being
629 invalidated has been observed by other observers. The
630 workaround repeats the TLBI+DSB operation.
632 config ARM64_ERRATUM_1463225
633 bool "Cortex-A76: Software Step might prevent interrupt recognition"
636 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
638 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
639 of a system call instruction (SVC) can prevent recognition of
640 subsequent interrupts when software stepping is disabled in the
641 exception handler of the system call and either kernel debugging
642 is enabled or VHE is in use.
644 Work around the erratum by triggering a dummy step exception
645 when handling a system call from a task that is being stepped
646 in a VHE configuration of the kernel.
650 config ARM64_ERRATUM_1542419
651 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
654 This option adds a workaround for ARM Neoverse-N1 erratum
657 Affected Neoverse-N1 cores could execute a stale instruction when
658 modified by another CPU. The workaround depends on a firmware
661 Workaround the issue by hiding the DIC feature from EL0. This
662 forces user-space to perform cache maintenance.
666 config ARM64_ERRATUM_1508412
667 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
670 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
672 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
673 of a store-exclusive or read of PAR_EL1 and a load with device or
674 non-cacheable memory attributes. The workaround depends on a firmware
677 KVM guests must also have the workaround implemented or they can
680 Work around the issue by inserting DMB SY barriers around PAR_EL1
681 register reads and warning KVM users. The DMB barrier is sufficient
682 to prevent a speculative PAR_EL1 read.
686 config ARM64_ERRATUM_2441009
687 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
689 select ARM64_WORKAROUND_REPEAT_TLBI
691 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
693 Under very rare circumstances, affected Cortex-A510 CPUs
694 may not handle a race between a break-before-make sequence on one
695 CPU, and another CPU accessing the same page. This could allow a
696 store to a page that has been unmapped.
698 Work around this by adding the affected CPUs to the list that needs
699 TLB sequences to be done twice.
703 config ARM64_ERRATUM_2457168
704 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
705 depends on ARM64_AMU_EXTN
708 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
710 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
711 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
712 incorrectly giving a significantly higher output value.
714 Work around this problem by returning 0 when reading the affected counter in
715 key locations that results in disabling all users of this counter. This effect
716 is the same to firmware disabling affected counters.
720 config CAVIUM_ERRATUM_22375
721 bool "Cavium erratum 22375, 24313"
724 Enable workaround for errata 22375 and 24313.
726 This implements two gicv3-its errata workarounds for ThunderX. Both
727 with a small impact affecting only ITS table allocation.
729 erratum 22375: only alloc 8MB table size
730 erratum 24313: ignore memory access type
732 The fixes are in ITS initialization and basically ignore memory access
733 type and table size provided by the TYPER and BASER registers.
737 config CAVIUM_ERRATUM_23144
738 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
742 ITS SYNC command hang for cross node io and collections/cpu mapping.
746 config CAVIUM_ERRATUM_23154
747 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
750 The gicv3 of ThunderX requires a modified version for
751 reading the IAR status to ensure data synchronization
752 (access to icc_iar1_el1 is not sync'ed before and after).
756 config CAVIUM_ERRATUM_27456
757 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
760 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
761 instructions may cause the icache to become corrupted if it
762 contains data for a non-current ASID. The fix is to
763 invalidate the icache when changing the mm context.
767 config CAVIUM_ERRATUM_30115
768 bool "Cavium erratum 30115: Guest may disable interrupts in host"
771 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
772 1.2, and T83 Pass 1.0, KVM guest execution may disable
773 interrupts in host. Trapping both GICv3 group-0 and group-1
774 accesses sidesteps the issue.
778 config CAVIUM_TX2_ERRATUM_219
779 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
782 On Cavium ThunderX2, a load, store or prefetch instruction between a
783 TTBR update and the corresponding context synchronizing operation can
784 cause a spurious Data Abort to be delivered to any hardware thread in
787 Work around the issue by avoiding the problematic code sequence and
788 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
789 trap handler performs the corresponding register access, skips the
790 instruction and ensures context synchronization by virtue of the
795 config FUJITSU_ERRATUM_010001
796 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
799 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
800 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
801 accesses may cause undefined fault (Data abort, DFSC=0b111111).
802 This fault occurs under a specific hardware condition when a
803 load/store instruction performs an address translation using:
804 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
805 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
806 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
807 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
809 The workaround is to ensure these bits are clear in TCR_ELx.
810 The workaround only affects the Fujitsu-A64FX.
814 config HISILICON_ERRATUM_161600802
815 bool "Hip07 161600802: Erroneous redistributor VLPI base"
818 The HiSilicon Hip07 SoC uses the wrong redistributor base
819 when issued ITS commands such as VMOVP and VMAPP, and requires
820 a 128kB offset to be applied to the target address in this commands.
824 config QCOM_FALKOR_ERRATUM_1003
825 bool "Falkor E1003: Incorrect translation due to ASID change"
828 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
829 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
830 in TTBR1_EL1, this situation only occurs in the entry trampoline and
831 then only for entries in the walk cache, since the leaf translation
832 is unchanged. Work around the erratum by invalidating the walk cache
833 entries for the trampoline before entering the kernel proper.
835 config QCOM_FALKOR_ERRATUM_1009
836 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
838 select ARM64_WORKAROUND_REPEAT_TLBI
840 On Falkor v1, the CPU may prematurely complete a DSB following a
841 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
842 one more time to fix the issue.
846 config QCOM_QDF2400_ERRATUM_0065
847 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
850 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
851 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
852 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
856 config QCOM_FALKOR_ERRATUM_E1041
857 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
860 Falkor CPU may speculatively fetch instructions from an improper
861 memory location when MMU translation is changed from SCTLR_ELn[M]=1
862 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
866 config NVIDIA_CARMEL_CNP_ERRATUM
867 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
870 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
871 invalidate shared TLB entries installed by a different core, as it would
872 on standard ARM cores.
876 config SOCIONEXT_SYNQUACER_PREITS
877 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
880 Socionext Synquacer SoCs implement a separate h/w block to generate
881 MSI doorbell writes with non-zero values for the device ID.
890 default ARM64_4K_PAGES
892 Page size (translation granule) configuration.
894 config ARM64_4K_PAGES
897 This feature enables 4KB pages support.
899 config ARM64_16K_PAGES
902 The system will use 16KB pages support. AArch32 emulation
903 requires applications compiled with 16K (or a multiple of 16K)
906 config ARM64_64K_PAGES
909 This feature enables 64KB pages support (4KB by default)
910 allowing only two levels of page tables and faster TLB
911 look-up. AArch32 emulation requires applications compiled
912 with 64K aligned segments.
917 prompt "Virtual address space size"
918 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
919 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
920 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
922 Allows choosing one of multiple possible virtual address
923 space sizes. The level of translation table is determined by
924 a combination of page size and virtual address space size.
926 config ARM64_VA_BITS_36
927 bool "36-bit" if EXPERT
928 depends on ARM64_16K_PAGES
930 config ARM64_VA_BITS_39
932 depends on ARM64_4K_PAGES
934 config ARM64_VA_BITS_42
936 depends on ARM64_64K_PAGES
938 config ARM64_VA_BITS_47
940 depends on ARM64_16K_PAGES
942 config ARM64_VA_BITS_48
945 config ARM64_VA_BITS_52
947 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
949 Enable 52-bit virtual addressing for userspace when explicitly
950 requested via a hint to mmap(). The kernel will also use 52-bit
951 virtual addresses for its own mappings (provided HW support for
952 this feature is available, otherwise it reverts to 48-bit).
954 NOTE: Enabling 52-bit virtual addressing in conjunction with
955 ARMv8.3 Pointer Authentication will result in the PAC being
956 reduced from 7 bits to 3 bits, which may have a significant
957 impact on its susceptibility to brute-force attacks.
959 If unsure, select 48-bit virtual addressing instead.
963 config ARM64_FORCE_52BIT
964 bool "Force 52-bit virtual addresses for userspace"
965 depends on ARM64_VA_BITS_52 && EXPERT
967 For systems with 52-bit userspace VAs enabled, the kernel will attempt
968 to maintain compatibility with older software by providing 48-bit VAs
969 unless a hint is supplied to mmap.
971 This configuration option disables the 48-bit compatibility logic, and
972 forces all userspace addresses to be 52-bit on HW that supports it. One
973 should only enable this configuration option for stress testing userspace
974 memory management code. If unsure say N here.
978 default 36 if ARM64_VA_BITS_36
979 default 39 if ARM64_VA_BITS_39
980 default 42 if ARM64_VA_BITS_42
981 default 47 if ARM64_VA_BITS_47
982 default 48 if ARM64_VA_BITS_48
983 default 52 if ARM64_VA_BITS_52
986 prompt "Physical address space size"
987 default ARM64_PA_BITS_48
989 Choose the maximum physical address range that the kernel will
992 config ARM64_PA_BITS_48
995 config ARM64_PA_BITS_52
996 bool "52-bit (ARMv8.2)"
997 depends on ARM64_64K_PAGES
998 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1000 Enable support for a 52-bit physical address space, introduced as
1001 part of the ARMv8.2-LPA extension.
1003 With this enabled, the kernel will also continue to work on CPUs that
1004 do not support ARMv8.2-LPA, but with some added memory overhead (and
1005 minor performance overhead).
1009 config ARM64_PA_BITS
1011 default 48 if ARM64_PA_BITS_48
1012 default 52 if ARM64_PA_BITS_52
1016 default CPU_LITTLE_ENDIAN
1018 Select the endianness of data accesses performed by the CPU. Userspace
1019 applications will need to be compiled and linked for the endianness
1020 that is selected here.
1022 config CPU_BIG_ENDIAN
1023 bool "Build big-endian kernel"
1024 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1026 Say Y if you plan on running a kernel with a big-endian userspace.
1028 config CPU_LITTLE_ENDIAN
1029 bool "Build little-endian kernel"
1031 Say Y if you plan on running a kernel with a little-endian userspace.
1032 This is usually the case for distributions targeting arm64.
1037 bool "Multi-core scheduler support"
1039 Multi-core scheduler support improves the CPU scheduler's decision
1040 making when dealing with multi-core CPU chips at a cost of slightly
1041 increased overhead in some places. If unsure say N here.
1044 bool "SMT scheduler support"
1046 Improves the CPU scheduler's decision making when dealing with
1047 MultiThreading at a cost of slightly increased overhead in some
1048 places. If unsure say N here.
1051 int "Maximum number of CPUs (2-4096)"
1056 bool "Support for hot-pluggable CPUs"
1057 select GENERIC_IRQ_MIGRATION
1059 Say Y here to experiment with turning CPUs off and on. CPUs
1060 can be controlled through /sys/devices/system/cpu.
1062 # Common NUMA Features
1064 bool "NUMA Memory Allocation and Scheduler Support"
1065 select GENERIC_ARCH_NUMA
1066 select ACPI_NUMA if ACPI
1069 Enable NUMA (Non-Uniform Memory Access) support.
1071 The kernel will try to allocate memory used by a CPU on the
1072 local memory of the CPU and add some more
1073 NUMA awareness to the kernel.
1076 int "Maximum NUMA Nodes (as a power of 2)"
1081 Specify the maximum number of NUMA Nodes available on the target
1082 system. Increases memory reserved to accommodate various tables.
1084 config USE_PERCPU_NUMA_NODE_ID
1088 config HAVE_SETUP_PER_CPU_AREA
1092 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1096 source "kernel/Kconfig.hz"
1098 config ARCH_SPARSEMEM_ENABLE
1100 select SPARSEMEM_VMEMMAP_ENABLE
1101 select SPARSEMEM_VMEMMAP
1103 config HW_PERF_EVENTS
1107 # Supported by clang >= 7.0
1108 config CC_HAVE_SHADOW_CALL_STACK
1109 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1112 bool "Enable paravirtualization code"
1114 This changes the kernel so it can modify itself when it is run
1115 under a hypervisor, potentially improving performance significantly
1116 over full virtualization.
1118 config PARAVIRT_TIME_ACCOUNTING
1119 bool "Paravirtual steal time accounting"
1122 Select this option to enable fine granularity task steal time
1123 accounting. Time spent executing other tasks in parallel with
1124 the current vCPU is discounted from the vCPU power. To account for
1125 that, there can be a small performance impact.
1127 If in doubt, say N here.
1130 depends on PM_SLEEP_SMP
1132 bool "kexec system call"
1134 kexec is a system call that implements the ability to shutdown your
1135 current kernel, and to start another kernel. It is like a reboot
1136 but it is independent of the system firmware. And like a reboot
1137 you can start any kernel with it, not just Linux.
1140 bool "kexec file based system call"
1142 select HAVE_IMA_KEXEC if IMA
1144 This is new version of kexec system call. This system call is
1145 file based and takes file descriptors as system call argument
1146 for kernel and initramfs as opposed to list of segments as
1147 accepted by previous system call.
1150 bool "Verify kernel signature during kexec_file_load() syscall"
1151 depends on KEXEC_FILE
1153 Select this option to verify a signature with loaded kernel
1154 image. If configured, any attempt of loading a image without
1155 valid signature will fail.
1157 In addition to that option, you need to enable signature
1158 verification for the corresponding kernel image type being
1159 loaded in order for this to work.
1161 config KEXEC_IMAGE_VERIFY_SIG
1162 bool "Enable Image signature verification support"
1164 depends on KEXEC_SIG
1165 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1167 Enable Image signature verification support.
1169 comment "Support for PE file signature verification disabled"
1170 depends on KEXEC_SIG
1171 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1174 bool "Build kdump crash kernel"
1176 Generate crash dump after being started by kexec. This should
1177 be normally only set in special crash dump kernels which are
1178 loaded in the main kernel with kexec-tools into a specially
1179 reserved region and then later executed after a crash by
1182 For more details see Documentation/admin-guide/kdump/kdump.rst
1186 depends on HIBERNATION
1193 bool "Xen guest support on ARM64"
1194 depends on ARM64 && OF
1198 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1200 config FORCE_MAX_ZONEORDER
1202 default "14" if ARM64_64K_PAGES
1203 default "12" if ARM64_16K_PAGES
1206 The kernel memory allocator divides physically contiguous memory
1207 blocks into "zones", where each zone is a power of two number of
1208 pages. This option selects the largest power of two that the kernel
1209 keeps in the memory allocator. If you need to allocate very large
1210 blocks of physically contiguous memory, then you may need to
1211 increase this value.
1213 This config option is actually maximum order plus one. For example,
1214 a value of 11 means that the largest free memory block is 2^10 pages.
1216 We make sure that we can allocate upto a HugePage size for each configuration.
1218 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1220 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1221 4M allocations matching the default size used by generic code.
1223 config UNMAP_KERNEL_AT_EL0
1224 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1227 Speculation attacks against some high-performance processors can
1228 be used to bypass MMU permission checks and leak kernel data to
1229 userspace. This can be defended against by unmapping the kernel
1230 when running in userspace, mapping it back in on exception entry
1231 via a trampoline page in the vector table.
1235 config MITIGATE_SPECTRE_BRANCH_HISTORY
1236 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1239 Speculation attacks against some high-performance processors can
1240 make use of branch history to influence future speculation.
1241 When taking an exception from user-space, a sequence of branches
1242 or a firmware call overwrites the branch history.
1244 config RODATA_FULL_DEFAULT_ENABLED
1245 bool "Apply r/o permissions of VM areas also to their linear aliases"
1248 Apply read-only attributes of VM areas to the linear alias of
1249 the backing pages as well. This prevents code or read-only data
1250 from being modified (inadvertently or intentionally) via another
1251 mapping of the same memory page. This additional enhancement can
1252 be turned off at runtime by passing rodata=[off|on] (and turned on
1253 with rodata=full if this option is set to 'n')
1255 This requires the linear region to be mapped down to pages,
1256 which may adversely affect performance in some cases.
1258 config ARM64_SW_TTBR0_PAN
1259 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1261 Enabling this option prevents the kernel from accessing
1262 user-space memory directly by pointing TTBR0_EL1 to a reserved
1263 zeroed area and reserved ASID. The user access routines
1264 restore the valid TTBR0_EL1 temporarily.
1266 config ARM64_TAGGED_ADDR_ABI
1267 bool "Enable the tagged user addresses syscall ABI"
1270 When this option is enabled, user applications can opt in to a
1271 relaxed ABI via prctl() allowing tagged addresses to be passed
1272 to system calls as pointer arguments. For details, see
1273 Documentation/arm64/tagged-address-abi.rst.
1276 bool "Kernel support for 32-bit EL0"
1277 depends on ARM64_4K_PAGES || EXPERT
1279 select OLD_SIGSUSPEND3
1280 select COMPAT_OLD_SIGACTION
1282 This option enables support for a 32-bit EL0 running under a 64-bit
1283 kernel at EL1. AArch32-specific components such as system calls,
1284 the user helper functions, VFP support and the ptrace interface are
1285 handled appropriately by the kernel.
1287 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1288 that you will only be able to execute AArch32 binaries that were compiled
1289 with page size aligned segments.
1291 If you want to execute 32-bit userspace applications, say Y.
1295 config KUSER_HELPERS
1296 bool "Enable kuser helpers page for 32-bit applications"
1299 Warning: disabling this option may break 32-bit user programs.
1301 Provide kuser helpers to compat tasks. The kernel provides
1302 helper code to userspace in read only form at a fixed location
1303 to allow userspace to be independent of the CPU type fitted to
1304 the system. This permits binaries to be run on ARMv4 through
1305 to ARMv8 without modification.
1307 See Documentation/arm/kernel_user_helpers.rst for details.
1309 However, the fixed address nature of these helpers can be used
1310 by ROP (return orientated programming) authors when creating
1313 If all of the binaries and libraries which run on your platform
1314 are built specifically for your platform, and make no use of
1315 these helpers, then you can turn this option off to hinder
1316 such exploits. However, in that case, if a binary or library
1317 relying on those helpers is run, it will not function correctly.
1319 Say N here only if you are absolutely certain that you do not
1320 need these helpers; otherwise, the safe option is to say Y.
1323 bool "Enable vDSO for 32-bit applications"
1324 depends on !CPU_BIG_ENDIAN
1325 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1326 select GENERIC_COMPAT_VDSO
1329 Place in the process address space of 32-bit applications an
1330 ELF shared object providing fast implementations of gettimeofday
1333 You must have a 32-bit build of glibc 2.22 or later for programs
1334 to seamlessly take advantage of this.
1336 config THUMB2_COMPAT_VDSO
1337 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1338 depends on COMPAT_VDSO
1341 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1342 otherwise with '-marm'.
1344 menuconfig ARMV8_DEPRECATED
1345 bool "Emulate deprecated/obsolete ARMv8 instructions"
1348 Legacy software support may require certain instructions
1349 that have been deprecated or obsoleted in the architecture.
1351 Enable this config to enable selective emulation of these
1358 config SWP_EMULATION
1359 bool "Emulate SWP/SWPB instructions"
1361 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1362 they are always undefined. Say Y here to enable software
1363 emulation of these instructions for userspace using LDXR/STXR.
1364 This feature can be controlled at runtime with the abi.swp
1365 sysctl which is disabled by default.
1367 In some older versions of glibc [<=2.8] SWP is used during futex
1368 trylock() operations with the assumption that the code will not
1369 be preempted. This invalid assumption may be more likely to fail
1370 with SWP emulation enabled, leading to deadlock of the user
1373 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1374 on an external transaction monitoring block called a global
1375 monitor to maintain update atomicity. If your system does not
1376 implement a global monitor, this option can cause programs that
1377 perform SWP operations to uncached memory to deadlock.
1381 config CP15_BARRIER_EMULATION
1382 bool "Emulate CP15 Barrier instructions"
1384 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1385 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1386 strongly recommended to use the ISB, DSB, and DMB
1387 instructions instead.
1389 Say Y here to enable software emulation of these
1390 instructions for AArch32 userspace code. When this option is
1391 enabled, CP15 barrier usage is traced which can help
1392 identify software that needs updating. This feature can be
1393 controlled at runtime with the abi.cp15_barrier sysctl.
1397 config SETEND_EMULATION
1398 bool "Emulate SETEND instruction"
1400 The SETEND instruction alters the data-endianness of the
1401 AArch32 EL0, and is deprecated in ARMv8.
1403 Say Y here to enable software emulation of the instruction
1404 for AArch32 userspace code. This feature can be controlled
1405 at runtime with the abi.setend sysctl.
1407 Note: All the cpus on the system must have mixed endian support at EL0
1408 for this feature to be enabled. If a new CPU - which doesn't support mixed
1409 endian - is hotplugged in after this feature has been enabled, there could
1410 be unexpected results in the applications.
1417 menu "ARMv8.1 architectural features"
1419 config ARM64_HW_AFDBM
1420 bool "Support for hardware updates of the Access and Dirty page flags"
1423 The ARMv8.1 architecture extensions introduce support for
1424 hardware updates of the access and dirty information in page
1425 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1426 capable processors, accesses to pages with PTE_AF cleared will
1427 set this bit instead of raising an access flag fault.
1428 Similarly, writes to read-only pages with the DBM bit set will
1429 clear the read-only bit (AP[2]) instead of raising a
1432 Kernels built with this configuration option enabled continue
1433 to work on pre-ARMv8.1 hardware and the performance impact is
1434 minimal. If unsure, say Y.
1437 bool "Enable support for Privileged Access Never (PAN)"
1440 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1441 prevents the kernel or hypervisor from accessing user-space (EL0)
1444 Choosing this option will cause any unprotected (not using
1445 copy_to_user et al) memory access to fail with a permission fault.
1447 The feature is detected at runtime, and will remain as a 'nop'
1448 instruction if the cpu does not implement the feature.
1451 def_bool $(as-instr,.arch_extension rcpc)
1453 config AS_HAS_LSE_ATOMICS
1454 def_bool $(as-instr,.arch_extension lse)
1456 config ARM64_LSE_ATOMICS
1458 default ARM64_USE_LSE_ATOMICS
1459 depends on AS_HAS_LSE_ATOMICS
1461 config ARM64_USE_LSE_ATOMICS
1462 bool "Atomic instructions"
1463 depends on JUMP_LABEL
1466 As part of the Large System Extensions, ARMv8.1 introduces new
1467 atomic instructions that are designed specifically to scale in
1470 Say Y here to make use of these instructions for the in-kernel
1471 atomic routines. This incurs a small overhead on CPUs that do
1472 not support these instructions and requires the kernel to be
1473 built with binutils >= 2.25 in order for the new instructions
1478 menu "ARMv8.2 architectural features"
1481 bool "Enable support for persistent memory"
1482 select ARCH_HAS_PMEM_API
1483 select ARCH_HAS_UACCESS_FLUSHCACHE
1485 Say Y to enable support for the persistent memory API based on the
1486 ARMv8.2 DCPoP feature.
1488 The feature is detected at runtime, and the kernel will use DC CVAC
1489 operations if DC CVAP is not supported (following the behaviour of
1490 DC CVAP itself if the system does not define a point of persistence).
1492 config ARM64_RAS_EXTN
1493 bool "Enable support for RAS CPU Extensions"
1496 CPUs that support the Reliability, Availability and Serviceability
1497 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1498 errors, classify them and report them to software.
1500 On CPUs with these extensions system software can use additional
1501 barriers to determine if faults are pending and read the
1502 classification from a new set of registers.
1504 Selecting this feature will allow the kernel to use these barriers
1505 and access the new registers if the system supports the extension.
1506 Platform RAS features may additionally depend on firmware support.
1509 bool "Enable support for Common Not Private (CNP) translations"
1511 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1513 Common Not Private (CNP) allows translation table entries to
1514 be shared between different PEs in the same inner shareable
1515 domain, so the hardware can use this fact to optimise the
1516 caching of such entries in the TLB.
1518 Selecting this option allows the CNP feature to be detected
1519 at runtime, and does not affect PEs that do not implement
1524 menu "ARMv8.3 architectural features"
1526 config ARM64_PTR_AUTH
1527 bool "Enable support for pointer authentication"
1530 Pointer authentication (part of the ARMv8.3 Extensions) provides
1531 instructions for signing and authenticating pointers against secret
1532 keys, which can be used to mitigate Return Oriented Programming (ROP)
1535 This option enables these instructions at EL0 (i.e. for userspace).
1536 Choosing this option will cause the kernel to initialise secret keys
1537 for each process at exec() time, with these keys being
1538 context-switched along with the process.
1540 The feature is detected at runtime. If the feature is not present in
1541 hardware it will not be advertised to userspace/KVM guest nor will it
1544 If the feature is present on the boot CPU but not on a late CPU, then
1545 the late CPU will be parked. Also, if the boot CPU does not have
1546 address auth and the late CPU has then the late CPU will still boot
1547 but with the feature disabled. On such a system, this option should
1550 config ARM64_PTR_AUTH_KERNEL
1551 bool "Use pointer authentication for kernel"
1553 depends on ARM64_PTR_AUTH
1554 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1555 # Modern compilers insert a .note.gnu.property section note for PAC
1556 # which is only understood by binutils starting with version 2.33.1.
1557 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1558 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1559 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1561 If the compiler supports the -mbranch-protection or
1562 -msign-return-address flag (e.g. GCC 7 or later), then this option
1563 will cause the kernel itself to be compiled with return address
1564 protection. In this case, and if the target hardware is known to
1565 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1566 disabled with minimal loss of protection.
1568 This feature works with FUNCTION_GRAPH_TRACER option only if
1569 DYNAMIC_FTRACE_WITH_REGS is enabled.
1571 config CC_HAS_BRANCH_PROT_PAC_RET
1572 # GCC 9 or later, clang 8 or later
1573 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1575 config CC_HAS_SIGN_RETURN_ADDRESS
1577 def_bool $(cc-option,-msign-return-address=all)
1580 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1582 config AS_HAS_CFI_NEGATE_RA_STATE
1583 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1587 menu "ARMv8.4 architectural features"
1589 config ARM64_AMU_EXTN
1590 bool "Enable support for the Activity Monitors Unit CPU extension"
1593 The activity monitors extension is an optional extension introduced
1594 by the ARMv8.4 CPU architecture. This enables support for version 1
1595 of the activity monitors architecture, AMUv1.
1597 To enable the use of this extension on CPUs that implement it, say Y.
1599 Note that for architectural reasons, firmware _must_ implement AMU
1600 support when running on CPUs that present the activity monitors
1601 extension. The required support is present in:
1602 * Version 1.5 and later of the ARM Trusted Firmware
1604 For kernels that have this configuration enabled but boot with broken
1605 firmware, you may need to say N here until the firmware is fixed.
1606 Otherwise you may experience firmware panics or lockups when
1607 accessing the counter registers. Even if you are not observing these
1608 symptoms, the values returned by the register reads might not
1609 correctly reflect reality. Most commonly, the value read will be 0,
1610 indicating that the counter is not enabled.
1612 config AS_HAS_ARMV8_4
1613 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1615 config ARM64_TLB_RANGE
1616 bool "Enable support for tlbi range feature"
1618 depends on AS_HAS_ARMV8_4
1620 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1621 range of input addresses.
1623 The feature introduces new assembly instructions, and they were
1624 support when binutils >= 2.30.
1628 menu "ARMv8.5 architectural features"
1630 config AS_HAS_ARMV8_5
1631 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1634 bool "Branch Target Identification support"
1637 Branch Target Identification (part of the ARMv8.5 Extensions)
1638 provides a mechanism to limit the set of locations to which computed
1639 branch instructions such as BR or BLR can jump.
1641 To make use of BTI on CPUs that support it, say Y.
1643 BTI is intended to provide complementary protection to other control
1644 flow integrity protection mechanisms, such as the Pointer
1645 authentication mechanism provided as part of the ARMv8.3 Extensions.
1646 For this reason, it does not make sense to enable this option without
1647 also enabling support for pointer authentication. Thus, when
1648 enabling this option you should also select ARM64_PTR_AUTH=y.
1650 Userspace binaries must also be specifically compiled to make use of
1651 this mechanism. If you say N here or the hardware does not support
1652 BTI, such binaries can still run, but you get no additional
1653 enforcement of branch destinations.
1655 config ARM64_BTI_KERNEL
1656 bool "Use Branch Target Identification for kernel"
1658 depends on ARM64_BTI
1659 depends on ARM64_PTR_AUTH_KERNEL
1660 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1661 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1662 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1663 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1664 depends on !CC_IS_GCC
1665 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1666 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1667 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1669 Build the kernel with Branch Target Identification annotations
1670 and enable enforcement of this for kernel code. When this option
1671 is enabled and the system supports BTI all kernel code including
1672 modular code must have BTI enabled.
1674 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1675 # GCC 9 or later, clang 8 or later
1676 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1679 bool "Enable support for E0PD"
1682 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1683 that EL0 accesses made via TTBR1 always fault in constant time,
1684 providing similar benefits to KASLR as those provided by KPTI, but
1685 with lower overhead and without disrupting legitimate access to
1686 kernel memory such as SPE.
1688 This option enables E0PD for TTBR1 where available.
1691 bool "Enable support for random number generation"
1694 Random number generation (part of the ARMv8.5 Extensions)
1695 provides a high bandwidth, cryptographically secure
1696 hardware random number generator.
1698 config ARM64_AS_HAS_MTE
1699 # Initial support for MTE went in binutils 2.32.0, checked with
1700 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1701 # as a late addition to the final architecture spec (LDGM/STGM)
1702 # is only supported in the newer 2.32.x and 2.33 binutils
1703 # versions, hence the extra "stgm" instruction check below.
1704 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1707 bool "Memory Tagging Extension support"
1709 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1710 depends on AS_HAS_ARMV8_5
1711 depends on AS_HAS_LSE_ATOMICS
1712 # Required for tag checking in the uaccess routines
1713 depends on ARM64_PAN
1714 select ARCH_USES_HIGH_VMA_FLAGS
1716 Memory Tagging (part of the ARMv8.5 Extensions) provides
1717 architectural support for run-time, always-on detection of
1718 various classes of memory error to aid with software debugging
1719 to eliminate vulnerabilities arising from memory-unsafe
1722 This option enables the support for the Memory Tagging
1723 Extension at EL0 (i.e. for userspace).
1725 Selecting this option allows the feature to be detected at
1726 runtime. Any secondary CPU not implementing this feature will
1727 not be allowed a late bring-up.
1729 Userspace binaries that want to use this feature must
1730 explicitly opt in. The mechanism for the userspace is
1733 Documentation/arm64/memory-tagging-extension.rst.
1737 menu "ARMv8.7 architectural features"
1740 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1742 depends on ARM64_PAN
1744 Enhanced Privileged Access Never (EPAN) allows Privileged
1745 Access Never to be used with Execute-only mappings.
1747 The feature is detected at runtime, and will remain disabled
1748 if the cpu does not implement the feature.
1752 bool "ARM Scalable Vector Extension support"
1755 The Scalable Vector Extension (SVE) is an extension to the AArch64
1756 execution state which complements and extends the SIMD functionality
1757 of the base architecture to support much larger vectors and to enable
1758 additional vectorisation opportunities.
1760 To enable use of this extension on CPUs that implement it, say Y.
1762 On CPUs that support the SVE2 extensions, this option will enable
1765 Note that for architectural reasons, firmware _must_ implement SVE
1766 support when running on SVE capable hardware. The required support
1769 * version 1.5 and later of the ARM Trusted Firmware
1770 * the AArch64 boot wrapper since commit 5e1261e08abf
1771 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1773 For other firmware implementations, consult the firmware documentation
1776 If you need the kernel to boot on SVE-capable hardware with broken
1777 firmware, you may need to say N here until you get your firmware
1778 fixed. Otherwise, you may experience firmware panics or lockups when
1779 booting the kernel. If unsure and you are not observing these
1780 symptoms, you should assume that it is safe to say Y.
1782 config ARM64_MODULE_PLTS
1783 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1785 select HAVE_MOD_ARCH_SPECIFIC
1787 Allocate PLTs when loading modules so that jumps and calls whose
1788 targets are too far away for their relative offsets to be encoded
1789 in the instructions themselves can be bounced via veneers in the
1790 module's PLT. This allows modules to be allocated in the generic
1791 vmalloc area after the dedicated module memory area has been
1794 When running with address space randomization (KASLR), the module
1795 region itself may be too far away for ordinary relative jumps and
1796 calls, and so in that case, module PLTs are required and cannot be
1799 Specific errata workaround(s) might also force module PLTs to be
1800 enabled (ARM64_ERRATUM_843419).
1802 config ARM64_PSEUDO_NMI
1803 bool "Support for NMI-like interrupts"
1806 Adds support for mimicking Non-Maskable Interrupts through the use of
1807 GIC interrupt priority. This support requires version 3 or later of
1810 This high priority configuration for interrupts needs to be
1811 explicitly enabled by setting the kernel parameter
1812 "irqchip.gicv3_pseudo_nmi" to 1.
1817 config ARM64_DEBUG_PRIORITY_MASKING
1818 bool "Debug interrupt priority masking"
1820 This adds runtime checks to functions enabling/disabling
1821 interrupts when using priority masking. The additional checks verify
1822 the validity of ICC_PMR_EL1 when calling concerned functions.
1828 bool "Build a relocatable kernel image" if EXPERT
1829 select ARCH_HAS_RELR
1832 This builds the kernel as a Position Independent Executable (PIE),
1833 which retains all relocation metadata required to relocate the
1834 kernel binary at runtime to a different virtual address than the
1835 address it was linked at.
1836 Since AArch64 uses the RELA relocation format, this requires a
1837 relocation pass at runtime even if the kernel is loaded at the
1838 same address it was linked at.
1840 config RANDOMIZE_BASE
1841 bool "Randomize the address of the kernel image"
1842 select ARM64_MODULE_PLTS if MODULES
1845 Randomizes the virtual address at which the kernel image is
1846 loaded, as a security feature that deters exploit attempts
1847 relying on knowledge of the location of kernel internals.
1849 It is the bootloader's job to provide entropy, by passing a
1850 random u64 value in /chosen/kaslr-seed at kernel entry.
1852 When booting via the UEFI stub, it will invoke the firmware's
1853 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1854 to the kernel proper. In addition, it will randomise the physical
1855 location of the kernel Image as well.
1859 config RANDOMIZE_MODULE_REGION_FULL
1860 bool "Randomize the module region over a 2 GB range"
1861 depends on RANDOMIZE_BASE
1864 Randomizes the location of the module region inside a 2 GB window
1865 covering the core kernel. This way, it is less likely for modules
1866 to leak information about the location of core kernel data structures
1867 but it does imply that function calls between modules and the core
1868 kernel will need to be resolved via veneers in the module PLT.
1870 When this option is not set, the module region will be randomized over
1871 a limited range that contains the [_stext, _etext] interval of the
1872 core kernel, so branch relocations are almost always in range unless
1873 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1874 particular case of region exhaustion, modules might be able to fall
1875 back to a larger 2GB area.
1877 config CC_HAVE_STACKPROTECTOR_SYSREG
1878 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1880 config STACKPROTECTOR_PER_TASK
1882 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1888 config ARM64_ACPI_PARKING_PROTOCOL
1889 bool "Enable support for the ARM64 ACPI parking protocol"
1892 Enable support for the ARM64 ACPI parking protocol. If disabled
1893 the kernel will not allow booting through the ARM64 ACPI parking
1894 protocol even if the corresponding data is present in the ACPI
1898 string "Default kernel command string"
1901 Provide a set of default command-line options at build time by
1902 entering them here. As a minimum, you should specify the the
1903 root device (e.g. root=/dev/nfs).
1906 prompt "Kernel command line type" if CMDLINE != ""
1907 default CMDLINE_FROM_BOOTLOADER
1909 Choose how the kernel will handle the provided default kernel
1910 command line string.
1912 config CMDLINE_FROM_BOOTLOADER
1913 bool "Use bootloader kernel arguments if available"
1915 Uses the command-line options passed by the boot loader. If
1916 the boot loader doesn't provide any, the default kernel command
1917 string provided in CMDLINE will be used.
1919 config CMDLINE_FORCE
1920 bool "Always use the default kernel command string"
1922 Always use the default kernel command string, even if the boot
1923 loader passes other arguments to the kernel.
1924 This is useful if you cannot or don't want to change the
1925 command-line options your boot loader passes to the kernel.
1933 bool "UEFI runtime support"
1934 depends on OF && !CPU_BIG_ENDIAN
1935 depends on KERNEL_MODE_NEON
1936 select ARCH_SUPPORTS_ACPI
1939 select EFI_PARAMS_FROM_FDT
1940 select EFI_RUNTIME_WRAPPERS
1942 select EFI_GENERIC_STUB
1943 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1946 This option provides support for runtime services provided
1947 by UEFI firmware (such as non-volatile variables, realtime
1948 clock, and platform reset). A UEFI stub is also provided to
1949 allow the kernel to be booted as an EFI application. This
1950 is only useful on systems that have UEFI firmware.
1953 bool "Enable support for SMBIOS (DMI) tables"
1957 This enables SMBIOS/DMI feature for systems.
1959 This option is only useful on systems that have UEFI firmware.
1960 However, even with this option, the resultant kernel should
1961 continue to boot on existing non-UEFI platforms.
1965 config SYSVIPC_COMPAT
1967 depends on COMPAT && SYSVIPC
1969 menu "Power management options"
1971 source "kernel/power/Kconfig"
1973 config ARCH_HIBERNATION_POSSIBLE
1977 config ARCH_HIBERNATION_HEADER
1979 depends on HIBERNATION
1981 config ARCH_SUSPEND_POSSIBLE
1986 menu "CPU Power Management"
1988 source "drivers/cpuidle/Kconfig"
1990 source "drivers/cpufreq/Kconfig"
1994 source "drivers/acpi/Kconfig"
1996 source "arch/arm64/kvm/Kconfig"
1999 source "arch/arm64/crypto/Kconfig"